magma.c revision 1.12
1 /* $NetBSD: magma.c,v 1.12 2001/11/13 06:58:17 lukem Exp $ */ 2 /* 3 * magma.c 4 * 5 * Copyright (c) 1998 Iain Hibbert 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Iain Hibbert 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35 /* 36 * Driver for Magma SBus Serial/Parallel cards using the Cirrus Logic 37 * CD1400 & CD1190 chips 38 */ 39 40 #include <sys/cdefs.h> 41 __KERNEL_RCSID(0, "$NetBSD: magma.c,v 1.12 2001/11/13 06:58:17 lukem Exp $"); 42 43 #if 0 44 #define MAGMA_DEBUG 45 #endif 46 47 #include "magma.h" 48 #if NMAGMA > 0 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/proc.h> 53 #include <sys/device.h> 54 #include <sys/file.h> 55 #include <sys/ioctl.h> 56 #include <sys/malloc.h> 57 #include <sys/tty.h> 58 #include <sys/time.h> 59 #include <sys/kernel.h> 60 #include <sys/syslog.h> 61 #include <sys/conf.h> 62 #include <sys/errno.h> 63 64 #include <machine/bus.h> 65 #include <machine/intr.h> 66 #include <machine/autoconf.h> 67 #include <machine/conf.h> 68 69 #include <dev/sbus/sbusvar.h> 70 71 #include <dev/ic/cd1400reg.h> 72 #include <dev/ic/cd1190reg.h> 73 74 #include <dev/sbus/mbppio.h> 75 #include <dev/sbus/magmareg.h> 76 77 /* 78 * Select tty soft interrupt bit based on TTY ipl. (stole from zs.c) 79 */ 80 #if PIL_TTY == 1 81 # define IE_MSOFT IE_L1 82 #elif PIL_TTY == 4 83 # define IE_MSOFT IE_L4 84 #elif PIL_TTY == 6 85 # define IE_MSOFT IE_L6 86 #else 87 # error "no suitable software interrupt bit" 88 #endif 89 90 /* supported cards 91 * 92 * The table below lists the cards that this driver is likely to 93 * be able to support. 94 * 95 * Cards with parallel ports: except for the LC2+1Sp, they all use 96 * the CD1190 chip which I know nothing about. I've tried to leave 97 * hooks for it so it shouldn't be too hard to add support later. 98 * (I think somebody is working on this separately) 99 * 100 * Thanks to Bruce at Magma for telling me the hardware offsets. 101 */ 102 static struct magma_board_info supported_cards[] = { 103 { 104 "MAGMA,4_Sp", "Magma 4 Sp", 4, 0, 105 1, 0xa000, 0xc000, 0xe000, { 0x8000, 0, 0, 0 }, 106 0, { 0, 0 } 107 }, 108 { 109 "MAGMA,8_Sp", "Magma 8 Sp", 8, 0, 110 2, 0xa000, 0xc000, 0xe000, { 0x4000, 0x6000, 0, 0 }, 111 0, { 0, 0 } 112 }, 113 { 114 "MAGMA,_8HS_Sp", "Magma Fast 8 Sp", 8, 0, 115 2, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0, 0 }, 116 0, { 0, 0 } 117 }, 118 { 119 "MAGMA,_8SP_422", "Magma 8 Sp - 422", 8, 0, 120 2, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0, 0 }, 121 0, { 0, 0 } 122 }, 123 { 124 "MAGMA,12_Sp", "Magma 12 Sp", 12, 0, 125 3, 0xa000, 0xc000, 0xe000, { 0x2000, 0x4000, 0x6000, 0 }, 126 0, { 0, 0 } 127 }, 128 { 129 "MAGMA,16_Sp", "Magma 16 Sp", 16, 0, 130 4, 0xd000, 0xe000, 0xf000, { 0x8000, 0x9000, 0xa000, 0xb000 }, 131 0, { 0, 0 } 132 }, 133 { 134 "MAGMA,16_Sp_2", "Magma 16 Sp", 16, 0, 135 4, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0xc000, 0xe000 }, 136 0, { 0, 0 } 137 }, 138 { 139 "MAGMA,16HS_Sp", "Magma Fast 16 Sp", 16, 0, 140 4, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0xc000, 0xe000 }, 141 0, { 0, 0 } 142 }, 143 { 144 "MAGMA,21_Sp", "Magma LC 2+1 Sp", 2, 1, 145 1, 0xa000, 0xc000, 0xe000, { 0x8000, 0, 0, 0 }, 146 0, { 0, 0 } 147 }, 148 { 149 "MAGMA,21HS_Sp", "Magma 2+1 Sp", 2, 1, 150 1, 0xa000, 0xc000, 0xe000, { 0x4000, 0, 0, 0 }, 151 1, { 0x6000, 0 } 152 }, 153 { 154 "MAGMA,41_Sp", "Magma 4+1 Sp", 4, 1, 155 1, 0xa000, 0xc000, 0xe000, { 0x4000, 0, 0, 0 }, 156 1, { 0x6000, 0 } 157 }, 158 { 159 "MAGMA,82_Sp", "Magma 8+2 Sp", 8, 2, 160 2, 0xd000, 0xe000, 0xf000, { 0x8000, 0x9000, 0, 0 }, 161 2, { 0xa000, 0xb000 } 162 }, 163 { 164 "MAGMA,P1_Sp", "Magma P1 Sp", 0, 1, 165 0, 0, 0, 0, { 0, 0, 0, 0 }, 166 1, { 0x8000, 0 } 167 }, 168 { 169 "MAGMA,P2_Sp", "Magma P2 Sp", 0, 2, 170 0, 0, 0, 0, { 0, 0, 0, 0 }, 171 2, { 0x4000, 0x8000 } 172 }, 173 { 174 NULL, NULL, 0, 0, 175 0, 0, 0, 0, { 0, 0, 0, 0 }, 176 0, { 0, 0 } 177 } 178 }; 179 180 /************************************************************************ 181 * 182 * Autoconfig Stuff 183 */ 184 185 struct cfattach magma_ca = { 186 sizeof(struct magma_softc), magma_match, magma_attach 187 }; 188 189 struct cfattach mtty_ca = { 190 sizeof(struct mtty_softc), mtty_match, mtty_attach 191 }; 192 193 struct cfattach mbpp_ca = { 194 sizeof(struct mbpp_softc), mbpp_match, mbpp_attach 195 }; 196 197 extern struct cfdriver mtty_cd; 198 extern struct cfdriver mbpp_cd; 199 200 /************************************************************************ 201 * 202 * CD1400 Routines 203 * 204 * cd1400_compute_baud calculate COR/BPR register values 205 * cd1400_write_ccr write a value to CD1400 ccr 206 * cd1400_read_reg read from a CD1400 register 207 * cd1400_write_reg write to a CD1400 register 208 * cd1400_enable_transmitter enable transmitting on CD1400 channel 209 */ 210 211 /* 212 * compute the bpr/cor pair for any baud rate 213 * returns 0 for success, 1 for failure 214 */ 215 int 216 cd1400_compute_baud(speed, clock, cor, bpr) 217 speed_t speed; 218 int clock; 219 int *cor, *bpr; 220 { 221 int c, co, br; 222 223 if( speed < 50 || speed > 150000 ) 224 return(1); 225 226 for( c = 0, co = 8 ; co <= 2048 ; co <<= 2, c++ ) { 227 br = ((clock * 1000000) + (co * speed) / 2) / (co * speed); 228 if( br < 0x100 ) { 229 *bpr = br; 230 *cor = c; 231 return(0); 232 } 233 } 234 235 return(1); 236 } 237 238 /* 239 * Write a CD1400 channel command, should have a timeout? 240 */ 241 __inline void 242 cd1400_write_ccr(cd, cmd) 243 struct cd1400 *cd; 244 u_char cmd; 245 { 246 while( cd1400_read_reg(cd, CD1400_CCR) ) 247 ; 248 249 cd1400_write_reg(cd, CD1400_CCR, cmd); 250 } 251 252 /* 253 * read a value from a cd1400 register 254 */ 255 __inline u_char 256 cd1400_read_reg(cd, reg) 257 struct cd1400 *cd; 258 int reg; 259 { 260 return(cd->cd_reg[reg]); 261 } 262 263 /* 264 * write a value to a cd1400 register 265 */ 266 __inline void 267 cd1400_write_reg(cd, reg, value) 268 struct cd1400 *cd; 269 int reg; 270 u_char value; 271 { 272 cd->cd_reg[reg] = value; 273 } 274 275 /* 276 * enable transmit service requests for cd1400 channel 277 */ 278 void 279 cd1400_enable_transmitter(cd, channel) 280 struct cd1400 *cd; 281 int channel; 282 { 283 int s, srer; 284 285 s = spltty(); 286 cd1400_write_reg(cd, CD1400_CAR, channel); 287 srer = cd1400_read_reg(cd, CD1400_SRER); 288 SET(srer, CD1400_SRER_TXRDY); 289 cd1400_write_reg(cd, CD1400_SRER, srer); 290 splx(s); 291 } 292 293 /************************************************************************ 294 * 295 * CD1190 Routines 296 */ 297 298 /* well, there are none yet */ 299 300 /************************************************************************ 301 * 302 * Magma Routines 303 * 304 * magma_match reports if we have a magma board available 305 * magma_attach attaches magma boards to the sbus 306 * magma_hard hardware level interrupt routine 307 * magma_soft software level interrupt routine 308 */ 309 310 int 311 magma_match(parent, cf, aux) 312 struct device *parent; 313 struct cfdata *cf; 314 void *aux; 315 { 316 struct sbus_attach_args *sa = aux; 317 318 /* is it a magma Sp card? */ 319 if( strcmp(sa->sa_name, "MAGMA_Sp") != 0 ) 320 return(0); 321 322 dprintf(("magma: matched `%s'\n", sa->sa_name)); 323 dprintf(("magma: magma_prom `%s'\n", 324 PROM_getpropstring(sa->sa_node, "magma_prom"))); 325 dprintf(("magma: intlevels `%s'\n", 326 PROM_getpropstring(sa->sa_node, "intlevels"))); 327 dprintf(("magma: chiprev `%s'\n", 328 PROM_getpropstring(sa->sa_node, "chiprev"))); 329 dprintf(("magma: clock `%s'\n", 330 PROM_getpropstring(sa->sa_node, "clock"))); 331 332 return (1); 333 } 334 335 void 336 magma_attach(parent, self, aux) 337 struct device *parent; 338 struct device *self; 339 void *aux; 340 { 341 struct sbus_attach_args *sa = aux; 342 struct magma_softc *sc = (struct magma_softc *)self; 343 struct magma_board_info *card = supported_cards; 344 bus_space_handle_t bh; 345 char *magma_prom; 346 int node, chip; 347 348 node = sa->sa_node; 349 magma_prom = PROM_getpropstring(node, "magma_prom"); 350 351 /* find the card type */ 352 while (card->mb_name && strcmp(magma_prom, card->mb_name) != 0) 353 card++; 354 355 dprintf((" addr %p", sc)); 356 printf(" softpri %d:", PIL_TTY); 357 358 if( card->mb_name == NULL ) { 359 printf(" %s (unsupported)\n", magma_prom); 360 return; 361 } 362 363 printf(" %s\n", card->mb_realname); 364 365 sc->ms_board = card; 366 sc->ms_ncd1400 = card->mb_ncd1400; 367 sc->ms_ncd1190 = card->mb_ncd1190; 368 369 if (sbus_bus_map(sa->sa_bustag, 370 sa->sa_slot, 371 sa->sa_offset, 372 sa->sa_size, 373 BUS_SPACE_MAP_LINEAR, 374 0, &bh) != 0) { 375 printf("%s @ sbus: cannot map registers\n", self->dv_xname); 376 return; 377 } 378 379 /* the SVCACK* lines are daisychained */ 380 sc->ms_svcackr = (caddr_t)bh + card->mb_svcackr; 381 sc->ms_svcackt = (caddr_t)bh + card->mb_svcackt; 382 sc->ms_svcackm = (caddr_t)bh + card->mb_svcackm; 383 384 /* init the cd1400 chips */ 385 for( chip = 0 ; chip < card->mb_ncd1400 ; chip++ ) { 386 struct cd1400 *cd = &sc->ms_cd1400[chip]; 387 388 cd->cd_reg = (caddr_t)bh + card->mb_cd1400[chip]; 389 390 /* XXX PROM_getpropstring(node, "clock") */ 391 cd->cd_clock = 25; 392 393 /* PROM_getpropstring(node, "chiprev"); */ 394 /* seemingly the Magma drivers just ignore the propstring */ 395 cd->cd_chiprev = cd1400_read_reg(cd, CD1400_GFRCR); 396 397 dprintf(("%s attach CD1400 %d addr %p rev %x clock %dMhz\n", 398 sc->ms_dev.dv_xname, chip, 399 cd->cd_reg, cd->cd_chiprev, cd->cd_clock)); 400 401 /* clear GFRCR */ 402 cd1400_write_reg(cd, CD1400_GFRCR, 0x00); 403 404 /* reset whole chip */ 405 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET | CD1400_CCR_FULLRESET); 406 407 /* wait for revision code to be restored */ 408 while( cd1400_read_reg(cd, CD1400_GFRCR) != cd->cd_chiprev ) 409 ; 410 411 /* set the Prescaler Period Register to tick at 1ms */ 412 cd1400_write_reg(cd, CD1400_PPR, 413 ((cd->cd_clock * 1000000 / CD1400_PPR_PRESCALER + 500) / 1000)); 414 415 /* The LC2+1Sp card is the only card that doesn't have 416 * a CD1190 for the parallel port, but uses channel 0 of 417 * the CD1400, so we make a note of it for later and set up 418 * the CD1400 for parallel mode operation. 419 */ 420 if( card->mb_npar && card->mb_ncd1190 == 0 ) { 421 cd1400_write_reg(cd, CD1400_GCR, CD1400_GCR_PARALLEL); 422 cd->cd_parmode = 1; 423 } 424 } 425 426 /* init the cd1190 chips */ 427 for( chip = 0 ; chip < card->mb_ncd1190 ; chip++ ) { 428 struct cd1190 *cd = &sc->ms_cd1190[chip]; 429 430 cd->cd_reg = (caddr_t)bh + card->mb_cd1190[chip]; 431 dprintf(("%s attach CD1190 %d addr %p (failed)\n", 432 self->dv_xname, chip, cd->cd_reg)); 433 /* XXX don't know anything about these chips yet */ 434 } 435 436 sbus_establish(&sc->ms_sd, &sc->ms_dev); 437 438 /* configure the children */ 439 (void)config_found(self, mtty_match, NULL); 440 (void)config_found(self, mbpp_match, NULL); 441 442 /* 443 * Establish the interrupt handlers. 444 */ 445 if (sa->sa_nintr == 0) 446 return; /* No interrupts to service!? */ 447 448 (void)bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_TTY, 449 0, magma_hard, sc); 450 (void)bus_intr_establish(sa->sa_bustag, PIL_TTY, IPL_SOFTSERIAL, 451 BUS_INTR_ESTABLISH_SOFTINTR, 452 magma_soft, sc); 453 evcnt_attach_dynamic(&sc->ms_intrcnt, EVCNT_TYPE_INTR, NULL, 454 sc->ms_dev.dv_xname, "intr"); 455 } 456 457 /* 458 * hard interrupt routine 459 * 460 * returns 1 if it handled it, otherwise 0 461 * 462 * runs at interrupt priority 463 */ 464 int 465 magma_hard(arg) 466 void *arg; 467 { 468 struct magma_softc *sc = arg; 469 struct cd1400 *cd; 470 int chip, status = 0; 471 int serviced = 0; 472 int needsoftint = 0; 473 474 /* 475 * check status of all the CD1400 chips 476 */ 477 for( chip = 0 ; chip < sc->ms_ncd1400 ; chip++ ) 478 status |= cd1400_read_reg(&sc->ms_cd1400[chip], CD1400_SVRR); 479 480 if( ISSET(status, CD1400_SVRR_RXRDY) ) { 481 u_char rivr = *sc->ms_svcackr; /* enter rx service context */ 482 int port = rivr >> 4; 483 484 if( rivr & (1<<3) ) { /* parallel port */ 485 struct mbpp_port *mbpp; 486 int n_chars; 487 488 mbpp = &sc->ms_mbpp->ms_port[port]; 489 cd = mbpp->mp_cd1400; 490 491 /* don't think we have to handle exceptions */ 492 n_chars = cd1400_read_reg(cd, CD1400_RDCR); 493 while (n_chars--) { 494 if( mbpp->mp_cnt == 0 ) { 495 SET(mbpp->mp_flags, MBPPF_WAKEUP); 496 needsoftint = 1; 497 break; 498 } 499 *mbpp->mp_ptr = cd1400_read_reg(cd,CD1400_RDSR); 500 mbpp->mp_ptr++; 501 mbpp->mp_cnt--; 502 } 503 } else { /* serial port */ 504 struct mtty_port *mtty; 505 u_char *ptr, n_chars, line_stat; 506 507 mtty = &sc->ms_mtty->ms_port[port]; 508 cd = mtty->mp_cd1400; 509 510 if( ISSET(rivr, CD1400_RIVR_EXCEPTION) ) { 511 line_stat = cd1400_read_reg(cd, CD1400_RDSR); 512 n_chars = 1; 513 } else { /* no exception, received data OK */ 514 line_stat = 0; 515 n_chars = cd1400_read_reg(cd, CD1400_RDCR); 516 } 517 518 ptr = mtty->mp_rput; 519 while( n_chars-- ) { 520 *ptr++ = line_stat; 521 *ptr++ = cd1400_read_reg(cd, CD1400_RDSR); 522 if( ptr == mtty->mp_rend ) ptr = mtty->mp_rbuf; 523 if( ptr == mtty->mp_rget ) { 524 if( ptr == mtty->mp_rbuf ) 525 ptr = mtty->mp_rend; 526 ptr -= 2; 527 SET(mtty->mp_flags, MTTYF_RING_OVERFLOW); 528 break; 529 } 530 } 531 mtty->mp_rput = ptr; 532 533 needsoftint = 1; 534 } 535 536 cd1400_write_reg(cd, CD1400_EOSRR, 0); /* end service context */ 537 serviced = 1; 538 } /* if(rx_service...) */ 539 540 if( ISSET(status, CD1400_SVRR_MDMCH) ) { 541 u_char mivr = *sc->ms_svcackm; /* enter mdm service context */ 542 int port = mivr >> 4; 543 struct mtty_port *mtty; 544 int carrier; 545 u_char msvr; 546 547 /* 548 * Handle CD (LC2+1Sp = DSR) changes. 549 */ 550 mtty = &sc->ms_mtty->ms_port[port]; 551 cd = mtty->mp_cd1400; 552 msvr = cd1400_read_reg(cd, CD1400_MSVR2); 553 carrier = ISSET(msvr, cd->cd_parmode ? CD1400_MSVR2_DSR : CD1400_MSVR2_CD); 554 555 if( mtty->mp_carrier != carrier ) { 556 SET(mtty->mp_flags, MTTYF_CARRIER_CHANGED); 557 mtty->mp_carrier = carrier; 558 needsoftint = 1; 559 } 560 561 cd1400_write_reg(cd, CD1400_EOSRR, 0); /* end service context */ 562 serviced = 1; 563 } /* if(mdm_service...) */ 564 565 if( ISSET(status, CD1400_SVRR_TXRDY) ) { 566 u_char tivr = *sc->ms_svcackt; /* enter tx service context */ 567 int port = tivr >> 4; 568 569 if( tivr & (1<<3) ) { /* parallel port */ 570 struct mbpp_port *mbpp; 571 572 mbpp = &sc->ms_mbpp->ms_port[port]; 573 cd = mbpp->mp_cd1400; 574 575 if( mbpp->mp_cnt ) { 576 int count = 0; 577 578 /* fill the fifo */ 579 while (mbpp->mp_cnt && 580 count++ < CD1400_PAR_FIFO_SIZE) { 581 cd1400_write_reg(cd, CD1400_TDR, 582 *mbpp->mp_ptr); 583 mbpp->mp_ptr++; 584 mbpp->mp_cnt--; 585 } 586 } else { 587 /* 588 * fifo is empty and we got no more data 589 * to send, so shut off interrupts and 590 * signal for a wakeup, which can't be 591 * done here in case we beat mbpp_send to 592 * the tsleep call (we are running at >spltty) 593 */ 594 cd1400_write_reg(cd, CD1400_SRER, 0); 595 SET(mbpp->mp_flags, MBPPF_WAKEUP); 596 needsoftint = 1; 597 } 598 } else { /* serial port */ 599 struct mtty_port *mtty; 600 struct tty *tp; 601 602 mtty = &sc->ms_mtty->ms_port[port]; 603 cd = mtty->mp_cd1400; 604 tp = mtty->mp_tty; 605 606 if( !ISSET(mtty->mp_flags, MTTYF_STOP) ) { 607 int count = 0; 608 609 /* check if we should start/stop a break */ 610 if( ISSET(mtty->mp_flags, MTTYF_SET_BREAK) ) { 611 cd1400_write_reg(cd, CD1400_TDR, 0); 612 cd1400_write_reg(cd, CD1400_TDR, 0x81); 613 /* should we delay too? */ 614 CLR(mtty->mp_flags, MTTYF_SET_BREAK); 615 count += 2; 616 } 617 618 if( ISSET(mtty->mp_flags, MTTYF_CLR_BREAK) ) { 619 cd1400_write_reg(cd, CD1400_TDR, 0); 620 cd1400_write_reg(cd, CD1400_TDR, 0x83); 621 CLR(mtty->mp_flags, MTTYF_CLR_BREAK); 622 count += 2; 623 } 624 625 /* I don't quite fill the fifo in case the last one is a 626 * NULL which I have to double up because its the escape 627 * code for embedded transmit characters. 628 */ 629 while( mtty->mp_txc > 0 && count < CD1400_TX_FIFO_SIZE - 1 ) { 630 u_char ch; 631 632 ch = *mtty->mp_txp; 633 634 mtty->mp_txc--; 635 mtty->mp_txp++; 636 637 if( ch == 0 ) { 638 cd1400_write_reg(cd, CD1400_TDR, ch); 639 count++; 640 } 641 642 cd1400_write_reg(cd, CD1400_TDR, ch); 643 count++; 644 } 645 } 646 647 /* if we ran out of work or are requested to STOP then 648 * shut off the txrdy interrupts and signal DONE to flush 649 * out the chars we have sent. 650 */ 651 if( mtty->mp_txc == 0 || ISSET(mtty->mp_flags, MTTYF_STOP) ) { 652 register int srer; 653 654 srer = cd1400_read_reg(cd, CD1400_SRER); 655 CLR(srer, CD1400_SRER_TXRDY); 656 cd1400_write_reg(cd, CD1400_SRER, srer); 657 CLR(mtty->mp_flags, MTTYF_STOP); 658 659 SET(mtty->mp_flags, MTTYF_DONE); 660 needsoftint = 1; 661 } 662 } 663 664 cd1400_write_reg(cd, CD1400_EOSRR, 0); /* end service context */ 665 serviced = 1; 666 } /* if(tx_service...) */ 667 668 /* XXX service CD1190 interrupts too 669 for( chip = 0 ; chip < sc->ms_ncd1190 ; chip++ ) { 670 } 671 */ 672 673 if( needsoftint ) { /* trigger the soft interrupt */ 674 #if defined(SUN4M) 675 if( CPU_ISSUN4M ) 676 raise(0, PIL_TTY); 677 else 678 #endif 679 ienab_bis(IE_MSOFT); 680 } 681 682 return(serviced); 683 } 684 685 /* 686 * magma soft interrupt handler 687 * 688 * returns 1 if it handled it, 0 otherwise 689 * 690 * runs at spltty() 691 */ 692 int 693 magma_soft(arg) 694 void *arg; 695 { 696 struct magma_softc *sc = arg; 697 struct mtty_softc *mtty = sc->ms_mtty; 698 struct mbpp_softc *mbpp = sc->ms_mbpp; 699 int port; 700 int serviced = 0; 701 int s, flags; 702 703 if (mtty == NULL) 704 goto chkbpp; 705 706 /* 707 * check the tty ports to see what needs doing 708 */ 709 for( port = 0 ; port < mtty->ms_nports ; port++ ) { 710 struct mtty_port *mp = &mtty->ms_port[port]; 711 struct tty *tp = mp->mp_tty; 712 713 if( !ISSET(tp->t_state, TS_ISOPEN) ) 714 continue; 715 716 /* 717 * handle any received data 718 */ 719 while( mp->mp_rget != mp->mp_rput ) { 720 u_char stat; 721 int data; 722 723 stat = mp->mp_rget[0]; 724 data = mp->mp_rget[1]; 725 mp->mp_rget = ((mp->mp_rget + 2) == mp->mp_rend) 726 ? mp->mp_rbuf : (mp->mp_rget + 2); 727 728 if( stat & (CD1400_RDSR_BREAK | CD1400_RDSR_FE) ) 729 data |= TTY_FE; 730 if( stat & CD1400_RDSR_PE ) 731 data |= TTY_PE; 732 733 if( stat & CD1400_RDSR_OE ) 734 log(LOG_WARNING, "%s%x: fifo overflow\n", 735 mtty->ms_dev.dv_xname, port); 736 737 (*tp->t_linesw->l_rint)(data, tp); 738 serviced = 1; 739 } 740 741 s = splhigh(); /* block out hard interrupt routine */ 742 flags = mp->mp_flags; 743 CLR(mp->mp_flags, MTTYF_DONE | MTTYF_CARRIER_CHANGED | MTTYF_RING_OVERFLOW); 744 splx(s); /* ok */ 745 746 if( ISSET(flags, MTTYF_CARRIER_CHANGED) ) { 747 dprintf(("%s%x: cd %s\n", mtty->ms_dev.dv_xname, 748 port, mp->mp_carrier ? "on" : "off")); 749 (*tp->t_linesw->l_modem)(tp, mp->mp_carrier); 750 serviced = 1; 751 } 752 753 if( ISSET(flags, MTTYF_RING_OVERFLOW) ) { 754 log(LOG_WARNING, "%s%x: ring buffer overflow\n", 755 mtty->ms_dev.dv_xname, port); 756 serviced = 1; 757 } 758 759 if( ISSET(flags, MTTYF_DONE) ) { 760 ndflush(&tp->t_outq, mp->mp_txp - tp->t_outq.c_cf); 761 CLR(tp->t_state, TS_BUSY); 762 (*tp->t_linesw->l_start)(tp); /* might be some more */ 763 serviced = 1; 764 } 765 } /* for(each mtty...) */ 766 767 768 chkbpp: 769 /* 770 * Check the bpp ports (if any) to see what needs doing 771 */ 772 if (mbpp == NULL) 773 return (serviced); 774 775 for( port = 0 ; port < mbpp->ms_nports ; port++ ) { 776 struct mbpp_port *mp = &mbpp->ms_port[port]; 777 778 if( !ISSET(mp->mp_flags, MBPPF_OPEN) ) 779 continue; 780 781 s = splhigh(); 782 flags = mp->mp_flags; 783 CLR(mp->mp_flags, MBPPF_WAKEUP); 784 splx(s); 785 786 if( ISSET(flags, MBPPF_WAKEUP) ) { 787 wakeup(mp); 788 serviced = 1; 789 } 790 791 } /* for(each mbpp...) */ 792 793 return(serviced); 794 } 795 796 /************************************************************************ 797 * 798 * MTTY Routines 799 * 800 * mtty_match match one mtty device 801 * mtty_attach attach mtty devices 802 * mttyopen open mtty device 803 * mttyclose close mtty device 804 * mttyread read from mtty 805 * mttywrite write to mtty 806 * mttyioctl do ioctl on mtty 807 * mttytty return tty pointer for mtty 808 * mttystop stop mtty device 809 * mtty_start start mtty device 810 * mtty_param set mtty parameters 811 * mtty_modem_control set modem control lines 812 */ 813 814 int 815 mtty_match(parent, cf, args) 816 struct device *parent; 817 struct cfdata *cf; 818 void *args; 819 { 820 struct magma_softc *sc = (struct magma_softc *)parent; 821 822 return( args == mtty_match && sc->ms_board->mb_nser && sc->ms_mtty == NULL ); 823 } 824 825 void 826 mtty_attach(parent, dev, args) 827 struct device *parent; 828 struct device *dev; 829 void *args; 830 { 831 struct magma_softc *sc = (struct magma_softc *)parent; 832 struct mtty_softc *ms = (struct mtty_softc *)dev; 833 int port, chip, chan; 834 835 sc->ms_mtty = ms; 836 dprintf((" addr %p", ms)); 837 838 for( port = 0, chip = 0, chan = 0 ; port < sc->ms_board->mb_nser ; port++ ) { 839 struct mtty_port *mp = &ms->ms_port[port]; 840 struct tty *tp; 841 842 mp->mp_cd1400 = &sc->ms_cd1400[chip]; 843 if( mp->mp_cd1400->cd_parmode && chan == 0 ) 844 chan = 1; /* skip channel 0 if parmode */ 845 mp->mp_channel = chan; 846 847 tp = ttymalloc(); 848 if( tp == NULL ) break; 849 tty_attach(tp); 850 tp->t_oproc = mtty_start; 851 tp->t_param = mtty_param; 852 853 mp->mp_tty = tp; 854 855 mp->mp_rbuf = malloc(MTTY_RBUF_SIZE, M_DEVBUF, M_NOWAIT); 856 if( mp->mp_rbuf == NULL ) break; 857 858 mp->mp_rend = mp->mp_rbuf + MTTY_RBUF_SIZE; 859 860 chan = (chan + 1) % CD1400_NO_OF_CHANNELS; 861 if( chan == 0 ) chip++; 862 } 863 864 ms->ms_nports = port; 865 printf(": %d tty%s\n", port, port == 1 ? "" : "s"); 866 } 867 868 /* 869 * open routine. returns zero if successful, else error code 870 */ 871 int 872 mttyopen(dev, flags, mode, p) 873 dev_t dev; 874 int flags; 875 int mode; 876 struct proc *p; 877 { 878 int card = MAGMA_CARD(dev); 879 int port = MAGMA_PORT(dev); 880 struct mtty_softc *ms; 881 struct mtty_port *mp; 882 struct tty *tp; 883 struct cd1400 *cd; 884 int error, s; 885 886 if( card >= mtty_cd.cd_ndevs || 887 (ms = mtty_cd.cd_devs[card]) == NULL || port >= ms->ms_nports ) 888 return(ENXIO); /* device not configured */ 889 890 mp = &ms->ms_port[port]; 891 tp = mp->mp_tty; 892 tp->t_dev = dev; 893 894 if (ISSET(tp->t_state, TS_ISOPEN) && 895 ISSET(tp->t_state, TS_XCLUDE) && 896 p->p_ucred->cr_uid != 0) 897 return (EBUSY); 898 899 s = spltty(); 900 901 if( !ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 902 903 /* set defaults */ 904 ttychars(tp); 905 tp->t_iflag = TTYDEF_IFLAG; 906 tp->t_oflag = TTYDEF_OFLAG; 907 tp->t_cflag = TTYDEF_CFLAG; 908 if( ISSET(mp->mp_openflags, TIOCFLAG_CLOCAL) ) 909 SET(tp->t_cflag, CLOCAL); 910 if( ISSET(mp->mp_openflags, TIOCFLAG_CRTSCTS) ) 911 SET(tp->t_cflag, CRTSCTS); 912 if( ISSET(mp->mp_openflags, TIOCFLAG_MDMBUF) ) 913 SET(tp->t_cflag, MDMBUF); 914 tp->t_lflag = TTYDEF_LFLAG; 915 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 916 917 /* init ring buffer */ 918 mp->mp_rput = mp->mp_rget = mp->mp_rbuf; 919 920 /* reset CD1400 channel */ 921 cd = mp->mp_cd1400; 922 cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel); 923 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET); 924 925 /* encode the port number in top half of LIVR */ 926 cd1400_write_reg(cd, CD1400_LIVR, port << 4 ); 927 928 /* sets parameters and raises DTR */ 929 (void)mtty_param(tp, &tp->t_termios); 930 931 /* set tty watermarks */ 932 ttsetwater(tp); 933 934 /* enable service requests */ 935 cd1400_write_reg(cd, CD1400_SRER, 936 CD1400_SRER_RXDATA | CD1400_SRER_MDMCH); 937 938 /* tell the tty about the carrier status */ 939 if( ISSET(mp->mp_openflags, TIOCFLAG_SOFTCAR) || 940 mp->mp_carrier ) 941 SET(tp->t_state, TS_CARR_ON); 942 else 943 CLR(tp->t_state, TS_CARR_ON); 944 } 945 splx(s); 946 947 error = ttyopen(tp, MTTY_DIALOUT(dev), ISSET(flags, O_NONBLOCK)); 948 if (error != 0) 949 goto bad; 950 951 error = (*tp->t_linesw->l_open)(dev, tp); 952 if (error != 0) 953 goto bad; 954 955 bad: 956 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 957 /* 958 * We failed to open the device, and nobody else had it opened. 959 * Clean up the state as appropriate. 960 */ 961 /* XXX - do that here */ 962 } 963 964 return (error); 965 } 966 967 /* 968 * close routine. returns zero if successful, else error code 969 */ 970 int 971 mttyclose(dev, flag, mode, p) 972 dev_t dev; 973 int flag; 974 int mode; 975 struct proc *p; 976 { 977 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(dev)]; 978 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 979 struct tty *tp = mp->mp_tty; 980 int s; 981 982 (*tp->t_linesw->l_close)(tp, flag); 983 ttyclose(tp); 984 985 s = spltty(); 986 987 /* if HUPCL is set, and the tty is no longer open 988 * shut down the port 989 */ 990 if( ISSET(tp->t_cflag, HUPCL) || !ISSET(tp->t_state, TS_ISOPEN) ) { 991 /* XXX wait until FIFO is empty before turning off the channel 992 struct cd1400 *cd = mp->mp_cd1400; 993 */ 994 995 /* drop DTR and RTS */ 996 (void)mtty_modem_control(mp, 0, DMSET); 997 998 /* turn off the channel 999 cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel); 1000 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET); 1001 */ 1002 } 1003 1004 splx(s); 1005 1006 return(0); 1007 } 1008 1009 /* 1010 * Read routine 1011 */ 1012 int 1013 mttyread(dev, uio, flags) 1014 dev_t dev; 1015 struct uio *uio; 1016 int flags; 1017 { 1018 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(dev)]; 1019 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1020 struct tty *tp = mp->mp_tty; 1021 1022 return( (*tp->t_linesw->l_read)(tp, uio, flags) ); 1023 } 1024 1025 /* 1026 * Write routine 1027 */ 1028 int 1029 mttywrite(dev, uio, flags) 1030 dev_t dev; 1031 struct uio *uio; 1032 int flags; 1033 { 1034 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(dev)]; 1035 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1036 struct tty *tp = mp->mp_tty; 1037 1038 return( (*tp->t_linesw->l_write)(tp, uio, flags) ); 1039 } 1040 1041 /* 1042 * Poll routine 1043 */ 1044 int 1045 mttypoll(dev, events, p) 1046 dev_t dev; 1047 int events; 1048 struct proc *p; 1049 { 1050 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(dev)]; 1051 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1052 struct tty *tp = mp->mp_tty; 1053 1054 return ((*tp->t_linesw->l_poll)(tp, events, p)); 1055 } 1056 1057 /* 1058 * return tty pointer 1059 */ 1060 struct tty * 1061 mttytty(dev) 1062 dev_t dev; 1063 { 1064 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(dev)]; 1065 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1066 1067 return(mp->mp_tty); 1068 } 1069 1070 /* 1071 * ioctl routine 1072 */ 1073 int 1074 mttyioctl(dev, cmd, data, flags, p) 1075 dev_t dev; 1076 u_long cmd; 1077 caddr_t data; 1078 int flags; 1079 struct proc *p; 1080 { 1081 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(dev)]; 1082 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1083 struct tty *tp = mp->mp_tty; 1084 int error; 1085 1086 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flags, p); 1087 if( error >= 0 ) return(error); 1088 1089 error = ttioctl(tp, cmd, data, flags, p); 1090 if( error >= 0 ) return(error); 1091 1092 error = 0; 1093 1094 switch(cmd) { 1095 case TIOCSBRK: /* set break */ 1096 SET(mp->mp_flags, MTTYF_SET_BREAK); 1097 cd1400_enable_transmitter(mp->mp_cd1400, mp->mp_channel); 1098 break; 1099 1100 case TIOCCBRK: /* clear break */ 1101 SET(mp->mp_flags, MTTYF_CLR_BREAK); 1102 cd1400_enable_transmitter(mp->mp_cd1400, mp->mp_channel); 1103 break; 1104 1105 case TIOCSDTR: /* set DTR */ 1106 mtty_modem_control(mp, TIOCM_DTR, DMBIS); 1107 break; 1108 1109 case TIOCCDTR: /* clear DTR */ 1110 mtty_modem_control(mp, TIOCM_DTR, DMBIC); 1111 break; 1112 1113 case TIOCMSET: /* set modem lines */ 1114 mtty_modem_control(mp, *((int *)data), DMSET); 1115 break; 1116 1117 case TIOCMBIS: /* bit set modem lines */ 1118 mtty_modem_control(mp, *((int *)data), DMBIS); 1119 break; 1120 1121 case TIOCMBIC: /* bit clear modem lines */ 1122 mtty_modem_control(mp, *((int *)data), DMBIC); 1123 break; 1124 1125 case TIOCMGET: /* get modem lines */ 1126 *((int *)data) = mtty_modem_control(mp, 0, DMGET); 1127 break; 1128 1129 case TIOCGFLAGS: 1130 *((int *)data) = mp->mp_openflags; 1131 break; 1132 1133 case TIOCSFLAGS: 1134 if( suser(p->p_ucred, &p->p_acflag) ) 1135 error = EPERM; 1136 else 1137 mp->mp_openflags = *((int *)data) & 1138 (TIOCFLAG_SOFTCAR | TIOCFLAG_CLOCAL | 1139 TIOCFLAG_CRTSCTS | TIOCFLAG_MDMBUF); 1140 break; 1141 1142 default: 1143 error = ENOTTY; 1144 } 1145 1146 return(error); 1147 } 1148 1149 /* 1150 * Stop output, e.g., for ^S or output flush. 1151 */ 1152 void 1153 mttystop(tp, flags) 1154 struct tty *tp; 1155 int flags; 1156 { 1157 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(tp->t_dev)]; 1158 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(tp->t_dev)]; 1159 int s; 1160 1161 s = spltty(); 1162 1163 if( ISSET(tp->t_state, TS_BUSY) ) { 1164 if( !ISSET(tp->t_state, TS_TTSTOP) ) 1165 SET(tp->t_state, TS_FLUSH); 1166 1167 /* 1168 * the transmit interrupt routine will disable transmit when it 1169 * notices that MTTYF_STOP has been set. 1170 */ 1171 SET(mp->mp_flags, MTTYF_STOP); 1172 } 1173 1174 splx(s); 1175 } 1176 1177 /* 1178 * Start output, after a stop. 1179 */ 1180 void 1181 mtty_start(tp) 1182 struct tty *tp; 1183 { 1184 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(tp->t_dev)]; 1185 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(tp->t_dev)]; 1186 int s; 1187 1188 s = spltty(); 1189 1190 /* we only need to do something if we are not already busy 1191 * or delaying or stopped 1192 */ 1193 if( !ISSET(tp->t_state, TS_TTSTOP | TS_TIMEOUT | TS_BUSY) ) { 1194 1195 /* if we are sleeping and output has drained below 1196 * low water mark, awaken 1197 */ 1198 if( tp->t_outq.c_cc <= tp->t_lowat ) { 1199 if( ISSET(tp->t_state, TS_ASLEEP) ) { 1200 CLR(tp->t_state, TS_ASLEEP); 1201 wakeup(&tp->t_outq); 1202 } 1203 1204 selwakeup(&tp->t_wsel); 1205 } 1206 1207 /* if something to send, start transmitting 1208 */ 1209 if( tp->t_outq.c_cc ) { 1210 mp->mp_txc = ndqb(&tp->t_outq, 0); 1211 mp->mp_txp = tp->t_outq.c_cf; 1212 SET(tp->t_state, TS_BUSY); 1213 cd1400_enable_transmitter(mp->mp_cd1400, mp->mp_channel); 1214 } 1215 } 1216 1217 splx(s); 1218 } 1219 1220 /* 1221 * set/get modem line status 1222 * 1223 * bits can be: TIOCM_DTR, TIOCM_RTS, TIOCM_CTS, TIOCM_CD, TIOCM_RI, TIOCM_DSR 1224 * 1225 * note that DTR and RTS lines are exchanged, and that DSR is 1226 * not available on the LC2+1Sp card (used as CD) 1227 * 1228 * only let them fiddle with RTS if CRTSCTS is not enabled 1229 */ 1230 int 1231 mtty_modem_control(mp, bits, howto) 1232 struct mtty_port *mp; 1233 int bits; 1234 int howto; 1235 { 1236 struct cd1400 *cd = mp->mp_cd1400; 1237 struct tty *tp = mp->mp_tty; 1238 int s, msvr; 1239 1240 s = spltty(); 1241 1242 cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel); 1243 1244 switch(howto) { 1245 case DMGET: /* get bits */ 1246 bits = 0; 1247 1248 bits |= TIOCM_LE; 1249 1250 msvr = cd1400_read_reg(cd, CD1400_MSVR1); 1251 if( msvr & CD1400_MSVR1_RTS ) bits |= TIOCM_DTR; 1252 1253 msvr = cd1400_read_reg(cd, CD1400_MSVR2); 1254 if( msvr & CD1400_MSVR2_DTR ) bits |= TIOCM_RTS; 1255 if( msvr & CD1400_MSVR2_CTS ) bits |= TIOCM_CTS; 1256 if( msvr & CD1400_MSVR2_RI ) bits |= TIOCM_RI; 1257 if( msvr & CD1400_MSVR2_DSR ) bits |= (cd->cd_parmode ? TIOCM_CD : TIOCM_DSR); 1258 if( msvr & CD1400_MSVR2_CD ) bits |= (cd->cd_parmode ? 0 : TIOCM_CD); 1259 1260 break; 1261 1262 case DMSET: /* reset bits */ 1263 if( !ISSET(tp->t_cflag, CRTSCTS) ) 1264 cd1400_write_reg(cd, CD1400_MSVR2, ((bits & TIOCM_RTS) ? CD1400_MSVR2_DTR : 0)); 1265 1266 cd1400_write_reg(cd, CD1400_MSVR1, ((bits & TIOCM_DTR) ? CD1400_MSVR1_RTS : 0)); 1267 1268 break; 1269 1270 case DMBIS: /* set bits */ 1271 if( (bits & TIOCM_RTS) && !ISSET(tp->t_cflag, CRTSCTS) ) 1272 cd1400_write_reg(cd, CD1400_MSVR2, CD1400_MSVR2_DTR); 1273 1274 if( bits & TIOCM_DTR ) 1275 cd1400_write_reg(cd, CD1400_MSVR1, CD1400_MSVR1_RTS); 1276 1277 break; 1278 1279 case DMBIC: /* clear bits */ 1280 if( (bits & TIOCM_RTS) && !ISSET(tp->t_cflag, CRTSCTS) ) 1281 cd1400_write_reg(cd, CD1400_MSVR2, 0); 1282 1283 if( bits & TIOCM_DTR ) 1284 cd1400_write_reg(cd, CD1400_MSVR1, 0); 1285 1286 break; 1287 } 1288 1289 splx(s); 1290 return(bits); 1291 } 1292 1293 /* 1294 * Set tty parameters, returns error or 0 on success 1295 */ 1296 int 1297 mtty_param(tp, t) 1298 struct tty *tp; 1299 struct termios *t; 1300 { 1301 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(tp->t_dev)]; 1302 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(tp->t_dev)]; 1303 struct cd1400 *cd = mp->mp_cd1400; 1304 int rbpr, tbpr, rcor, tcor; 1305 u_char mcor1 = 0, mcor2 = 0; 1306 int s, opt; 1307 1308 if( t->c_ospeed && cd1400_compute_baud(t->c_ospeed, cd->cd_clock, &tcor, &tbpr) ) 1309 return(EINVAL); 1310 1311 if( t->c_ispeed && cd1400_compute_baud(t->c_ispeed, cd->cd_clock, &rcor, &rbpr) ) 1312 return(EINVAL); 1313 1314 s = spltty(); 1315 1316 /* hang up the line if ospeed is zero, else raise DTR */ 1317 (void)mtty_modem_control(mp, TIOCM_DTR, (t->c_ospeed == 0 ? DMBIC : DMBIS)); 1318 1319 /* select channel, done in mtty_modem_control() */ 1320 /* cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel); */ 1321 1322 /* set transmit speed */ 1323 if( t->c_ospeed ) { 1324 cd1400_write_reg(cd, CD1400_TCOR, tcor); 1325 cd1400_write_reg(cd, CD1400_TBPR, tbpr); 1326 } 1327 1328 /* set receive speed */ 1329 if( t->c_ispeed ) { 1330 cd1400_write_reg(cd, CD1400_RCOR, rcor); 1331 cd1400_write_reg(cd, CD1400_RBPR, rbpr); 1332 } 1333 1334 /* enable transmitting and receiving on this channel */ 1335 opt = CD1400_CCR_CMDCHANCTL | CD1400_CCR_XMTEN | CD1400_CCR_RCVEN; 1336 cd1400_write_ccr(cd, opt); 1337 1338 /* set parity, data and stop bits */ 1339 opt = 0; 1340 if( ISSET(t->c_cflag, PARENB) ) 1341 opt |= (ISSET(t->c_cflag, PARODD) ? CD1400_COR1_PARODD : CD1400_COR1_PARNORMAL); 1342 1343 if( !ISSET(t->c_iflag, INPCK) ) 1344 opt |= CD1400_COR1_NOINPCK; /* no parity checking */ 1345 1346 if( ISSET(t->c_cflag, CSTOPB) ) 1347 opt |= CD1400_COR1_STOP2; 1348 1349 switch( t->c_cflag & CSIZE ) { 1350 case CS5: 1351 opt |= CD1400_COR1_CS5; 1352 break; 1353 1354 case CS6: 1355 opt |= CD1400_COR1_CS6; 1356 break; 1357 1358 case CS7: 1359 opt |= CD1400_COR1_CS7; 1360 break; 1361 1362 default: 1363 opt |= CD1400_COR1_CS8; 1364 break; 1365 } 1366 1367 cd1400_write_reg(cd, CD1400_COR1, opt); 1368 1369 /* 1370 * enable Embedded Transmit Commands (for breaks) 1371 * use the CD1400 automatic CTS flow control if CRTSCTS is set 1372 */ 1373 opt = CD1400_COR2_ETC; 1374 if( ISSET(t->c_cflag, CRTSCTS) ) opt |= CD1400_COR2_CCTS_OFLOW; 1375 cd1400_write_reg(cd, CD1400_COR2, opt); 1376 1377 cd1400_write_reg(cd, CD1400_COR3, MTTY_RX_FIFO_THRESHOLD); 1378 1379 cd1400_write_ccr(cd, CD1400_CCR_CMDCORCHG | CD1400_CCR_COR1 | CD1400_CCR_COR2 | CD1400_CCR_COR3); 1380 1381 cd1400_write_reg(cd, CD1400_COR4, CD1400_COR4_PFO_EXCEPTION); 1382 cd1400_write_reg(cd, CD1400_COR5, 0); 1383 1384 /* 1385 * if automatic RTS handshaking enabled, set DTR threshold 1386 * (RTS and DTR lines are switched, CD1400 thinks its DTR) 1387 */ 1388 if( ISSET(t->c_cflag, CRTSCTS) ) 1389 mcor1 = MTTY_RX_DTR_THRESHOLD; 1390 1391 /* set up `carrier detect' interrupts */ 1392 if( cd->cd_parmode ) { 1393 SET(mcor1, CD1400_MCOR1_DSRzd); 1394 SET(mcor2, CD1400_MCOR2_DSRod); 1395 } else { 1396 SET(mcor1, CD1400_MCOR1_CDzd); 1397 SET(mcor2, CD1400_MCOR2_CDod); 1398 } 1399 1400 cd1400_write_reg(cd, CD1400_MCOR1, mcor1); 1401 cd1400_write_reg(cd, CD1400_MCOR2, mcor2); 1402 1403 /* receive timeout 2ms */ 1404 cd1400_write_reg(cd, CD1400_RTPR, 2); 1405 1406 splx(s); 1407 return(0); 1408 } 1409 1410 /************************************************************************ 1411 * 1412 * MBPP Routines 1413 * 1414 * mbpp_match match one mbpp device 1415 * mbpp_attach attach mbpp devices 1416 * mbppopen open mbpp device 1417 * mbppclose close mbpp device 1418 * mbppread read from mbpp 1419 * mbppwrite write to mbpp 1420 * mbppioctl do ioctl on mbpp 1421 * mbppselect do select on mbpp 1422 * mbpp_rw general rw routine 1423 * mbpp_timeout rw timeout 1424 * mbpp_start rw start after delay 1425 * mbpp_send send data 1426 * mbpp_recv recv data 1427 */ 1428 1429 int 1430 mbpp_match(parent, cf, args) 1431 struct device *parent; 1432 struct cfdata *cf; 1433 void *args; 1434 { 1435 struct magma_softc *sc = (struct magma_softc *)parent; 1436 1437 return( args == mbpp_match && sc->ms_board->mb_npar && sc->ms_mbpp == NULL ); 1438 } 1439 1440 void 1441 mbpp_attach(parent, dev, args) 1442 struct device *parent; 1443 struct device *dev; 1444 void *args; 1445 { 1446 struct magma_softc *sc = (struct magma_softc *)parent; 1447 struct mbpp_softc *ms = (struct mbpp_softc *)dev; 1448 struct mbpp_port *mp; 1449 int port; 1450 1451 sc->ms_mbpp = ms; 1452 dprintf((" addr %p", ms)); 1453 1454 for( port = 0 ; port < sc->ms_board->mb_npar ; port++ ) { 1455 mp = &ms->ms_port[port]; 1456 1457 callout_init(&mp->mp_timeout_ch); 1458 callout_init(&mp->mp_start_ch); 1459 1460 if( sc->ms_ncd1190 ) 1461 mp->mp_cd1190 = &sc->ms_cd1190[port]; 1462 else 1463 mp->mp_cd1400 = &sc->ms_cd1400[0]; 1464 } 1465 1466 ms->ms_nports = port; 1467 printf(": %d port%s\n", port, port == 1 ? "" : "s"); 1468 } 1469 1470 /* 1471 * open routine. returns zero if successful, else error code 1472 */ 1473 int 1474 mbppopen(dev, flags, mode, p) 1475 dev_t dev; 1476 int flags; 1477 int mode; 1478 struct proc *p; 1479 { 1480 int card = MAGMA_CARD(dev); 1481 int port = MAGMA_PORT(dev); 1482 struct mbpp_softc *ms; 1483 struct mbpp_port *mp; 1484 int s; 1485 1486 if( card >= mbpp_cd.cd_ndevs || 1487 (ms = mbpp_cd.cd_devs[card]) == NULL || port >= ms->ms_nports ) 1488 return(ENXIO); 1489 1490 mp = &ms->ms_port[port]; 1491 1492 s = spltty(); 1493 if( ISSET(mp->mp_flags, MBPPF_OPEN) ) { 1494 splx(s); 1495 return(EBUSY); 1496 } 1497 SET(mp->mp_flags, MBPPF_OPEN); 1498 splx(s); 1499 1500 /* set defaults */ 1501 mp->mp_burst = MBPP_BURST; 1502 mp->mp_timeout = mbpp_mstohz(MBPP_TIMEOUT); 1503 mp->mp_delay = mbpp_mstohz(MBPP_DELAY); 1504 1505 /* init chips */ 1506 if( mp->mp_cd1400 ) { /* CD1400 */ 1507 struct cd1400 *cd = mp->mp_cd1400; 1508 1509 /* set up CD1400 channel */ 1510 s = spltty(); 1511 cd1400_write_reg(cd, CD1400_CAR, 0); 1512 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET); 1513 cd1400_write_reg(cd, CD1400_LIVR, (1<<3)); 1514 splx(s); 1515 } else { /* CD1190 */ 1516 mp->mp_flags = 0; 1517 return (ENXIO); 1518 } 1519 1520 return (0); 1521 } 1522 1523 /* 1524 * close routine. returns zero if successful, else error code 1525 */ 1526 int 1527 mbppclose(dev, flag, mode, p) 1528 dev_t dev; 1529 int flag; 1530 int mode; 1531 struct proc *p; 1532 { 1533 struct mbpp_softc *ms = mbpp_cd.cd_devs[MAGMA_CARD(dev)]; 1534 struct mbpp_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1535 1536 mp->mp_flags = 0; 1537 return(0); 1538 } 1539 1540 /* 1541 * Read routine 1542 */ 1543 int 1544 mbppread(dev, uio, flags) 1545 dev_t dev; 1546 struct uio *uio; 1547 int flags; 1548 { 1549 1550 return( mbpp_rw(dev, uio) ); 1551 } 1552 1553 /* 1554 * Write routine 1555 */ 1556 int 1557 mbppwrite(dev, uio, flags) 1558 dev_t dev; 1559 struct uio *uio; 1560 int flags; 1561 { 1562 1563 return( mbpp_rw(dev, uio) ); 1564 } 1565 1566 /* 1567 * ioctl routine 1568 */ 1569 int 1570 mbppioctl(dev, cmd, data, flags, p) 1571 dev_t dev; 1572 u_long cmd; 1573 caddr_t data; 1574 int flags; 1575 struct proc *p; 1576 { 1577 struct mbpp_softc *ms = mbpp_cd.cd_devs[MAGMA_CARD(dev)]; 1578 struct mbpp_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1579 struct mbpp_param *bp; 1580 int error = 0; 1581 int s; 1582 1583 switch(cmd) { 1584 case MBPPIOCSPARAM: 1585 bp = (struct mbpp_param *)data; 1586 if( bp->bp_burst < MBPP_BURST_MIN || bp->bp_burst > MBPP_BURST_MAX || 1587 bp->bp_delay < MBPP_DELAY_MIN || bp->bp_delay > MBPP_DELAY_MIN ) { 1588 error = EINVAL; 1589 } else { 1590 mp->mp_burst = bp->bp_burst; 1591 mp->mp_timeout = mbpp_mstohz(bp->bp_timeout); 1592 mp->mp_delay = mbpp_mstohz(bp->bp_delay); 1593 } 1594 break; 1595 case MBPPIOCGPARAM: 1596 bp = (struct mbpp_param *)data; 1597 bp->bp_burst = mp->mp_burst; 1598 bp->bp_timeout = mbpp_hztoms(mp->mp_timeout); 1599 bp->bp_delay = mbpp_hztoms(mp->mp_delay); 1600 break; 1601 case MBPPIOCGSTAT: 1602 /* XXX make this more generic */ 1603 s = spltty(); 1604 cd1400_write_reg(mp->mp_cd1400, CD1400_CAR, 0); 1605 *(int *)data = cd1400_read_reg(mp->mp_cd1400, CD1400_PSVR); 1606 splx(s); 1607 break; 1608 default: 1609 error = ENOTTY; 1610 } 1611 1612 return(error); 1613 } 1614 1615 /* 1616 * poll routine 1617 */ 1618 int 1619 mbpppoll(dev, rw, p) 1620 dev_t dev; 1621 int rw; 1622 struct proc *p; 1623 { 1624 1625 return(ENODEV); 1626 } 1627 1628 int 1629 mbpp_rw(dev, uio) 1630 dev_t dev; 1631 struct uio *uio; 1632 { 1633 int card = MAGMA_CARD(dev); 1634 int port = MAGMA_PORT(dev); 1635 struct mbpp_softc *ms = mbpp_cd.cd_devs[card]; 1636 struct mbpp_port *mp = &ms->ms_port[port]; 1637 caddr_t buffer, ptr; 1638 int buflen, cnt, len; 1639 int s, error = 0; 1640 int gotdata = 0; 1641 1642 if( uio->uio_resid == 0 ) 1643 return(0); 1644 1645 buflen = min(uio->uio_resid, mp->mp_burst); 1646 buffer = malloc(buflen, M_DEVBUF, M_WAITOK); 1647 if( buffer == NULL ) 1648 return(ENOMEM); 1649 1650 SET(mp->mp_flags, MBPPF_UIO); 1651 1652 /* 1653 * start timeout, if needed 1654 */ 1655 if( mp->mp_timeout > 0 ) { 1656 SET(mp->mp_flags, MBPPF_TIMEOUT); 1657 callout_reset(&mp->mp_timeout_ch, mp->mp_timeout, 1658 mbpp_timeout, mp); 1659 } 1660 1661 len = cnt = 0; 1662 while( uio->uio_resid > 0 ) { 1663 len = min(buflen, uio->uio_resid); 1664 ptr = buffer; 1665 1666 if( uio->uio_rw == UIO_WRITE ) { 1667 error = uiomove(ptr, len, uio); 1668 if( error ) break; 1669 } 1670 again: /* goto bad */ 1671 /* timed out? */ 1672 if( !ISSET(mp->mp_flags, MBPPF_UIO) ) 1673 break; 1674 1675 /* 1676 * perform the operation 1677 */ 1678 if( uio->uio_rw == UIO_WRITE ) { 1679 cnt = mbpp_send(mp, ptr, len); 1680 } else { 1681 cnt = mbpp_recv(mp, ptr, len); 1682 } 1683 1684 if( uio->uio_rw == UIO_READ ) { 1685 if( cnt ) { 1686 error = uiomove(ptr, cnt, uio); 1687 if( error ) break; 1688 gotdata++; 1689 } 1690 else if( gotdata ) /* consider us done */ 1691 break; 1692 } 1693 1694 /* timed out? */ 1695 if( !ISSET(mp->mp_flags, MBPPF_UIO) ) 1696 break; 1697 1698 /* 1699 * poll delay? 1700 */ 1701 if( mp->mp_delay > 0 ) { 1702 s = splsoftclock(); 1703 SET(mp->mp_flags, MBPPF_DELAY); 1704 callout_reset(&mp->mp_start_ch, mp->mp_delay, 1705 mbpp_start, mp); 1706 error = tsleep(mp, PCATCH | PZERO, "mbppdelay", 0); 1707 splx(s); 1708 if( error ) break; 1709 } 1710 1711 /* 1712 * don't call uiomove again until we used all the data we grabbed 1713 */ 1714 if( uio->uio_rw == UIO_WRITE && cnt != len ) { 1715 ptr += cnt; 1716 len -= cnt; 1717 cnt = 0; 1718 goto again; 1719 } 1720 } 1721 1722 /* 1723 * clear timeouts 1724 */ 1725 s = splsoftclock(); 1726 if( ISSET(mp->mp_flags, MBPPF_TIMEOUT) ) { 1727 callout_stop(&mp->mp_timeout_ch); 1728 CLR(mp->mp_flags, MBPPF_TIMEOUT); 1729 } 1730 if( ISSET(mp->mp_flags, MBPPF_DELAY) ) { 1731 callout_stop(&mp->mp_start_ch); 1732 CLR(mp->mp_flags, MBPPF_DELAY); 1733 } 1734 splx(s); 1735 1736 /* 1737 * adjust for those chars that we uiomoved but never actually wrote 1738 */ 1739 if( uio->uio_rw == UIO_WRITE && cnt != len ) { 1740 uio->uio_resid += (len - cnt); 1741 } 1742 1743 free(buffer, M_DEVBUF); 1744 return(error); 1745 } 1746 1747 void 1748 mbpp_timeout(arg) 1749 void *arg; 1750 { 1751 struct mbpp_port *mp = arg; 1752 1753 CLR(mp->mp_flags, MBPPF_UIO | MBPPF_TIMEOUT); 1754 wakeup(mp); 1755 } 1756 1757 void 1758 mbpp_start(arg) 1759 void *arg; 1760 { 1761 struct mbpp_port *mp = arg; 1762 1763 CLR(mp->mp_flags, MBPPF_DELAY); 1764 wakeup(mp); 1765 } 1766 1767 int 1768 mbpp_send(mp, ptr, len) 1769 struct mbpp_port *mp; 1770 caddr_t ptr; 1771 int len; 1772 { 1773 int s; 1774 struct cd1400 *cd = mp->mp_cd1400; 1775 1776 /* set up io information */ 1777 mp->mp_ptr = ptr; 1778 mp->mp_cnt = len; 1779 1780 /* start transmitting */ 1781 s = spltty(); 1782 if( cd ) { 1783 cd1400_write_reg(cd, CD1400_CAR, 0); 1784 1785 /* output strobe width ~1microsecond */ 1786 cd1400_write_reg(cd, CD1400_TBPR, 10); 1787 1788 /* enable channel */ 1789 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_XMTEN); 1790 cd1400_write_reg(cd, CD1400_SRER, CD1400_SRER_TXRDY); 1791 } 1792 1793 /* ZZzzz... */ 1794 tsleep(mp, PCATCH | PZERO, "mbpp_send", 0); 1795 1796 /* stop transmitting */ 1797 if( cd ) { 1798 cd1400_write_reg(cd, CD1400_CAR, 0); 1799 1800 /* disable transmitter */ 1801 cd1400_write_reg(cd, CD1400_SRER, 0); 1802 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_XMTDIS); 1803 1804 /* flush fifo */ 1805 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET | CD1400_CCR_FTF); 1806 } 1807 splx(s); 1808 1809 /* return number of chars sent */ 1810 return(len - mp->mp_cnt); 1811 } 1812 1813 int 1814 mbpp_recv(mp, ptr, len) 1815 struct mbpp_port *mp; 1816 caddr_t ptr; 1817 int len; 1818 { 1819 int s; 1820 struct cd1400 *cd = mp->mp_cd1400; 1821 1822 /* set up io information */ 1823 mp->mp_ptr = ptr; 1824 mp->mp_cnt = len; 1825 1826 /* start receiving */ 1827 s = spltty(); 1828 if( cd ) { 1829 int rcor, rbpr; 1830 1831 cd1400_write_reg(cd, CD1400_CAR, 0); 1832 1833 /* input strobe at 100kbaud (10microseconds) */ 1834 cd1400_compute_baud(100000, cd->cd_clock, &rcor, &rbpr); 1835 cd1400_write_reg(cd, CD1400_RCOR, rcor); 1836 cd1400_write_reg(cd, CD1400_RBPR, rbpr); 1837 1838 /* rx threshold */ 1839 cd1400_write_reg(cd, CD1400_COR3, MBPP_RX_FIFO_THRESHOLD); 1840 cd1400_write_ccr(cd, CD1400_CCR_CMDCORCHG | CD1400_CCR_COR3); 1841 1842 /* enable channel */ 1843 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_RCVEN); 1844 cd1400_write_reg(cd, CD1400_SRER, CD1400_SRER_RXDATA); 1845 } 1846 1847 /* ZZzzz... */ 1848 tsleep(mp, PCATCH | PZERO, "mbpp_recv", 0); 1849 1850 /* stop receiving */ 1851 if( cd ) { 1852 cd1400_write_reg(cd, CD1400_CAR, 0); 1853 1854 /* disable receiving */ 1855 cd1400_write_reg(cd, CD1400_SRER, 0); 1856 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_RCVDIS); 1857 } 1858 splx(s); 1859 1860 /* return number of chars received */ 1861 return(len - mp->mp_cnt); 1862 } 1863 1864 int 1865 mbpp_hztoms(h) 1866 int h; 1867 { 1868 int m = h; 1869 1870 if( m > 0 ) 1871 m = m * 1000 / hz; 1872 return(m); 1873 } 1874 1875 int 1876 mbpp_mstohz(m) 1877 int m; 1878 { 1879 int h = m; 1880 1881 if( h > 0 ) { 1882 h = h * hz / 1000; 1883 if( h == 0 ) 1884 h = 1000 / hz; 1885 } 1886 return(h); 1887 } 1888 1889 #endif /* NMAGMA */ 1890
Indexes created Tue Sep 23 14:10:03 GMT 2025