magma.c revision 1.15
1 /* $NetBSD: magma.c,v 1.15 2002/03/17 19:41:01 atatat Exp $ */ 2 /* 3 * magma.c 4 * 5 * Copyright (c) 1998 Iain Hibbert 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Iain Hibbert 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35 /* 36 * Driver for Magma SBus Serial/Parallel cards using the Cirrus Logic 37 * CD1400 & CD1190 chips 38 */ 39 40 #include <sys/cdefs.h> 41 __KERNEL_RCSID(0, "$NetBSD: magma.c,v 1.15 2002/03/17 19:41:01 atatat Exp $"); 42 43 #if 0 44 #define MAGMA_DEBUG 45 #endif 46 47 #include "magma.h" 48 #if NMAGMA > 0 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/proc.h> 53 #include <sys/device.h> 54 #include <sys/file.h> 55 #include <sys/ioctl.h> 56 #include <sys/malloc.h> 57 #include <sys/tty.h> 58 #include <sys/time.h> 59 #include <sys/kernel.h> 60 #include <sys/syslog.h> 61 #include <sys/conf.h> 62 #include <sys/errno.h> 63 64 #include <machine/bus.h> 65 #include <machine/intr.h> 66 #include <machine/autoconf.h> 67 #include <machine/conf.h> 68 69 #include <dev/sbus/sbusvar.h> 70 71 #include <dev/ic/cd1400reg.h> 72 #include <dev/ic/cd1190reg.h> 73 74 #include <dev/sbus/mbppio.h> 75 #include <dev/sbus/magmareg.h> 76 77 /* 78 * Select tty soft interrupt bit based on TTY ipl. (stole from zs.c) 79 */ 80 #if PIL_TTY == 1 81 # define IE_MSOFT IE_L1 82 #elif PIL_TTY == 4 83 # define IE_MSOFT IE_L4 84 #elif PIL_TTY == 6 85 # define IE_MSOFT IE_L6 86 #else 87 # error "no suitable software interrupt bit" 88 #endif 89 90 /* supported cards 91 * 92 * The table below lists the cards that this driver is likely to 93 * be able to support. 94 * 95 * Cards with parallel ports: except for the LC2+1Sp, they all use 96 * the CD1190 chip which I know nothing about. I've tried to leave 97 * hooks for it so it shouldn't be too hard to add support later. 98 * (I think somebody is working on this separately) 99 * 100 * Thanks to Bruce at Magma for telling me the hardware offsets. 101 */ 102 static struct magma_board_info supported_cards[] = { 103 { 104 "MAGMA_Sp", "MAGMA,4_Sp", "Magma 4 Sp", 4, 0, 105 1, 0xa000, 0xc000, 0xe000, { 0x8000, 0, 0, 0 }, 106 0, { 0, 0 } 107 }, 108 { 109 "MAGMA_Sp", "MAGMA,8_Sp", "Magma 8 Sp", 8, 0, 110 2, 0xa000, 0xc000, 0xe000, { 0x4000, 0x6000, 0, 0 }, 111 0, { 0, 0 } 112 }, 113 { 114 "MAGMA_Sp", "MAGMA,_8HS_Sp", "Magma Fast 8 Sp", 8, 0, 115 2, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0, 0 }, 116 0, { 0, 0 } 117 }, 118 { 119 "MAGMA_Sp", "MAGMA,_8SP_422", "Magma 8 Sp - 422", 8, 0, 120 2, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0, 0 }, 121 0, { 0, 0 } 122 }, 123 { 124 "MAGMA_Sp", "MAGMA,12_Sp", "Magma 12 Sp", 12, 0, 125 3, 0xa000, 0xc000, 0xe000, { 0x2000, 0x4000, 0x6000, 0 }, 126 0, { 0, 0 } 127 }, 128 { 129 "MAGMA_Sp", "MAGMA,16_Sp", "Magma 16 Sp", 16, 0, 130 4, 0xd000, 0xe000, 0xf000, { 0x8000, 0x9000, 0xa000, 0xb000 }, 131 0, { 0, 0 } 132 }, 133 { 134 "MAGMA_Sp", "MAGMA,16_Sp_2", "Magma 16 Sp", 16, 0, 135 4, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0xc000, 0xe000 }, 136 0, { 0, 0 } 137 }, 138 { 139 "MAGMA_Sp", "MAGMA,16HS_Sp", "Magma Fast 16 Sp", 16, 0, 140 4, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0xc000, 0xe000 }, 141 0, { 0, 0 } 142 }, 143 { 144 "MAGMA_Sp", "MAGMA,21_Sp", "Magma LC 2+1 Sp", 2, 1, 145 1, 0xa000, 0xc000, 0xe000, { 0x8000, 0, 0, 0 }, 146 0, { 0, 0 } 147 }, 148 { 149 "MAGMA_Sp", "MAGMA,21HS_Sp", "Magma 2+1 Sp", 2, 1, 150 1, 0xa000, 0xc000, 0xe000, { 0x4000, 0, 0, 0 }, 151 1, { 0x6000, 0 } 152 }, 153 { 154 "MAGMA_Sp", "MAGMA,41_Sp", "Magma 4+1 Sp", 4, 1, 155 1, 0xa000, 0xc000, 0xe000, { 0x4000, 0, 0, 0 }, 156 1, { 0x6000, 0 } 157 }, 158 { 159 "MAGMA_Sp", "MAGMA,82_Sp", "Magma 8+2 Sp", 8, 2, 160 2, 0xd000, 0xe000, 0xf000, { 0x8000, 0x9000, 0, 0 }, 161 2, { 0xa000, 0xb000 } 162 }, 163 { 164 "MAGMA_Sp", "MAGMA,P1_Sp", "Magma P1 Sp", 0, 1, 165 0, 0, 0, 0, { 0, 0, 0, 0 }, 166 1, { 0x8000, 0 } 167 }, 168 { 169 "MAGMA_Sp", "MAGMA,P2_Sp", "Magma P2 Sp", 0, 2, 170 0, 0, 0, 0, { 0, 0, 0, 0 }, 171 2, { 0x4000, 0x8000 } 172 }, 173 { 174 "MAGMA 2+1HS Sp", "", "Magma 2+1HS Sp", 2, 0, 175 1, 0xa000, 0xc000, 0xe000, { 0x4000, 0, 0, 0 }, 176 1, { 0x8000, 0 } 177 }, 178 { 179 NULL, NULL, NULL, 0, 0, 180 0, 0, 0, 0, { 0, 0, 0, 0 }, 181 0, { 0, 0 } 182 } 183 }; 184 185 /************************************************************************ 186 * 187 * Autoconfig Stuff 188 */ 189 190 struct cfattach magma_ca = { 191 sizeof(struct magma_softc), magma_match, magma_attach 192 }; 193 194 struct cfattach mtty_ca = { 195 sizeof(struct mtty_softc), mtty_match, mtty_attach 196 }; 197 198 struct cfattach mbpp_ca = { 199 sizeof(struct mbpp_softc), mbpp_match, mbpp_attach 200 }; 201 202 extern struct cfdriver mtty_cd; 203 extern struct cfdriver mbpp_cd; 204 205 /************************************************************************ 206 * 207 * CD1400 Routines 208 * 209 * cd1400_compute_baud calculate COR/BPR register values 210 * cd1400_write_ccr write a value to CD1400 ccr 211 * cd1400_read_reg read from a CD1400 register 212 * cd1400_write_reg write to a CD1400 register 213 * cd1400_enable_transmitter enable transmitting on CD1400 channel 214 */ 215 216 /* 217 * compute the bpr/cor pair for any baud rate 218 * returns 0 for success, 1 for failure 219 */ 220 int 221 cd1400_compute_baud(speed, clock, cor, bpr) 222 speed_t speed; 223 int clock; 224 int *cor, *bpr; 225 { 226 int c, co, br; 227 228 if( speed < 50 || speed > 150000 ) 229 return(1); 230 231 for( c = 0, co = 8 ; co <= 2048 ; co <<= 2, c++ ) { 232 br = ((clock * 1000000) + (co * speed) / 2) / (co * speed); 233 if( br < 0x100 ) { 234 *bpr = br; 235 *cor = c; 236 return(0); 237 } 238 } 239 240 return(1); 241 } 242 243 /* 244 * Write a CD1400 channel command, should have a timeout? 245 */ 246 __inline void 247 cd1400_write_ccr(cd, cmd) 248 struct cd1400 *cd; 249 u_char cmd; 250 { 251 while( cd1400_read_reg(cd, CD1400_CCR) ) 252 ; 253 254 cd1400_write_reg(cd, CD1400_CCR, cmd); 255 } 256 257 /* 258 * read a value from a cd1400 register 259 */ 260 __inline u_char 261 cd1400_read_reg(cd, reg) 262 struct cd1400 *cd; 263 int reg; 264 { 265 return(cd->cd_reg[reg]); 266 } 267 268 /* 269 * write a value to a cd1400 register 270 */ 271 __inline void 272 cd1400_write_reg(cd, reg, value) 273 struct cd1400 *cd; 274 int reg; 275 u_char value; 276 { 277 cd->cd_reg[reg] = value; 278 } 279 280 /* 281 * enable transmit service requests for cd1400 channel 282 */ 283 void 284 cd1400_enable_transmitter(cd, channel) 285 struct cd1400 *cd; 286 int channel; 287 { 288 int s, srer; 289 290 s = spltty(); 291 cd1400_write_reg(cd, CD1400_CAR, channel); 292 srer = cd1400_read_reg(cd, CD1400_SRER); 293 SET(srer, CD1400_SRER_TXRDY); 294 cd1400_write_reg(cd, CD1400_SRER, srer); 295 splx(s); 296 } 297 298 /************************************************************************ 299 * 300 * CD1190 Routines 301 */ 302 303 /* well, there are none yet */ 304 305 /************************************************************************ 306 * 307 * Magma Routines 308 * 309 * magma_match reports if we have a magma board available 310 * magma_attach attaches magma boards to the sbus 311 * magma_hard hardware level interrupt routine 312 * magma_soft software level interrupt routine 313 */ 314 315 int 316 magma_match(parent, cf, aux) 317 struct device *parent; 318 struct cfdata *cf; 319 void *aux; 320 { 321 struct sbus_attach_args *sa = aux; 322 struct magma_board_info *card; 323 324 /* See if we support this device */ 325 for (card = supported_cards; ; card++) { 326 if (card->mb_sbusname == NULL) 327 /* End of table: no match */ 328 return (0); 329 if (strcmp(sa->sa_name, card->mb_sbusname) == 0) 330 break; 331 } 332 333 dprintf(("magma: matched `%s'\n", sa->sa_name)); 334 dprintf(("magma: magma_prom `%s'\n", 335 PROM_getpropstring(sa->sa_node, "magma_prom"))); 336 dprintf(("magma: intlevels `%s'\n", 337 PROM_getpropstring(sa->sa_node, "intlevels"))); 338 dprintf(("magma: chiprev `%s'\n", 339 PROM_getpropstring(sa->sa_node, "chiprev"))); 340 dprintf(("magma: clock `%s'\n", 341 PROM_getpropstring(sa->sa_node, "clock"))); 342 343 return (1); 344 } 345 346 void 347 magma_attach(parent, self, aux) 348 struct device *parent; 349 struct device *self; 350 void *aux; 351 { 352 struct sbus_attach_args *sa = aux; 353 struct magma_softc *sc = (struct magma_softc *)self; 354 struct magma_board_info *card; 355 bus_space_handle_t bh; 356 char *magma_prom, *clockstr; 357 int cd_clock; 358 int node, chip; 359 360 node = sa->sa_node; 361 362 /* 363 * Find the card model. 364 * Older models all have sbus node name `MAGMA_Sp' (see 365 * `supported_cards[]' above), and must be distinguished 366 * by the `magma_prom' property. 367 */ 368 magma_prom = PROM_getpropstring(node, "magma_prom"); 369 370 for (card = supported_cards; card->mb_name != NULL; card++) { 371 if (strcmp(sa->sa_name, card->mb_sbusname) != 0) 372 /* Sbus node name doesn't match */ 373 continue; 374 if (strcmp(magma_prom, card->mb_name) == 0) 375 /* Model name match */ 376 break; 377 } 378 379 if( card->mb_name == NULL ) { 380 printf(": %s (unsupported)\n", magma_prom); 381 return; 382 } 383 384 dprintf((" addr %p", sc)); 385 printf(" softpri %d: %s\n", PIL_TTY, card->mb_realname); 386 387 sc->ms_board = card; 388 sc->ms_ncd1400 = card->mb_ncd1400; 389 sc->ms_ncd1190 = card->mb_ncd1190; 390 391 if (sbus_bus_map(sa->sa_bustag, 392 sa->sa_slot, sa->sa_offset, sa->sa_size, 393 BUS_SPACE_MAP_LINEAR, &bh) != 0) { 394 printf("%s @ sbus: cannot map registers\n", self->dv_xname); 395 return; 396 } 397 398 /* the SVCACK* lines are daisychained */ 399 sc->ms_svcackr = (caddr_t)bh + card->mb_svcackr; 400 sc->ms_svcackt = (caddr_t)bh + card->mb_svcackt; 401 sc->ms_svcackm = (caddr_t)bh + card->mb_svcackm; 402 403 /* 404 * Find the clock speed; it's the same for all CD1400 chips 405 * on the board. 406 */ 407 clockstr = PROM_getpropstring(node, "clock"); 408 if (*clockstr == '\0') 409 /* Default to 25MHz */ 410 cd_clock = 25; 411 else { 412 cd_clock = 0; 413 while (*clockstr != '\0') 414 cd_clock = (cd_clock * 10) + (*clockstr++ - '0'); 415 } 416 417 /* init the cd1400 chips */ 418 for( chip = 0 ; chip < card->mb_ncd1400 ; chip++ ) { 419 struct cd1400 *cd = &sc->ms_cd1400[chip]; 420 421 cd->cd_clock = cd_clock; 422 cd->cd_reg = (caddr_t)bh + card->mb_cd1400[chip]; 423 424 /* PROM_getpropstring(node, "chiprev"); */ 425 /* seemingly the Magma drivers just ignore the propstring */ 426 cd->cd_chiprev = cd1400_read_reg(cd, CD1400_GFRCR); 427 428 dprintf(("%s attach CD1400 %d addr %p rev %x clock %dMhz\n", 429 sc->ms_dev.dv_xname, chip, 430 cd->cd_reg, cd->cd_chiprev, cd->cd_clock)); 431 432 /* clear GFRCR */ 433 cd1400_write_reg(cd, CD1400_GFRCR, 0x00); 434 435 /* reset whole chip */ 436 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET | CD1400_CCR_FULLRESET); 437 438 /* wait for revision code to be restored */ 439 while( cd1400_read_reg(cd, CD1400_GFRCR) != cd->cd_chiprev ) 440 ; 441 442 /* set the Prescaler Period Register to tick at 1ms */ 443 cd1400_write_reg(cd, CD1400_PPR, 444 ((cd->cd_clock * 1000000 / CD1400_PPR_PRESCALER + 500) / 1000)); 445 446 /* The LC2+1Sp card is the only card that doesn't have 447 * a CD1190 for the parallel port, but uses channel 0 of 448 * the CD1400, so we make a note of it for later and set up 449 * the CD1400 for parallel mode operation. 450 */ 451 if( card->mb_npar && card->mb_ncd1190 == 0 ) { 452 cd1400_write_reg(cd, CD1400_GCR, CD1400_GCR_PARALLEL); 453 cd->cd_parmode = 1; 454 } 455 } 456 457 /* init the cd1190 chips */ 458 for( chip = 0 ; chip < card->mb_ncd1190 ; chip++ ) { 459 struct cd1190 *cd = &sc->ms_cd1190[chip]; 460 461 cd->cd_reg = (caddr_t)bh + card->mb_cd1190[chip]; 462 463 /* XXX don't know anything about these chips yet */ 464 printf("%s: CD1190 %d addr %p (unsupported)\n", 465 self->dv_xname, chip, cd->cd_reg); 466 } 467 468 sbus_establish(&sc->ms_sd, &sc->ms_dev); 469 470 /* configure the children */ 471 (void)config_found(self, mtty_match, NULL); 472 (void)config_found(self, mbpp_match, NULL); 473 474 /* 475 * Establish the interrupt handlers. 476 */ 477 if (sa->sa_nintr == 0) 478 return; /* No interrupts to service!? */ 479 480 (void)bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_TTY, 481 0, magma_hard, sc); 482 (void)bus_intr_establish(sa->sa_bustag, PIL_TTY, IPL_SOFTSERIAL, 483 BUS_INTR_ESTABLISH_SOFTINTR, 484 magma_soft, sc); 485 evcnt_attach_dynamic(&sc->ms_intrcnt, EVCNT_TYPE_INTR, NULL, 486 sc->ms_dev.dv_xname, "intr"); 487 } 488 489 /* 490 * hard interrupt routine 491 * 492 * returns 1 if it handled it, otherwise 0 493 * 494 * runs at interrupt priority 495 */ 496 int 497 magma_hard(arg) 498 void *arg; 499 { 500 struct magma_softc *sc = arg; 501 struct cd1400 *cd; 502 int chip, status = 0; 503 int serviced = 0; 504 int needsoftint = 0; 505 506 /* 507 * check status of all the CD1400 chips 508 */ 509 for( chip = 0 ; chip < sc->ms_ncd1400 ; chip++ ) 510 status |= cd1400_read_reg(&sc->ms_cd1400[chip], CD1400_SVRR); 511 512 if( ISSET(status, CD1400_SVRR_RXRDY) ) { 513 u_char rivr = *sc->ms_svcackr; /* enter rx service context */ 514 int port = rivr >> 4; 515 516 if( rivr & (1<<3) ) { /* parallel port */ 517 struct mbpp_port *mbpp; 518 int n_chars; 519 520 mbpp = &sc->ms_mbpp->ms_port[port]; 521 cd = mbpp->mp_cd1400; 522 523 /* don't think we have to handle exceptions */ 524 n_chars = cd1400_read_reg(cd, CD1400_RDCR); 525 while (n_chars--) { 526 if( mbpp->mp_cnt == 0 ) { 527 SET(mbpp->mp_flags, MBPPF_WAKEUP); 528 needsoftint = 1; 529 break; 530 } 531 *mbpp->mp_ptr = cd1400_read_reg(cd,CD1400_RDSR); 532 mbpp->mp_ptr++; 533 mbpp->mp_cnt--; 534 } 535 } else { /* serial port */ 536 struct mtty_port *mtty; 537 u_char *ptr, n_chars, line_stat; 538 539 mtty = &sc->ms_mtty->ms_port[port]; 540 cd = mtty->mp_cd1400; 541 542 if( ISSET(rivr, CD1400_RIVR_EXCEPTION) ) { 543 line_stat = cd1400_read_reg(cd, CD1400_RDSR); 544 n_chars = 1; 545 } else { /* no exception, received data OK */ 546 line_stat = 0; 547 n_chars = cd1400_read_reg(cd, CD1400_RDCR); 548 } 549 550 ptr = mtty->mp_rput; 551 while( n_chars-- ) { 552 *ptr++ = line_stat; 553 *ptr++ = cd1400_read_reg(cd, CD1400_RDSR); 554 if( ptr == mtty->mp_rend ) ptr = mtty->mp_rbuf; 555 if( ptr == mtty->mp_rget ) { 556 if( ptr == mtty->mp_rbuf ) 557 ptr = mtty->mp_rend; 558 ptr -= 2; 559 SET(mtty->mp_flags, MTTYF_RING_OVERFLOW); 560 break; 561 } 562 } 563 mtty->mp_rput = ptr; 564 565 needsoftint = 1; 566 } 567 568 cd1400_write_reg(cd, CD1400_EOSRR, 0); /* end service context */ 569 serviced = 1; 570 } /* if(rx_service...) */ 571 572 if( ISSET(status, CD1400_SVRR_MDMCH) ) { 573 u_char mivr = *sc->ms_svcackm; /* enter mdm service context */ 574 int port = mivr >> 4; 575 struct mtty_port *mtty; 576 int carrier; 577 u_char msvr; 578 579 /* 580 * Handle CD (LC2+1Sp = DSR) changes. 581 */ 582 mtty = &sc->ms_mtty->ms_port[port]; 583 cd = mtty->mp_cd1400; 584 msvr = cd1400_read_reg(cd, CD1400_MSVR2); 585 carrier = ISSET(msvr, cd->cd_parmode ? CD1400_MSVR2_DSR : CD1400_MSVR2_CD); 586 587 if( mtty->mp_carrier != carrier ) { 588 SET(mtty->mp_flags, MTTYF_CARRIER_CHANGED); 589 mtty->mp_carrier = carrier; 590 needsoftint = 1; 591 } 592 593 cd1400_write_reg(cd, CD1400_EOSRR, 0); /* end service context */ 594 serviced = 1; 595 } /* if(mdm_service...) */ 596 597 if( ISSET(status, CD1400_SVRR_TXRDY) ) { 598 u_char tivr = *sc->ms_svcackt; /* enter tx service context */ 599 int port = tivr >> 4; 600 601 if( tivr & (1<<3) ) { /* parallel port */ 602 struct mbpp_port *mbpp; 603 604 mbpp = &sc->ms_mbpp->ms_port[port]; 605 cd = mbpp->mp_cd1400; 606 607 if( mbpp->mp_cnt ) { 608 int count = 0; 609 610 /* fill the fifo */ 611 while (mbpp->mp_cnt && 612 count++ < CD1400_PAR_FIFO_SIZE) { 613 cd1400_write_reg(cd, CD1400_TDR, 614 *mbpp->mp_ptr); 615 mbpp->mp_ptr++; 616 mbpp->mp_cnt--; 617 } 618 } else { 619 /* 620 * fifo is empty and we got no more data 621 * to send, so shut off interrupts and 622 * signal for a wakeup, which can't be 623 * done here in case we beat mbpp_send to 624 * the tsleep call (we are running at >spltty) 625 */ 626 cd1400_write_reg(cd, CD1400_SRER, 0); 627 SET(mbpp->mp_flags, MBPPF_WAKEUP); 628 needsoftint = 1; 629 } 630 } else { /* serial port */ 631 struct mtty_port *mtty; 632 struct tty *tp; 633 634 mtty = &sc->ms_mtty->ms_port[port]; 635 cd = mtty->mp_cd1400; 636 tp = mtty->mp_tty; 637 638 if( !ISSET(mtty->mp_flags, MTTYF_STOP) ) { 639 int count = 0; 640 641 /* check if we should start/stop a break */ 642 if( ISSET(mtty->mp_flags, MTTYF_SET_BREAK) ) { 643 cd1400_write_reg(cd, CD1400_TDR, 0); 644 cd1400_write_reg(cd, CD1400_TDR, 0x81); 645 /* should we delay too? */ 646 CLR(mtty->mp_flags, MTTYF_SET_BREAK); 647 count += 2; 648 } 649 650 if( ISSET(mtty->mp_flags, MTTYF_CLR_BREAK) ) { 651 cd1400_write_reg(cd, CD1400_TDR, 0); 652 cd1400_write_reg(cd, CD1400_TDR, 0x83); 653 CLR(mtty->mp_flags, MTTYF_CLR_BREAK); 654 count += 2; 655 } 656 657 /* I don't quite fill the fifo in case the last one is a 658 * NULL which I have to double up because its the escape 659 * code for embedded transmit characters. 660 */ 661 while( mtty->mp_txc > 0 && count < CD1400_TX_FIFO_SIZE - 1 ) { 662 u_char ch; 663 664 ch = *mtty->mp_txp; 665 666 mtty->mp_txc--; 667 mtty->mp_txp++; 668 669 if( ch == 0 ) { 670 cd1400_write_reg(cd, CD1400_TDR, ch); 671 count++; 672 } 673 674 cd1400_write_reg(cd, CD1400_TDR, ch); 675 count++; 676 } 677 } 678 679 /* if we ran out of work or are requested to STOP then 680 * shut off the txrdy interrupts and signal DONE to flush 681 * out the chars we have sent. 682 */ 683 if( mtty->mp_txc == 0 || ISSET(mtty->mp_flags, MTTYF_STOP) ) { 684 register int srer; 685 686 srer = cd1400_read_reg(cd, CD1400_SRER); 687 CLR(srer, CD1400_SRER_TXRDY); 688 cd1400_write_reg(cd, CD1400_SRER, srer); 689 CLR(mtty->mp_flags, MTTYF_STOP); 690 691 SET(mtty->mp_flags, MTTYF_DONE); 692 needsoftint = 1; 693 } 694 } 695 696 cd1400_write_reg(cd, CD1400_EOSRR, 0); /* end service context */ 697 serviced = 1; 698 } /* if(tx_service...) */ 699 700 /* XXX service CD1190 interrupts too 701 for( chip = 0 ; chip < sc->ms_ncd1190 ; chip++ ) { 702 } 703 */ 704 705 if( needsoftint ) { /* trigger the soft interrupt */ 706 #if defined(SUN4M) 707 if( CPU_ISSUN4M ) 708 raise(0, PIL_TTY); 709 else 710 #endif 711 ienab_bis(IE_MSOFT); 712 } 713 714 return(serviced); 715 } 716 717 /* 718 * magma soft interrupt handler 719 * 720 * returns 1 if it handled it, 0 otherwise 721 * 722 * runs at spltty() 723 */ 724 int 725 magma_soft(arg) 726 void *arg; 727 { 728 struct magma_softc *sc = arg; 729 struct mtty_softc *mtty = sc->ms_mtty; 730 struct mbpp_softc *mbpp = sc->ms_mbpp; 731 int port; 732 int serviced = 0; 733 int s, flags; 734 735 if (mtty == NULL) 736 goto chkbpp; 737 738 /* 739 * check the tty ports to see what needs doing 740 */ 741 for( port = 0 ; port < mtty->ms_nports ; port++ ) { 742 struct mtty_port *mp = &mtty->ms_port[port]; 743 struct tty *tp = mp->mp_tty; 744 745 if( !ISSET(tp->t_state, TS_ISOPEN) ) 746 continue; 747 748 /* 749 * handle any received data 750 */ 751 while( mp->mp_rget != mp->mp_rput ) { 752 u_char stat; 753 int data; 754 755 stat = mp->mp_rget[0]; 756 data = mp->mp_rget[1]; 757 mp->mp_rget = ((mp->mp_rget + 2) == mp->mp_rend) 758 ? mp->mp_rbuf : (mp->mp_rget + 2); 759 760 if( stat & (CD1400_RDSR_BREAK | CD1400_RDSR_FE) ) 761 data |= TTY_FE; 762 if( stat & CD1400_RDSR_PE ) 763 data |= TTY_PE; 764 765 if( stat & CD1400_RDSR_OE ) 766 log(LOG_WARNING, "%s%x: fifo overflow\n", 767 mtty->ms_dev.dv_xname, port); 768 769 (*tp->t_linesw->l_rint)(data, tp); 770 serviced = 1; 771 } 772 773 s = splhigh(); /* block out hard interrupt routine */ 774 flags = mp->mp_flags; 775 CLR(mp->mp_flags, MTTYF_DONE | MTTYF_CARRIER_CHANGED | MTTYF_RING_OVERFLOW); 776 splx(s); /* ok */ 777 778 if( ISSET(flags, MTTYF_CARRIER_CHANGED) ) { 779 dprintf(("%s%x: cd %s\n", mtty->ms_dev.dv_xname, 780 port, mp->mp_carrier ? "on" : "off")); 781 (*tp->t_linesw->l_modem)(tp, mp->mp_carrier); 782 serviced = 1; 783 } 784 785 if( ISSET(flags, MTTYF_RING_OVERFLOW) ) { 786 log(LOG_WARNING, "%s%x: ring buffer overflow\n", 787 mtty->ms_dev.dv_xname, port); 788 serviced = 1; 789 } 790 791 if( ISSET(flags, MTTYF_DONE) ) { 792 ndflush(&tp->t_outq, mp->mp_txp - tp->t_outq.c_cf); 793 CLR(tp->t_state, TS_BUSY); 794 (*tp->t_linesw->l_start)(tp); /* might be some more */ 795 serviced = 1; 796 } 797 } /* for(each mtty...) */ 798 799 800 chkbpp: 801 /* 802 * Check the bpp ports (if any) to see what needs doing 803 */ 804 if (mbpp == NULL) 805 return (serviced); 806 807 for( port = 0 ; port < mbpp->ms_nports ; port++ ) { 808 struct mbpp_port *mp = &mbpp->ms_port[port]; 809 810 if( !ISSET(mp->mp_flags, MBPPF_OPEN) ) 811 continue; 812 813 s = splhigh(); 814 flags = mp->mp_flags; 815 CLR(mp->mp_flags, MBPPF_WAKEUP); 816 splx(s); 817 818 if( ISSET(flags, MBPPF_WAKEUP) ) { 819 wakeup(mp); 820 serviced = 1; 821 } 822 823 } /* for(each mbpp...) */ 824 825 return(serviced); 826 } 827 828 /************************************************************************ 829 * 830 * MTTY Routines 831 * 832 * mtty_match match one mtty device 833 * mtty_attach attach mtty devices 834 * mttyopen open mtty device 835 * mttyclose close mtty device 836 * mttyread read from mtty 837 * mttywrite write to mtty 838 * mttyioctl do ioctl on mtty 839 * mttytty return tty pointer for mtty 840 * mttystop stop mtty device 841 * mtty_start start mtty device 842 * mtty_param set mtty parameters 843 * mtty_modem_control set modem control lines 844 */ 845 846 int 847 mtty_match(parent, cf, args) 848 struct device *parent; 849 struct cfdata *cf; 850 void *args; 851 { 852 struct magma_softc *sc = (struct magma_softc *)parent; 853 854 return( args == mtty_match && sc->ms_board->mb_nser && sc->ms_mtty == NULL ); 855 } 856 857 void 858 mtty_attach(parent, dev, args) 859 struct device *parent; 860 struct device *dev; 861 void *args; 862 { 863 struct magma_softc *sc = (struct magma_softc *)parent; 864 struct mtty_softc *ms = (struct mtty_softc *)dev; 865 int port, chip, chan; 866 867 sc->ms_mtty = ms; 868 dprintf((" addr %p", ms)); 869 870 for( port = 0, chip = 0, chan = 0 ; port < sc->ms_board->mb_nser ; port++ ) { 871 struct mtty_port *mp = &ms->ms_port[port]; 872 struct tty *tp; 873 874 mp->mp_cd1400 = &sc->ms_cd1400[chip]; 875 if (mp->mp_cd1400->cd_parmode && chan == 0) 876 chan = 1; /* skip channel 0 if parmode */ 877 mp->mp_channel = chan; 878 879 tp = ttymalloc(); 880 if (tp == NULL) break; 881 tty_attach(tp); 882 tp->t_oproc = mtty_start; 883 tp->t_param = mtty_param; 884 885 mp->mp_tty = tp; 886 887 mp->mp_rbuf = malloc(MTTY_RBUF_SIZE, M_DEVBUF, M_NOWAIT); 888 if (mp->mp_rbuf == NULL) break; 889 890 mp->mp_rend = mp->mp_rbuf + MTTY_RBUF_SIZE; 891 892 chan = (chan + 1) % CD1400_NO_OF_CHANNELS; 893 if (chan == 0) 894 chip++; 895 } 896 897 ms->ms_nports = port; 898 printf(": %d tty%s\n", port, port == 1 ? "" : "s"); 899 } 900 901 /* 902 * open routine. returns zero if successful, else error code 903 */ 904 int 905 mttyopen(dev, flags, mode, p) 906 dev_t dev; 907 int flags; 908 int mode; 909 struct proc *p; 910 { 911 int card = MAGMA_CARD(dev); 912 int port = MAGMA_PORT(dev); 913 struct mtty_softc *ms; 914 struct mtty_port *mp; 915 struct tty *tp; 916 struct cd1400 *cd; 917 int error, s; 918 919 if( card >= mtty_cd.cd_ndevs || 920 (ms = mtty_cd.cd_devs[card]) == NULL || port >= ms->ms_nports ) 921 return(ENXIO); /* device not configured */ 922 923 mp = &ms->ms_port[port]; 924 tp = mp->mp_tty; 925 tp->t_dev = dev; 926 927 if (ISSET(tp->t_state, TS_ISOPEN) && 928 ISSET(tp->t_state, TS_XCLUDE) && 929 p->p_ucred->cr_uid != 0) 930 return (EBUSY); 931 932 s = spltty(); 933 934 if( !ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 935 936 /* set defaults */ 937 ttychars(tp); 938 tp->t_iflag = TTYDEF_IFLAG; 939 tp->t_oflag = TTYDEF_OFLAG; 940 tp->t_cflag = TTYDEF_CFLAG; 941 if( ISSET(mp->mp_openflags, TIOCFLAG_CLOCAL) ) 942 SET(tp->t_cflag, CLOCAL); 943 if( ISSET(mp->mp_openflags, TIOCFLAG_CRTSCTS) ) 944 SET(tp->t_cflag, CRTSCTS); 945 if( ISSET(mp->mp_openflags, TIOCFLAG_MDMBUF) ) 946 SET(tp->t_cflag, MDMBUF); 947 tp->t_lflag = TTYDEF_LFLAG; 948 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 949 950 /* init ring buffer */ 951 mp->mp_rput = mp->mp_rget = mp->mp_rbuf; 952 953 /* reset CD1400 channel */ 954 cd = mp->mp_cd1400; 955 cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel); 956 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET); 957 958 /* encode the port number in top half of LIVR */ 959 cd1400_write_reg(cd, CD1400_LIVR, port << 4 ); 960 961 /* sets parameters and raises DTR */ 962 (void)mtty_param(tp, &tp->t_termios); 963 964 /* set tty watermarks */ 965 ttsetwater(tp); 966 967 /* enable service requests */ 968 cd1400_write_reg(cd, CD1400_SRER, 969 CD1400_SRER_RXDATA | CD1400_SRER_MDMCH); 970 971 /* tell the tty about the carrier status */ 972 if( ISSET(mp->mp_openflags, TIOCFLAG_SOFTCAR) || 973 mp->mp_carrier ) 974 SET(tp->t_state, TS_CARR_ON); 975 else 976 CLR(tp->t_state, TS_CARR_ON); 977 } 978 splx(s); 979 980 error = ttyopen(tp, MTTY_DIALOUT(dev), ISSET(flags, O_NONBLOCK)); 981 if (error != 0) 982 goto bad; 983 984 error = (*tp->t_linesw->l_open)(dev, tp); 985 if (error != 0) 986 goto bad; 987 988 bad: 989 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 990 /* 991 * We failed to open the device, and nobody else had it opened. 992 * Clean up the state as appropriate. 993 */ 994 /* XXX - do that here */ 995 } 996 997 return (error); 998 } 999 1000 /* 1001 * close routine. returns zero if successful, else error code 1002 */ 1003 int 1004 mttyclose(dev, flag, mode, p) 1005 dev_t dev; 1006 int flag; 1007 int mode; 1008 struct proc *p; 1009 { 1010 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(dev)]; 1011 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1012 struct tty *tp = mp->mp_tty; 1013 int s; 1014 1015 (*tp->t_linesw->l_close)(tp, flag); 1016 ttyclose(tp); 1017 1018 s = spltty(); 1019 1020 /* if HUPCL is set, and the tty is no longer open 1021 * shut down the port 1022 */ 1023 if( ISSET(tp->t_cflag, HUPCL) || !ISSET(tp->t_state, TS_ISOPEN) ) { 1024 /* XXX wait until FIFO is empty before turning off the channel 1025 struct cd1400 *cd = mp->mp_cd1400; 1026 */ 1027 1028 /* drop DTR and RTS */ 1029 (void)mtty_modem_control(mp, 0, DMSET); 1030 1031 /* turn off the channel 1032 cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel); 1033 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET); 1034 */ 1035 } 1036 1037 splx(s); 1038 1039 return(0); 1040 } 1041 1042 /* 1043 * Read routine 1044 */ 1045 int 1046 mttyread(dev, uio, flags) 1047 dev_t dev; 1048 struct uio *uio; 1049 int flags; 1050 { 1051 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(dev)]; 1052 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1053 struct tty *tp = mp->mp_tty; 1054 1055 return( (*tp->t_linesw->l_read)(tp, uio, flags) ); 1056 } 1057 1058 /* 1059 * Write routine 1060 */ 1061 int 1062 mttywrite(dev, uio, flags) 1063 dev_t dev; 1064 struct uio *uio; 1065 int flags; 1066 { 1067 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(dev)]; 1068 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1069 struct tty *tp = mp->mp_tty; 1070 1071 return( (*tp->t_linesw->l_write)(tp, uio, flags) ); 1072 } 1073 1074 /* 1075 * Poll routine 1076 */ 1077 int 1078 mttypoll(dev, events, p) 1079 dev_t dev; 1080 int events; 1081 struct proc *p; 1082 { 1083 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(dev)]; 1084 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1085 struct tty *tp = mp->mp_tty; 1086 1087 return ((*tp->t_linesw->l_poll)(tp, events, p)); 1088 } 1089 1090 /* 1091 * return tty pointer 1092 */ 1093 struct tty * 1094 mttytty(dev) 1095 dev_t dev; 1096 { 1097 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(dev)]; 1098 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1099 1100 return(mp->mp_tty); 1101 } 1102 1103 /* 1104 * ioctl routine 1105 */ 1106 int 1107 mttyioctl(dev, cmd, data, flags, p) 1108 dev_t dev; 1109 u_long cmd; 1110 caddr_t data; 1111 int flags; 1112 struct proc *p; 1113 { 1114 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(dev)]; 1115 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1116 struct tty *tp = mp->mp_tty; 1117 int error; 1118 1119 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flags, p); 1120 if( error != EPASSTHROUGH ) return(error); 1121 1122 error = ttioctl(tp, cmd, data, flags, p); 1123 if( error != EPASSTHROUGH ) return(error); 1124 1125 error = 0; 1126 1127 switch(cmd) { 1128 case TIOCSBRK: /* set break */ 1129 SET(mp->mp_flags, MTTYF_SET_BREAK); 1130 cd1400_enable_transmitter(mp->mp_cd1400, mp->mp_channel); 1131 break; 1132 1133 case TIOCCBRK: /* clear break */ 1134 SET(mp->mp_flags, MTTYF_CLR_BREAK); 1135 cd1400_enable_transmitter(mp->mp_cd1400, mp->mp_channel); 1136 break; 1137 1138 case TIOCSDTR: /* set DTR */ 1139 mtty_modem_control(mp, TIOCM_DTR, DMBIS); 1140 break; 1141 1142 case TIOCCDTR: /* clear DTR */ 1143 mtty_modem_control(mp, TIOCM_DTR, DMBIC); 1144 break; 1145 1146 case TIOCMSET: /* set modem lines */ 1147 mtty_modem_control(mp, *((int *)data), DMSET); 1148 break; 1149 1150 case TIOCMBIS: /* bit set modem lines */ 1151 mtty_modem_control(mp, *((int *)data), DMBIS); 1152 break; 1153 1154 case TIOCMBIC: /* bit clear modem lines */ 1155 mtty_modem_control(mp, *((int *)data), DMBIC); 1156 break; 1157 1158 case TIOCMGET: /* get modem lines */ 1159 *((int *)data) = mtty_modem_control(mp, 0, DMGET); 1160 break; 1161 1162 case TIOCGFLAGS: 1163 *((int *)data) = mp->mp_openflags; 1164 break; 1165 1166 case TIOCSFLAGS: 1167 if( suser(p->p_ucred, &p->p_acflag) ) 1168 error = EPERM; 1169 else 1170 mp->mp_openflags = *((int *)data) & 1171 (TIOCFLAG_SOFTCAR | TIOCFLAG_CLOCAL | 1172 TIOCFLAG_CRTSCTS | TIOCFLAG_MDMBUF); 1173 break; 1174 1175 default: 1176 error = EPASSTHROUGH; 1177 } 1178 1179 return(error); 1180 } 1181 1182 /* 1183 * Stop output, e.g., for ^S or output flush. 1184 */ 1185 void 1186 mttystop(tp, flags) 1187 struct tty *tp; 1188 int flags; 1189 { 1190 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(tp->t_dev)]; 1191 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(tp->t_dev)]; 1192 int s; 1193 1194 s = spltty(); 1195 1196 if( ISSET(tp->t_state, TS_BUSY) ) { 1197 if( !ISSET(tp->t_state, TS_TTSTOP) ) 1198 SET(tp->t_state, TS_FLUSH); 1199 1200 /* 1201 * the transmit interrupt routine will disable transmit when it 1202 * notices that MTTYF_STOP has been set. 1203 */ 1204 SET(mp->mp_flags, MTTYF_STOP); 1205 } 1206 1207 splx(s); 1208 } 1209 1210 /* 1211 * Start output, after a stop. 1212 */ 1213 void 1214 mtty_start(tp) 1215 struct tty *tp; 1216 { 1217 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(tp->t_dev)]; 1218 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(tp->t_dev)]; 1219 int s; 1220 1221 s = spltty(); 1222 1223 /* we only need to do something if we are not already busy 1224 * or delaying or stopped 1225 */ 1226 if( !ISSET(tp->t_state, TS_TTSTOP | TS_TIMEOUT | TS_BUSY) ) { 1227 1228 /* if we are sleeping and output has drained below 1229 * low water mark, awaken 1230 */ 1231 if( tp->t_outq.c_cc <= tp->t_lowat ) { 1232 if( ISSET(tp->t_state, TS_ASLEEP) ) { 1233 CLR(tp->t_state, TS_ASLEEP); 1234 wakeup(&tp->t_outq); 1235 } 1236 1237 selwakeup(&tp->t_wsel); 1238 } 1239 1240 /* if something to send, start transmitting 1241 */ 1242 if( tp->t_outq.c_cc ) { 1243 mp->mp_txc = ndqb(&tp->t_outq, 0); 1244 mp->mp_txp = tp->t_outq.c_cf; 1245 SET(tp->t_state, TS_BUSY); 1246 cd1400_enable_transmitter(mp->mp_cd1400, mp->mp_channel); 1247 } 1248 } 1249 1250 splx(s); 1251 } 1252 1253 /* 1254 * set/get modem line status 1255 * 1256 * bits can be: TIOCM_DTR, TIOCM_RTS, TIOCM_CTS, TIOCM_CD, TIOCM_RI, TIOCM_DSR 1257 * 1258 * note that DTR and RTS lines are exchanged, and that DSR is 1259 * not available on the LC2+1Sp card (used as CD) 1260 * 1261 * only let them fiddle with RTS if CRTSCTS is not enabled 1262 */ 1263 int 1264 mtty_modem_control(mp, bits, howto) 1265 struct mtty_port *mp; 1266 int bits; 1267 int howto; 1268 { 1269 struct cd1400 *cd = mp->mp_cd1400; 1270 struct tty *tp = mp->mp_tty; 1271 int s, msvr; 1272 1273 s = spltty(); 1274 1275 cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel); 1276 1277 switch(howto) { 1278 case DMGET: /* get bits */ 1279 bits = 0; 1280 1281 bits |= TIOCM_LE; 1282 1283 msvr = cd1400_read_reg(cd, CD1400_MSVR1); 1284 if( msvr & CD1400_MSVR1_RTS ) bits |= TIOCM_DTR; 1285 1286 msvr = cd1400_read_reg(cd, CD1400_MSVR2); 1287 if( msvr & CD1400_MSVR2_DTR ) bits |= TIOCM_RTS; 1288 if( msvr & CD1400_MSVR2_CTS ) bits |= TIOCM_CTS; 1289 if( msvr & CD1400_MSVR2_RI ) bits |= TIOCM_RI; 1290 if( msvr & CD1400_MSVR2_DSR ) bits |= (cd->cd_parmode ? TIOCM_CD : TIOCM_DSR); 1291 if( msvr & CD1400_MSVR2_CD ) bits |= (cd->cd_parmode ? 0 : TIOCM_CD); 1292 1293 break; 1294 1295 case DMSET: /* reset bits */ 1296 if( !ISSET(tp->t_cflag, CRTSCTS) ) 1297 cd1400_write_reg(cd, CD1400_MSVR2, ((bits & TIOCM_RTS) ? CD1400_MSVR2_DTR : 0)); 1298 1299 cd1400_write_reg(cd, CD1400_MSVR1, ((bits & TIOCM_DTR) ? CD1400_MSVR1_RTS : 0)); 1300 1301 break; 1302 1303 case DMBIS: /* set bits */ 1304 if( (bits & TIOCM_RTS) && !ISSET(tp->t_cflag, CRTSCTS) ) 1305 cd1400_write_reg(cd, CD1400_MSVR2, CD1400_MSVR2_DTR); 1306 1307 if( bits & TIOCM_DTR ) 1308 cd1400_write_reg(cd, CD1400_MSVR1, CD1400_MSVR1_RTS); 1309 1310 break; 1311 1312 case DMBIC: /* clear bits */ 1313 if( (bits & TIOCM_RTS) && !ISSET(tp->t_cflag, CRTSCTS) ) 1314 cd1400_write_reg(cd, CD1400_MSVR2, 0); 1315 1316 if( bits & TIOCM_DTR ) 1317 cd1400_write_reg(cd, CD1400_MSVR1, 0); 1318 1319 break; 1320 } 1321 1322 splx(s); 1323 return(bits); 1324 } 1325 1326 /* 1327 * Set tty parameters, returns error or 0 on success 1328 */ 1329 int 1330 mtty_param(tp, t) 1331 struct tty *tp; 1332 struct termios *t; 1333 { 1334 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(tp->t_dev)]; 1335 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(tp->t_dev)]; 1336 struct cd1400 *cd = mp->mp_cd1400; 1337 int rbpr, tbpr, rcor, tcor; 1338 u_char mcor1 = 0, mcor2 = 0; 1339 int s, opt; 1340 1341 if( t->c_ospeed && cd1400_compute_baud(t->c_ospeed, cd->cd_clock, &tcor, &tbpr) ) 1342 return(EINVAL); 1343 1344 if( t->c_ispeed && cd1400_compute_baud(t->c_ispeed, cd->cd_clock, &rcor, &rbpr) ) 1345 return(EINVAL); 1346 1347 s = spltty(); 1348 1349 /* hang up the line if ospeed is zero, else raise DTR */ 1350 (void)mtty_modem_control(mp, TIOCM_DTR, (t->c_ospeed == 0 ? DMBIC : DMBIS)); 1351 1352 /* select channel, done in mtty_modem_control() */ 1353 /* cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel); */ 1354 1355 /* set transmit speed */ 1356 if( t->c_ospeed ) { 1357 cd1400_write_reg(cd, CD1400_TCOR, tcor); 1358 cd1400_write_reg(cd, CD1400_TBPR, tbpr); 1359 } 1360 1361 /* set receive speed */ 1362 if( t->c_ispeed ) { 1363 cd1400_write_reg(cd, CD1400_RCOR, rcor); 1364 cd1400_write_reg(cd, CD1400_RBPR, rbpr); 1365 } 1366 1367 /* enable transmitting and receiving on this channel */ 1368 opt = CD1400_CCR_CMDCHANCTL | CD1400_CCR_XMTEN | CD1400_CCR_RCVEN; 1369 cd1400_write_ccr(cd, opt); 1370 1371 /* set parity, data and stop bits */ 1372 opt = 0; 1373 if( ISSET(t->c_cflag, PARENB) ) 1374 opt |= (ISSET(t->c_cflag, PARODD) ? CD1400_COR1_PARODD : CD1400_COR1_PARNORMAL); 1375 1376 if( !ISSET(t->c_iflag, INPCK) ) 1377 opt |= CD1400_COR1_NOINPCK; /* no parity checking */ 1378 1379 if( ISSET(t->c_cflag, CSTOPB) ) 1380 opt |= CD1400_COR1_STOP2; 1381 1382 switch( t->c_cflag & CSIZE ) { 1383 case CS5: 1384 opt |= CD1400_COR1_CS5; 1385 break; 1386 1387 case CS6: 1388 opt |= CD1400_COR1_CS6; 1389 break; 1390 1391 case CS7: 1392 opt |= CD1400_COR1_CS7; 1393 break; 1394 1395 default: 1396 opt |= CD1400_COR1_CS8; 1397 break; 1398 } 1399 1400 cd1400_write_reg(cd, CD1400_COR1, opt); 1401 1402 /* 1403 * enable Embedded Transmit Commands (for breaks) 1404 * use the CD1400 automatic CTS flow control if CRTSCTS is set 1405 */ 1406 opt = CD1400_COR2_ETC; 1407 if( ISSET(t->c_cflag, CRTSCTS) ) opt |= CD1400_COR2_CCTS_OFLOW; 1408 cd1400_write_reg(cd, CD1400_COR2, opt); 1409 1410 cd1400_write_reg(cd, CD1400_COR3, MTTY_RX_FIFO_THRESHOLD); 1411 1412 cd1400_write_ccr(cd, CD1400_CCR_CMDCORCHG | CD1400_CCR_COR1 | CD1400_CCR_COR2 | CD1400_CCR_COR3); 1413 1414 cd1400_write_reg(cd, CD1400_COR4, CD1400_COR4_PFO_EXCEPTION); 1415 cd1400_write_reg(cd, CD1400_COR5, 0); 1416 1417 /* 1418 * if automatic RTS handshaking enabled, set DTR threshold 1419 * (RTS and DTR lines are switched, CD1400 thinks its DTR) 1420 */ 1421 if( ISSET(t->c_cflag, CRTSCTS) ) 1422 mcor1 = MTTY_RX_DTR_THRESHOLD; 1423 1424 /* set up `carrier detect' interrupts */ 1425 if( cd->cd_parmode ) { 1426 SET(mcor1, CD1400_MCOR1_DSRzd); 1427 SET(mcor2, CD1400_MCOR2_DSRod); 1428 } else { 1429 SET(mcor1, CD1400_MCOR1_CDzd); 1430 SET(mcor2, CD1400_MCOR2_CDod); 1431 } 1432 1433 cd1400_write_reg(cd, CD1400_MCOR1, mcor1); 1434 cd1400_write_reg(cd, CD1400_MCOR2, mcor2); 1435 1436 /* receive timeout 2ms */ 1437 cd1400_write_reg(cd, CD1400_RTPR, 2); 1438 1439 splx(s); 1440 return(0); 1441 } 1442 1443 /************************************************************************ 1444 * 1445 * MBPP Routines 1446 * 1447 * mbpp_match match one mbpp device 1448 * mbpp_attach attach mbpp devices 1449 * mbppopen open mbpp device 1450 * mbppclose close mbpp device 1451 * mbppread read from mbpp 1452 * mbppwrite write to mbpp 1453 * mbppioctl do ioctl on mbpp 1454 * mbppselect do select on mbpp 1455 * mbpp_rw general rw routine 1456 * mbpp_timeout rw timeout 1457 * mbpp_start rw start after delay 1458 * mbpp_send send data 1459 * mbpp_recv recv data 1460 */ 1461 1462 int 1463 mbpp_match(parent, cf, args) 1464 struct device *parent; 1465 struct cfdata *cf; 1466 void *args; 1467 { 1468 struct magma_softc *sc = (struct magma_softc *)parent; 1469 1470 return( args == mbpp_match && sc->ms_board->mb_npar && sc->ms_mbpp == NULL ); 1471 } 1472 1473 void 1474 mbpp_attach(parent, dev, args) 1475 struct device *parent; 1476 struct device *dev; 1477 void *args; 1478 { 1479 struct magma_softc *sc = (struct magma_softc *)parent; 1480 struct mbpp_softc *ms = (struct mbpp_softc *)dev; 1481 struct mbpp_port *mp; 1482 int port; 1483 1484 sc->ms_mbpp = ms; 1485 dprintf((" addr %p", ms)); 1486 1487 for( port = 0 ; port < sc->ms_board->mb_npar ; port++ ) { 1488 mp = &ms->ms_port[port]; 1489 1490 callout_init(&mp->mp_timeout_ch); 1491 callout_init(&mp->mp_start_ch); 1492 1493 if( sc->ms_ncd1190 ) 1494 mp->mp_cd1190 = &sc->ms_cd1190[port]; 1495 else 1496 mp->mp_cd1400 = &sc->ms_cd1400[0]; 1497 } 1498 1499 ms->ms_nports = port; 1500 printf(": %d port%s\n", port, port == 1 ? "" : "s"); 1501 } 1502 1503 /* 1504 * open routine. returns zero if successful, else error code 1505 */ 1506 int 1507 mbppopen(dev, flags, mode, p) 1508 dev_t dev; 1509 int flags; 1510 int mode; 1511 struct proc *p; 1512 { 1513 int card = MAGMA_CARD(dev); 1514 int port = MAGMA_PORT(dev); 1515 struct mbpp_softc *ms; 1516 struct mbpp_port *mp; 1517 int s; 1518 1519 if( card >= mbpp_cd.cd_ndevs || 1520 (ms = mbpp_cd.cd_devs[card]) == NULL || port >= ms->ms_nports ) 1521 return(ENXIO); 1522 1523 mp = &ms->ms_port[port]; 1524 1525 s = spltty(); 1526 if( ISSET(mp->mp_flags, MBPPF_OPEN) ) { 1527 splx(s); 1528 return(EBUSY); 1529 } 1530 SET(mp->mp_flags, MBPPF_OPEN); 1531 splx(s); 1532 1533 /* set defaults */ 1534 mp->mp_burst = MBPP_BURST; 1535 mp->mp_timeout = mbpp_mstohz(MBPP_TIMEOUT); 1536 mp->mp_delay = mbpp_mstohz(MBPP_DELAY); 1537 1538 /* init chips */ 1539 if( mp->mp_cd1400 ) { /* CD1400 */ 1540 struct cd1400 *cd = mp->mp_cd1400; 1541 1542 /* set up CD1400 channel */ 1543 s = spltty(); 1544 cd1400_write_reg(cd, CD1400_CAR, 0); 1545 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET); 1546 cd1400_write_reg(cd, CD1400_LIVR, (1<<3)); 1547 splx(s); 1548 } else { /* CD1190 */ 1549 mp->mp_flags = 0; 1550 return (ENXIO); 1551 } 1552 1553 return (0); 1554 } 1555 1556 /* 1557 * close routine. returns zero if successful, else error code 1558 */ 1559 int 1560 mbppclose(dev, flag, mode, p) 1561 dev_t dev; 1562 int flag; 1563 int mode; 1564 struct proc *p; 1565 { 1566 struct mbpp_softc *ms = mbpp_cd.cd_devs[MAGMA_CARD(dev)]; 1567 struct mbpp_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1568 1569 mp->mp_flags = 0; 1570 return(0); 1571 } 1572 1573 /* 1574 * Read routine 1575 */ 1576 int 1577 mbppread(dev, uio, flags) 1578 dev_t dev; 1579 struct uio *uio; 1580 int flags; 1581 { 1582 1583 return( mbpp_rw(dev, uio) ); 1584 } 1585 1586 /* 1587 * Write routine 1588 */ 1589 int 1590 mbppwrite(dev, uio, flags) 1591 dev_t dev; 1592 struct uio *uio; 1593 int flags; 1594 { 1595 1596 return( mbpp_rw(dev, uio) ); 1597 } 1598 1599 /* 1600 * ioctl routine 1601 */ 1602 int 1603 mbppioctl(dev, cmd, data, flags, p) 1604 dev_t dev; 1605 u_long cmd; 1606 caddr_t data; 1607 int flags; 1608 struct proc *p; 1609 { 1610 struct mbpp_softc *ms = mbpp_cd.cd_devs[MAGMA_CARD(dev)]; 1611 struct mbpp_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1612 struct mbpp_param *bp; 1613 int error = 0; 1614 int s; 1615 1616 switch(cmd) { 1617 case MBPPIOCSPARAM: 1618 bp = (struct mbpp_param *)data; 1619 if( bp->bp_burst < MBPP_BURST_MIN || bp->bp_burst > MBPP_BURST_MAX || 1620 bp->bp_delay < MBPP_DELAY_MIN || bp->bp_delay > MBPP_DELAY_MIN ) { 1621 error = EINVAL; 1622 } else { 1623 mp->mp_burst = bp->bp_burst; 1624 mp->mp_timeout = mbpp_mstohz(bp->bp_timeout); 1625 mp->mp_delay = mbpp_mstohz(bp->bp_delay); 1626 } 1627 break; 1628 case MBPPIOCGPARAM: 1629 bp = (struct mbpp_param *)data; 1630 bp->bp_burst = mp->mp_burst; 1631 bp->bp_timeout = mbpp_hztoms(mp->mp_timeout); 1632 bp->bp_delay = mbpp_hztoms(mp->mp_delay); 1633 break; 1634 case MBPPIOCGSTAT: 1635 /* XXX make this more generic */ 1636 s = spltty(); 1637 cd1400_write_reg(mp->mp_cd1400, CD1400_CAR, 0); 1638 *(int *)data = cd1400_read_reg(mp->mp_cd1400, CD1400_PSVR); 1639 splx(s); 1640 break; 1641 default: 1642 error = ENOTTY; 1643 } 1644 1645 return(error); 1646 } 1647 1648 /* 1649 * poll routine 1650 */ 1651 int 1652 mbpppoll(dev, rw, p) 1653 dev_t dev; 1654 int rw; 1655 struct proc *p; 1656 { 1657 1658 return(ENODEV); 1659 } 1660 1661 int 1662 mbpp_rw(dev, uio) 1663 dev_t dev; 1664 struct uio *uio; 1665 { 1666 int card = MAGMA_CARD(dev); 1667 int port = MAGMA_PORT(dev); 1668 struct mbpp_softc *ms = mbpp_cd.cd_devs[card]; 1669 struct mbpp_port *mp = &ms->ms_port[port]; 1670 caddr_t buffer, ptr; 1671 int buflen, cnt, len; 1672 int s, error = 0; 1673 int gotdata = 0; 1674 1675 if( uio->uio_resid == 0 ) 1676 return(0); 1677 1678 buflen = min(uio->uio_resid, mp->mp_burst); 1679 buffer = malloc(buflen, M_DEVBUF, M_WAITOK); 1680 if( buffer == NULL ) 1681 return(ENOMEM); 1682 1683 SET(mp->mp_flags, MBPPF_UIO); 1684 1685 /* 1686 * start timeout, if needed 1687 */ 1688 if( mp->mp_timeout > 0 ) { 1689 SET(mp->mp_flags, MBPPF_TIMEOUT); 1690 callout_reset(&mp->mp_timeout_ch, mp->mp_timeout, 1691 mbpp_timeout, mp); 1692 } 1693 1694 len = cnt = 0; 1695 while( uio->uio_resid > 0 ) { 1696 len = min(buflen, uio->uio_resid); 1697 ptr = buffer; 1698 1699 if( uio->uio_rw == UIO_WRITE ) { 1700 error = uiomove(ptr, len, uio); 1701 if( error ) break; 1702 } 1703 again: /* goto bad */ 1704 /* timed out? */ 1705 if( !ISSET(mp->mp_flags, MBPPF_UIO) ) 1706 break; 1707 1708 /* 1709 * perform the operation 1710 */ 1711 if( uio->uio_rw == UIO_WRITE ) { 1712 cnt = mbpp_send(mp, ptr, len); 1713 } else { 1714 cnt = mbpp_recv(mp, ptr, len); 1715 } 1716 1717 if( uio->uio_rw == UIO_READ ) { 1718 if( cnt ) { 1719 error = uiomove(ptr, cnt, uio); 1720 if( error ) break; 1721 gotdata++; 1722 } 1723 else if( gotdata ) /* consider us done */ 1724 break; 1725 } 1726 1727 /* timed out? */ 1728 if( !ISSET(mp->mp_flags, MBPPF_UIO) ) 1729 break; 1730 1731 /* 1732 * poll delay? 1733 */ 1734 if( mp->mp_delay > 0 ) { 1735 s = splsoftclock(); 1736 SET(mp->mp_flags, MBPPF_DELAY); 1737 callout_reset(&mp->mp_start_ch, mp->mp_delay, 1738 mbpp_start, mp); 1739 error = tsleep(mp, PCATCH | PZERO, "mbppdelay", 0); 1740 splx(s); 1741 if( error ) break; 1742 } 1743 1744 /* 1745 * don't call uiomove again until we used all the data we grabbed 1746 */ 1747 if( uio->uio_rw == UIO_WRITE && cnt != len ) { 1748 ptr += cnt; 1749 len -= cnt; 1750 cnt = 0; 1751 goto again; 1752 } 1753 } 1754 1755 /* 1756 * clear timeouts 1757 */ 1758 s = splsoftclock(); 1759 if( ISSET(mp->mp_flags, MBPPF_TIMEOUT) ) { 1760 callout_stop(&mp->mp_timeout_ch); 1761 CLR(mp->mp_flags, MBPPF_TIMEOUT); 1762 } 1763 if( ISSET(mp->mp_flags, MBPPF_DELAY) ) { 1764 callout_stop(&mp->mp_start_ch); 1765 CLR(mp->mp_flags, MBPPF_DELAY); 1766 } 1767 splx(s); 1768 1769 /* 1770 * adjust for those chars that we uiomoved but never actually wrote 1771 */ 1772 if( uio->uio_rw == UIO_WRITE && cnt != len ) { 1773 uio->uio_resid += (len - cnt); 1774 } 1775 1776 free(buffer, M_DEVBUF); 1777 return(error); 1778 } 1779 1780 void 1781 mbpp_timeout(arg) 1782 void *arg; 1783 { 1784 struct mbpp_port *mp = arg; 1785 1786 CLR(mp->mp_flags, MBPPF_UIO | MBPPF_TIMEOUT); 1787 wakeup(mp); 1788 } 1789 1790 void 1791 mbpp_start(arg) 1792 void *arg; 1793 { 1794 struct mbpp_port *mp = arg; 1795 1796 CLR(mp->mp_flags, MBPPF_DELAY); 1797 wakeup(mp); 1798 } 1799 1800 int 1801 mbpp_send(mp, ptr, len) 1802 struct mbpp_port *mp; 1803 caddr_t ptr; 1804 int len; 1805 { 1806 int s; 1807 struct cd1400 *cd = mp->mp_cd1400; 1808 1809 /* set up io information */ 1810 mp->mp_ptr = ptr; 1811 mp->mp_cnt = len; 1812 1813 /* start transmitting */ 1814 s = spltty(); 1815 if( cd ) { 1816 cd1400_write_reg(cd, CD1400_CAR, 0); 1817 1818 /* output strobe width ~1microsecond */ 1819 cd1400_write_reg(cd, CD1400_TBPR, 10); 1820 1821 /* enable channel */ 1822 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_XMTEN); 1823 cd1400_write_reg(cd, CD1400_SRER, CD1400_SRER_TXRDY); 1824 } 1825 1826 /* ZZzzz... */ 1827 tsleep(mp, PCATCH | PZERO, "mbpp_send", 0); 1828 1829 /* stop transmitting */ 1830 if( cd ) { 1831 cd1400_write_reg(cd, CD1400_CAR, 0); 1832 1833 /* disable transmitter */ 1834 cd1400_write_reg(cd, CD1400_SRER, 0); 1835 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_XMTDIS); 1836 1837 /* flush fifo */ 1838 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET | CD1400_CCR_FTF); 1839 } 1840 splx(s); 1841 1842 /* return number of chars sent */ 1843 return(len - mp->mp_cnt); 1844 } 1845 1846 int 1847 mbpp_recv(mp, ptr, len) 1848 struct mbpp_port *mp; 1849 caddr_t ptr; 1850 int len; 1851 { 1852 int s; 1853 struct cd1400 *cd = mp->mp_cd1400; 1854 1855 /* set up io information */ 1856 mp->mp_ptr = ptr; 1857 mp->mp_cnt = len; 1858 1859 /* start receiving */ 1860 s = spltty(); 1861 if( cd ) { 1862 int rcor, rbpr; 1863 1864 cd1400_write_reg(cd, CD1400_CAR, 0); 1865 1866 /* input strobe at 100kbaud (10microseconds) */ 1867 cd1400_compute_baud(100000, cd->cd_clock, &rcor, &rbpr); 1868 cd1400_write_reg(cd, CD1400_RCOR, rcor); 1869 cd1400_write_reg(cd, CD1400_RBPR, rbpr); 1870 1871 /* rx threshold */ 1872 cd1400_write_reg(cd, CD1400_COR3, MBPP_RX_FIFO_THRESHOLD); 1873 cd1400_write_ccr(cd, CD1400_CCR_CMDCORCHG | CD1400_CCR_COR3); 1874 1875 /* enable channel */ 1876 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_RCVEN); 1877 cd1400_write_reg(cd, CD1400_SRER, CD1400_SRER_RXDATA); 1878 } 1879 1880 /* ZZzzz... */ 1881 tsleep(mp, PCATCH | PZERO, "mbpp_recv", 0); 1882 1883 /* stop receiving */ 1884 if( cd ) { 1885 cd1400_write_reg(cd, CD1400_CAR, 0); 1886 1887 /* disable receiving */ 1888 cd1400_write_reg(cd, CD1400_SRER, 0); 1889 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_RCVDIS); 1890 } 1891 splx(s); 1892 1893 /* return number of chars received */ 1894 return(len - mp->mp_cnt); 1895 } 1896 1897 int 1898 mbpp_hztoms(h) 1899 int h; 1900 { 1901 int m = h; 1902 1903 if( m > 0 ) 1904 m = m * 1000 / hz; 1905 return(m); 1906 } 1907 1908 int 1909 mbpp_mstohz(m) 1910 int m; 1911 { 1912 int h = m; 1913 1914 if( h > 0 ) { 1915 h = h * hz / 1000; 1916 if( h == 0 ) 1917 h = 1000 / hz; 1918 } 1919 return(h); 1920 } 1921 1922 #endif /* NMAGMA */ 1923
Indexes created Tue Sep 23 14:10:03 GMT 2025