magma.c revision 1.16
1 /* $NetBSD: magma.c,v 1.16 2002/03/21 00:18:36 eeh Exp $ */ 2 /* 3 * magma.c 4 * 5 * Copyright (c) 1998 Iain Hibbert 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Iain Hibbert 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35 /* 36 * Driver for Magma SBus Serial/Parallel cards using the Cirrus Logic 37 * CD1400 & CD1190 chips 38 */ 39 40 #include <sys/cdefs.h> 41 __KERNEL_RCSID(0, "$NetBSD: magma.c,v 1.16 2002/03/21 00:18:36 eeh Exp $"); 42 43 #if 0 44 #define MAGMA_DEBUG 45 #endif 46 47 #include "magma.h" 48 #if NMAGMA > 0 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/proc.h> 53 #include <sys/device.h> 54 #include <sys/file.h> 55 #include <sys/ioctl.h> 56 #include <sys/malloc.h> 57 #include <sys/tty.h> 58 #include <sys/time.h> 59 #include <sys/kernel.h> 60 #include <sys/syslog.h> 61 #include <sys/conf.h> 62 #include <sys/errno.h> 63 64 #include <machine/bus.h> 65 #include <machine/intr.h> 66 #include <machine/autoconf.h> 67 #include <machine/conf.h> 68 69 #include <dev/sbus/sbusvar.h> 70 71 #include <dev/ic/cd1400reg.h> 72 #include <dev/ic/cd1190reg.h> 73 74 #include <dev/sbus/mbppio.h> 75 #include <dev/sbus/magmareg.h> 76 77 /* 78 * Select tty soft interrupt bit based on TTY ipl. (stole from zs.c) 79 */ 80 #if PIL_TTY == 1 81 # define IE_MSOFT IE_L1 82 #elif PIL_TTY == 4 83 # define IE_MSOFT IE_L4 84 #elif PIL_TTY == 6 85 # define IE_MSOFT IE_L6 86 #else 87 # error "no suitable software interrupt bit" 88 #endif 89 90 /* supported cards 91 * 92 * The table below lists the cards that this driver is likely to 93 * be able to support. 94 * 95 * Cards with parallel ports: except for the LC2+1Sp, they all use 96 * the CD1190 chip which I know nothing about. I've tried to leave 97 * hooks for it so it shouldn't be too hard to add support later. 98 * (I think somebody is working on this separately) 99 * 100 * Thanks to Bruce at Magma for telling me the hardware offsets. 101 */ 102 static struct magma_board_info supported_cards[] = { 103 { 104 "MAGMA_Sp", "MAGMA,4_Sp", "Magma 4 Sp", 4, 0, 105 1, 0xa000, 0xc000, 0xe000, { 0x8000, 0, 0, 0 }, 106 0, { 0, 0 } 107 }, 108 { 109 "MAGMA_Sp", "MAGMA,8_Sp", "Magma 8 Sp", 8, 0, 110 2, 0xa000, 0xc000, 0xe000, { 0x4000, 0x6000, 0, 0 }, 111 0, { 0, 0 } 112 }, 113 { 114 "MAGMA_Sp", "MAGMA,_8HS_Sp", "Magma Fast 8 Sp", 8, 0, 115 2, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0, 0 }, 116 0, { 0, 0 } 117 }, 118 { 119 "MAGMA_Sp", "MAGMA,_8SP_422", "Magma 8 Sp - 422", 8, 0, 120 2, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0, 0 }, 121 0, { 0, 0 } 122 }, 123 { 124 "MAGMA_Sp", "MAGMA,12_Sp", "Magma 12 Sp", 12, 0, 125 3, 0xa000, 0xc000, 0xe000, { 0x2000, 0x4000, 0x6000, 0 }, 126 0, { 0, 0 } 127 }, 128 { 129 "MAGMA_Sp", "MAGMA,16_Sp", "Magma 16 Sp", 16, 0, 130 4, 0xd000, 0xe000, 0xf000, { 0x8000, 0x9000, 0xa000, 0xb000 }, 131 0, { 0, 0 } 132 }, 133 { 134 "MAGMA_Sp", "MAGMA,16_Sp_2", "Magma 16 Sp", 16, 0, 135 4, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0xc000, 0xe000 }, 136 0, { 0, 0 } 137 }, 138 { 139 "MAGMA_Sp", "MAGMA,16HS_Sp", "Magma Fast 16 Sp", 16, 0, 140 4, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0xc000, 0xe000 }, 141 0, { 0, 0 } 142 }, 143 { 144 "MAGMA_Sp", "MAGMA,21_Sp", "Magma LC 2+1 Sp", 2, 1, 145 1, 0xa000, 0xc000, 0xe000, { 0x8000, 0, 0, 0 }, 146 0, { 0, 0 } 147 }, 148 { 149 "MAGMA_Sp", "MAGMA,21HS_Sp", "Magma 2+1 Sp", 2, 1, 150 1, 0xa000, 0xc000, 0xe000, { 0x4000, 0, 0, 0 }, 151 1, { 0x6000, 0 } 152 }, 153 { 154 "MAGMA_Sp", "MAGMA,41_Sp", "Magma 4+1 Sp", 4, 1, 155 1, 0xa000, 0xc000, 0xe000, { 0x4000, 0, 0, 0 }, 156 1, { 0x6000, 0 } 157 }, 158 { 159 "MAGMA_Sp", "MAGMA,82_Sp", "Magma 8+2 Sp", 8, 2, 160 2, 0xd000, 0xe000, 0xf000, { 0x8000, 0x9000, 0, 0 }, 161 2, { 0xa000, 0xb000 } 162 }, 163 { 164 "MAGMA_Sp", "MAGMA,P1_Sp", "Magma P1 Sp", 0, 1, 165 0, 0, 0, 0, { 0, 0, 0, 0 }, 166 1, { 0x8000, 0 } 167 }, 168 { 169 "MAGMA_Sp", "MAGMA,P2_Sp", "Magma P2 Sp", 0, 2, 170 0, 0, 0, 0, { 0, 0, 0, 0 }, 171 2, { 0x4000, 0x8000 } 172 }, 173 { 174 "MAGMA 2+1HS Sp", "", "Magma 2+1HS Sp", 2, 0, 175 1, 0xa000, 0xc000, 0xe000, { 0x4000, 0, 0, 0 }, 176 1, { 0x8000, 0 } 177 }, 178 { 179 NULL, NULL, NULL, 0, 0, 180 0, 0, 0, 0, { 0, 0, 0, 0 }, 181 0, { 0, 0 } 182 } 183 }; 184 185 /************************************************************************ 186 * 187 * Autoconfig Stuff 188 */ 189 190 struct cfattach magma_ca = { 191 sizeof(struct magma_softc), magma_match, magma_attach 192 }; 193 194 struct cfattach mtty_ca = { 195 sizeof(struct mtty_softc), mtty_match, mtty_attach 196 }; 197 198 struct cfattach mbpp_ca = { 199 sizeof(struct mbpp_softc), mbpp_match, mbpp_attach 200 }; 201 202 extern struct cfdriver mtty_cd; 203 extern struct cfdriver mbpp_cd; 204 205 /************************************************************************ 206 * 207 * CD1400 Routines 208 * 209 * cd1400_compute_baud calculate COR/BPR register values 210 * cd1400_write_ccr write a value to CD1400 ccr 211 * cd1400_read_reg read from a CD1400 register 212 * cd1400_write_reg write to a CD1400 register 213 * cd1400_enable_transmitter enable transmitting on CD1400 channel 214 */ 215 216 /* 217 * compute the bpr/cor pair for any baud rate 218 * returns 0 for success, 1 for failure 219 */ 220 int 221 cd1400_compute_baud(speed, clock, cor, bpr) 222 speed_t speed; 223 int clock; 224 int *cor, *bpr; 225 { 226 int c, co, br; 227 228 if( speed < 50 || speed > 150000 ) 229 return(1); 230 231 for( c = 0, co = 8 ; co <= 2048 ; co <<= 2, c++ ) { 232 br = ((clock * 1000000) + (co * speed) / 2) / (co * speed); 233 if( br < 0x100 ) { 234 *bpr = br; 235 *cor = c; 236 return(0); 237 } 238 } 239 240 return(1); 241 } 242 243 /* 244 * Write a CD1400 channel command, should have a timeout? 245 */ 246 __inline void 247 cd1400_write_ccr(cd, cmd) 248 struct cd1400 *cd; 249 u_char cmd; 250 { 251 while( cd1400_read_reg(cd, CD1400_CCR) ) 252 ; 253 254 cd1400_write_reg(cd, CD1400_CCR, cmd); 255 } 256 257 /* 258 * read a value from a cd1400 register 259 */ 260 __inline u_char 261 cd1400_read_reg(cd, reg) 262 struct cd1400 *cd; 263 int reg; 264 { 265 return(cd->cd_reg[reg]); 266 } 267 268 /* 269 * write a value to a cd1400 register 270 */ 271 __inline void 272 cd1400_write_reg(cd, reg, value) 273 struct cd1400 *cd; 274 int reg; 275 u_char value; 276 { 277 cd->cd_reg[reg] = value; 278 } 279 280 /* 281 * enable transmit service requests for cd1400 channel 282 */ 283 void 284 cd1400_enable_transmitter(cd, channel) 285 struct cd1400 *cd; 286 int channel; 287 { 288 int s, srer; 289 290 s = spltty(); 291 cd1400_write_reg(cd, CD1400_CAR, channel); 292 srer = cd1400_read_reg(cd, CD1400_SRER); 293 SET(srer, CD1400_SRER_TXRDY); 294 cd1400_write_reg(cd, CD1400_SRER, srer); 295 splx(s); 296 } 297 298 /************************************************************************ 299 * 300 * CD1190 Routines 301 */ 302 303 /* well, there are none yet */ 304 305 /************************************************************************ 306 * 307 * Magma Routines 308 * 309 * magma_match reports if we have a magma board available 310 * magma_attach attaches magma boards to the sbus 311 * magma_hard hardware level interrupt routine 312 * magma_soft software level interrupt routine 313 */ 314 315 int 316 magma_match(parent, cf, aux) 317 struct device *parent; 318 struct cfdata *cf; 319 void *aux; 320 { 321 struct sbus_attach_args *sa = aux; 322 struct magma_board_info *card; 323 324 /* See if we support this device */ 325 for (card = supported_cards; ; card++) { 326 if (card->mb_sbusname == NULL) 327 /* End of table: no match */ 328 return (0); 329 if (strcmp(sa->sa_name, card->mb_sbusname) == 0) 330 break; 331 } 332 333 dprintf(("magma: matched `%s'\n", sa->sa_name)); 334 dprintf(("magma: magma_prom `%s'\n", 335 PROM_getpropstring(sa->sa_node, "magma_prom"))); 336 dprintf(("magma: intlevels `%s'\n", 337 PROM_getpropstring(sa->sa_node, "intlevels"))); 338 dprintf(("magma: chiprev `%s'\n", 339 PROM_getpropstring(sa->sa_node, "chiprev"))); 340 dprintf(("magma: clock `%s'\n", 341 PROM_getpropstring(sa->sa_node, "clock"))); 342 343 return (1); 344 } 345 346 void 347 magma_attach(parent, self, aux) 348 struct device *parent; 349 struct device *self; 350 void *aux; 351 { 352 struct sbus_attach_args *sa = aux; 353 struct magma_softc *sc = (struct magma_softc *)self; 354 struct magma_board_info *card; 355 bus_space_handle_t bh; 356 char *magma_prom, *clockstr; 357 int cd_clock; 358 int node, chip; 359 360 node = sa->sa_node; 361 362 /* 363 * Find the card model. 364 * Older models all have sbus node name `MAGMA_Sp' (see 365 * `supported_cards[]' above), and must be distinguished 366 * by the `magma_prom' property. 367 */ 368 magma_prom = PROM_getpropstring(node, "magma_prom"); 369 370 for (card = supported_cards; card->mb_name != NULL; card++) { 371 if (strcmp(sa->sa_name, card->mb_sbusname) != 0) 372 /* Sbus node name doesn't match */ 373 continue; 374 if (strcmp(magma_prom, card->mb_name) == 0) 375 /* Model name match */ 376 break; 377 } 378 379 if( card->mb_name == NULL ) { 380 printf(": %s (unsupported)\n", magma_prom); 381 return; 382 } 383 384 dprintf((" addr %p", sc)); 385 printf(" softpri %d: %s\n", PIL_TTY, card->mb_realname); 386 387 sc->ms_board = card; 388 sc->ms_ncd1400 = card->mb_ncd1400; 389 sc->ms_ncd1190 = card->mb_ncd1190; 390 391 if (sbus_bus_map(sa->sa_bustag, 392 sa->sa_slot, sa->sa_offset, sa->sa_size, 393 BUS_SPACE_MAP_LINEAR, &bh) != 0) { 394 printf("%s @ sbus: cannot map registers\n", self->dv_xname); 395 return; 396 } 397 398 /* the SVCACK* lines are daisychained */ 399 sc->ms_svcackr = (caddr_t)bus_space_vaddr(sa->sa_bustag, bh) 400 + card->mb_svcackr; 401 sc->ms_svcackt = (caddr_t)bus_space_vaddr(sa->sa_bustag, bh) 402 + card->mb_svcackt; 403 sc->ms_svcackm = (caddr_t)bus_space_vaddr(sa->sa_bustag, bh) 404 + card->mb_svcackm; 405 406 /* 407 * Find the clock speed; it's the same for all CD1400 chips 408 * on the board. 409 */ 410 clockstr = PROM_getpropstring(node, "clock"); 411 if (*clockstr == '\0') 412 /* Default to 25MHz */ 413 cd_clock = 25; 414 else { 415 cd_clock = 0; 416 while (*clockstr != '\0') 417 cd_clock = (cd_clock * 10) + (*clockstr++ - '0'); 418 } 419 420 /* init the cd1400 chips */ 421 for( chip = 0 ; chip < card->mb_ncd1400 ; chip++ ) { 422 struct cd1400 *cd = &sc->ms_cd1400[chip]; 423 424 cd->cd_clock = cd_clock; 425 cd->cd_reg = (caddr_t)bh + card->mb_cd1400[chip]; 426 427 /* PROM_getpropstring(node, "chiprev"); */ 428 /* seemingly the Magma drivers just ignore the propstring */ 429 cd->cd_chiprev = cd1400_read_reg(cd, CD1400_GFRCR); 430 431 dprintf(("%s attach CD1400 %d addr %p rev %x clock %dMhz\n", 432 sc->ms_dev.dv_xname, chip, 433 cd->cd_reg, cd->cd_chiprev, cd->cd_clock)); 434 435 /* clear GFRCR */ 436 cd1400_write_reg(cd, CD1400_GFRCR, 0x00); 437 438 /* reset whole chip */ 439 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET | CD1400_CCR_FULLRESET); 440 441 /* wait for revision code to be restored */ 442 while( cd1400_read_reg(cd, CD1400_GFRCR) != cd->cd_chiprev ) 443 ; 444 445 /* set the Prescaler Period Register to tick at 1ms */ 446 cd1400_write_reg(cd, CD1400_PPR, 447 ((cd->cd_clock * 1000000 / CD1400_PPR_PRESCALER + 500) / 1000)); 448 449 /* The LC2+1Sp card is the only card that doesn't have 450 * a CD1190 for the parallel port, but uses channel 0 of 451 * the CD1400, so we make a note of it for later and set up 452 * the CD1400 for parallel mode operation. 453 */ 454 if( card->mb_npar && card->mb_ncd1190 == 0 ) { 455 cd1400_write_reg(cd, CD1400_GCR, CD1400_GCR_PARALLEL); 456 cd->cd_parmode = 1; 457 } 458 } 459 460 /* init the cd1190 chips */ 461 for( chip = 0 ; chip < card->mb_ncd1190 ; chip++ ) { 462 struct cd1190 *cd = &sc->ms_cd1190[chip]; 463 464 cd->cd_reg = (caddr_t)bh + card->mb_cd1190[chip]; 465 466 /* XXX don't know anything about these chips yet */ 467 printf("%s: CD1190 %d addr %p (unsupported)\n", 468 self->dv_xname, chip, cd->cd_reg); 469 } 470 471 sbus_establish(&sc->ms_sd, &sc->ms_dev); 472 473 /* configure the children */ 474 (void)config_found(self, mtty_match, NULL); 475 (void)config_found(self, mbpp_match, NULL); 476 477 /* 478 * Establish the interrupt handlers. 479 */ 480 if (sa->sa_nintr == 0) 481 return; /* No interrupts to service!? */ 482 483 (void)bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_TTY, 484 0, magma_hard, sc); 485 (void)bus_intr_establish(sa->sa_bustag, PIL_TTY, IPL_SOFTSERIAL, 486 BUS_INTR_ESTABLISH_SOFTINTR, 487 magma_soft, sc); 488 evcnt_attach_dynamic(&sc->ms_intrcnt, EVCNT_TYPE_INTR, NULL, 489 sc->ms_dev.dv_xname, "intr"); 490 } 491 492 /* 493 * hard interrupt routine 494 * 495 * returns 1 if it handled it, otherwise 0 496 * 497 * runs at interrupt priority 498 */ 499 int 500 magma_hard(arg) 501 void *arg; 502 { 503 struct magma_softc *sc = arg; 504 struct cd1400 *cd; 505 int chip, status = 0; 506 int serviced = 0; 507 int needsoftint = 0; 508 509 /* 510 * check status of all the CD1400 chips 511 */ 512 for( chip = 0 ; chip < sc->ms_ncd1400 ; chip++ ) 513 status |= cd1400_read_reg(&sc->ms_cd1400[chip], CD1400_SVRR); 514 515 if( ISSET(status, CD1400_SVRR_RXRDY) ) { 516 u_char rivr = *sc->ms_svcackr; /* enter rx service context */ 517 int port = rivr >> 4; 518 519 if( rivr & (1<<3) ) { /* parallel port */ 520 struct mbpp_port *mbpp; 521 int n_chars; 522 523 mbpp = &sc->ms_mbpp->ms_port[port]; 524 cd = mbpp->mp_cd1400; 525 526 /* don't think we have to handle exceptions */ 527 n_chars = cd1400_read_reg(cd, CD1400_RDCR); 528 while (n_chars--) { 529 if( mbpp->mp_cnt == 0 ) { 530 SET(mbpp->mp_flags, MBPPF_WAKEUP); 531 needsoftint = 1; 532 break; 533 } 534 *mbpp->mp_ptr = cd1400_read_reg(cd,CD1400_RDSR); 535 mbpp->mp_ptr++; 536 mbpp->mp_cnt--; 537 } 538 } else { /* serial port */ 539 struct mtty_port *mtty; 540 u_char *ptr, n_chars, line_stat; 541 542 mtty = &sc->ms_mtty->ms_port[port]; 543 cd = mtty->mp_cd1400; 544 545 if( ISSET(rivr, CD1400_RIVR_EXCEPTION) ) { 546 line_stat = cd1400_read_reg(cd, CD1400_RDSR); 547 n_chars = 1; 548 } else { /* no exception, received data OK */ 549 line_stat = 0; 550 n_chars = cd1400_read_reg(cd, CD1400_RDCR); 551 } 552 553 ptr = mtty->mp_rput; 554 while( n_chars-- ) { 555 *ptr++ = line_stat; 556 *ptr++ = cd1400_read_reg(cd, CD1400_RDSR); 557 if( ptr == mtty->mp_rend ) ptr = mtty->mp_rbuf; 558 if( ptr == mtty->mp_rget ) { 559 if( ptr == mtty->mp_rbuf ) 560 ptr = mtty->mp_rend; 561 ptr -= 2; 562 SET(mtty->mp_flags, MTTYF_RING_OVERFLOW); 563 break; 564 } 565 } 566 mtty->mp_rput = ptr; 567 568 needsoftint = 1; 569 } 570 571 cd1400_write_reg(cd, CD1400_EOSRR, 0); /* end service context */ 572 serviced = 1; 573 } /* if(rx_service...) */ 574 575 if( ISSET(status, CD1400_SVRR_MDMCH) ) { 576 u_char mivr = *sc->ms_svcackm; /* enter mdm service context */ 577 int port = mivr >> 4; 578 struct mtty_port *mtty; 579 int carrier; 580 u_char msvr; 581 582 /* 583 * Handle CD (LC2+1Sp = DSR) changes. 584 */ 585 mtty = &sc->ms_mtty->ms_port[port]; 586 cd = mtty->mp_cd1400; 587 msvr = cd1400_read_reg(cd, CD1400_MSVR2); 588 carrier = ISSET(msvr, cd->cd_parmode ? CD1400_MSVR2_DSR : CD1400_MSVR2_CD); 589 590 if( mtty->mp_carrier != carrier ) { 591 SET(mtty->mp_flags, MTTYF_CARRIER_CHANGED); 592 mtty->mp_carrier = carrier; 593 needsoftint = 1; 594 } 595 596 cd1400_write_reg(cd, CD1400_EOSRR, 0); /* end service context */ 597 serviced = 1; 598 } /* if(mdm_service...) */ 599 600 if( ISSET(status, CD1400_SVRR_TXRDY) ) { 601 u_char tivr = *sc->ms_svcackt; /* enter tx service context */ 602 int port = tivr >> 4; 603 604 if( tivr & (1<<3) ) { /* parallel port */ 605 struct mbpp_port *mbpp; 606 607 mbpp = &sc->ms_mbpp->ms_port[port]; 608 cd = mbpp->mp_cd1400; 609 610 if( mbpp->mp_cnt ) { 611 int count = 0; 612 613 /* fill the fifo */ 614 while (mbpp->mp_cnt && 615 count++ < CD1400_PAR_FIFO_SIZE) { 616 cd1400_write_reg(cd, CD1400_TDR, 617 *mbpp->mp_ptr); 618 mbpp->mp_ptr++; 619 mbpp->mp_cnt--; 620 } 621 } else { 622 /* 623 * fifo is empty and we got no more data 624 * to send, so shut off interrupts and 625 * signal for a wakeup, which can't be 626 * done here in case we beat mbpp_send to 627 * the tsleep call (we are running at >spltty) 628 */ 629 cd1400_write_reg(cd, CD1400_SRER, 0); 630 SET(mbpp->mp_flags, MBPPF_WAKEUP); 631 needsoftint = 1; 632 } 633 } else { /* serial port */ 634 struct mtty_port *mtty; 635 struct tty *tp; 636 637 mtty = &sc->ms_mtty->ms_port[port]; 638 cd = mtty->mp_cd1400; 639 tp = mtty->mp_tty; 640 641 if( !ISSET(mtty->mp_flags, MTTYF_STOP) ) { 642 int count = 0; 643 644 /* check if we should start/stop a break */ 645 if( ISSET(mtty->mp_flags, MTTYF_SET_BREAK) ) { 646 cd1400_write_reg(cd, CD1400_TDR, 0); 647 cd1400_write_reg(cd, CD1400_TDR, 0x81); 648 /* should we delay too? */ 649 CLR(mtty->mp_flags, MTTYF_SET_BREAK); 650 count += 2; 651 } 652 653 if( ISSET(mtty->mp_flags, MTTYF_CLR_BREAK) ) { 654 cd1400_write_reg(cd, CD1400_TDR, 0); 655 cd1400_write_reg(cd, CD1400_TDR, 0x83); 656 CLR(mtty->mp_flags, MTTYF_CLR_BREAK); 657 count += 2; 658 } 659 660 /* I don't quite fill the fifo in case the last one is a 661 * NULL which I have to double up because its the escape 662 * code for embedded transmit characters. 663 */ 664 while( mtty->mp_txc > 0 && count < CD1400_TX_FIFO_SIZE - 1 ) { 665 u_char ch; 666 667 ch = *mtty->mp_txp; 668 669 mtty->mp_txc--; 670 mtty->mp_txp++; 671 672 if( ch == 0 ) { 673 cd1400_write_reg(cd, CD1400_TDR, ch); 674 count++; 675 } 676 677 cd1400_write_reg(cd, CD1400_TDR, ch); 678 count++; 679 } 680 } 681 682 /* if we ran out of work or are requested to STOP then 683 * shut off the txrdy interrupts and signal DONE to flush 684 * out the chars we have sent. 685 */ 686 if( mtty->mp_txc == 0 || ISSET(mtty->mp_flags, MTTYF_STOP) ) { 687 register int srer; 688 689 srer = cd1400_read_reg(cd, CD1400_SRER); 690 CLR(srer, CD1400_SRER_TXRDY); 691 cd1400_write_reg(cd, CD1400_SRER, srer); 692 CLR(mtty->mp_flags, MTTYF_STOP); 693 694 SET(mtty->mp_flags, MTTYF_DONE); 695 needsoftint = 1; 696 } 697 } 698 699 cd1400_write_reg(cd, CD1400_EOSRR, 0); /* end service context */ 700 serviced = 1; 701 } /* if(tx_service...) */ 702 703 /* XXX service CD1190 interrupts too 704 for( chip = 0 ; chip < sc->ms_ncd1190 ; chip++ ) { 705 } 706 */ 707 708 if( needsoftint ) { /* trigger the soft interrupt */ 709 #if defined(SUN4M) 710 if( CPU_ISSUN4M ) 711 raise(0, PIL_TTY); 712 else 713 #endif 714 ienab_bis(IE_MSOFT); 715 } 716 717 return(serviced); 718 } 719 720 /* 721 * magma soft interrupt handler 722 * 723 * returns 1 if it handled it, 0 otherwise 724 * 725 * runs at spltty() 726 */ 727 int 728 magma_soft(arg) 729 void *arg; 730 { 731 struct magma_softc *sc = arg; 732 struct mtty_softc *mtty = sc->ms_mtty; 733 struct mbpp_softc *mbpp = sc->ms_mbpp; 734 int port; 735 int serviced = 0; 736 int s, flags; 737 738 if (mtty == NULL) 739 goto chkbpp; 740 741 /* 742 * check the tty ports to see what needs doing 743 */ 744 for( port = 0 ; port < mtty->ms_nports ; port++ ) { 745 struct mtty_port *mp = &mtty->ms_port[port]; 746 struct tty *tp = mp->mp_tty; 747 748 if( !ISSET(tp->t_state, TS_ISOPEN) ) 749 continue; 750 751 /* 752 * handle any received data 753 */ 754 while( mp->mp_rget != mp->mp_rput ) { 755 u_char stat; 756 int data; 757 758 stat = mp->mp_rget[0]; 759 data = mp->mp_rget[1]; 760 mp->mp_rget = ((mp->mp_rget + 2) == mp->mp_rend) 761 ? mp->mp_rbuf : (mp->mp_rget + 2); 762 763 if( stat & (CD1400_RDSR_BREAK | CD1400_RDSR_FE) ) 764 data |= TTY_FE; 765 if( stat & CD1400_RDSR_PE ) 766 data |= TTY_PE; 767 768 if( stat & CD1400_RDSR_OE ) 769 log(LOG_WARNING, "%s%x: fifo overflow\n", 770 mtty->ms_dev.dv_xname, port); 771 772 (*tp->t_linesw->l_rint)(data, tp); 773 serviced = 1; 774 } 775 776 s = splhigh(); /* block out hard interrupt routine */ 777 flags = mp->mp_flags; 778 CLR(mp->mp_flags, MTTYF_DONE | MTTYF_CARRIER_CHANGED | MTTYF_RING_OVERFLOW); 779 splx(s); /* ok */ 780 781 if( ISSET(flags, MTTYF_CARRIER_CHANGED) ) { 782 dprintf(("%s%x: cd %s\n", mtty->ms_dev.dv_xname, 783 port, mp->mp_carrier ? "on" : "off")); 784 (*tp->t_linesw->l_modem)(tp, mp->mp_carrier); 785 serviced = 1; 786 } 787 788 if( ISSET(flags, MTTYF_RING_OVERFLOW) ) { 789 log(LOG_WARNING, "%s%x: ring buffer overflow\n", 790 mtty->ms_dev.dv_xname, port); 791 serviced = 1; 792 } 793 794 if( ISSET(flags, MTTYF_DONE) ) { 795 ndflush(&tp->t_outq, mp->mp_txp - tp->t_outq.c_cf); 796 CLR(tp->t_state, TS_BUSY); 797 (*tp->t_linesw->l_start)(tp); /* might be some more */ 798 serviced = 1; 799 } 800 } /* for(each mtty...) */ 801 802 803 chkbpp: 804 /* 805 * Check the bpp ports (if any) to see what needs doing 806 */ 807 if (mbpp == NULL) 808 return (serviced); 809 810 for( port = 0 ; port < mbpp->ms_nports ; port++ ) { 811 struct mbpp_port *mp = &mbpp->ms_port[port]; 812 813 if( !ISSET(mp->mp_flags, MBPPF_OPEN) ) 814 continue; 815 816 s = splhigh(); 817 flags = mp->mp_flags; 818 CLR(mp->mp_flags, MBPPF_WAKEUP); 819 splx(s); 820 821 if( ISSET(flags, MBPPF_WAKEUP) ) { 822 wakeup(mp); 823 serviced = 1; 824 } 825 826 } /* for(each mbpp...) */ 827 828 return(serviced); 829 } 830 831 /************************************************************************ 832 * 833 * MTTY Routines 834 * 835 * mtty_match match one mtty device 836 * mtty_attach attach mtty devices 837 * mttyopen open mtty device 838 * mttyclose close mtty device 839 * mttyread read from mtty 840 * mttywrite write to mtty 841 * mttyioctl do ioctl on mtty 842 * mttytty return tty pointer for mtty 843 * mttystop stop mtty device 844 * mtty_start start mtty device 845 * mtty_param set mtty parameters 846 * mtty_modem_control set modem control lines 847 */ 848 849 int 850 mtty_match(parent, cf, args) 851 struct device *parent; 852 struct cfdata *cf; 853 void *args; 854 { 855 struct magma_softc *sc = (struct magma_softc *)parent; 856 857 return( args == mtty_match && sc->ms_board->mb_nser && sc->ms_mtty == NULL ); 858 } 859 860 void 861 mtty_attach(parent, dev, args) 862 struct device *parent; 863 struct device *dev; 864 void *args; 865 { 866 struct magma_softc *sc = (struct magma_softc *)parent; 867 struct mtty_softc *ms = (struct mtty_softc *)dev; 868 int port, chip, chan; 869 870 sc->ms_mtty = ms; 871 dprintf((" addr %p", ms)); 872 873 for( port = 0, chip = 0, chan = 0 ; port < sc->ms_board->mb_nser ; port++ ) { 874 struct mtty_port *mp = &ms->ms_port[port]; 875 struct tty *tp; 876 877 mp->mp_cd1400 = &sc->ms_cd1400[chip]; 878 if (mp->mp_cd1400->cd_parmode && chan == 0) 879 chan = 1; /* skip channel 0 if parmode */ 880 mp->mp_channel = chan; 881 882 tp = ttymalloc(); 883 if (tp == NULL) break; 884 tty_attach(tp); 885 tp->t_oproc = mtty_start; 886 tp->t_param = mtty_param; 887 888 mp->mp_tty = tp; 889 890 mp->mp_rbuf = malloc(MTTY_RBUF_SIZE, M_DEVBUF, M_NOWAIT); 891 if (mp->mp_rbuf == NULL) break; 892 893 mp->mp_rend = mp->mp_rbuf + MTTY_RBUF_SIZE; 894 895 chan = (chan + 1) % CD1400_NO_OF_CHANNELS; 896 if (chan == 0) 897 chip++; 898 } 899 900 ms->ms_nports = port; 901 printf(": %d tty%s\n", port, port == 1 ? "" : "s"); 902 } 903 904 /* 905 * open routine. returns zero if successful, else error code 906 */ 907 int 908 mttyopen(dev, flags, mode, p) 909 dev_t dev; 910 int flags; 911 int mode; 912 struct proc *p; 913 { 914 int card = MAGMA_CARD(dev); 915 int port = MAGMA_PORT(dev); 916 struct mtty_softc *ms; 917 struct mtty_port *mp; 918 struct tty *tp; 919 struct cd1400 *cd; 920 int error, s; 921 922 if( card >= mtty_cd.cd_ndevs || 923 (ms = mtty_cd.cd_devs[card]) == NULL || port >= ms->ms_nports ) 924 return(ENXIO); /* device not configured */ 925 926 mp = &ms->ms_port[port]; 927 tp = mp->mp_tty; 928 tp->t_dev = dev; 929 930 if (ISSET(tp->t_state, TS_ISOPEN) && 931 ISSET(tp->t_state, TS_XCLUDE) && 932 p->p_ucred->cr_uid != 0) 933 return (EBUSY); 934 935 s = spltty(); 936 937 if( !ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 938 939 /* set defaults */ 940 ttychars(tp); 941 tp->t_iflag = TTYDEF_IFLAG; 942 tp->t_oflag = TTYDEF_OFLAG; 943 tp->t_cflag = TTYDEF_CFLAG; 944 if( ISSET(mp->mp_openflags, TIOCFLAG_CLOCAL) ) 945 SET(tp->t_cflag, CLOCAL); 946 if( ISSET(mp->mp_openflags, TIOCFLAG_CRTSCTS) ) 947 SET(tp->t_cflag, CRTSCTS); 948 if( ISSET(mp->mp_openflags, TIOCFLAG_MDMBUF) ) 949 SET(tp->t_cflag, MDMBUF); 950 tp->t_lflag = TTYDEF_LFLAG; 951 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 952 953 /* init ring buffer */ 954 mp->mp_rput = mp->mp_rget = mp->mp_rbuf; 955 956 /* reset CD1400 channel */ 957 cd = mp->mp_cd1400; 958 cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel); 959 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET); 960 961 /* encode the port number in top half of LIVR */ 962 cd1400_write_reg(cd, CD1400_LIVR, port << 4 ); 963 964 /* sets parameters and raises DTR */ 965 (void)mtty_param(tp, &tp->t_termios); 966 967 /* set tty watermarks */ 968 ttsetwater(tp); 969 970 /* enable service requests */ 971 cd1400_write_reg(cd, CD1400_SRER, 972 CD1400_SRER_RXDATA | CD1400_SRER_MDMCH); 973 974 /* tell the tty about the carrier status */ 975 if( ISSET(mp->mp_openflags, TIOCFLAG_SOFTCAR) || 976 mp->mp_carrier ) 977 SET(tp->t_state, TS_CARR_ON); 978 else 979 CLR(tp->t_state, TS_CARR_ON); 980 } 981 splx(s); 982 983 error = ttyopen(tp, MTTY_DIALOUT(dev), ISSET(flags, O_NONBLOCK)); 984 if (error != 0) 985 goto bad; 986 987 error = (*tp->t_linesw->l_open)(dev, tp); 988 if (error != 0) 989 goto bad; 990 991 bad: 992 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 993 /* 994 * We failed to open the device, and nobody else had it opened. 995 * Clean up the state as appropriate. 996 */ 997 /* XXX - do that here */ 998 } 999 1000 return (error); 1001 } 1002 1003 /* 1004 * close routine. returns zero if successful, else error code 1005 */ 1006 int 1007 mttyclose(dev, flag, mode, p) 1008 dev_t dev; 1009 int flag; 1010 int mode; 1011 struct proc *p; 1012 { 1013 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(dev)]; 1014 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1015 struct tty *tp = mp->mp_tty; 1016 int s; 1017 1018 (*tp->t_linesw->l_close)(tp, flag); 1019 ttyclose(tp); 1020 1021 s = spltty(); 1022 1023 /* if HUPCL is set, and the tty is no longer open 1024 * shut down the port 1025 */ 1026 if( ISSET(tp->t_cflag, HUPCL) || !ISSET(tp->t_state, TS_ISOPEN) ) { 1027 /* XXX wait until FIFO is empty before turning off the channel 1028 struct cd1400 *cd = mp->mp_cd1400; 1029 */ 1030 1031 /* drop DTR and RTS */ 1032 (void)mtty_modem_control(mp, 0, DMSET); 1033 1034 /* turn off the channel 1035 cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel); 1036 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET); 1037 */ 1038 } 1039 1040 splx(s); 1041 1042 return(0); 1043 } 1044 1045 /* 1046 * Read routine 1047 */ 1048 int 1049 mttyread(dev, uio, flags) 1050 dev_t dev; 1051 struct uio *uio; 1052 int flags; 1053 { 1054 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(dev)]; 1055 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1056 struct tty *tp = mp->mp_tty; 1057 1058 return( (*tp->t_linesw->l_read)(tp, uio, flags) ); 1059 } 1060 1061 /* 1062 * Write routine 1063 */ 1064 int 1065 mttywrite(dev, uio, flags) 1066 dev_t dev; 1067 struct uio *uio; 1068 int flags; 1069 { 1070 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(dev)]; 1071 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1072 struct tty *tp = mp->mp_tty; 1073 1074 return( (*tp->t_linesw->l_write)(tp, uio, flags) ); 1075 } 1076 1077 /* 1078 * Poll routine 1079 */ 1080 int 1081 mttypoll(dev, events, p) 1082 dev_t dev; 1083 int events; 1084 struct proc *p; 1085 { 1086 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(dev)]; 1087 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1088 struct tty *tp = mp->mp_tty; 1089 1090 return ((*tp->t_linesw->l_poll)(tp, events, p)); 1091 } 1092 1093 /* 1094 * return tty pointer 1095 */ 1096 struct tty * 1097 mttytty(dev) 1098 dev_t dev; 1099 { 1100 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(dev)]; 1101 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1102 1103 return(mp->mp_tty); 1104 } 1105 1106 /* 1107 * ioctl routine 1108 */ 1109 int 1110 mttyioctl(dev, cmd, data, flags, p) 1111 dev_t dev; 1112 u_long cmd; 1113 caddr_t data; 1114 int flags; 1115 struct proc *p; 1116 { 1117 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(dev)]; 1118 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1119 struct tty *tp = mp->mp_tty; 1120 int error; 1121 1122 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flags, p); 1123 if( error != EPASSTHROUGH ) return(error); 1124 1125 error = ttioctl(tp, cmd, data, flags, p); 1126 if( error != EPASSTHROUGH ) return(error); 1127 1128 error = 0; 1129 1130 switch(cmd) { 1131 case TIOCSBRK: /* set break */ 1132 SET(mp->mp_flags, MTTYF_SET_BREAK); 1133 cd1400_enable_transmitter(mp->mp_cd1400, mp->mp_channel); 1134 break; 1135 1136 case TIOCCBRK: /* clear break */ 1137 SET(mp->mp_flags, MTTYF_CLR_BREAK); 1138 cd1400_enable_transmitter(mp->mp_cd1400, mp->mp_channel); 1139 break; 1140 1141 case TIOCSDTR: /* set DTR */ 1142 mtty_modem_control(mp, TIOCM_DTR, DMBIS); 1143 break; 1144 1145 case TIOCCDTR: /* clear DTR */ 1146 mtty_modem_control(mp, TIOCM_DTR, DMBIC); 1147 break; 1148 1149 case TIOCMSET: /* set modem lines */ 1150 mtty_modem_control(mp, *((int *)data), DMSET); 1151 break; 1152 1153 case TIOCMBIS: /* bit set modem lines */ 1154 mtty_modem_control(mp, *((int *)data), DMBIS); 1155 break; 1156 1157 case TIOCMBIC: /* bit clear modem lines */ 1158 mtty_modem_control(mp, *((int *)data), DMBIC); 1159 break; 1160 1161 case TIOCMGET: /* get modem lines */ 1162 *((int *)data) = mtty_modem_control(mp, 0, DMGET); 1163 break; 1164 1165 case TIOCGFLAGS: 1166 *((int *)data) = mp->mp_openflags; 1167 break; 1168 1169 case TIOCSFLAGS: 1170 if( suser(p->p_ucred, &p->p_acflag) ) 1171 error = EPERM; 1172 else 1173 mp->mp_openflags = *((int *)data) & 1174 (TIOCFLAG_SOFTCAR | TIOCFLAG_CLOCAL | 1175 TIOCFLAG_CRTSCTS | TIOCFLAG_MDMBUF); 1176 break; 1177 1178 default: 1179 error = EPASSTHROUGH; 1180 } 1181 1182 return(error); 1183 } 1184 1185 /* 1186 * Stop output, e.g., for ^S or output flush. 1187 */ 1188 void 1189 mttystop(tp, flags) 1190 struct tty *tp; 1191 int flags; 1192 { 1193 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(tp->t_dev)]; 1194 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(tp->t_dev)]; 1195 int s; 1196 1197 s = spltty(); 1198 1199 if( ISSET(tp->t_state, TS_BUSY) ) { 1200 if( !ISSET(tp->t_state, TS_TTSTOP) ) 1201 SET(tp->t_state, TS_FLUSH); 1202 1203 /* 1204 * the transmit interrupt routine will disable transmit when it 1205 * notices that MTTYF_STOP has been set. 1206 */ 1207 SET(mp->mp_flags, MTTYF_STOP); 1208 } 1209 1210 splx(s); 1211 } 1212 1213 /* 1214 * Start output, after a stop. 1215 */ 1216 void 1217 mtty_start(tp) 1218 struct tty *tp; 1219 { 1220 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(tp->t_dev)]; 1221 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(tp->t_dev)]; 1222 int s; 1223 1224 s = spltty(); 1225 1226 /* we only need to do something if we are not already busy 1227 * or delaying or stopped 1228 */ 1229 if( !ISSET(tp->t_state, TS_TTSTOP | TS_TIMEOUT | TS_BUSY) ) { 1230 1231 /* if we are sleeping and output has drained below 1232 * low water mark, awaken 1233 */ 1234 if( tp->t_outq.c_cc <= tp->t_lowat ) { 1235 if( ISSET(tp->t_state, TS_ASLEEP) ) { 1236 CLR(tp->t_state, TS_ASLEEP); 1237 wakeup(&tp->t_outq); 1238 } 1239 1240 selwakeup(&tp->t_wsel); 1241 } 1242 1243 /* if something to send, start transmitting 1244 */ 1245 if( tp->t_outq.c_cc ) { 1246 mp->mp_txc = ndqb(&tp->t_outq, 0); 1247 mp->mp_txp = tp->t_outq.c_cf; 1248 SET(tp->t_state, TS_BUSY); 1249 cd1400_enable_transmitter(mp->mp_cd1400, mp->mp_channel); 1250 } 1251 } 1252 1253 splx(s); 1254 } 1255 1256 /* 1257 * set/get modem line status 1258 * 1259 * bits can be: TIOCM_DTR, TIOCM_RTS, TIOCM_CTS, TIOCM_CD, TIOCM_RI, TIOCM_DSR 1260 * 1261 * note that DTR and RTS lines are exchanged, and that DSR is 1262 * not available on the LC2+1Sp card (used as CD) 1263 * 1264 * only let them fiddle with RTS if CRTSCTS is not enabled 1265 */ 1266 int 1267 mtty_modem_control(mp, bits, howto) 1268 struct mtty_port *mp; 1269 int bits; 1270 int howto; 1271 { 1272 struct cd1400 *cd = mp->mp_cd1400; 1273 struct tty *tp = mp->mp_tty; 1274 int s, msvr; 1275 1276 s = spltty(); 1277 1278 cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel); 1279 1280 switch(howto) { 1281 case DMGET: /* get bits */ 1282 bits = 0; 1283 1284 bits |= TIOCM_LE; 1285 1286 msvr = cd1400_read_reg(cd, CD1400_MSVR1); 1287 if( msvr & CD1400_MSVR1_RTS ) bits |= TIOCM_DTR; 1288 1289 msvr = cd1400_read_reg(cd, CD1400_MSVR2); 1290 if( msvr & CD1400_MSVR2_DTR ) bits |= TIOCM_RTS; 1291 if( msvr & CD1400_MSVR2_CTS ) bits |= TIOCM_CTS; 1292 if( msvr & CD1400_MSVR2_RI ) bits |= TIOCM_RI; 1293 if( msvr & CD1400_MSVR2_DSR ) bits |= (cd->cd_parmode ? TIOCM_CD : TIOCM_DSR); 1294 if( msvr & CD1400_MSVR2_CD ) bits |= (cd->cd_parmode ? 0 : TIOCM_CD); 1295 1296 break; 1297 1298 case DMSET: /* reset bits */ 1299 if( !ISSET(tp->t_cflag, CRTSCTS) ) 1300 cd1400_write_reg(cd, CD1400_MSVR2, ((bits & TIOCM_RTS) ? CD1400_MSVR2_DTR : 0)); 1301 1302 cd1400_write_reg(cd, CD1400_MSVR1, ((bits & TIOCM_DTR) ? CD1400_MSVR1_RTS : 0)); 1303 1304 break; 1305 1306 case DMBIS: /* set bits */ 1307 if( (bits & TIOCM_RTS) && !ISSET(tp->t_cflag, CRTSCTS) ) 1308 cd1400_write_reg(cd, CD1400_MSVR2, CD1400_MSVR2_DTR); 1309 1310 if( bits & TIOCM_DTR ) 1311 cd1400_write_reg(cd, CD1400_MSVR1, CD1400_MSVR1_RTS); 1312 1313 break; 1314 1315 case DMBIC: /* clear bits */ 1316 if( (bits & TIOCM_RTS) && !ISSET(tp->t_cflag, CRTSCTS) ) 1317 cd1400_write_reg(cd, CD1400_MSVR2, 0); 1318 1319 if( bits & TIOCM_DTR ) 1320 cd1400_write_reg(cd, CD1400_MSVR1, 0); 1321 1322 break; 1323 } 1324 1325 splx(s); 1326 return(bits); 1327 } 1328 1329 /* 1330 * Set tty parameters, returns error or 0 on success 1331 */ 1332 int 1333 mtty_param(tp, t) 1334 struct tty *tp; 1335 struct termios *t; 1336 { 1337 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(tp->t_dev)]; 1338 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(tp->t_dev)]; 1339 struct cd1400 *cd = mp->mp_cd1400; 1340 int rbpr, tbpr, rcor, tcor; 1341 u_char mcor1 = 0, mcor2 = 0; 1342 int s, opt; 1343 1344 if( t->c_ospeed && cd1400_compute_baud(t->c_ospeed, cd->cd_clock, &tcor, &tbpr) ) 1345 return(EINVAL); 1346 1347 if( t->c_ispeed && cd1400_compute_baud(t->c_ispeed, cd->cd_clock, &rcor, &rbpr) ) 1348 return(EINVAL); 1349 1350 s = spltty(); 1351 1352 /* hang up the line if ospeed is zero, else raise DTR */ 1353 (void)mtty_modem_control(mp, TIOCM_DTR, (t->c_ospeed == 0 ? DMBIC : DMBIS)); 1354 1355 /* select channel, done in mtty_modem_control() */ 1356 /* cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel); */ 1357 1358 /* set transmit speed */ 1359 if( t->c_ospeed ) { 1360 cd1400_write_reg(cd, CD1400_TCOR, tcor); 1361 cd1400_write_reg(cd, CD1400_TBPR, tbpr); 1362 } 1363 1364 /* set receive speed */ 1365 if( t->c_ispeed ) { 1366 cd1400_write_reg(cd, CD1400_RCOR, rcor); 1367 cd1400_write_reg(cd, CD1400_RBPR, rbpr); 1368 } 1369 1370 /* enable transmitting and receiving on this channel */ 1371 opt = CD1400_CCR_CMDCHANCTL | CD1400_CCR_XMTEN | CD1400_CCR_RCVEN; 1372 cd1400_write_ccr(cd, opt); 1373 1374 /* set parity, data and stop bits */ 1375 opt = 0; 1376 if( ISSET(t->c_cflag, PARENB) ) 1377 opt |= (ISSET(t->c_cflag, PARODD) ? CD1400_COR1_PARODD : CD1400_COR1_PARNORMAL); 1378 1379 if( !ISSET(t->c_iflag, INPCK) ) 1380 opt |= CD1400_COR1_NOINPCK; /* no parity checking */ 1381 1382 if( ISSET(t->c_cflag, CSTOPB) ) 1383 opt |= CD1400_COR1_STOP2; 1384 1385 switch( t->c_cflag & CSIZE ) { 1386 case CS5: 1387 opt |= CD1400_COR1_CS5; 1388 break; 1389 1390 case CS6: 1391 opt |= CD1400_COR1_CS6; 1392 break; 1393 1394 case CS7: 1395 opt |= CD1400_COR1_CS7; 1396 break; 1397 1398 default: 1399 opt |= CD1400_COR1_CS8; 1400 break; 1401 } 1402 1403 cd1400_write_reg(cd, CD1400_COR1, opt); 1404 1405 /* 1406 * enable Embedded Transmit Commands (for breaks) 1407 * use the CD1400 automatic CTS flow control if CRTSCTS is set 1408 */ 1409 opt = CD1400_COR2_ETC; 1410 if( ISSET(t->c_cflag, CRTSCTS) ) opt |= CD1400_COR2_CCTS_OFLOW; 1411 cd1400_write_reg(cd, CD1400_COR2, opt); 1412 1413 cd1400_write_reg(cd, CD1400_COR3, MTTY_RX_FIFO_THRESHOLD); 1414 1415 cd1400_write_ccr(cd, CD1400_CCR_CMDCORCHG | CD1400_CCR_COR1 | CD1400_CCR_COR2 | CD1400_CCR_COR3); 1416 1417 cd1400_write_reg(cd, CD1400_COR4, CD1400_COR4_PFO_EXCEPTION); 1418 cd1400_write_reg(cd, CD1400_COR5, 0); 1419 1420 /* 1421 * if automatic RTS handshaking enabled, set DTR threshold 1422 * (RTS and DTR lines are switched, CD1400 thinks its DTR) 1423 */ 1424 if( ISSET(t->c_cflag, CRTSCTS) ) 1425 mcor1 = MTTY_RX_DTR_THRESHOLD; 1426 1427 /* set up `carrier detect' interrupts */ 1428 if( cd->cd_parmode ) { 1429 SET(mcor1, CD1400_MCOR1_DSRzd); 1430 SET(mcor2, CD1400_MCOR2_DSRod); 1431 } else { 1432 SET(mcor1, CD1400_MCOR1_CDzd); 1433 SET(mcor2, CD1400_MCOR2_CDod); 1434 } 1435 1436 cd1400_write_reg(cd, CD1400_MCOR1, mcor1); 1437 cd1400_write_reg(cd, CD1400_MCOR2, mcor2); 1438 1439 /* receive timeout 2ms */ 1440 cd1400_write_reg(cd, CD1400_RTPR, 2); 1441 1442 splx(s); 1443 return(0); 1444 } 1445 1446 /************************************************************************ 1447 * 1448 * MBPP Routines 1449 * 1450 * mbpp_match match one mbpp device 1451 * mbpp_attach attach mbpp devices 1452 * mbppopen open mbpp device 1453 * mbppclose close mbpp device 1454 * mbppread read from mbpp 1455 * mbppwrite write to mbpp 1456 * mbppioctl do ioctl on mbpp 1457 * mbppselect do select on mbpp 1458 * mbpp_rw general rw routine 1459 * mbpp_timeout rw timeout 1460 * mbpp_start rw start after delay 1461 * mbpp_send send data 1462 * mbpp_recv recv data 1463 */ 1464 1465 int 1466 mbpp_match(parent, cf, args) 1467 struct device *parent; 1468 struct cfdata *cf; 1469 void *args; 1470 { 1471 struct magma_softc *sc = (struct magma_softc *)parent; 1472 1473 return( args == mbpp_match && sc->ms_board->mb_npar && sc->ms_mbpp == NULL ); 1474 } 1475 1476 void 1477 mbpp_attach(parent, dev, args) 1478 struct device *parent; 1479 struct device *dev; 1480 void *args; 1481 { 1482 struct magma_softc *sc = (struct magma_softc *)parent; 1483 struct mbpp_softc *ms = (struct mbpp_softc *)dev; 1484 struct mbpp_port *mp; 1485 int port; 1486 1487 sc->ms_mbpp = ms; 1488 dprintf((" addr %p", ms)); 1489 1490 for( port = 0 ; port < sc->ms_board->mb_npar ; port++ ) { 1491 mp = &ms->ms_port[port]; 1492 1493 callout_init(&mp->mp_timeout_ch); 1494 callout_init(&mp->mp_start_ch); 1495 1496 if( sc->ms_ncd1190 ) 1497 mp->mp_cd1190 = &sc->ms_cd1190[port]; 1498 else 1499 mp->mp_cd1400 = &sc->ms_cd1400[0]; 1500 } 1501 1502 ms->ms_nports = port; 1503 printf(": %d port%s\n", port, port == 1 ? "" : "s"); 1504 } 1505 1506 /* 1507 * open routine. returns zero if successful, else error code 1508 */ 1509 int 1510 mbppopen(dev, flags, mode, p) 1511 dev_t dev; 1512 int flags; 1513 int mode; 1514 struct proc *p; 1515 { 1516 int card = MAGMA_CARD(dev); 1517 int port = MAGMA_PORT(dev); 1518 struct mbpp_softc *ms; 1519 struct mbpp_port *mp; 1520 int s; 1521 1522 if( card >= mbpp_cd.cd_ndevs || 1523 (ms = mbpp_cd.cd_devs[card]) == NULL || port >= ms->ms_nports ) 1524 return(ENXIO); 1525 1526 mp = &ms->ms_port[port]; 1527 1528 s = spltty(); 1529 if( ISSET(mp->mp_flags, MBPPF_OPEN) ) { 1530 splx(s); 1531 return(EBUSY); 1532 } 1533 SET(mp->mp_flags, MBPPF_OPEN); 1534 splx(s); 1535 1536 /* set defaults */ 1537 mp->mp_burst = MBPP_BURST; 1538 mp->mp_timeout = mbpp_mstohz(MBPP_TIMEOUT); 1539 mp->mp_delay = mbpp_mstohz(MBPP_DELAY); 1540 1541 /* init chips */ 1542 if( mp->mp_cd1400 ) { /* CD1400 */ 1543 struct cd1400 *cd = mp->mp_cd1400; 1544 1545 /* set up CD1400 channel */ 1546 s = spltty(); 1547 cd1400_write_reg(cd, CD1400_CAR, 0); 1548 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET); 1549 cd1400_write_reg(cd, CD1400_LIVR, (1<<3)); 1550 splx(s); 1551 } else { /* CD1190 */ 1552 mp->mp_flags = 0; 1553 return (ENXIO); 1554 } 1555 1556 return (0); 1557 } 1558 1559 /* 1560 * close routine. returns zero if successful, else error code 1561 */ 1562 int 1563 mbppclose(dev, flag, mode, p) 1564 dev_t dev; 1565 int flag; 1566 int mode; 1567 struct proc *p; 1568 { 1569 struct mbpp_softc *ms = mbpp_cd.cd_devs[MAGMA_CARD(dev)]; 1570 struct mbpp_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1571 1572 mp->mp_flags = 0; 1573 return(0); 1574 } 1575 1576 /* 1577 * Read routine 1578 */ 1579 int 1580 mbppread(dev, uio, flags) 1581 dev_t dev; 1582 struct uio *uio; 1583 int flags; 1584 { 1585 1586 return( mbpp_rw(dev, uio) ); 1587 } 1588 1589 /* 1590 * Write routine 1591 */ 1592 int 1593 mbppwrite(dev, uio, flags) 1594 dev_t dev; 1595 struct uio *uio; 1596 int flags; 1597 { 1598 1599 return( mbpp_rw(dev, uio) ); 1600 } 1601 1602 /* 1603 * ioctl routine 1604 */ 1605 int 1606 mbppioctl(dev, cmd, data, flags, p) 1607 dev_t dev; 1608 u_long cmd; 1609 caddr_t data; 1610 int flags; 1611 struct proc *p; 1612 { 1613 struct mbpp_softc *ms = mbpp_cd.cd_devs[MAGMA_CARD(dev)]; 1614 struct mbpp_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1615 struct mbpp_param *bp; 1616 int error = 0; 1617 int s; 1618 1619 switch(cmd) { 1620 case MBPPIOCSPARAM: 1621 bp = (struct mbpp_param *)data; 1622 if( bp->bp_burst < MBPP_BURST_MIN || bp->bp_burst > MBPP_BURST_MAX || 1623 bp->bp_delay < MBPP_DELAY_MIN || bp->bp_delay > MBPP_DELAY_MIN ) { 1624 error = EINVAL; 1625 } else { 1626 mp->mp_burst = bp->bp_burst; 1627 mp->mp_timeout = mbpp_mstohz(bp->bp_timeout); 1628 mp->mp_delay = mbpp_mstohz(bp->bp_delay); 1629 } 1630 break; 1631 case MBPPIOCGPARAM: 1632 bp = (struct mbpp_param *)data; 1633 bp->bp_burst = mp->mp_burst; 1634 bp->bp_timeout = mbpp_hztoms(mp->mp_timeout); 1635 bp->bp_delay = mbpp_hztoms(mp->mp_delay); 1636 break; 1637 case MBPPIOCGSTAT: 1638 /* XXX make this more generic */ 1639 s = spltty(); 1640 cd1400_write_reg(mp->mp_cd1400, CD1400_CAR, 0); 1641 *(int *)data = cd1400_read_reg(mp->mp_cd1400, CD1400_PSVR); 1642 splx(s); 1643 break; 1644 default: 1645 error = ENOTTY; 1646 } 1647 1648 return(error); 1649 } 1650 1651 /* 1652 * poll routine 1653 */ 1654 int 1655 mbpppoll(dev, rw, p) 1656 dev_t dev; 1657 int rw; 1658 struct proc *p; 1659 { 1660 1661 return(ENODEV); 1662 } 1663 1664 int 1665 mbpp_rw(dev, uio) 1666 dev_t dev; 1667 struct uio *uio; 1668 { 1669 int card = MAGMA_CARD(dev); 1670 int port = MAGMA_PORT(dev); 1671 struct mbpp_softc *ms = mbpp_cd.cd_devs[card]; 1672 struct mbpp_port *mp = &ms->ms_port[port]; 1673 caddr_t buffer, ptr; 1674 int buflen, cnt, len; 1675 int s, error = 0; 1676 int gotdata = 0; 1677 1678 if( uio->uio_resid == 0 ) 1679 return(0); 1680 1681 buflen = min(uio->uio_resid, mp->mp_burst); 1682 buffer = malloc(buflen, M_DEVBUF, M_WAITOK); 1683 if( buffer == NULL ) 1684 return(ENOMEM); 1685 1686 SET(mp->mp_flags, MBPPF_UIO); 1687 1688 /* 1689 * start timeout, if needed 1690 */ 1691 if( mp->mp_timeout > 0 ) { 1692 SET(mp->mp_flags, MBPPF_TIMEOUT); 1693 callout_reset(&mp->mp_timeout_ch, mp->mp_timeout, 1694 mbpp_timeout, mp); 1695 } 1696 1697 len = cnt = 0; 1698 while( uio->uio_resid > 0 ) { 1699 len = min(buflen, uio->uio_resid); 1700 ptr = buffer; 1701 1702 if( uio->uio_rw == UIO_WRITE ) { 1703 error = uiomove(ptr, len, uio); 1704 if( error ) break; 1705 } 1706 again: /* goto bad */ 1707 /* timed out? */ 1708 if( !ISSET(mp->mp_flags, MBPPF_UIO) ) 1709 break; 1710 1711 /* 1712 * perform the operation 1713 */ 1714 if( uio->uio_rw == UIO_WRITE ) { 1715 cnt = mbpp_send(mp, ptr, len); 1716 } else { 1717 cnt = mbpp_recv(mp, ptr, len); 1718 } 1719 1720 if( uio->uio_rw == UIO_READ ) { 1721 if( cnt ) { 1722 error = uiomove(ptr, cnt, uio); 1723 if( error ) break; 1724 gotdata++; 1725 } 1726 else if( gotdata ) /* consider us done */ 1727 break; 1728 } 1729 1730 /* timed out? */ 1731 if( !ISSET(mp->mp_flags, MBPPF_UIO) ) 1732 break; 1733 1734 /* 1735 * poll delay? 1736 */ 1737 if( mp->mp_delay > 0 ) { 1738 s = splsoftclock(); 1739 SET(mp->mp_flags, MBPPF_DELAY); 1740 callout_reset(&mp->mp_start_ch, mp->mp_delay, 1741 mbpp_start, mp); 1742 error = tsleep(mp, PCATCH | PZERO, "mbppdelay", 0); 1743 splx(s); 1744 if( error ) break; 1745 } 1746 1747 /* 1748 * don't call uiomove again until we used all the data we grabbed 1749 */ 1750 if( uio->uio_rw == UIO_WRITE && cnt != len ) { 1751 ptr += cnt; 1752 len -= cnt; 1753 cnt = 0; 1754 goto again; 1755 } 1756 } 1757 1758 /* 1759 * clear timeouts 1760 */ 1761 s = splsoftclock(); 1762 if( ISSET(mp->mp_flags, MBPPF_TIMEOUT) ) { 1763 callout_stop(&mp->mp_timeout_ch); 1764 CLR(mp->mp_flags, MBPPF_TIMEOUT); 1765 } 1766 if( ISSET(mp->mp_flags, MBPPF_DELAY) ) { 1767 callout_stop(&mp->mp_start_ch); 1768 CLR(mp->mp_flags, MBPPF_DELAY); 1769 } 1770 splx(s); 1771 1772 /* 1773 * adjust for those chars that we uiomoved but never actually wrote 1774 */ 1775 if( uio->uio_rw == UIO_WRITE && cnt != len ) { 1776 uio->uio_resid += (len - cnt); 1777 } 1778 1779 free(buffer, M_DEVBUF); 1780 return(error); 1781 } 1782 1783 void 1784 mbpp_timeout(arg) 1785 void *arg; 1786 { 1787 struct mbpp_port *mp = arg; 1788 1789 CLR(mp->mp_flags, MBPPF_UIO | MBPPF_TIMEOUT); 1790 wakeup(mp); 1791 } 1792 1793 void 1794 mbpp_start(arg) 1795 void *arg; 1796 { 1797 struct mbpp_port *mp = arg; 1798 1799 CLR(mp->mp_flags, MBPPF_DELAY); 1800 wakeup(mp); 1801 } 1802 1803 int 1804 mbpp_send(mp, ptr, len) 1805 struct mbpp_port *mp; 1806 caddr_t ptr; 1807 int len; 1808 { 1809 int s; 1810 struct cd1400 *cd = mp->mp_cd1400; 1811 1812 /* set up io information */ 1813 mp->mp_ptr = ptr; 1814 mp->mp_cnt = len; 1815 1816 /* start transmitting */ 1817 s = spltty(); 1818 if( cd ) { 1819 cd1400_write_reg(cd, CD1400_CAR, 0); 1820 1821 /* output strobe width ~1microsecond */ 1822 cd1400_write_reg(cd, CD1400_TBPR, 10); 1823 1824 /* enable channel */ 1825 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_XMTEN); 1826 cd1400_write_reg(cd, CD1400_SRER, CD1400_SRER_TXRDY); 1827 } 1828 1829 /* ZZzzz... */ 1830 tsleep(mp, PCATCH | PZERO, "mbpp_send", 0); 1831 1832 /* stop transmitting */ 1833 if( cd ) { 1834 cd1400_write_reg(cd, CD1400_CAR, 0); 1835 1836 /* disable transmitter */ 1837 cd1400_write_reg(cd, CD1400_SRER, 0); 1838 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_XMTDIS); 1839 1840 /* flush fifo */ 1841 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET | CD1400_CCR_FTF); 1842 } 1843 splx(s); 1844 1845 /* return number of chars sent */ 1846 return(len - mp->mp_cnt); 1847 } 1848 1849 int 1850 mbpp_recv(mp, ptr, len) 1851 struct mbpp_port *mp; 1852 caddr_t ptr; 1853 int len; 1854 { 1855 int s; 1856 struct cd1400 *cd = mp->mp_cd1400; 1857 1858 /* set up io information */ 1859 mp->mp_ptr = ptr; 1860 mp->mp_cnt = len; 1861 1862 /* start receiving */ 1863 s = spltty(); 1864 if( cd ) { 1865 int rcor, rbpr; 1866 1867 cd1400_write_reg(cd, CD1400_CAR, 0); 1868 1869 /* input strobe at 100kbaud (10microseconds) */ 1870 cd1400_compute_baud(100000, cd->cd_clock, &rcor, &rbpr); 1871 cd1400_write_reg(cd, CD1400_RCOR, rcor); 1872 cd1400_write_reg(cd, CD1400_RBPR, rbpr); 1873 1874 /* rx threshold */ 1875 cd1400_write_reg(cd, CD1400_COR3, MBPP_RX_FIFO_THRESHOLD); 1876 cd1400_write_ccr(cd, CD1400_CCR_CMDCORCHG | CD1400_CCR_COR3); 1877 1878 /* enable channel */ 1879 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_RCVEN); 1880 cd1400_write_reg(cd, CD1400_SRER, CD1400_SRER_RXDATA); 1881 } 1882 1883 /* ZZzzz... */ 1884 tsleep(mp, PCATCH | PZERO, "mbpp_recv", 0); 1885 1886 /* stop receiving */ 1887 if( cd ) { 1888 cd1400_write_reg(cd, CD1400_CAR, 0); 1889 1890 /* disable receiving */ 1891 cd1400_write_reg(cd, CD1400_SRER, 0); 1892 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_RCVDIS); 1893 } 1894 splx(s); 1895 1896 /* return number of chars received */ 1897 return(len - mp->mp_cnt); 1898 } 1899 1900 int 1901 mbpp_hztoms(h) 1902 int h; 1903 { 1904 int m = h; 1905 1906 if( m > 0 ) 1907 m = m * 1000 / hz; 1908 return(m); 1909 } 1910 1911 int 1912 mbpp_mstohz(m) 1913 int m; 1914 { 1915 int h = m; 1916 1917 if( h > 0 ) { 1918 h = h * hz / 1000; 1919 if( h == 0 ) 1920 h = 1000 / hz; 1921 } 1922 return(h); 1923 } 1924 1925 #endif /* NMAGMA */ 1926
Indexes created Fri Sep 26 08:10:20 GMT 2025