magma.c revision 1.18
1 /* $NetBSD: magma.c,v 1.18 2002/09/27 20:41:32 thorpej Exp $ */ 2 /* 3 * magma.c 4 * 5 * Copyright (c) 1998 Iain Hibbert 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Iain Hibbert 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35 /* 36 * Driver for Magma SBus Serial/Parallel cards using the Cirrus Logic 37 * CD1400 & CD1190 chips 38 */ 39 40 #include <sys/cdefs.h> 41 __KERNEL_RCSID(0, "$NetBSD: magma.c,v 1.18 2002/09/27 20:41:32 thorpej Exp $"); 42 43 #if 0 44 #define MAGMA_DEBUG 45 #endif 46 47 #include "magma.h" 48 #if NMAGMA > 0 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/proc.h> 53 #include <sys/device.h> 54 #include <sys/file.h> 55 #include <sys/ioctl.h> 56 #include <sys/malloc.h> 57 #include <sys/tty.h> 58 #include <sys/time.h> 59 #include <sys/kernel.h> 60 #include <sys/syslog.h> 61 #include <sys/conf.h> 62 #include <sys/errno.h> 63 64 #include <machine/bus.h> 65 #include <machine/intr.h> 66 #include <machine/autoconf.h> 67 68 #include <dev/sbus/sbusvar.h> 69 70 #include <dev/ic/cd1400reg.h> 71 #include <dev/ic/cd1190reg.h> 72 73 #include <dev/sbus/mbppio.h> 74 #include <dev/sbus/magmareg.h> 75 76 /* 77 * Select tty soft interrupt bit based on TTY ipl. (stole from zs.c) 78 */ 79 #if PIL_TTY == 1 80 # define IE_MSOFT IE_L1 81 #elif PIL_TTY == 4 82 # define IE_MSOFT IE_L4 83 #elif PIL_TTY == 6 84 # define IE_MSOFT IE_L6 85 #else 86 # error "no suitable software interrupt bit" 87 #endif 88 89 /* supported cards 90 * 91 * The table below lists the cards that this driver is likely to 92 * be able to support. 93 * 94 * Cards with parallel ports: except for the LC2+1Sp, they all use 95 * the CD1190 chip which I know nothing about. I've tried to leave 96 * hooks for it so it shouldn't be too hard to add support later. 97 * (I think somebody is working on this separately) 98 * 99 * Thanks to Bruce at Magma for telling me the hardware offsets. 100 */ 101 static struct magma_board_info supported_cards[] = { 102 { 103 "MAGMA_Sp", "MAGMA,4_Sp", "Magma 4 Sp", 4, 0, 104 1, 0xa000, 0xc000, 0xe000, { 0x8000, 0, 0, 0 }, 105 0, { 0, 0 } 106 }, 107 { 108 "MAGMA_Sp", "MAGMA,8_Sp", "Magma 8 Sp", 8, 0, 109 2, 0xa000, 0xc000, 0xe000, { 0x4000, 0x6000, 0, 0 }, 110 0, { 0, 0 } 111 }, 112 { 113 "MAGMA_Sp", "MAGMA,_8HS_Sp", "Magma Fast 8 Sp", 8, 0, 114 2, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0, 0 }, 115 0, { 0, 0 } 116 }, 117 { 118 "MAGMA_Sp", "MAGMA,_8SP_422", "Magma 8 Sp - 422", 8, 0, 119 2, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0, 0 }, 120 0, { 0, 0 } 121 }, 122 { 123 "MAGMA_Sp", "MAGMA,12_Sp", "Magma 12 Sp", 12, 0, 124 3, 0xa000, 0xc000, 0xe000, { 0x2000, 0x4000, 0x6000, 0 }, 125 0, { 0, 0 } 126 }, 127 { 128 "MAGMA_Sp", "MAGMA,16_Sp", "Magma 16 Sp", 16, 0, 129 4, 0xd000, 0xe000, 0xf000, { 0x8000, 0x9000, 0xa000, 0xb000 }, 130 0, { 0, 0 } 131 }, 132 { 133 "MAGMA_Sp", "MAGMA,16_Sp_2", "Magma 16 Sp", 16, 0, 134 4, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0xc000, 0xe000 }, 135 0, { 0, 0 } 136 }, 137 { 138 "MAGMA_Sp", "MAGMA,16HS_Sp", "Magma Fast 16 Sp", 16, 0, 139 4, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0xc000, 0xe000 }, 140 0, { 0, 0 } 141 }, 142 { 143 "MAGMA_Sp", "MAGMA,21_Sp", "Magma LC 2+1 Sp", 2, 1, 144 1, 0xa000, 0xc000, 0xe000, { 0x8000, 0, 0, 0 }, 145 0, { 0, 0 } 146 }, 147 { 148 "MAGMA_Sp", "MAGMA,21HS_Sp", "Magma 2+1 Sp", 2, 1, 149 1, 0xa000, 0xc000, 0xe000, { 0x4000, 0, 0, 0 }, 150 1, { 0x6000, 0 } 151 }, 152 { 153 "MAGMA_Sp", "MAGMA,41_Sp", "Magma 4+1 Sp", 4, 1, 154 1, 0xa000, 0xc000, 0xe000, { 0x4000, 0, 0, 0 }, 155 1, { 0x6000, 0 } 156 }, 157 { 158 "MAGMA_Sp", "MAGMA,82_Sp", "Magma 8+2 Sp", 8, 2, 159 2, 0xd000, 0xe000, 0xf000, { 0x8000, 0x9000, 0, 0 }, 160 2, { 0xa000, 0xb000 } 161 }, 162 { 163 "MAGMA_Sp", "MAGMA,P1_Sp", "Magma P1 Sp", 0, 1, 164 0, 0, 0, 0, { 0, 0, 0, 0 }, 165 1, { 0x8000, 0 } 166 }, 167 { 168 "MAGMA_Sp", "MAGMA,P2_Sp", "Magma P2 Sp", 0, 2, 169 0, 0, 0, 0, { 0, 0, 0, 0 }, 170 2, { 0x4000, 0x8000 } 171 }, 172 { 173 "MAGMA 2+1HS Sp", "", "Magma 2+1HS Sp", 2, 0, 174 1, 0xa000, 0xc000, 0xe000, { 0x4000, 0, 0, 0 }, 175 1, { 0x8000, 0 } 176 }, 177 { 178 NULL, NULL, NULL, 0, 0, 179 0, 0, 0, 0, { 0, 0, 0, 0 }, 180 0, { 0, 0 } 181 } 182 }; 183 184 /************************************************************************ 185 * 186 * Autoconfig Stuff 187 */ 188 189 const struct cfattach magma_ca = { 190 sizeof(struct magma_softc), magma_match, magma_attach 191 }; 192 193 const struct cfattach mtty_ca = { 194 sizeof(struct mtty_softc), mtty_match, mtty_attach 195 }; 196 197 const struct cfattach mbpp_ca = { 198 sizeof(struct mbpp_softc), mbpp_match, mbpp_attach 199 }; 200 201 extern struct cfdriver mtty_cd; 202 extern struct cfdriver mbpp_cd; 203 204 dev_type_open(mttyopen); 205 dev_type_close(mttyclose); 206 dev_type_read(mttyread); 207 dev_type_write(mttywrite); 208 dev_type_ioctl(mttyioctl); 209 dev_type_stop(mttystop); 210 dev_type_tty(mttytty); 211 dev_type_poll(mttypoll); 212 213 const struct cdevsw mtty_cdevsw = { 214 mttyopen, mttyclose, mttyread, mttywrite, mttyioctl, 215 mttystop, mttytty, mttypoll, nommap, D_TTY 216 }; 217 218 dev_type_open(mbppopen); 219 dev_type_close(mbppclose); 220 dev_type_read(mbpp_rw); 221 dev_type_ioctl(mbppioctl); 222 223 const struct cdevsw mbpp_cdevsw = { 224 mbppopen, mbppclose, mbpp_rw, mbpp_rw, mbppioctl, 225 nostop, notty, nopoll, nommap, 226 }; 227 228 /************************************************************************ 229 * 230 * CD1400 Routines 231 * 232 * cd1400_compute_baud calculate COR/BPR register values 233 * cd1400_write_ccr write a value to CD1400 ccr 234 * cd1400_read_reg read from a CD1400 register 235 * cd1400_write_reg write to a CD1400 register 236 * cd1400_enable_transmitter enable transmitting on CD1400 channel 237 */ 238 239 /* 240 * compute the bpr/cor pair for any baud rate 241 * returns 0 for success, 1 for failure 242 */ 243 int 244 cd1400_compute_baud(speed, clock, cor, bpr) 245 speed_t speed; 246 int clock; 247 int *cor, *bpr; 248 { 249 int c, co, br; 250 251 if( speed < 50 || speed > 150000 ) 252 return(1); 253 254 for( c = 0, co = 8 ; co <= 2048 ; co <<= 2, c++ ) { 255 br = ((clock * 1000000) + (co * speed) / 2) / (co * speed); 256 if( br < 0x100 ) { 257 *bpr = br; 258 *cor = c; 259 return(0); 260 } 261 } 262 263 return(1); 264 } 265 266 /* 267 * Write a CD1400 channel command, should have a timeout? 268 */ 269 __inline void 270 cd1400_write_ccr(cd, cmd) 271 struct cd1400 *cd; 272 u_char cmd; 273 { 274 while( cd1400_read_reg(cd, CD1400_CCR) ) 275 ; 276 277 cd1400_write_reg(cd, CD1400_CCR, cmd); 278 } 279 280 /* 281 * read a value from a cd1400 register 282 */ 283 __inline u_char 284 cd1400_read_reg(cd, reg) 285 struct cd1400 *cd; 286 int reg; 287 { 288 return(cd->cd_reg[reg]); 289 } 290 291 /* 292 * write a value to a cd1400 register 293 */ 294 __inline void 295 cd1400_write_reg(cd, reg, value) 296 struct cd1400 *cd; 297 int reg; 298 u_char value; 299 { 300 cd->cd_reg[reg] = value; 301 } 302 303 /* 304 * enable transmit service requests for cd1400 channel 305 */ 306 void 307 cd1400_enable_transmitter(cd, channel) 308 struct cd1400 *cd; 309 int channel; 310 { 311 int s, srer; 312 313 s = spltty(); 314 cd1400_write_reg(cd, CD1400_CAR, channel); 315 srer = cd1400_read_reg(cd, CD1400_SRER); 316 SET(srer, CD1400_SRER_TXRDY); 317 cd1400_write_reg(cd, CD1400_SRER, srer); 318 splx(s); 319 } 320 321 /************************************************************************ 322 * 323 * CD1190 Routines 324 */ 325 326 /* well, there are none yet */ 327 328 /************************************************************************ 329 * 330 * Magma Routines 331 * 332 * magma_match reports if we have a magma board available 333 * magma_attach attaches magma boards to the sbus 334 * magma_hard hardware level interrupt routine 335 * magma_soft software level interrupt routine 336 */ 337 338 int 339 magma_match(parent, cf, aux) 340 struct device *parent; 341 struct cfdata *cf; 342 void *aux; 343 { 344 struct sbus_attach_args *sa = aux; 345 struct magma_board_info *card; 346 347 /* See if we support this device */ 348 for (card = supported_cards; ; card++) { 349 if (card->mb_sbusname == NULL) 350 /* End of table: no match */ 351 return (0); 352 if (strcmp(sa->sa_name, card->mb_sbusname) == 0) 353 break; 354 } 355 356 dprintf(("magma: matched `%s'\n", sa->sa_name)); 357 dprintf(("magma: magma_prom `%s'\n", 358 PROM_getpropstring(sa->sa_node, "magma_prom"))); 359 dprintf(("magma: intlevels `%s'\n", 360 PROM_getpropstring(sa->sa_node, "intlevels"))); 361 dprintf(("magma: chiprev `%s'\n", 362 PROM_getpropstring(sa->sa_node, "chiprev"))); 363 dprintf(("magma: clock `%s'\n", 364 PROM_getpropstring(sa->sa_node, "clock"))); 365 366 return (1); 367 } 368 369 void 370 magma_attach(parent, self, aux) 371 struct device *parent; 372 struct device *self; 373 void *aux; 374 { 375 struct sbus_attach_args *sa = aux; 376 struct magma_softc *sc = (struct magma_softc *)self; 377 struct magma_board_info *card; 378 bus_space_handle_t bh; 379 char *magma_prom, *clockstr; 380 int cd_clock; 381 int node, chip; 382 383 node = sa->sa_node; 384 385 /* 386 * Find the card model. 387 * Older models all have sbus node name `MAGMA_Sp' (see 388 * `supported_cards[]' above), and must be distinguished 389 * by the `magma_prom' property. 390 */ 391 magma_prom = PROM_getpropstring(node, "magma_prom"); 392 393 for (card = supported_cards; card->mb_name != NULL; card++) { 394 if (strcmp(sa->sa_name, card->mb_sbusname) != 0) 395 /* Sbus node name doesn't match */ 396 continue; 397 if (strcmp(magma_prom, card->mb_name) == 0) 398 /* Model name match */ 399 break; 400 } 401 402 if( card->mb_name == NULL ) { 403 printf(": %s (unsupported)\n", magma_prom); 404 return; 405 } 406 407 dprintf((" addr %p", sc)); 408 printf(" softpri %d: %s\n", PIL_TTY, card->mb_realname); 409 410 sc->ms_board = card; 411 sc->ms_ncd1400 = card->mb_ncd1400; 412 sc->ms_ncd1190 = card->mb_ncd1190; 413 414 if (sbus_bus_map(sa->sa_bustag, 415 sa->sa_slot, sa->sa_offset, sa->sa_size, 416 BUS_SPACE_MAP_LINEAR, &bh) != 0) { 417 printf("%s @ sbus: cannot map registers\n", self->dv_xname); 418 return; 419 } 420 421 /* the SVCACK* lines are daisychained */ 422 sc->ms_svcackr = (caddr_t)bus_space_vaddr(sa->sa_bustag, bh) 423 + card->mb_svcackr; 424 sc->ms_svcackt = (caddr_t)bus_space_vaddr(sa->sa_bustag, bh) 425 + card->mb_svcackt; 426 sc->ms_svcackm = (caddr_t)bus_space_vaddr(sa->sa_bustag, bh) 427 + card->mb_svcackm; 428 429 /* 430 * Find the clock speed; it's the same for all CD1400 chips 431 * on the board. 432 */ 433 clockstr = PROM_getpropstring(node, "clock"); 434 if (*clockstr == '\0') 435 /* Default to 25MHz */ 436 cd_clock = 25; 437 else { 438 cd_clock = 0; 439 while (*clockstr != '\0') 440 cd_clock = (cd_clock * 10) + (*clockstr++ - '0'); 441 } 442 443 /* init the cd1400 chips */ 444 for( chip = 0 ; chip < card->mb_ncd1400 ; chip++ ) { 445 struct cd1400 *cd = &sc->ms_cd1400[chip]; 446 447 cd->cd_clock = cd_clock; 448 cd->cd_reg = (caddr_t)bh + card->mb_cd1400[chip]; 449 450 /* PROM_getpropstring(node, "chiprev"); */ 451 /* seemingly the Magma drivers just ignore the propstring */ 452 cd->cd_chiprev = cd1400_read_reg(cd, CD1400_GFRCR); 453 454 dprintf(("%s attach CD1400 %d addr %p rev %x clock %dMhz\n", 455 sc->ms_dev.dv_xname, chip, 456 cd->cd_reg, cd->cd_chiprev, cd->cd_clock)); 457 458 /* clear GFRCR */ 459 cd1400_write_reg(cd, CD1400_GFRCR, 0x00); 460 461 /* reset whole chip */ 462 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET | CD1400_CCR_FULLRESET); 463 464 /* wait for revision code to be restored */ 465 while( cd1400_read_reg(cd, CD1400_GFRCR) != cd->cd_chiprev ) 466 ; 467 468 /* set the Prescaler Period Register to tick at 1ms */ 469 cd1400_write_reg(cd, CD1400_PPR, 470 ((cd->cd_clock * 1000000 / CD1400_PPR_PRESCALER + 500) / 1000)); 471 472 /* The LC2+1Sp card is the only card that doesn't have 473 * a CD1190 for the parallel port, but uses channel 0 of 474 * the CD1400, so we make a note of it for later and set up 475 * the CD1400 for parallel mode operation. 476 */ 477 if( card->mb_npar && card->mb_ncd1190 == 0 ) { 478 cd1400_write_reg(cd, CD1400_GCR, CD1400_GCR_PARALLEL); 479 cd->cd_parmode = 1; 480 } 481 } 482 483 /* init the cd1190 chips */ 484 for( chip = 0 ; chip < card->mb_ncd1190 ; chip++ ) { 485 struct cd1190 *cd = &sc->ms_cd1190[chip]; 486 487 cd->cd_reg = (caddr_t)bh + card->mb_cd1190[chip]; 488 489 /* XXX don't know anything about these chips yet */ 490 printf("%s: CD1190 %d addr %p (unsupported)\n", 491 self->dv_xname, chip, cd->cd_reg); 492 } 493 494 sbus_establish(&sc->ms_sd, &sc->ms_dev); 495 496 /* configure the children */ 497 (void)config_found(self, mtty_match, NULL); 498 (void)config_found(self, mbpp_match, NULL); 499 500 /* 501 * Establish the interrupt handlers. 502 */ 503 if (sa->sa_nintr == 0) 504 return; /* No interrupts to service!? */ 505 506 (void)bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_TTY, 507 0, magma_hard, sc); 508 (void)bus_intr_establish(sa->sa_bustag, PIL_TTY, IPL_SOFTSERIAL, 509 BUS_INTR_ESTABLISH_SOFTINTR, 510 magma_soft, sc); 511 evcnt_attach_dynamic(&sc->ms_intrcnt, EVCNT_TYPE_INTR, NULL, 512 sc->ms_dev.dv_xname, "intr"); 513 } 514 515 /* 516 * hard interrupt routine 517 * 518 * returns 1 if it handled it, otherwise 0 519 * 520 * runs at interrupt priority 521 */ 522 int 523 magma_hard(arg) 524 void *arg; 525 { 526 struct magma_softc *sc = arg; 527 struct cd1400 *cd; 528 int chip, status = 0; 529 int serviced = 0; 530 int needsoftint = 0; 531 532 /* 533 * check status of all the CD1400 chips 534 */ 535 for( chip = 0 ; chip < sc->ms_ncd1400 ; chip++ ) 536 status |= cd1400_read_reg(&sc->ms_cd1400[chip], CD1400_SVRR); 537 538 if( ISSET(status, CD1400_SVRR_RXRDY) ) { 539 u_char rivr = *sc->ms_svcackr; /* enter rx service context */ 540 int port = rivr >> 4; 541 542 if( rivr & (1<<3) ) { /* parallel port */ 543 struct mbpp_port *mbpp; 544 int n_chars; 545 546 mbpp = &sc->ms_mbpp->ms_port[port]; 547 cd = mbpp->mp_cd1400; 548 549 /* don't think we have to handle exceptions */ 550 n_chars = cd1400_read_reg(cd, CD1400_RDCR); 551 while (n_chars--) { 552 if( mbpp->mp_cnt == 0 ) { 553 SET(mbpp->mp_flags, MBPPF_WAKEUP); 554 needsoftint = 1; 555 break; 556 } 557 *mbpp->mp_ptr = cd1400_read_reg(cd,CD1400_RDSR); 558 mbpp->mp_ptr++; 559 mbpp->mp_cnt--; 560 } 561 } else { /* serial port */ 562 struct mtty_port *mtty; 563 u_char *ptr, n_chars, line_stat; 564 565 mtty = &sc->ms_mtty->ms_port[port]; 566 cd = mtty->mp_cd1400; 567 568 if( ISSET(rivr, CD1400_RIVR_EXCEPTION) ) { 569 line_stat = cd1400_read_reg(cd, CD1400_RDSR); 570 n_chars = 1; 571 } else { /* no exception, received data OK */ 572 line_stat = 0; 573 n_chars = cd1400_read_reg(cd, CD1400_RDCR); 574 } 575 576 ptr = mtty->mp_rput; 577 while( n_chars-- ) { 578 *ptr++ = line_stat; 579 *ptr++ = cd1400_read_reg(cd, CD1400_RDSR); 580 if( ptr == mtty->mp_rend ) ptr = mtty->mp_rbuf; 581 if( ptr == mtty->mp_rget ) { 582 if( ptr == mtty->mp_rbuf ) 583 ptr = mtty->mp_rend; 584 ptr -= 2; 585 SET(mtty->mp_flags, MTTYF_RING_OVERFLOW); 586 break; 587 } 588 } 589 mtty->mp_rput = ptr; 590 591 needsoftint = 1; 592 } 593 594 cd1400_write_reg(cd, CD1400_EOSRR, 0); /* end service context */ 595 serviced = 1; 596 } /* if(rx_service...) */ 597 598 if( ISSET(status, CD1400_SVRR_MDMCH) ) { 599 u_char mivr = *sc->ms_svcackm; /* enter mdm service context */ 600 int port = mivr >> 4; 601 struct mtty_port *mtty; 602 int carrier; 603 u_char msvr; 604 605 /* 606 * Handle CD (LC2+1Sp = DSR) changes. 607 */ 608 mtty = &sc->ms_mtty->ms_port[port]; 609 cd = mtty->mp_cd1400; 610 msvr = cd1400_read_reg(cd, CD1400_MSVR2); 611 carrier = ISSET(msvr, cd->cd_parmode ? CD1400_MSVR2_DSR : CD1400_MSVR2_CD); 612 613 if( mtty->mp_carrier != carrier ) { 614 SET(mtty->mp_flags, MTTYF_CARRIER_CHANGED); 615 mtty->mp_carrier = carrier; 616 needsoftint = 1; 617 } 618 619 cd1400_write_reg(cd, CD1400_EOSRR, 0); /* end service context */ 620 serviced = 1; 621 } /* if(mdm_service...) */ 622 623 if( ISSET(status, CD1400_SVRR_TXRDY) ) { 624 u_char tivr = *sc->ms_svcackt; /* enter tx service context */ 625 int port = tivr >> 4; 626 627 if( tivr & (1<<3) ) { /* parallel port */ 628 struct mbpp_port *mbpp; 629 630 mbpp = &sc->ms_mbpp->ms_port[port]; 631 cd = mbpp->mp_cd1400; 632 633 if( mbpp->mp_cnt ) { 634 int count = 0; 635 636 /* fill the fifo */ 637 while (mbpp->mp_cnt && 638 count++ < CD1400_PAR_FIFO_SIZE) { 639 cd1400_write_reg(cd, CD1400_TDR, 640 *mbpp->mp_ptr); 641 mbpp->mp_ptr++; 642 mbpp->mp_cnt--; 643 } 644 } else { 645 /* 646 * fifo is empty and we got no more data 647 * to send, so shut off interrupts and 648 * signal for a wakeup, which can't be 649 * done here in case we beat mbpp_send to 650 * the tsleep call (we are running at >spltty) 651 */ 652 cd1400_write_reg(cd, CD1400_SRER, 0); 653 SET(mbpp->mp_flags, MBPPF_WAKEUP); 654 needsoftint = 1; 655 } 656 } else { /* serial port */ 657 struct mtty_port *mtty; 658 struct tty *tp; 659 660 mtty = &sc->ms_mtty->ms_port[port]; 661 cd = mtty->mp_cd1400; 662 tp = mtty->mp_tty; 663 664 if( !ISSET(mtty->mp_flags, MTTYF_STOP) ) { 665 int count = 0; 666 667 /* check if we should start/stop a break */ 668 if( ISSET(mtty->mp_flags, MTTYF_SET_BREAK) ) { 669 cd1400_write_reg(cd, CD1400_TDR, 0); 670 cd1400_write_reg(cd, CD1400_TDR, 0x81); 671 /* should we delay too? */ 672 CLR(mtty->mp_flags, MTTYF_SET_BREAK); 673 count += 2; 674 } 675 676 if( ISSET(mtty->mp_flags, MTTYF_CLR_BREAK) ) { 677 cd1400_write_reg(cd, CD1400_TDR, 0); 678 cd1400_write_reg(cd, CD1400_TDR, 0x83); 679 CLR(mtty->mp_flags, MTTYF_CLR_BREAK); 680 count += 2; 681 } 682 683 /* I don't quite fill the fifo in case the last one is a 684 * NULL which I have to double up because its the escape 685 * code for embedded transmit characters. 686 */ 687 while( mtty->mp_txc > 0 && count < CD1400_TX_FIFO_SIZE - 1 ) { 688 u_char ch; 689 690 ch = *mtty->mp_txp; 691 692 mtty->mp_txc--; 693 mtty->mp_txp++; 694 695 if( ch == 0 ) { 696 cd1400_write_reg(cd, CD1400_TDR, ch); 697 count++; 698 } 699 700 cd1400_write_reg(cd, CD1400_TDR, ch); 701 count++; 702 } 703 } 704 705 /* if we ran out of work or are requested to STOP then 706 * shut off the txrdy interrupts and signal DONE to flush 707 * out the chars we have sent. 708 */ 709 if( mtty->mp_txc == 0 || ISSET(mtty->mp_flags, MTTYF_STOP) ) { 710 register int srer; 711 712 srer = cd1400_read_reg(cd, CD1400_SRER); 713 CLR(srer, CD1400_SRER_TXRDY); 714 cd1400_write_reg(cd, CD1400_SRER, srer); 715 CLR(mtty->mp_flags, MTTYF_STOP); 716 717 SET(mtty->mp_flags, MTTYF_DONE); 718 needsoftint = 1; 719 } 720 } 721 722 cd1400_write_reg(cd, CD1400_EOSRR, 0); /* end service context */ 723 serviced = 1; 724 } /* if(tx_service...) */ 725 726 /* XXX service CD1190 interrupts too 727 for( chip = 0 ; chip < sc->ms_ncd1190 ; chip++ ) { 728 } 729 */ 730 731 if( needsoftint ) { /* trigger the soft interrupt */ 732 #if defined(SUN4M) 733 if( CPU_ISSUN4M ) 734 raise(0, PIL_TTY); 735 else 736 #endif 737 ienab_bis(IE_MSOFT); 738 } 739 740 return(serviced); 741 } 742 743 /* 744 * magma soft interrupt handler 745 * 746 * returns 1 if it handled it, 0 otherwise 747 * 748 * runs at spltty() 749 */ 750 int 751 magma_soft(arg) 752 void *arg; 753 { 754 struct magma_softc *sc = arg; 755 struct mtty_softc *mtty = sc->ms_mtty; 756 struct mbpp_softc *mbpp = sc->ms_mbpp; 757 int port; 758 int serviced = 0; 759 int s, flags; 760 761 if (mtty == NULL) 762 goto chkbpp; 763 764 /* 765 * check the tty ports to see what needs doing 766 */ 767 for( port = 0 ; port < mtty->ms_nports ; port++ ) { 768 struct mtty_port *mp = &mtty->ms_port[port]; 769 struct tty *tp = mp->mp_tty; 770 771 if( !ISSET(tp->t_state, TS_ISOPEN) ) 772 continue; 773 774 /* 775 * handle any received data 776 */ 777 while( mp->mp_rget != mp->mp_rput ) { 778 u_char stat; 779 int data; 780 781 stat = mp->mp_rget[0]; 782 data = mp->mp_rget[1]; 783 mp->mp_rget = ((mp->mp_rget + 2) == mp->mp_rend) 784 ? mp->mp_rbuf : (mp->mp_rget + 2); 785 786 if( stat & (CD1400_RDSR_BREAK | CD1400_RDSR_FE) ) 787 data |= TTY_FE; 788 if( stat & CD1400_RDSR_PE ) 789 data |= TTY_PE; 790 791 if( stat & CD1400_RDSR_OE ) 792 log(LOG_WARNING, "%s%x: fifo overflow\n", 793 mtty->ms_dev.dv_xname, port); 794 795 (*tp->t_linesw->l_rint)(data, tp); 796 serviced = 1; 797 } 798 799 s = splhigh(); /* block out hard interrupt routine */ 800 flags = mp->mp_flags; 801 CLR(mp->mp_flags, MTTYF_DONE | MTTYF_CARRIER_CHANGED | MTTYF_RING_OVERFLOW); 802 splx(s); /* ok */ 803 804 if( ISSET(flags, MTTYF_CARRIER_CHANGED) ) { 805 dprintf(("%s%x: cd %s\n", mtty->ms_dev.dv_xname, 806 port, mp->mp_carrier ? "on" : "off")); 807 (*tp->t_linesw->l_modem)(tp, mp->mp_carrier); 808 serviced = 1; 809 } 810 811 if( ISSET(flags, MTTYF_RING_OVERFLOW) ) { 812 log(LOG_WARNING, "%s%x: ring buffer overflow\n", 813 mtty->ms_dev.dv_xname, port); 814 serviced = 1; 815 } 816 817 if( ISSET(flags, MTTYF_DONE) ) { 818 ndflush(&tp->t_outq, mp->mp_txp - tp->t_outq.c_cf); 819 CLR(tp->t_state, TS_BUSY); 820 (*tp->t_linesw->l_start)(tp); /* might be some more */ 821 serviced = 1; 822 } 823 } /* for(each mtty...) */ 824 825 826 chkbpp: 827 /* 828 * Check the bpp ports (if any) to see what needs doing 829 */ 830 if (mbpp == NULL) 831 return (serviced); 832 833 for( port = 0 ; port < mbpp->ms_nports ; port++ ) { 834 struct mbpp_port *mp = &mbpp->ms_port[port]; 835 836 if( !ISSET(mp->mp_flags, MBPPF_OPEN) ) 837 continue; 838 839 s = splhigh(); 840 flags = mp->mp_flags; 841 CLR(mp->mp_flags, MBPPF_WAKEUP); 842 splx(s); 843 844 if( ISSET(flags, MBPPF_WAKEUP) ) { 845 wakeup(mp); 846 serviced = 1; 847 } 848 849 } /* for(each mbpp...) */ 850 851 return(serviced); 852 } 853 854 /************************************************************************ 855 * 856 * MTTY Routines 857 * 858 * mtty_match match one mtty device 859 * mtty_attach attach mtty devices 860 * mttyopen open mtty device 861 * mttyclose close mtty device 862 * mttyread read from mtty 863 * mttywrite write to mtty 864 * mttyioctl do ioctl on mtty 865 * mttytty return tty pointer for mtty 866 * mttystop stop mtty device 867 * mtty_start start mtty device 868 * mtty_param set mtty parameters 869 * mtty_modem_control set modem control lines 870 */ 871 872 int 873 mtty_match(parent, cf, args) 874 struct device *parent; 875 struct cfdata *cf; 876 void *args; 877 { 878 struct magma_softc *sc = (struct magma_softc *)parent; 879 880 return( args == mtty_match && sc->ms_board->mb_nser && sc->ms_mtty == NULL ); 881 } 882 883 void 884 mtty_attach(parent, dev, args) 885 struct device *parent; 886 struct device *dev; 887 void *args; 888 { 889 struct magma_softc *sc = (struct magma_softc *)parent; 890 struct mtty_softc *ms = (struct mtty_softc *)dev; 891 int port, chip, chan; 892 893 sc->ms_mtty = ms; 894 dprintf((" addr %p", ms)); 895 896 for( port = 0, chip = 0, chan = 0 ; port < sc->ms_board->mb_nser ; port++ ) { 897 struct mtty_port *mp = &ms->ms_port[port]; 898 struct tty *tp; 899 900 mp->mp_cd1400 = &sc->ms_cd1400[chip]; 901 if (mp->mp_cd1400->cd_parmode && chan == 0) 902 chan = 1; /* skip channel 0 if parmode */ 903 mp->mp_channel = chan; 904 905 tp = ttymalloc(); 906 if (tp == NULL) break; 907 tty_attach(tp); 908 tp->t_oproc = mtty_start; 909 tp->t_param = mtty_param; 910 911 mp->mp_tty = tp; 912 913 mp->mp_rbuf = malloc(MTTY_RBUF_SIZE, M_DEVBUF, M_NOWAIT); 914 if (mp->mp_rbuf == NULL) break; 915 916 mp->mp_rend = mp->mp_rbuf + MTTY_RBUF_SIZE; 917 918 chan = (chan + 1) % CD1400_NO_OF_CHANNELS; 919 if (chan == 0) 920 chip++; 921 } 922 923 ms->ms_nports = port; 924 printf(": %d tty%s\n", port, port == 1 ? "" : "s"); 925 } 926 927 /* 928 * open routine. returns zero if successful, else error code 929 */ 930 int 931 mttyopen(dev, flags, mode, p) 932 dev_t dev; 933 int flags; 934 int mode; 935 struct proc *p; 936 { 937 int card = MAGMA_CARD(dev); 938 int port = MAGMA_PORT(dev); 939 struct mtty_softc *ms; 940 struct mtty_port *mp; 941 struct tty *tp; 942 struct cd1400 *cd; 943 int error, s; 944 945 if( card >= mtty_cd.cd_ndevs || 946 (ms = mtty_cd.cd_devs[card]) == NULL || port >= ms->ms_nports ) 947 return(ENXIO); /* device not configured */ 948 949 mp = &ms->ms_port[port]; 950 tp = mp->mp_tty; 951 tp->t_dev = dev; 952 953 if (ISSET(tp->t_state, TS_ISOPEN) && 954 ISSET(tp->t_state, TS_XCLUDE) && 955 p->p_ucred->cr_uid != 0) 956 return (EBUSY); 957 958 s = spltty(); 959 960 if( !ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 961 962 /* set defaults */ 963 ttychars(tp); 964 tp->t_iflag = TTYDEF_IFLAG; 965 tp->t_oflag = TTYDEF_OFLAG; 966 tp->t_cflag = TTYDEF_CFLAG; 967 if( ISSET(mp->mp_openflags, TIOCFLAG_CLOCAL) ) 968 SET(tp->t_cflag, CLOCAL); 969 if( ISSET(mp->mp_openflags, TIOCFLAG_CRTSCTS) ) 970 SET(tp->t_cflag, CRTSCTS); 971 if( ISSET(mp->mp_openflags, TIOCFLAG_MDMBUF) ) 972 SET(tp->t_cflag, MDMBUF); 973 tp->t_lflag = TTYDEF_LFLAG; 974 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 975 976 /* init ring buffer */ 977 mp->mp_rput = mp->mp_rget = mp->mp_rbuf; 978 979 /* reset CD1400 channel */ 980 cd = mp->mp_cd1400; 981 cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel); 982 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET); 983 984 /* encode the port number in top half of LIVR */ 985 cd1400_write_reg(cd, CD1400_LIVR, port << 4 ); 986 987 /* sets parameters and raises DTR */ 988 (void)mtty_param(tp, &tp->t_termios); 989 990 /* set tty watermarks */ 991 ttsetwater(tp); 992 993 /* enable service requests */ 994 cd1400_write_reg(cd, CD1400_SRER, 995 CD1400_SRER_RXDATA | CD1400_SRER_MDMCH); 996 997 /* tell the tty about the carrier status */ 998 if( ISSET(mp->mp_openflags, TIOCFLAG_SOFTCAR) || 999 mp->mp_carrier ) 1000 SET(tp->t_state, TS_CARR_ON); 1001 else 1002 CLR(tp->t_state, TS_CARR_ON); 1003 } 1004 splx(s); 1005 1006 error = ttyopen(tp, MTTY_DIALOUT(dev), ISSET(flags, O_NONBLOCK)); 1007 if (error != 0) 1008 goto bad; 1009 1010 error = (*tp->t_linesw->l_open)(dev, tp); 1011 if (error != 0) 1012 goto bad; 1013 1014 bad: 1015 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1016 /* 1017 * We failed to open the device, and nobody else had it opened. 1018 * Clean up the state as appropriate. 1019 */ 1020 /* XXX - do that here */ 1021 } 1022 1023 return (error); 1024 } 1025 1026 /* 1027 * close routine. returns zero if successful, else error code 1028 */ 1029 int 1030 mttyclose(dev, flag, mode, p) 1031 dev_t dev; 1032 int flag; 1033 int mode; 1034 struct proc *p; 1035 { 1036 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(dev)]; 1037 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1038 struct tty *tp = mp->mp_tty; 1039 int s; 1040 1041 (*tp->t_linesw->l_close)(tp, flag); 1042 ttyclose(tp); 1043 1044 s = spltty(); 1045 1046 /* if HUPCL is set, and the tty is no longer open 1047 * shut down the port 1048 */ 1049 if( ISSET(tp->t_cflag, HUPCL) || !ISSET(tp->t_state, TS_ISOPEN) ) { 1050 /* XXX wait until FIFO is empty before turning off the channel 1051 struct cd1400 *cd = mp->mp_cd1400; 1052 */ 1053 1054 /* drop DTR and RTS */ 1055 (void)mtty_modem_control(mp, 0, DMSET); 1056 1057 /* turn off the channel 1058 cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel); 1059 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET); 1060 */ 1061 } 1062 1063 splx(s); 1064 1065 return(0); 1066 } 1067 1068 /* 1069 * Read routine 1070 */ 1071 int 1072 mttyread(dev, uio, flags) 1073 dev_t dev; 1074 struct uio *uio; 1075 int flags; 1076 { 1077 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(dev)]; 1078 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1079 struct tty *tp = mp->mp_tty; 1080 1081 return( (*tp->t_linesw->l_read)(tp, uio, flags) ); 1082 } 1083 1084 /* 1085 * Write routine 1086 */ 1087 int 1088 mttywrite(dev, uio, flags) 1089 dev_t dev; 1090 struct uio *uio; 1091 int flags; 1092 { 1093 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(dev)]; 1094 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1095 struct tty *tp = mp->mp_tty; 1096 1097 return( (*tp->t_linesw->l_write)(tp, uio, flags) ); 1098 } 1099 1100 /* 1101 * Poll routine 1102 */ 1103 int 1104 mttypoll(dev, events, p) 1105 dev_t dev; 1106 int events; 1107 struct proc *p; 1108 { 1109 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(dev)]; 1110 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1111 struct tty *tp = mp->mp_tty; 1112 1113 return ((*tp->t_linesw->l_poll)(tp, events, p)); 1114 } 1115 1116 /* 1117 * return tty pointer 1118 */ 1119 struct tty * 1120 mttytty(dev) 1121 dev_t dev; 1122 { 1123 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(dev)]; 1124 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1125 1126 return(mp->mp_tty); 1127 } 1128 1129 /* 1130 * ioctl routine 1131 */ 1132 int 1133 mttyioctl(dev, cmd, data, flags, p) 1134 dev_t dev; 1135 u_long cmd; 1136 caddr_t data; 1137 int flags; 1138 struct proc *p; 1139 { 1140 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(dev)]; 1141 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1142 struct tty *tp = mp->mp_tty; 1143 int error; 1144 1145 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flags, p); 1146 if( error != EPASSTHROUGH ) return(error); 1147 1148 error = ttioctl(tp, cmd, data, flags, p); 1149 if( error != EPASSTHROUGH ) return(error); 1150 1151 error = 0; 1152 1153 switch(cmd) { 1154 case TIOCSBRK: /* set break */ 1155 SET(mp->mp_flags, MTTYF_SET_BREAK); 1156 cd1400_enable_transmitter(mp->mp_cd1400, mp->mp_channel); 1157 break; 1158 1159 case TIOCCBRK: /* clear break */ 1160 SET(mp->mp_flags, MTTYF_CLR_BREAK); 1161 cd1400_enable_transmitter(mp->mp_cd1400, mp->mp_channel); 1162 break; 1163 1164 case TIOCSDTR: /* set DTR */ 1165 mtty_modem_control(mp, TIOCM_DTR, DMBIS); 1166 break; 1167 1168 case TIOCCDTR: /* clear DTR */ 1169 mtty_modem_control(mp, TIOCM_DTR, DMBIC); 1170 break; 1171 1172 case TIOCMSET: /* set modem lines */ 1173 mtty_modem_control(mp, *((int *)data), DMSET); 1174 break; 1175 1176 case TIOCMBIS: /* bit set modem lines */ 1177 mtty_modem_control(mp, *((int *)data), DMBIS); 1178 break; 1179 1180 case TIOCMBIC: /* bit clear modem lines */ 1181 mtty_modem_control(mp, *((int *)data), DMBIC); 1182 break; 1183 1184 case TIOCMGET: /* get modem lines */ 1185 *((int *)data) = mtty_modem_control(mp, 0, DMGET); 1186 break; 1187 1188 case TIOCGFLAGS: 1189 *((int *)data) = mp->mp_openflags; 1190 break; 1191 1192 case TIOCSFLAGS: 1193 if( suser(p->p_ucred, &p->p_acflag) ) 1194 error = EPERM; 1195 else 1196 mp->mp_openflags = *((int *)data) & 1197 (TIOCFLAG_SOFTCAR | TIOCFLAG_CLOCAL | 1198 TIOCFLAG_CRTSCTS | TIOCFLAG_MDMBUF); 1199 break; 1200 1201 default: 1202 error = EPASSTHROUGH; 1203 } 1204 1205 return(error); 1206 } 1207 1208 /* 1209 * Stop output, e.g., for ^S or output flush. 1210 */ 1211 void 1212 mttystop(tp, flags) 1213 struct tty *tp; 1214 int flags; 1215 { 1216 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(tp->t_dev)]; 1217 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(tp->t_dev)]; 1218 int s; 1219 1220 s = spltty(); 1221 1222 if( ISSET(tp->t_state, TS_BUSY) ) { 1223 if( !ISSET(tp->t_state, TS_TTSTOP) ) 1224 SET(tp->t_state, TS_FLUSH); 1225 1226 /* 1227 * the transmit interrupt routine will disable transmit when it 1228 * notices that MTTYF_STOP has been set. 1229 */ 1230 SET(mp->mp_flags, MTTYF_STOP); 1231 } 1232 1233 splx(s); 1234 } 1235 1236 /* 1237 * Start output, after a stop. 1238 */ 1239 void 1240 mtty_start(tp) 1241 struct tty *tp; 1242 { 1243 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(tp->t_dev)]; 1244 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(tp->t_dev)]; 1245 int s; 1246 1247 s = spltty(); 1248 1249 /* we only need to do something if we are not already busy 1250 * or delaying or stopped 1251 */ 1252 if( !ISSET(tp->t_state, TS_TTSTOP | TS_TIMEOUT | TS_BUSY) ) { 1253 1254 /* if we are sleeping and output has drained below 1255 * low water mark, awaken 1256 */ 1257 if( tp->t_outq.c_cc <= tp->t_lowat ) { 1258 if( ISSET(tp->t_state, TS_ASLEEP) ) { 1259 CLR(tp->t_state, TS_ASLEEP); 1260 wakeup(&tp->t_outq); 1261 } 1262 1263 selwakeup(&tp->t_wsel); 1264 } 1265 1266 /* if something to send, start transmitting 1267 */ 1268 if( tp->t_outq.c_cc ) { 1269 mp->mp_txc = ndqb(&tp->t_outq, 0); 1270 mp->mp_txp = tp->t_outq.c_cf; 1271 SET(tp->t_state, TS_BUSY); 1272 cd1400_enable_transmitter(mp->mp_cd1400, mp->mp_channel); 1273 } 1274 } 1275 1276 splx(s); 1277 } 1278 1279 /* 1280 * set/get modem line status 1281 * 1282 * bits can be: TIOCM_DTR, TIOCM_RTS, TIOCM_CTS, TIOCM_CD, TIOCM_RI, TIOCM_DSR 1283 * 1284 * note that DTR and RTS lines are exchanged, and that DSR is 1285 * not available on the LC2+1Sp card (used as CD) 1286 * 1287 * only let them fiddle with RTS if CRTSCTS is not enabled 1288 */ 1289 int 1290 mtty_modem_control(mp, bits, howto) 1291 struct mtty_port *mp; 1292 int bits; 1293 int howto; 1294 { 1295 struct cd1400 *cd = mp->mp_cd1400; 1296 struct tty *tp = mp->mp_tty; 1297 int s, msvr; 1298 1299 s = spltty(); 1300 1301 cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel); 1302 1303 switch(howto) { 1304 case DMGET: /* get bits */ 1305 bits = 0; 1306 1307 bits |= TIOCM_LE; 1308 1309 msvr = cd1400_read_reg(cd, CD1400_MSVR1); 1310 if( msvr & CD1400_MSVR1_RTS ) bits |= TIOCM_DTR; 1311 1312 msvr = cd1400_read_reg(cd, CD1400_MSVR2); 1313 if( msvr & CD1400_MSVR2_DTR ) bits |= TIOCM_RTS; 1314 if( msvr & CD1400_MSVR2_CTS ) bits |= TIOCM_CTS; 1315 if( msvr & CD1400_MSVR2_RI ) bits |= TIOCM_RI; 1316 if( msvr & CD1400_MSVR2_DSR ) bits |= (cd->cd_parmode ? TIOCM_CD : TIOCM_DSR); 1317 if( msvr & CD1400_MSVR2_CD ) bits |= (cd->cd_parmode ? 0 : TIOCM_CD); 1318 1319 break; 1320 1321 case DMSET: /* reset bits */ 1322 if( !ISSET(tp->t_cflag, CRTSCTS) ) 1323 cd1400_write_reg(cd, CD1400_MSVR2, ((bits & TIOCM_RTS) ? CD1400_MSVR2_DTR : 0)); 1324 1325 cd1400_write_reg(cd, CD1400_MSVR1, ((bits & TIOCM_DTR) ? CD1400_MSVR1_RTS : 0)); 1326 1327 break; 1328 1329 case DMBIS: /* set bits */ 1330 if( (bits & TIOCM_RTS) && !ISSET(tp->t_cflag, CRTSCTS) ) 1331 cd1400_write_reg(cd, CD1400_MSVR2, CD1400_MSVR2_DTR); 1332 1333 if( bits & TIOCM_DTR ) 1334 cd1400_write_reg(cd, CD1400_MSVR1, CD1400_MSVR1_RTS); 1335 1336 break; 1337 1338 case DMBIC: /* clear bits */ 1339 if( (bits & TIOCM_RTS) && !ISSET(tp->t_cflag, CRTSCTS) ) 1340 cd1400_write_reg(cd, CD1400_MSVR2, 0); 1341 1342 if( bits & TIOCM_DTR ) 1343 cd1400_write_reg(cd, CD1400_MSVR1, 0); 1344 1345 break; 1346 } 1347 1348 splx(s); 1349 return(bits); 1350 } 1351 1352 /* 1353 * Set tty parameters, returns error or 0 on success 1354 */ 1355 int 1356 mtty_param(tp, t) 1357 struct tty *tp; 1358 struct termios *t; 1359 { 1360 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(tp->t_dev)]; 1361 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(tp->t_dev)]; 1362 struct cd1400 *cd = mp->mp_cd1400; 1363 int rbpr, tbpr, rcor, tcor; 1364 u_char mcor1 = 0, mcor2 = 0; 1365 int s, opt; 1366 1367 if( t->c_ospeed && cd1400_compute_baud(t->c_ospeed, cd->cd_clock, &tcor, &tbpr) ) 1368 return(EINVAL); 1369 1370 if( t->c_ispeed && cd1400_compute_baud(t->c_ispeed, cd->cd_clock, &rcor, &rbpr) ) 1371 return(EINVAL); 1372 1373 s = spltty(); 1374 1375 /* hang up the line if ospeed is zero, else raise DTR */ 1376 (void)mtty_modem_control(mp, TIOCM_DTR, (t->c_ospeed == 0 ? DMBIC : DMBIS)); 1377 1378 /* select channel, done in mtty_modem_control() */ 1379 /* cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel); */ 1380 1381 /* set transmit speed */ 1382 if( t->c_ospeed ) { 1383 cd1400_write_reg(cd, CD1400_TCOR, tcor); 1384 cd1400_write_reg(cd, CD1400_TBPR, tbpr); 1385 } 1386 1387 /* set receive speed */ 1388 if( t->c_ispeed ) { 1389 cd1400_write_reg(cd, CD1400_RCOR, rcor); 1390 cd1400_write_reg(cd, CD1400_RBPR, rbpr); 1391 } 1392 1393 /* enable transmitting and receiving on this channel */ 1394 opt = CD1400_CCR_CMDCHANCTL | CD1400_CCR_XMTEN | CD1400_CCR_RCVEN; 1395 cd1400_write_ccr(cd, opt); 1396 1397 /* set parity, data and stop bits */ 1398 opt = 0; 1399 if( ISSET(t->c_cflag, PARENB) ) 1400 opt |= (ISSET(t->c_cflag, PARODD) ? CD1400_COR1_PARODD : CD1400_COR1_PARNORMAL); 1401 1402 if( !ISSET(t->c_iflag, INPCK) ) 1403 opt |= CD1400_COR1_NOINPCK; /* no parity checking */ 1404 1405 if( ISSET(t->c_cflag, CSTOPB) ) 1406 opt |= CD1400_COR1_STOP2; 1407 1408 switch( t->c_cflag & CSIZE ) { 1409 case CS5: 1410 opt |= CD1400_COR1_CS5; 1411 break; 1412 1413 case CS6: 1414 opt |= CD1400_COR1_CS6; 1415 break; 1416 1417 case CS7: 1418 opt |= CD1400_COR1_CS7; 1419 break; 1420 1421 default: 1422 opt |= CD1400_COR1_CS8; 1423 break; 1424 } 1425 1426 cd1400_write_reg(cd, CD1400_COR1, opt); 1427 1428 /* 1429 * enable Embedded Transmit Commands (for breaks) 1430 * use the CD1400 automatic CTS flow control if CRTSCTS is set 1431 */ 1432 opt = CD1400_COR2_ETC; 1433 if( ISSET(t->c_cflag, CRTSCTS) ) opt |= CD1400_COR2_CCTS_OFLOW; 1434 cd1400_write_reg(cd, CD1400_COR2, opt); 1435 1436 cd1400_write_reg(cd, CD1400_COR3, MTTY_RX_FIFO_THRESHOLD); 1437 1438 cd1400_write_ccr(cd, CD1400_CCR_CMDCORCHG | CD1400_CCR_COR1 | CD1400_CCR_COR2 | CD1400_CCR_COR3); 1439 1440 cd1400_write_reg(cd, CD1400_COR4, CD1400_COR4_PFO_EXCEPTION); 1441 cd1400_write_reg(cd, CD1400_COR5, 0); 1442 1443 /* 1444 * if automatic RTS handshaking enabled, set DTR threshold 1445 * (RTS and DTR lines are switched, CD1400 thinks its DTR) 1446 */ 1447 if( ISSET(t->c_cflag, CRTSCTS) ) 1448 mcor1 = MTTY_RX_DTR_THRESHOLD; 1449 1450 /* set up `carrier detect' interrupts */ 1451 if( cd->cd_parmode ) { 1452 SET(mcor1, CD1400_MCOR1_DSRzd); 1453 SET(mcor2, CD1400_MCOR2_DSRod); 1454 } else { 1455 SET(mcor1, CD1400_MCOR1_CDzd); 1456 SET(mcor2, CD1400_MCOR2_CDod); 1457 } 1458 1459 cd1400_write_reg(cd, CD1400_MCOR1, mcor1); 1460 cd1400_write_reg(cd, CD1400_MCOR2, mcor2); 1461 1462 /* receive timeout 2ms */ 1463 cd1400_write_reg(cd, CD1400_RTPR, 2); 1464 1465 splx(s); 1466 return(0); 1467 } 1468 1469 /************************************************************************ 1470 * 1471 * MBPP Routines 1472 * 1473 * mbpp_match match one mbpp device 1474 * mbpp_attach attach mbpp devices 1475 * mbppopen open mbpp device 1476 * mbppclose close mbpp device 1477 * mbppioctl do ioctl on mbpp 1478 * mbpp_rw general rw routine 1479 * mbpp_timeout rw timeout 1480 * mbpp_start rw start after delay 1481 * mbpp_send send data 1482 * mbpp_recv recv data 1483 */ 1484 1485 int 1486 mbpp_match(parent, cf, args) 1487 struct device *parent; 1488 struct cfdata *cf; 1489 void *args; 1490 { 1491 struct magma_softc *sc = (struct magma_softc *)parent; 1492 1493 return( args == mbpp_match && sc->ms_board->mb_npar && sc->ms_mbpp == NULL ); 1494 } 1495 1496 void 1497 mbpp_attach(parent, dev, args) 1498 struct device *parent; 1499 struct device *dev; 1500 void *args; 1501 { 1502 struct magma_softc *sc = (struct magma_softc *)parent; 1503 struct mbpp_softc *ms = (struct mbpp_softc *)dev; 1504 struct mbpp_port *mp; 1505 int port; 1506 1507 sc->ms_mbpp = ms; 1508 dprintf((" addr %p", ms)); 1509 1510 for( port = 0 ; port < sc->ms_board->mb_npar ; port++ ) { 1511 mp = &ms->ms_port[port]; 1512 1513 callout_init(&mp->mp_timeout_ch); 1514 callout_init(&mp->mp_start_ch); 1515 1516 if( sc->ms_ncd1190 ) 1517 mp->mp_cd1190 = &sc->ms_cd1190[port]; 1518 else 1519 mp->mp_cd1400 = &sc->ms_cd1400[0]; 1520 } 1521 1522 ms->ms_nports = port; 1523 printf(": %d port%s\n", port, port == 1 ? "" : "s"); 1524 } 1525 1526 /* 1527 * open routine. returns zero if successful, else error code 1528 */ 1529 int 1530 mbppopen(dev, flags, mode, p) 1531 dev_t dev; 1532 int flags; 1533 int mode; 1534 struct proc *p; 1535 { 1536 int card = MAGMA_CARD(dev); 1537 int port = MAGMA_PORT(dev); 1538 struct mbpp_softc *ms; 1539 struct mbpp_port *mp; 1540 int s; 1541 1542 if( card >= mbpp_cd.cd_ndevs || 1543 (ms = mbpp_cd.cd_devs[card]) == NULL || port >= ms->ms_nports ) 1544 return(ENXIO); 1545 1546 mp = &ms->ms_port[port]; 1547 1548 s = spltty(); 1549 if( ISSET(mp->mp_flags, MBPPF_OPEN) ) { 1550 splx(s); 1551 return(EBUSY); 1552 } 1553 SET(mp->mp_flags, MBPPF_OPEN); 1554 splx(s); 1555 1556 /* set defaults */ 1557 mp->mp_burst = MBPP_BURST; 1558 mp->mp_timeout = mbpp_mstohz(MBPP_TIMEOUT); 1559 mp->mp_delay = mbpp_mstohz(MBPP_DELAY); 1560 1561 /* init chips */ 1562 if( mp->mp_cd1400 ) { /* CD1400 */ 1563 struct cd1400 *cd = mp->mp_cd1400; 1564 1565 /* set up CD1400 channel */ 1566 s = spltty(); 1567 cd1400_write_reg(cd, CD1400_CAR, 0); 1568 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET); 1569 cd1400_write_reg(cd, CD1400_LIVR, (1<<3)); 1570 splx(s); 1571 } else { /* CD1190 */ 1572 mp->mp_flags = 0; 1573 return (ENXIO); 1574 } 1575 1576 return (0); 1577 } 1578 1579 /* 1580 * close routine. returns zero if successful, else error code 1581 */ 1582 int 1583 mbppclose(dev, flag, mode, p) 1584 dev_t dev; 1585 int flag; 1586 int mode; 1587 struct proc *p; 1588 { 1589 struct mbpp_softc *ms = mbpp_cd.cd_devs[MAGMA_CARD(dev)]; 1590 struct mbpp_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1591 1592 mp->mp_flags = 0; 1593 return(0); 1594 } 1595 1596 /* 1597 * ioctl routine 1598 */ 1599 int 1600 mbppioctl(dev, cmd, data, flags, p) 1601 dev_t dev; 1602 u_long cmd; 1603 caddr_t data; 1604 int flags; 1605 struct proc *p; 1606 { 1607 struct mbpp_softc *ms = mbpp_cd.cd_devs[MAGMA_CARD(dev)]; 1608 struct mbpp_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1609 struct mbpp_param *bp; 1610 int error = 0; 1611 int s; 1612 1613 switch(cmd) { 1614 case MBPPIOCSPARAM: 1615 bp = (struct mbpp_param *)data; 1616 if( bp->bp_burst < MBPP_BURST_MIN || bp->bp_burst > MBPP_BURST_MAX || 1617 bp->bp_delay < MBPP_DELAY_MIN || bp->bp_delay > MBPP_DELAY_MIN ) { 1618 error = EINVAL; 1619 } else { 1620 mp->mp_burst = bp->bp_burst; 1621 mp->mp_timeout = mbpp_mstohz(bp->bp_timeout); 1622 mp->mp_delay = mbpp_mstohz(bp->bp_delay); 1623 } 1624 break; 1625 case MBPPIOCGPARAM: 1626 bp = (struct mbpp_param *)data; 1627 bp->bp_burst = mp->mp_burst; 1628 bp->bp_timeout = mbpp_hztoms(mp->mp_timeout); 1629 bp->bp_delay = mbpp_hztoms(mp->mp_delay); 1630 break; 1631 case MBPPIOCGSTAT: 1632 /* XXX make this more generic */ 1633 s = spltty(); 1634 cd1400_write_reg(mp->mp_cd1400, CD1400_CAR, 0); 1635 *(int *)data = cd1400_read_reg(mp->mp_cd1400, CD1400_PSVR); 1636 splx(s); 1637 break; 1638 default: 1639 error = ENOTTY; 1640 } 1641 1642 return(error); 1643 } 1644 1645 int 1646 mbpp_rw(dev, uio, flag) 1647 dev_t dev; 1648 struct uio *uio; 1649 int flag; 1650 { 1651 int card = MAGMA_CARD(dev); 1652 int port = MAGMA_PORT(dev); 1653 struct mbpp_softc *ms = mbpp_cd.cd_devs[card]; 1654 struct mbpp_port *mp = &ms->ms_port[port]; 1655 caddr_t buffer, ptr; 1656 int buflen, cnt, len; 1657 int s, error = 0; 1658 int gotdata = 0; 1659 1660 if( uio->uio_resid == 0 ) 1661 return(0); 1662 1663 buflen = min(uio->uio_resid, mp->mp_burst); 1664 buffer = malloc(buflen, M_DEVBUF, M_WAITOK); 1665 if( buffer == NULL ) 1666 return(ENOMEM); 1667 1668 SET(mp->mp_flags, MBPPF_UIO); 1669 1670 /* 1671 * start timeout, if needed 1672 */ 1673 if( mp->mp_timeout > 0 ) { 1674 SET(mp->mp_flags, MBPPF_TIMEOUT); 1675 callout_reset(&mp->mp_timeout_ch, mp->mp_timeout, 1676 mbpp_timeout, mp); 1677 } 1678 1679 len = cnt = 0; 1680 while( uio->uio_resid > 0 ) { 1681 len = min(buflen, uio->uio_resid); 1682 ptr = buffer; 1683 1684 if( uio->uio_rw == UIO_WRITE ) { 1685 error = uiomove(ptr, len, uio); 1686 if( error ) break; 1687 } 1688 again: /* goto bad */ 1689 /* timed out? */ 1690 if( !ISSET(mp->mp_flags, MBPPF_UIO) ) 1691 break; 1692 1693 /* 1694 * perform the operation 1695 */ 1696 if( uio->uio_rw == UIO_WRITE ) { 1697 cnt = mbpp_send(mp, ptr, len); 1698 } else { 1699 cnt = mbpp_recv(mp, ptr, len); 1700 } 1701 1702 if( uio->uio_rw == UIO_READ ) { 1703 if( cnt ) { 1704 error = uiomove(ptr, cnt, uio); 1705 if( error ) break; 1706 gotdata++; 1707 } 1708 else if( gotdata ) /* consider us done */ 1709 break; 1710 } 1711 1712 /* timed out? */ 1713 if( !ISSET(mp->mp_flags, MBPPF_UIO) ) 1714 break; 1715 1716 /* 1717 * poll delay? 1718 */ 1719 if( mp->mp_delay > 0 ) { 1720 s = splsoftclock(); 1721 SET(mp->mp_flags, MBPPF_DELAY); 1722 callout_reset(&mp->mp_start_ch, mp->mp_delay, 1723 mbpp_start, mp); 1724 error = tsleep(mp, PCATCH | PZERO, "mbppdelay", 0); 1725 splx(s); 1726 if( error ) break; 1727 } 1728 1729 /* 1730 * don't call uiomove again until we used all the data we grabbed 1731 */ 1732 if( uio->uio_rw == UIO_WRITE && cnt != len ) { 1733 ptr += cnt; 1734 len -= cnt; 1735 cnt = 0; 1736 goto again; 1737 } 1738 } 1739 1740 /* 1741 * clear timeouts 1742 */ 1743 s = splsoftclock(); 1744 if( ISSET(mp->mp_flags, MBPPF_TIMEOUT) ) { 1745 callout_stop(&mp->mp_timeout_ch); 1746 CLR(mp->mp_flags, MBPPF_TIMEOUT); 1747 } 1748 if( ISSET(mp->mp_flags, MBPPF_DELAY) ) { 1749 callout_stop(&mp->mp_start_ch); 1750 CLR(mp->mp_flags, MBPPF_DELAY); 1751 } 1752 splx(s); 1753 1754 /* 1755 * adjust for those chars that we uiomoved but never actually wrote 1756 */ 1757 if( uio->uio_rw == UIO_WRITE && cnt != len ) { 1758 uio->uio_resid += (len - cnt); 1759 } 1760 1761 free(buffer, M_DEVBUF); 1762 return(error); 1763 } 1764 1765 void 1766 mbpp_timeout(arg) 1767 void *arg; 1768 { 1769 struct mbpp_port *mp = arg; 1770 1771 CLR(mp->mp_flags, MBPPF_UIO | MBPPF_TIMEOUT); 1772 wakeup(mp); 1773 } 1774 1775 void 1776 mbpp_start(arg) 1777 void *arg; 1778 { 1779 struct mbpp_port *mp = arg; 1780 1781 CLR(mp->mp_flags, MBPPF_DELAY); 1782 wakeup(mp); 1783 } 1784 1785 int 1786 mbpp_send(mp, ptr, len) 1787 struct mbpp_port *mp; 1788 caddr_t ptr; 1789 int len; 1790 { 1791 int s; 1792 struct cd1400 *cd = mp->mp_cd1400; 1793 1794 /* set up io information */ 1795 mp->mp_ptr = ptr; 1796 mp->mp_cnt = len; 1797 1798 /* start transmitting */ 1799 s = spltty(); 1800 if( cd ) { 1801 cd1400_write_reg(cd, CD1400_CAR, 0); 1802 1803 /* output strobe width ~1microsecond */ 1804 cd1400_write_reg(cd, CD1400_TBPR, 10); 1805 1806 /* enable channel */ 1807 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_XMTEN); 1808 cd1400_write_reg(cd, CD1400_SRER, CD1400_SRER_TXRDY); 1809 } 1810 1811 /* ZZzzz... */ 1812 tsleep(mp, PCATCH | PZERO, "mbpp_send", 0); 1813 1814 /* stop transmitting */ 1815 if( cd ) { 1816 cd1400_write_reg(cd, CD1400_CAR, 0); 1817 1818 /* disable transmitter */ 1819 cd1400_write_reg(cd, CD1400_SRER, 0); 1820 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_XMTDIS); 1821 1822 /* flush fifo */ 1823 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET | CD1400_CCR_FTF); 1824 } 1825 splx(s); 1826 1827 /* return number of chars sent */ 1828 return(len - mp->mp_cnt); 1829 } 1830 1831 int 1832 mbpp_recv(mp, ptr, len) 1833 struct mbpp_port *mp; 1834 caddr_t ptr; 1835 int len; 1836 { 1837 int s; 1838 struct cd1400 *cd = mp->mp_cd1400; 1839 1840 /* set up io information */ 1841 mp->mp_ptr = ptr; 1842 mp->mp_cnt = len; 1843 1844 /* start receiving */ 1845 s = spltty(); 1846 if( cd ) { 1847 int rcor, rbpr; 1848 1849 cd1400_write_reg(cd, CD1400_CAR, 0); 1850 1851 /* input strobe at 100kbaud (10microseconds) */ 1852 cd1400_compute_baud(100000, cd->cd_clock, &rcor, &rbpr); 1853 cd1400_write_reg(cd, CD1400_RCOR, rcor); 1854 cd1400_write_reg(cd, CD1400_RBPR, rbpr); 1855 1856 /* rx threshold */ 1857 cd1400_write_reg(cd, CD1400_COR3, MBPP_RX_FIFO_THRESHOLD); 1858 cd1400_write_ccr(cd, CD1400_CCR_CMDCORCHG | CD1400_CCR_COR3); 1859 1860 /* enable channel */ 1861 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_RCVEN); 1862 cd1400_write_reg(cd, CD1400_SRER, CD1400_SRER_RXDATA); 1863 } 1864 1865 /* ZZzzz... */ 1866 tsleep(mp, PCATCH | PZERO, "mbpp_recv", 0); 1867 1868 /* stop receiving */ 1869 if( cd ) { 1870 cd1400_write_reg(cd, CD1400_CAR, 0); 1871 1872 /* disable receiving */ 1873 cd1400_write_reg(cd, CD1400_SRER, 0); 1874 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_RCVDIS); 1875 } 1876 splx(s); 1877 1878 /* return number of chars received */ 1879 return(len - mp->mp_cnt); 1880 } 1881 1882 int 1883 mbpp_hztoms(h) 1884 int h; 1885 { 1886 int m = h; 1887 1888 if( m > 0 ) 1889 m = m * 1000 / hz; 1890 return(m); 1891 } 1892 1893 int 1894 mbpp_mstohz(m) 1895 int m; 1896 { 1897 int h = m; 1898 1899 if( h > 0 ) { 1900 h = h * hz / 1000; 1901 if( h == 0 ) 1902 h = 1000 / hz; 1903 } 1904 return(h); 1905 } 1906 1907 #endif /* NMAGMA */ 1908
Indexes created Thu Oct 02 10:09:58 GMT 2025