magma.c revision 1.2
1 /* $NetBSD: magma.c,v 1.2 1998/05/20 22:08:10 pk Exp $ */ 2 /* 3 * magma.c 4 * 5 * Copyright (c) 1998 Iain Hibbert 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Iain Hibbert 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 #if 0 35 #define MAGMA_DEBUG 36 #endif 37 38 /* 39 * Driver for Magma SBus Serial/Parallel cards using the Cirrus Logic 40 * CD1400 & CD1190 chips 41 */ 42 43 #include "magma.h" 44 #if NMAGMA > 0 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/proc.h> 49 #include <sys/device.h> 50 #include <sys/file.h> 51 #include <sys/ioctl.h> 52 #include <sys/malloc.h> 53 #include <sys/tty.h> 54 #include <sys/time.h> 55 #include <sys/kernel.h> 56 #include <sys/syslog.h> 57 #include <sys/conf.h> 58 #include <sys/errno.h> 59 60 #include <machine/bus.h> 61 #include <sparc/dev/sbusvar.h> 62 #include <sparc/autoconf.h> 63 #include <sparc/conf.h> 64 #include <sparc/cpu.h> 65 #include <sparc/ctlreg.h> 66 67 #include <sparc/sparc/asm.h> 68 69 #include <dev/ic/cd1400reg.h> 70 #include <dev/ic/cd1190reg.h> 71 72 #include "magmareg.h" 73 74 /* 75 * Select tty soft interrupt bit based on TTY ipl. (stole from zs.c) 76 */ 77 #if PIL_TTY == 1 78 # define IE_MSOFT IE_L1 79 #elif PIL_TTY == 4 80 # define IE_MSOFT IE_L4 81 #elif PIL_TTY == 6 82 # define IE_MSOFT IE_L6 83 #else 84 # error "no suitable software interrupt bit" 85 #endif 86 87 /* supported cards 88 * 89 * The table below lists the cards that this driver is likely to 90 * be able to support. 91 * 92 * Cards with parallel ports: except for the LC2+1Sp, they all use 93 * the CD1190 chip which I know nothing about. I've tried to leave 94 * hooks for it so it shouldn't be too hard to add support later. 95 * (I think somebody is working on this separately) 96 * 97 * Thanks to Bruce at Magma for telling me the hardware offsets. 98 */ 99 static struct magma_board_info supported_cards[] = { 100 { 101 "MAGMA,4_Sp", "Magma 4 Sp", 4, 0, 102 1, 0xa000, 0xc000, 0xe000, { 0x8000, 0, 0, 0 }, 103 0, { 0, 0 } 104 }, 105 { 106 "MAGMA,8_Sp", "Magma 8 Sp", 8, 0, 107 2, 0xa000, 0xc000, 0xe000, { 0x4000, 0x6000, 0, 0 }, 108 0, { 0, 0 } 109 }, 110 { 111 "MAGMA,_8HS_Sp", "Magma Fast 8 Sp", 8, 0, 112 2, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0, 0 }, 113 0, { 0, 0 } 114 }, 115 { 116 "MAGMA,_8SP_422", "Magma 8 Sp - 422", 8, 0, 117 2, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0, 0 }, 118 0, { 0, 0 } 119 }, 120 { 121 "MAGMA,12_Sp", "Magma 12 Sp", 12, 0, 122 3, 0xa000, 0xc000, 0xe000, { 0x2000, 0x4000, 0x6000, 0 }, 123 0, { 0, 0 } 124 }, 125 { 126 "MAGMA,16_Sp", "Magma 16 Sp", 16, 0, 127 4, 0xd000, 0xe000, 0xf000, { 0x8000, 0x9000, 0xa000, 0xb000 }, 128 0, { 0, 0 } 129 }, 130 { 131 "MAGMA,16_Sp_2", "Magma 16 Sp", 16, 0, 132 4, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0xc000, 0xe000 }, 133 0, { 0, 0 } 134 }, 135 { 136 "MAGMA,16HS_Sp", "Magma Fast 16 Sp", 16, 0, 137 4, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0xc000, 0xe000 }, 138 0, { 0, 0 } 139 }, 140 { 141 "MAGMA,21_Sp", "Magma LC 2+1 Sp", 2, 1, 142 1, 0xa000, 0xc000, 0xe000, { 0x8000, 0, 0, 0 }, 143 0, { 0, 0 } 144 }, 145 { 146 "MAGMA,21HS_Sp", "Magma 2+1 Sp", 2, 1, 147 1, 0xa000, 0xc000, 0xe000, { 0x4000, 0, 0, 0 }, 148 1, { 0x6000, 0 } 149 }, 150 { 151 "MAGMA,41_Sp", "Magma 4+1 Sp", 4, 1, 152 1, 0xa000, 0xc000, 0xe000, { 0x4000, 0, 0, 0 }, 153 1, { 0x6000, 0 } 154 }, 155 { 156 "MAGMA,82_Sp", "Magma 8+2 Sp", 8, 2, 157 2, 0xd000, 0xe000, 0xf000, { 0x8000, 0x9000, 0, 0 }, 158 2, { 0xa000, 0xb000 } 159 }, 160 { 161 "MAGMA,P1_Sp", "Magma P1 Sp", 0, 1, 162 0, 0, 0, 0, { 0, 0, 0, 0 }, 163 1, { 0x8000, 0 } 164 }, 165 { 166 "MAGMA,P2_Sp", "Magma P2 Sp", 0, 2, 167 0, 0, 0, 0, { 0, 0, 0, 0 }, 168 2, { 0x4000, 0x8000 } 169 }, 170 { 171 NULL, NULL, 0, 0, 172 0, 0, 0, 0, { 0, 0, 0, 0 }, 173 0, { 0, 0 } 174 } 175 }; 176 177 /************************************************************************ 178 * 179 * Autoconfig Stuff 180 */ 181 182 struct cfattach magma_ca = { 183 sizeof(struct magma_softc), magma_match, magma_attach 184 }; 185 186 struct cfattach mtty_ca = { 187 sizeof(struct mtty_softc), mtty_match, mtty_attach 188 }; 189 190 struct cfattach mbpp_ca = { 191 sizeof(struct mbpp_softc), mbpp_match, mbpp_attach 192 }; 193 194 extern struct cfdriver mtty_cd; 195 extern struct cfdriver mbpp_cd; 196 197 /************************************************************************ 198 * 199 * CD1400 Routines 200 * 201 * cd1400_compute_baud calculate COR/BPR register values 202 * cd1400_write_ccr write a value to CD1400 ccr 203 * cd1400_read_reg read from a CD1400 register 204 * cd1400_write_reg write to a CD1400 register 205 * cd1400_enable_transmitter enable transmitting on CD1400 channel 206 */ 207 208 /* 209 * compute the bpr/cor pair for any baud rate 210 * returns 0 for success, 1 for failure 211 */ 212 int 213 cd1400_compute_baud(speed, clock, cor, bpr) 214 speed_t speed; 215 int clock; 216 int *cor, *bpr; 217 { 218 int c, co, br; 219 220 if( speed < 50 || speed > 150000 ) 221 return(1); 222 223 for( c = 0, co = 8 ; co <= 2048 ; co <<= 2, c++ ) { 224 br = ((clock * 1000000) + (co * speed) / 2) / (co * speed); 225 if( br < 0x100 ) { 226 *bpr = br; 227 *cor = c; 228 return(0); 229 } 230 } 231 232 return(1); 233 } 234 235 /* 236 * Write a CD1400 channel command, should have a timeout? 237 */ 238 __inline void 239 cd1400_write_ccr(cd, cmd) 240 struct cd1400 *cd; 241 u_char cmd; 242 { 243 while( cd1400_read_reg(cd, CD1400_CCR) ) 244 ; 245 246 cd1400_write_reg(cd, CD1400_CCR, cmd); 247 } 248 249 /* 250 * read a value from a cd1400 register 251 */ 252 __inline u_char 253 cd1400_read_reg(cd, reg) 254 struct cd1400 *cd; 255 int reg; 256 { 257 return(cd->cd_reg[reg]); 258 } 259 260 /* 261 * write a value to a cd1400 register 262 */ 263 __inline void 264 cd1400_write_reg(cd, reg, value) 265 struct cd1400 *cd; 266 int reg; 267 u_char value; 268 { 269 cd->cd_reg[reg] = value; 270 } 271 272 /* 273 * enable transmit service requests for cd1400 channel 274 */ 275 void 276 cd1400_enable_transmitter(cd, channel) 277 struct cd1400 *cd; 278 int channel; 279 { 280 int s, srer; 281 282 s = spltty(); 283 cd1400_write_reg(cd, CD1400_CAR, channel); 284 srer = cd1400_read_reg(cd, CD1400_SRER); 285 SET(srer, CD1400_SRER_TXRDY); 286 cd1400_write_reg(cd, CD1400_SRER, srer); 287 splx(s); 288 } 289 290 /************************************************************************ 291 * 292 * CD1190 Routines 293 */ 294 295 /* well, there are none yet */ 296 297 /************************************************************************ 298 * 299 * Magma Routines 300 * 301 * magma_match reports if we have a magma board available 302 * magma_attach attaches magma boards to the sbus 303 * magma_hard hardware level interrupt routine 304 * magma_soft software level interrupt routine 305 */ 306 307 int 308 magma_match(parent, cf, aux) 309 struct device *parent; 310 struct cfdata *cf; 311 void *aux; 312 { 313 struct sbus_attach_args *sa = aux; 314 315 /* is it a magma Sp card? */ 316 if( strcmp(sa->sa_name, "MAGMA_Sp") != 0 ) 317 return(0); 318 319 #if defined(MAGMA_DEBUG) 320 printf("magma: matched `%s'\n", sa->sa_name); 321 printf("magma: magma_prom `%s'\n", 322 getpropstring(sa->sa_node, "magma_prom")); 323 printf("magma: intlevels `%s'\n", 324 getpropstring(sa->sa_node, "intlevels")); 325 printf("magma: chiprev `%s'\n", 326 getpropstring(sa->sa_node, "chiprev")); 327 printf("magma: clock `%s'\n", 328 getpropstring(sa->sa_node, "clock")); 329 #endif 330 331 return (1); 332 } 333 334 void 335 magma_attach(parent, self, aux) 336 struct device *parent; 337 struct device *self; 338 void *aux; 339 { 340 struct sbus_attach_args *sa = aux; 341 struct magma_softc *sc = (struct magma_softc *)self; 342 struct magma_board_info *card = supported_cards; 343 bus_space_handle_t bh; 344 char *magma_prom; 345 int node, chip; 346 347 node = sa->sa_node; 348 magma_prom = getpropstring(node, "magma_prom"); 349 350 /* find the card type */ 351 while (card->mb_name && strcmp(magma_prom, card->mb_name) != 0) 352 card++; 353 354 dprintf((" addr %p", sc)); 355 printf(" softpri %d:", PIL_TTY); 356 357 if( card->mb_name == NULL ) { 358 printf(" %s (unsupported)\n", magma_prom); 359 return; 360 } 361 362 printf(" %s\n", card->mb_realname); 363 364 sc->ms_board = card; 365 sc->ms_ncd1400 = card->mb_ncd1400; 366 sc->ms_ncd1190 = card->mb_ncd1190; 367 368 if (sbus_bus_map(sa->sa_bustag, 369 sa->sa_slot, 370 sa->sa_offset, 371 sa->sa_size, 372 BUS_SPACE_MAP_LINEAR, 373 0, &bh) != 0) { 374 printf("%s @ sbus: cannot map registers\n", self->dv_xname); 375 return; 376 } 377 378 /* the SVCACK* lines are daisychained */ 379 sc->ms_svcackr = (caddr_t)bh + card->mb_svcackr; 380 sc->ms_svcackt = (caddr_t)bh + card->mb_svcackt; 381 sc->ms_svcackm = (caddr_t)bh + card->mb_svcackm; 382 383 /* init the cd1400 chips */ 384 for( chip = 0 ; chip < card->mb_ncd1400 ; chip++ ) { 385 struct cd1400 *cd = &sc->ms_cd1400[chip]; 386 387 cd->cd_reg = (caddr_t)bh + card->mb_cd1400[chip]; 388 389 /* XXX getpropstring(node, "clock") */ 390 cd->cd_clock = 25; 391 392 /* getpropstring(node, "chiprev"); */ 393 /* seemingly the Magma drivers just ignore the propstring */ 394 cd->cd_chiprev = cd1400_read_reg(cd, CD1400_GFRCR); 395 396 dprintf(("%s attach CD1400 %d addr %p rev %x clock %dMhz\n", 397 sc->ms_dev.dv_xname, chip, 398 cd->cd_reg, cd->cd_chiprev, cd->cd_clock)); 399 400 /* clear GFRCR */ 401 cd1400_write_reg(cd, CD1400_GFRCR, 0x00); 402 403 /* reset whole chip */ 404 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET | CD1400_CCR_FULLRESET); 405 406 /* wait for revision code to be restored */ 407 while( cd1400_read_reg(cd, CD1400_GFRCR) != cd->cd_chiprev ) 408 ; 409 410 /* set the Prescaler Period Register to tick at 1ms */ 411 cd1400_write_reg(cd, CD1400_PPR, 412 ((cd->cd_clock * 1000000 / CD1400_PPR_PRESCALER + 500) / 1000)); 413 414 /* The LC2+1Sp card is the only card that doesn't have 415 * a CD1190 for the parallel port, but uses channel 0 of 416 * the CD1400, so we make a note of it for later and set up 417 * the CD1400 for parallel mode operation. 418 */ 419 if( card->mb_npar && card->mb_ncd1190 == 0 ) { 420 cd1400_write_reg(cd, CD1400_GCR, CD1400_GCR_PARALLEL); 421 cd->cd_parmode = 1; 422 } 423 } 424 425 /* init the cd1190 chips */ 426 for( chip = 0 ; chip < card->mb_ncd1190 ; chip++ ) { 427 struct cd1190 *cd = &sc->ms_cd1190[chip]; 428 429 cd->cd_reg = (caddr_t)bh + card->mb_cd1190[chip]; 430 dprintf(("%s attach CD1190 %d addr %p (failed)\n", 431 self->dv_xname, chip, cd->cd_reg)); 432 /* XXX don't know anything about these chips yet */ 433 } 434 435 sbus_establish(&sc->ms_sd, &sc->ms_dev); 436 437 /* configure the children */ 438 (void)config_found(self, mtty_match, NULL); 439 (void)config_found(self, mbpp_match, NULL); 440 441 /* 442 * Establish the interrupt handlers. 443 */ 444 (void)bus_intr_establish(sa->sa_bustag, sa->sa_pri, 0, magma_hard, sc); 445 (void)bus_intr_establish(sa->sa_bustag, PIL_TTY, 446 BUS_INTR_ESTABLISH_SOFTINTR, 447 magma_soft, sc); 448 evcnt_attach(&sc->ms_dev, "intr", &sc->ms_intrcnt); 449 } 450 451 /* 452 * hard interrupt routine 453 * 454 * returns 1 if it handled it, otherwise 0 455 * 456 * runs at interrupt priority 457 */ 458 int 459 magma_hard(arg) 460 void *arg; 461 { 462 struct magma_softc *sc = arg; 463 struct cd1400 *cd; 464 int chip, status = 0; 465 int serviced = 0; 466 int needsoftint = 0; 467 468 /* 469 * check status of all the CD1400 chips 470 */ 471 for( chip = 0 ; chip < sc->ms_ncd1400 ; chip++ ) 472 status |= cd1400_read_reg(&sc->ms_cd1400[chip], CD1400_SVRR); 473 474 if( ISSET(status, CD1400_SVRR_RXRDY) ) { 475 u_char rivr = *sc->ms_svcackr; /* enter rx service context */ 476 int port = rivr >> 4; 477 478 if( rivr & (1<<3) ) { /* parallel port */ 479 struct mbpp_port *mbpp = &sc->ms_mbpp->ms_port[port]; 480 481 cd = mbpp->mp_cd1400; 482 } else { /* serial port */ 483 struct mtty_port *mtty; 484 u_char *ptr, n_chars, line_stat; 485 486 mtty = &sc->ms_mtty->ms_port[port]; 487 cd = mtty->mp_cd1400; 488 489 if( ISSET(rivr, CD1400_RIVR_EXCEPTION) ) { 490 line_stat = cd1400_read_reg(cd, CD1400_RDSR); 491 n_chars = 1; 492 } else { /* no exception, received data OK */ 493 line_stat = 0; 494 n_chars = cd1400_read_reg(cd, CD1400_RDCR); 495 } 496 497 ptr = mtty->mp_rput; 498 while( n_chars-- ) { 499 *ptr++ = line_stat; 500 *ptr++ = cd1400_read_reg(cd, CD1400_RDSR); 501 if( ptr == mtty->mp_rend ) ptr = mtty->mp_rbuf; 502 if( ptr == mtty->mp_rget ) { 503 if( ptr == mtty->mp_rbuf ) 504 ptr = mtty->mp_rend; 505 ptr -= 2; 506 SET(mtty->mp_flags, MTTYF_RING_OVERFLOW); 507 break; 508 } 509 } 510 mtty->mp_rput = ptr; 511 512 needsoftint = 1; 513 } 514 515 cd1400_write_reg(cd, CD1400_EOSRR, 0); /* end service context */ 516 serviced = 1; 517 } /* if(rx_service...) */ 518 519 if( ISSET(status, CD1400_SVRR_MDMCH) ) { 520 u_char mivr = *sc->ms_svcackm; /* enter mdm service context */ 521 int port = mivr >> 4; 522 struct mtty_port *mtty; 523 int carrier; 524 u_char msvr; 525 526 /* 527 * Handle CD (LC2+1Sp = DSR) changes. 528 */ 529 mtty = &sc->ms_mtty->ms_port[port]; 530 cd = mtty->mp_cd1400; 531 msvr = cd1400_read_reg(cd, CD1400_MSVR2); 532 carrier = ISSET(msvr, cd->cd_parmode ? CD1400_MSVR2_DSR : CD1400_MSVR2_CD); 533 534 if( mtty->mp_carrier != carrier ) { 535 SET(mtty->mp_flags, MTTYF_CARRIER_CHANGED); 536 mtty->mp_carrier = carrier; 537 needsoftint = 1; 538 } 539 540 cd1400_write_reg(cd, CD1400_EOSRR, 0); /* end service context */ 541 serviced = 1; 542 } /* if(mdm_service...) */ 543 544 if( ISSET(status, CD1400_SVRR_TXRDY) ) { 545 u_char tivr = *sc->ms_svcackt; /* enter tx service context */ 546 int port = tivr >> 4; 547 548 if( tivr & (1<<3) ) { /* parallel port */ 549 struct mbpp_port *mbpp; 550 551 mbpp = &sc->ms_mbpp->ms_port[port]; 552 cd = mbpp->mp_cd1400; 553 554 /* if we have anything to send, then send what we can.. 555 * otherwise shut off the interrupts and signal for 556 * a wakeup (can't be done at this spl because its 557 * sleeping in spltty() in mbppwrite) 558 */ 559 if( mbpp->mp_txc ) { 560 int count = 0; 561 562 while( count++ < CD1400_PAR_FIFO_SIZE && 563 mbpp->mp_txc ) { 564 cd1400_write_reg(cd, CD1400_TDR, *mbpp->mp_txp); 565 mbpp->mp_txc--; 566 mbpp->mp_txp++; 567 } 568 } else { 569 int srer; 570 571 srer = cd1400_read_reg(cd, CD1400_SRER); 572 CLR(srer, CD1400_SRER_TXRDY); 573 cd1400_write_reg(cd, CD1400_SRER, srer); 574 575 SET(mbpp->mp_flags, MBPPF_DONE); 576 needsoftint = 1; 577 } 578 } else { /* serial port */ 579 struct mtty_port *mtty; 580 struct tty *tp; 581 582 mtty = &sc->ms_mtty->ms_port[port]; 583 cd = mtty->mp_cd1400; 584 tp = mtty->mp_tty; 585 586 if( !ISSET(mtty->mp_flags, MTTYF_STOP) ) { 587 int count = 0; 588 589 /* check if we should start/stop a break */ 590 if( ISSET(mtty->mp_flags, MTTYF_SET_BREAK) ) { 591 cd1400_write_reg(cd, CD1400_TDR, 0); 592 cd1400_write_reg(cd, CD1400_TDR, 0x81); 593 /* should we delay too? */ 594 CLR(mtty->mp_flags, MTTYF_SET_BREAK); 595 count += 2; 596 } 597 598 if( ISSET(mtty->mp_flags, MTTYF_CLR_BREAK) ) { 599 cd1400_write_reg(cd, CD1400_TDR, 0); 600 cd1400_write_reg(cd, CD1400_TDR, 0x83); 601 CLR(mtty->mp_flags, MTTYF_CLR_BREAK); 602 count += 2; 603 } 604 605 /* I don't quite fill the fifo in case the last one is a 606 * NULL which I have to double up because its the escape 607 * code for embedded transmit characters. 608 */ 609 while( mtty->mp_txc > 0 && count < CD1400_TX_FIFO_SIZE - 1 ) { 610 u_char ch; 611 612 ch = *mtty->mp_txp; 613 614 mtty->mp_txc--; 615 mtty->mp_txp++; 616 617 if( ch == 0 ) { 618 cd1400_write_reg(cd, CD1400_TDR, ch); 619 count++; 620 } 621 622 cd1400_write_reg(cd, CD1400_TDR, ch); 623 count++; 624 } 625 } 626 627 /* if we ran out of work or are requested to STOP then 628 * shut off the txrdy interrupts and signal DONE to flush 629 * out the chars we have sent. 630 */ 631 if( mtty->mp_txc == 0 || ISSET(mtty->mp_flags, MTTYF_STOP) ) { 632 register int srer; 633 634 srer = cd1400_read_reg(cd, CD1400_SRER); 635 CLR(srer, CD1400_SRER_TXRDY); 636 cd1400_write_reg(cd, CD1400_SRER, srer); 637 CLR(mtty->mp_flags, MTTYF_STOP); 638 639 SET(mtty->mp_flags, MTTYF_DONE); 640 needsoftint = 1; 641 } 642 } 643 644 cd1400_write_reg(cd, CD1400_EOSRR, 0); /* end service context */ 645 serviced = 1; 646 } /* if(tx_service...) */ 647 648 /* XXX service CD1190 interrupts too 649 for( chip = 0 ; chip < sc->ms_ncd1190 ; chip++ ) { 650 } 651 */ 652 653 if( needsoftint ) { /* trigger the soft interrupt */ 654 #if defined(SUN4M) 655 if( CPU_ISSUN4M ) 656 raise(0, PIL_TTY); 657 else 658 #endif 659 ienab_bis(IE_MSOFT); 660 } 661 662 return(serviced); 663 } 664 665 /* 666 * magma soft interrupt handler 667 * 668 * returns 1 if it handled it, 0 otherwise 669 * 670 * runs at spltty() 671 */ 672 int 673 magma_soft(arg) 674 void *arg; 675 { 676 struct magma_softc *sc = arg; 677 struct mtty_softc *mtty = sc->ms_mtty; 678 struct mbpp_softc *mbpp = sc->ms_mbpp; 679 int port; 680 int serviced = 0; 681 int s, flags; 682 683 if (mtty == NULL) 684 goto chkbpp; 685 686 /* 687 * check the tty ports to see what needs doing 688 */ 689 for( port = 0 ; port < mtty->ms_nports ; port++ ) { 690 struct mtty_port *mp = &mtty->ms_port[port]; 691 struct tty *tp = mp->mp_tty; 692 693 if( !ISSET(tp->t_state, TS_ISOPEN) ) 694 continue; 695 696 /* 697 * handle any received data 698 */ 699 while( mp->mp_rget != mp->mp_rput ) { 700 u_char stat; 701 int data; 702 703 stat = mp->mp_rget[0]; 704 data = mp->mp_rget[1]; 705 mp->mp_rget = ((mp->mp_rget + 2) == mp->mp_rend) 706 ? mp->mp_rbuf : (mp->mp_rget + 2); 707 708 if( stat & (CD1400_RDSR_BREAK | CD1400_RDSR_FE) ) 709 data |= TTY_FE; 710 if( stat & CD1400_RDSR_PE ) 711 data |= TTY_PE; 712 713 if( stat & CD1400_RDSR_OE ) 714 log(LOG_WARNING, "%s%x: fifo overflow\n", 715 mtty->ms_dev.dv_xname, port); 716 717 (*linesw[tp->t_line].l_rint)(data, tp); 718 serviced = 1; 719 } 720 721 s = splhigh(); /* block out hard interrupt routine */ 722 flags = mp->mp_flags; 723 CLR(mp->mp_flags, MTTYF_DONE | MTTYF_CARRIER_CHANGED | MTTYF_RING_OVERFLOW); 724 splx(s); /* ok */ 725 726 if( ISSET(flags, MTTYF_CARRIER_CHANGED) ) { 727 dprintf(("%s%x: cd %s\n", mtty->ms_dev.dv_xname, port, mp->mp_carrier ? "on" : "off")); 728 (*linesw[tp->t_line].l_modem)(tp, mp->mp_carrier); 729 serviced = 1; 730 } 731 732 if( ISSET(flags, MTTYF_RING_OVERFLOW) ) { 733 log(LOG_WARNING, "%s%x: ring buffer overflow\n", mtty->ms_dev.dv_xname, port); 734 serviced = 1; 735 } 736 737 if( ISSET(flags, MTTYF_DONE) ) { 738 ndflush(&tp->t_outq, mp->mp_txp - tp->t_outq.c_cf); 739 CLR(tp->t_state, TS_BUSY); 740 (*linesw[tp->t_line].l_start)(tp); /* might be some more */ 741 serviced = 1; 742 } 743 } /* for(each mtty...) */ 744 745 746 chkbpp: 747 /* 748 * Check the bpp ports (if any) to see what needs doing 749 */ 750 if (mbpp == NULL) 751 return (serviced); 752 753 for( port = 0 ; port < mbpp->ms_nports ; port++ ) { 754 struct mbpp_port *mp = &mbpp->ms_port[port]; 755 756 if( !ISSET(mp->mp_flags, MBPPF_OPEN) ) 757 continue; 758 759 s = splhigh(); 760 flags = mp->mp_flags; 761 CLR(mp->mp_flags, MBPPF_DONE); 762 splx(s); 763 764 if( ISSET(flags, MBPPF_DONE) ) { 765 wakeup(mp); 766 serviced = 1; 767 } 768 769 } /* for(each mbpp...) */ 770 771 return(serviced); 772 } 773 774 /************************************************************************ 775 * 776 * MTTY Routines 777 * 778 * mtty_match match one mtty device 779 * mtty_attach attach mtty devices 780 * mttyopen open mtty device 781 * mttyclose close mtty device 782 * mttyread read from mtty 783 * mttywrite write to mtty 784 * mttyioctl do ioctl on mtty 785 * mttytty return tty pointer for mtty 786 * mttystop stop mtty device 787 * mtty_start start mtty device 788 * mtty_param set mtty parameters 789 * mtty_modem_control set modem control lines 790 */ 791 792 int 793 mtty_match(parent, cf, args) 794 struct device *parent; 795 struct cfdata *cf; 796 void *args; 797 { 798 struct magma_softc *sc = (struct magma_softc *)parent; 799 800 return( args == mtty_match && sc->ms_board->mb_nser && sc->ms_mtty == NULL ); 801 } 802 803 void 804 mtty_attach(parent, dev, args) 805 struct device *parent; 806 struct device *dev; 807 void *args; 808 { 809 struct magma_softc *sc = (struct magma_softc *)parent; 810 struct mtty_softc *ms = (struct mtty_softc *)dev; 811 int port, chip, chan; 812 813 sc->ms_mtty = ms; 814 dprintf((" addr %p", ms)); 815 816 for( port = 0, chip = 0, chan = 0 ; port < sc->ms_board->mb_nser ; port++ ) { 817 struct mtty_port *mp = &ms->ms_port[port]; 818 struct tty *tp; 819 820 mp->mp_cd1400 = &sc->ms_cd1400[chip]; 821 if( mp->mp_cd1400->cd_parmode && chan == 0 ) 822 chan = 1; /* skip channel 0 if parmode */ 823 mp->mp_channel = chan; 824 825 tp = ttymalloc(); 826 if( tp == NULL ) break; 827 tty_attach(tp); 828 tp->t_oproc = mtty_start; 829 tp->t_param = mtty_param; 830 831 mp->mp_tty = tp; 832 833 mp->mp_rbuf = malloc(MTTY_RBUF_SIZE, M_DEVBUF, M_NOWAIT); 834 if( mp->mp_rbuf == NULL ) break; 835 836 mp->mp_rend = mp->mp_rbuf + MTTY_RBUF_SIZE; 837 838 chan = (chan + 1) % CD1400_NO_OF_CHANNELS; 839 if( chan == 0 ) chip++; 840 } 841 842 ms->ms_nports = port; 843 printf(": %d tty%s\n", port, port == 1 ? "" : "s"); 844 } 845 846 /* 847 * open routine. returns zero if successful, else error code 848 */ 849 int 850 mttyopen(dev, flags, mode, p) 851 dev_t dev; 852 int flags; 853 int mode; 854 struct proc *p; 855 { 856 int card = MAGMA_CARD(dev); 857 int port = MAGMA_PORT(dev); 858 struct mtty_softc *ms; 859 struct mtty_port *mp; 860 struct tty *tp; 861 struct cd1400 *cd; 862 int error, s; 863 864 if( card >= mtty_cd.cd_ndevs || 865 (ms = mtty_cd.cd_devs[card]) == NULL || port >= ms->ms_nports ) 866 return(ENXIO); /* device not configured */ 867 868 mp = &ms->ms_port[port]; 869 tp = mp->mp_tty; 870 tp->t_dev = dev; 871 872 if (ISSET(tp->t_state, TS_ISOPEN) && 873 ISSET(tp->t_state, TS_XCLUDE) && 874 p->p_ucred->cr_uid != 0) 875 return (EBUSY); 876 877 s = spltty(); 878 879 if( !ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 880 881 /* set defaults */ 882 ttychars(tp); 883 tp->t_iflag = TTYDEF_IFLAG; 884 tp->t_oflag = TTYDEF_OFLAG; 885 tp->t_cflag = TTYDEF_CFLAG; 886 if( ISSET(mp->mp_openflags, TIOCFLAG_CLOCAL) ) 887 SET(tp->t_cflag, CLOCAL); 888 if( ISSET(mp->mp_openflags, TIOCFLAG_CRTSCTS) ) 889 SET(tp->t_cflag, CRTSCTS); 890 if( ISSET(mp->mp_openflags, TIOCFLAG_MDMBUF) ) 891 SET(tp->t_cflag, MDMBUF); 892 tp->t_lflag = TTYDEF_LFLAG; 893 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 894 895 /* init ring buffer */ 896 mp->mp_rput = mp->mp_rget = mp->mp_rbuf; 897 898 /* reset CD1400 channel */ 899 cd = mp->mp_cd1400; 900 cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel); 901 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET); 902 903 /* encode the port number in top half of LIVR */ 904 cd1400_write_reg(cd, CD1400_LIVR, port << 4 ); 905 906 /* sets parameters and raises DTR */ 907 (void)mtty_param(tp, &tp->t_termios); 908 909 /* set tty watermarks */ 910 ttsetwater(tp); 911 912 /* enable service requests */ 913 cd1400_write_reg(cd, CD1400_SRER, 914 CD1400_SRER_RXDATA | CD1400_SRER_MDMCH); 915 916 /* tell the tty about the carrier status */ 917 if( ISSET(mp->mp_openflags, TIOCFLAG_SOFTCAR) || 918 mp->mp_carrier ) 919 SET(tp->t_state, TS_CARR_ON); 920 else 921 CLR(tp->t_state, TS_CARR_ON); 922 } 923 splx(s); 924 925 error = ttyopen(tp, MTTY_DIALOUT(dev), ISSET(flags, O_NONBLOCK)); 926 if (error != 0) 927 goto bad; 928 929 error = (*linesw[tp->t_line].l_open)(dev, tp); 930 if (error != 0) 931 goto bad; 932 933 bad: 934 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 935 /* 936 * We failed to open the device, and nobody else had it opened. 937 * Clean up the state as appropriate. 938 */ 939 /* XXX - do that here */ 940 } 941 942 return (error); 943 } 944 945 /* 946 * close routine. returns zero if successful, else error code 947 */ 948 int 949 mttyclose(dev, flag, mode, p) 950 dev_t dev; 951 int flag; 952 int mode; 953 struct proc *p; 954 { 955 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(dev)]; 956 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 957 struct tty *tp = mp->mp_tty; 958 int s; 959 960 (*linesw[tp->t_line].l_close)(tp, flag); 961 ttyclose(tp); 962 963 s = spltty(); 964 965 /* if HUPCL is set, and the tty is no longer open 966 * shut down the port 967 */ 968 if( ISSET(tp->t_cflag, HUPCL) || !ISSET(tp->t_state, TS_ISOPEN) ) { 969 /* XXX wait until FIFO is empty before turning off the channel 970 struct cd1400 *cd = mp->mp_cd1400; 971 */ 972 973 /* drop DTR and RTS */ 974 (void)mtty_modem_control(mp, 0, DMSET); 975 976 /* turn off the channel 977 cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel); 978 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET); 979 */ 980 } 981 982 splx(s); 983 984 return(0); 985 } 986 987 /* 988 * Read routine 989 */ 990 int 991 mttyread(dev, uio, flags) 992 dev_t dev; 993 struct uio *uio; 994 int flags; 995 { 996 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(dev)]; 997 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 998 struct tty *tp = mp->mp_tty; 999 1000 return( (*linesw[tp->t_line].l_read)(tp, uio, flags) ); 1001 } 1002 1003 /* 1004 * Write routine 1005 */ 1006 int 1007 mttywrite(dev, uio, flags) 1008 dev_t dev; 1009 struct uio *uio; 1010 int flags; 1011 { 1012 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(dev)]; 1013 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1014 struct tty *tp = mp->mp_tty; 1015 1016 return( (*linesw[tp->t_line].l_write)(tp, uio, flags) ); 1017 } 1018 1019 /* 1020 * return tty pointer 1021 */ 1022 struct tty * 1023 mttytty(dev) 1024 dev_t dev; 1025 { 1026 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(dev)]; 1027 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1028 1029 return(mp->mp_tty); 1030 } 1031 1032 /* 1033 * ioctl routine 1034 */ 1035 int 1036 mttyioctl(dev, cmd, data, flags, p) 1037 dev_t dev; 1038 u_long cmd; 1039 caddr_t data; 1040 int flags; 1041 struct proc *p; 1042 { 1043 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(dev)]; 1044 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1045 struct tty *tp = mp->mp_tty; 1046 int error; 1047 1048 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flags, p); 1049 if( error >= 0 ) return(error); 1050 1051 error = ttioctl(tp, cmd, data, flags, p); 1052 if( error >= 0 ) return(error); 1053 1054 error = 0; 1055 1056 switch(cmd) { 1057 case TIOCSBRK: /* set break */ 1058 SET(mp->mp_flags, MTTYF_SET_BREAK); 1059 cd1400_enable_transmitter(mp->mp_cd1400, mp->mp_channel); 1060 break; 1061 1062 case TIOCCBRK: /* clear break */ 1063 SET(mp->mp_flags, MTTYF_CLR_BREAK); 1064 cd1400_enable_transmitter(mp->mp_cd1400, mp->mp_channel); 1065 break; 1066 1067 case TIOCSDTR: /* set DTR */ 1068 mtty_modem_control(mp, TIOCM_DTR, DMBIS); 1069 break; 1070 1071 case TIOCCDTR: /* clear DTR */ 1072 mtty_modem_control(mp, TIOCM_DTR, DMBIC); 1073 break; 1074 1075 case TIOCMSET: /* set modem lines */ 1076 mtty_modem_control(mp, *((int *)data), DMSET); 1077 break; 1078 1079 case TIOCMBIS: /* bit set modem lines */ 1080 mtty_modem_control(mp, *((int *)data), DMBIS); 1081 break; 1082 1083 case TIOCMBIC: /* bit clear modem lines */ 1084 mtty_modem_control(mp, *((int *)data), DMBIC); 1085 break; 1086 1087 case TIOCMGET: /* get modem lines */ 1088 *((int *)data) = mtty_modem_control(mp, 0, DMGET); 1089 break; 1090 1091 case TIOCGFLAGS: 1092 *((int *)data) = mp->mp_openflags; 1093 break; 1094 1095 case TIOCSFLAGS: 1096 if( suser(p->p_ucred, &p->p_acflag) ) 1097 error = EPERM; 1098 else 1099 mp->mp_openflags = *((int *)data) & 1100 (TIOCFLAG_SOFTCAR | TIOCFLAG_CLOCAL | 1101 TIOCFLAG_CRTSCTS | TIOCFLAG_MDMBUF); 1102 break; 1103 1104 default: 1105 error = ENOTTY; 1106 } 1107 1108 return(error); 1109 } 1110 1111 /* 1112 * Stop output, e.g., for ^S or output flush. 1113 */ 1114 void 1115 mttystop(tp, flags) 1116 struct tty *tp; 1117 int flags; 1118 { 1119 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(tp->t_dev)]; 1120 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(tp->t_dev)]; 1121 int s; 1122 1123 s = spltty(); 1124 1125 if( ISSET(tp->t_state, TS_BUSY) ) { 1126 if( !ISSET(tp->t_state, TS_TTSTOP) ) 1127 SET(tp->t_state, TS_FLUSH); 1128 1129 /* 1130 * the transmit interrupt routine will disable transmit when it 1131 * notices that MTTYF_STOP has been set. 1132 */ 1133 SET(mp->mp_flags, MTTYF_STOP); 1134 } 1135 1136 splx(s); 1137 } 1138 1139 /* 1140 * Start output, after a stop. 1141 */ 1142 void 1143 mtty_start(tp) 1144 struct tty *tp; 1145 { 1146 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(tp->t_dev)]; 1147 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(tp->t_dev)]; 1148 int s; 1149 1150 s = spltty(); 1151 1152 /* we only need to do something if we are not already busy 1153 * or delaying or stopped 1154 */ 1155 if( !ISSET(tp->t_state, TS_TTSTOP | TS_TIMEOUT | TS_BUSY) ) { 1156 1157 /* if we are sleeping and output has drained below 1158 * low water mark, awaken 1159 */ 1160 if( tp->t_outq.c_cc <= tp->t_lowat ) { 1161 if( ISSET(tp->t_state, TS_ASLEEP) ) { 1162 CLR(tp->t_state, TS_ASLEEP); 1163 wakeup(&tp->t_outq); 1164 } 1165 1166 selwakeup(&tp->t_wsel); 1167 } 1168 1169 /* if something to send, start transmitting 1170 */ 1171 if( tp->t_outq.c_cc ) { 1172 mp->mp_txc = ndqb(&tp->t_outq, 0); 1173 mp->mp_txp = tp->t_outq.c_cf; 1174 SET(tp->t_state, TS_BUSY); 1175 cd1400_enable_transmitter(mp->mp_cd1400, mp->mp_channel); 1176 } 1177 } 1178 1179 splx(s); 1180 } 1181 1182 /* 1183 * set/get modem line status 1184 * 1185 * bits can be: TIOCM_DTR, TIOCM_RTS, TIOCM_CTS, TIOCM_CD, TIOCM_RI, TIOCM_DSR 1186 * 1187 * note that DTR and RTS lines are exchanged, and that DSR is 1188 * not available on the LC2+1Sp card (used as CD) 1189 * 1190 * only let them fiddle with RTS if CRTSCTS is not enabled 1191 */ 1192 int 1193 mtty_modem_control(mp, bits, howto) 1194 struct mtty_port *mp; 1195 int bits; 1196 int howto; 1197 { 1198 struct cd1400 *cd = mp->mp_cd1400; 1199 struct tty *tp = mp->mp_tty; 1200 int s, msvr; 1201 1202 s = spltty(); 1203 1204 cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel); 1205 1206 switch(howto) { 1207 case DMGET: /* get bits */ 1208 bits = 0; 1209 1210 bits |= TIOCM_LE; 1211 1212 msvr = cd1400_read_reg(cd, CD1400_MSVR1); 1213 if( msvr & CD1400_MSVR1_RTS ) bits |= TIOCM_DTR; 1214 1215 msvr = cd1400_read_reg(cd, CD1400_MSVR2); 1216 if( msvr & CD1400_MSVR2_DTR ) bits |= TIOCM_RTS; 1217 if( msvr & CD1400_MSVR2_CTS ) bits |= TIOCM_CTS; 1218 if( msvr & CD1400_MSVR2_RI ) bits |= TIOCM_RI; 1219 if( msvr & CD1400_MSVR2_DSR ) bits |= (cd->cd_parmode ? TIOCM_CD : TIOCM_DSR); 1220 if( msvr & CD1400_MSVR2_CD ) bits |= (cd->cd_parmode ? 0 : TIOCM_CD); 1221 1222 break; 1223 1224 case DMSET: /* reset bits */ 1225 if( !ISSET(tp->t_cflag, CRTSCTS) ) 1226 cd1400_write_reg(cd, CD1400_MSVR2, ((bits & TIOCM_RTS) ? CD1400_MSVR2_DTR : 0)); 1227 1228 cd1400_write_reg(cd, CD1400_MSVR1, ((bits & TIOCM_DTR) ? CD1400_MSVR1_RTS : 0)); 1229 1230 break; 1231 1232 case DMBIS: /* set bits */ 1233 if( (bits & TIOCM_RTS) && !ISSET(tp->t_cflag, CRTSCTS) ) 1234 cd1400_write_reg(cd, CD1400_MSVR2, CD1400_MSVR2_DTR); 1235 1236 if( bits & TIOCM_DTR ) 1237 cd1400_write_reg(cd, CD1400_MSVR1, CD1400_MSVR1_RTS); 1238 1239 break; 1240 1241 case DMBIC: /* clear bits */ 1242 if( (bits & TIOCM_RTS) && !ISSET(tp->t_cflag, CRTSCTS) ) 1243 cd1400_write_reg(cd, CD1400_MSVR2, 0); 1244 1245 if( bits & TIOCM_DTR ) 1246 cd1400_write_reg(cd, CD1400_MSVR1, 0); 1247 1248 break; 1249 } 1250 1251 splx(s); 1252 return(bits); 1253 } 1254 1255 /* 1256 * Set tty parameters, returns error or 0 on success 1257 */ 1258 int 1259 mtty_param(tp, t) 1260 struct tty *tp; 1261 struct termios *t; 1262 { 1263 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(tp->t_dev)]; 1264 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(tp->t_dev)]; 1265 struct cd1400 *cd = mp->mp_cd1400; 1266 int rbpr, tbpr, rcor, tcor; 1267 u_char mcor1 = 0, mcor2 = 0; 1268 int s, opt; 1269 1270 if( t->c_ospeed && cd1400_compute_baud(t->c_ospeed, cd->cd_clock, &tcor, &tbpr) ) 1271 return(EINVAL); 1272 1273 if( t->c_ispeed && cd1400_compute_baud(t->c_ispeed, cd->cd_clock, &rcor, &rbpr) ) 1274 return(EINVAL); 1275 1276 s = spltty(); 1277 1278 /* hang up the line if ospeed is zero, else raise DTR */ 1279 (void)mtty_modem_control(mp, TIOCM_DTR, (t->c_ospeed == 0 ? DMBIC : DMBIS)); 1280 1281 /* select channel, done in mtty_modem_control() */ 1282 /* cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel); */ 1283 1284 /* set transmit speed */ 1285 if( t->c_ospeed ) { 1286 cd1400_write_reg(cd, CD1400_TCOR, tcor); 1287 cd1400_write_reg(cd, CD1400_TBPR, tbpr); 1288 } 1289 1290 /* set receive speed */ 1291 if( t->c_ispeed ) { 1292 cd1400_write_reg(cd, CD1400_RCOR, rcor); 1293 cd1400_write_reg(cd, CD1400_RBPR, rbpr); 1294 } 1295 1296 /* enable transmitting and receiving on this channel */ 1297 opt = CD1400_CCR_CMDCHANCTL | CD1400_CCR_XMTEN | CD1400_CCR_RCVEN; 1298 cd1400_write_ccr(cd, opt); 1299 1300 /* set parity, data and stop bits */ 1301 opt = 0; 1302 if( ISSET(t->c_cflag, PARENB) ) 1303 opt |= (ISSET(t->c_cflag, PARODD) ? CD1400_COR1_PARODD : CD1400_COR1_PARNORMAL); 1304 1305 if( !ISSET(t->c_iflag, INPCK) ) 1306 opt |= CD1400_COR1_NOINPCK; /* no parity checking */ 1307 1308 if( ISSET(t->c_cflag, CSTOPB) ) 1309 opt |= CD1400_COR1_STOP2; 1310 1311 switch( t->c_cflag & CSIZE ) { 1312 case CS5: 1313 opt |= CD1400_COR1_CS5; 1314 break; 1315 1316 case CS6: 1317 opt |= CD1400_COR1_CS6; 1318 break; 1319 1320 case CS7: 1321 opt |= CD1400_COR1_CS7; 1322 break; 1323 1324 default: 1325 opt |= CD1400_COR1_CS8; 1326 break; 1327 } 1328 1329 cd1400_write_reg(cd, CD1400_COR1, opt); 1330 1331 /* 1332 * enable Embedded Transmit Commands (for breaks) 1333 * use the CD1400 automatic CTS flow control if CRTSCTS is set 1334 */ 1335 opt = CD1400_COR2_ETC; 1336 if( ISSET(t->c_cflag, CRTSCTS) ) opt |= CD1400_COR2_CCTS_OFLOW; 1337 cd1400_write_reg(cd, CD1400_COR2, opt); 1338 1339 cd1400_write_reg(cd, CD1400_COR3, MTTY_RX_FIFO_THRESHOLD); 1340 1341 cd1400_write_ccr(cd, CD1400_CCR_CMDCORCHG | CD1400_CCR_COR1 | CD1400_CCR_COR2 | CD1400_CCR_COR3); 1342 1343 cd1400_write_reg(cd, CD1400_COR4, CD1400_COR4_PFO_EXCEPTION); 1344 cd1400_write_reg(cd, CD1400_COR5, 0); 1345 1346 /* 1347 * if automatic RTS handshaking enabled, set DTR threshold 1348 * (RTS and DTR lines are switched, CD1400 thinks its DTR) 1349 */ 1350 if( ISSET(t->c_cflag, CRTSCTS) ) 1351 mcor1 = MTTY_RX_DTR_THRESHOLD; 1352 1353 /* set up `carrier detect' interrupts */ 1354 if( cd->cd_parmode ) { 1355 SET(mcor1, CD1400_MCOR1_DSRzd); 1356 SET(mcor2, CD1400_MCOR2_DSRod); 1357 } else { 1358 SET(mcor1, CD1400_MCOR1_CDzd); 1359 SET(mcor2, CD1400_MCOR2_CDod); 1360 } 1361 1362 cd1400_write_reg(cd, CD1400_MCOR1, mcor1); 1363 cd1400_write_reg(cd, CD1400_MCOR2, mcor2); 1364 1365 /* receive timeout 2ms */ 1366 cd1400_write_reg(cd, CD1400_RTPR, 2); 1367 1368 splx(s); 1369 return(0); 1370 } 1371 1372 /************************************************************************ 1373 * 1374 * MBPP Routines 1375 * 1376 * mbpp_match match one mbpp device 1377 * mbpp_attach attach mbpp devices 1378 * mbppopen open mbpp device 1379 * mbppclose close mbpp device 1380 * mbppread read from mbpp 1381 * mbppwrite write to mbpp 1382 * mbppioctl do ioctl on mbpp 1383 */ 1384 1385 int 1386 mbpp_match(parent, cf, args) 1387 struct device *parent; 1388 struct cfdata *cf; 1389 void *args; 1390 { 1391 struct magma_softc *sc = (struct magma_softc *)parent; 1392 1393 return( args == mbpp_match && sc->ms_board->mb_npar && sc->ms_mbpp == NULL ); 1394 } 1395 1396 void 1397 mbpp_attach(parent, dev, args) 1398 struct device *parent; 1399 struct device *dev; 1400 void *args; 1401 { 1402 struct magma_softc *sc = (struct magma_softc *)parent; 1403 struct mbpp_softc *ms = (struct mbpp_softc *)dev; 1404 struct mbpp_port *mp; 1405 int port = 0; 1406 1407 sc->ms_mbpp = ms; 1408 dprintf((" addr %p", ms)); 1409 1410 for( port = 0 ; port < sc->ms_board->mb_npar ; port++ ) { 1411 mp = &ms->ms_port[port]; 1412 1413 if( sc->ms_ncd1190 ) 1414 mp->mp_cd1190 = &sc->ms_cd1190[port]; 1415 else 1416 mp->mp_cd1400 = &sc->ms_cd1400[0]; 1417 1418 mp->mp_txbuf = malloc(MBPP_TXBUF_SIZE, M_DEVBUF, M_NOWAIT); 1419 if( mp->mp_txbuf == NULL ) break; 1420 1421 /* 1422 * default strobe and timeout settings 1423 */ 1424 mp->mp_read_strobe = 1000; /* 1 microsecond */ 1425 mp->mp_read_timeout = 5 * hz; /* 5 seconds */ 1426 mp->mp_write_strobe = 1000; /* 1 microsecond */ 1427 mp->mp_write_timeout = 5 * hz; /* 5 seconds */ 1428 } 1429 1430 ms->ms_nports = port; 1431 printf(": %d port%s\n", port, port == 1 ? "" : "s"); 1432 } 1433 1434 /* 1435 * open routine. returns zero if successful, else error code 1436 */ 1437 int 1438 mbppopen(dev, flags, mode, p) 1439 dev_t dev; 1440 int flags; 1441 int mode; 1442 struct proc *p; 1443 { 1444 int card = MAGMA_CARD(dev); 1445 int port = MAGMA_PORT(dev); 1446 struct mbpp_softc *ms; 1447 struct mbpp_port *mp; 1448 int error = 0, s; 1449 1450 if( card >= mbpp_cd.cd_ndevs || 1451 (ms = mbpp_cd.cd_devs[card]) == NULL || port >= ms->ms_nports ) 1452 return(ENXIO); 1453 1454 mp = &ms->ms_port[port]; 1455 1456 s = spltty(); 1457 if( ISSET(mp->mp_flags, MBPPF_OPEN) ) { 1458 splx(s); 1459 return(EBUSY); 1460 } 1461 SET(mp->mp_flags, MBPPF_OPEN); 1462 splx(s); 1463 1464 if( mp->mp_cd1400 ) { /* CD1400 chip */ 1465 struct cd1400 *cd = mp->mp_cd1400; 1466 1467 /* set up CD1400 channel */ 1468 s = spltty(); 1469 cd1400_write_reg(cd, CD1400_CAR, 0); 1470 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET); 1471 cd1400_write_reg(cd, CD1400_TBPR, (mp->mp_write_strobe * cd->cd_clock / 2000)); 1472 cd1400_write_reg(cd, CD1400_LIVR, (1<<3)); 1473 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_XMTEN); 1474 splx(s); 1475 } else { /* CD1190 chip */ 1476 error = ENXIO; 1477 } 1478 1479 return(error); 1480 } 1481 1482 /* 1483 * close routine. returns zero if successful, else error code 1484 */ 1485 int 1486 mbppclose(dev, flag, mode, p) 1487 dev_t dev; 1488 int flag; 1489 int mode; 1490 struct proc *p; 1491 { 1492 struct mbpp_softc *ms = mbpp_cd.cd_devs[MAGMA_CARD(dev)]; 1493 struct mbpp_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1494 1495 if( mp->mp_cd1400 ) { 1496 struct cd1400 *cd = mp->mp_cd1400; 1497 int s; 1498 1499 s = spltty(); 1500 /* turn off the channel */ 1501 cd1400_write_reg(cd, CD1400_CAR, 0); 1502 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET); 1503 splx(s); 1504 } 1505 1506 mp->mp_flags = 0; 1507 1508 return(0); 1509 } 1510 1511 /* 1512 * Read routine 1513 */ 1514 int 1515 mbppread(dev, uio, flags) 1516 dev_t dev; 1517 struct uio *uio; 1518 int flags; 1519 { 1520 return(ENODEV); 1521 } 1522 1523 /* 1524 * Write routine 1525 */ 1526 int 1527 mbppwrite(dev, uio, flags) 1528 dev_t dev; 1529 struct uio *uio; 1530 int flags; 1531 { 1532 struct mbpp_softc *ms = mbpp_cd.cd_devs[MAGMA_CARD(dev)]; 1533 struct mbpp_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1534 int error = 0; 1535 int s; 1536 1537 while( uio->uio_resid ) { 1538 mp->mp_txc = MIN(uio->uio_resid, MBPP_TXBUF_SIZE); 1539 mp->mp_txp = mp->mp_txbuf; 1540 1541 error = uiomove((caddr_t)mp->mp_txp, mp->mp_txc, uio); 1542 if( error ) break; 1543 1544 s = spltty(); 1545 if( mp->mp_cd1400 ) 1546 cd1400_enable_transmitter(mp->mp_cd1400, 0); 1547 error = tsleep(mp, PCATCH | PZERO, "mbppwrite", mp->mp_write_timeout); 1548 splx(s); 1549 1550 if( error ) break; 1551 } /* while(more to send...) */ 1552 1553 if( error == EWOULDBLOCK ) { 1554 log(LOG_INFO, "%s%d: write timeout\n", 1555 ms->ms_dev.dv_xname, MAGMA_PORT(dev)); 1556 /* XXX check paper out, printer offline etc.. */ 1557 } 1558 1559 return(error); 1560 } 1561 1562 /* 1563 * ioctl routine 1564 */ 1565 int 1566 mbppioctl(dev, cmd, data, flags, p) 1567 dev_t dev; 1568 u_long cmd; 1569 caddr_t data; 1570 int flags; 1571 struct proc *p; 1572 { 1573 /* we want to be able to get & set strobe and timeout values */ 1574 return(ENODEV); 1575 } 1576 1577 /* 1578 * poll routine 1579 */ 1580 int 1581 mbpppoll(dev, rw, p) 1582 dev_t dev; 1583 int rw; 1584 struct proc *p; 1585 { 1586 return(ENODEV); 1587 } 1588 1589 #endif /* NMAGMA */ 1590
Indexes created Thu Oct 02 10:09:58 GMT 2025