magma.c revision 1.32.4.1
1 /* $NetBSD: magma.c,v 1.32.4.1 2006/09/09 02:54:25 rpaulo Exp $ */ 2 /* 3 * magma.c 4 * 5 * Copyright (c) 1998 Iain Hibbert 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Iain Hibbert 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35 /* 36 * Driver for Magma SBus Serial/Parallel cards using the Cirrus Logic 37 * CD1400 & CD1190 chips 38 */ 39 40 #include <sys/cdefs.h> 41 __KERNEL_RCSID(0, "$NetBSD: magma.c,v 1.32.4.1 2006/09/09 02:54:25 rpaulo Exp $"); 42 43 #if 0 44 #define MAGMA_DEBUG 45 #endif 46 47 #include "magma.h" 48 #if NMAGMA > 0 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/proc.h> 53 #include <sys/device.h> 54 #include <sys/file.h> 55 #include <sys/ioctl.h> 56 #include <sys/malloc.h> 57 #include <sys/tty.h> 58 #include <sys/time.h> 59 #include <sys/kernel.h> 60 #include <sys/syslog.h> 61 #include <sys/conf.h> 62 #include <sys/errno.h> 63 #include <sys/kauth.h> 64 65 #include <machine/bus.h> 66 #include <machine/intr.h> 67 #include <machine/autoconf.h> 68 69 #include <dev/sbus/sbusvar.h> 70 71 #include <dev/ic/cd1400reg.h> 72 #include <dev/ic/cd1190reg.h> 73 74 #include <dev/sbus/mbppio.h> 75 #include <dev/sbus/magmareg.h> 76 77 /* supported cards 78 * 79 * The table below lists the cards that this driver is likely to 80 * be able to support. 81 * 82 * Cards with parallel ports: except for the LC2+1Sp, they all use 83 * the CD1190 chip which I know nothing about. I've tried to leave 84 * hooks for it so it shouldn't be too hard to add support later. 85 * (I think somebody is working on this separately) 86 * 87 * Thanks to Bruce at Magma for telling me the hardware offsets. 88 */ 89 static struct magma_board_info supported_cards[] = { 90 { 91 "MAGMA_Sp", "MAGMA,4_Sp", "Magma 4 Sp", 4, 0, 92 1, 0xa000, 0xc000, 0xe000, { 0x8000, 0, 0, 0 }, 93 0, { 0, 0 } 94 }, 95 { 96 "MAGMA_Sp", "MAGMA,8_Sp", "Magma 8 Sp", 8, 0, 97 2, 0xa000, 0xc000, 0xe000, { 0x4000, 0x6000, 0, 0 }, 98 0, { 0, 0 } 99 }, 100 { 101 "MAGMA_Sp", "MAGMA,_8HS_Sp", "Magma Fast 8 Sp", 8, 0, 102 2, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0, 0 }, 103 0, { 0, 0 } 104 }, 105 { 106 "MAGMA_Sp", "MAGMA,_8SP_422", "Magma 8 Sp - 422", 8, 0, 107 2, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0, 0 }, 108 0, { 0, 0 } 109 }, 110 { 111 "MAGMA_Sp", "MAGMA,12_Sp", "Magma 12 Sp", 12, 0, 112 3, 0xa000, 0xc000, 0xe000, { 0x2000, 0x4000, 0x6000, 0 }, 113 0, { 0, 0 } 114 }, 115 { 116 "MAGMA_Sp", "MAGMA,16_Sp", "Magma 16 Sp", 16, 0, 117 4, 0xd000, 0xe000, 0xf000, { 0x8000, 0x9000, 0xa000, 0xb000 }, 118 0, { 0, 0 } 119 }, 120 { 121 "MAGMA_Sp", "MAGMA,16_Sp_2", "Magma 16 Sp", 16, 0, 122 4, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0xc000, 0xe000 }, 123 0, { 0, 0 } 124 }, 125 { 126 "MAGMA_Sp", "MAGMA,16HS_Sp", "Magma Fast 16 Sp", 16, 0, 127 4, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0xc000, 0xe000 }, 128 0, { 0, 0 } 129 }, 130 { 131 "MAGMA_Sp", "MAGMA,21_Sp", "Magma LC 2+1 Sp", 2, 1, 132 1, 0xa000, 0xc000, 0xe000, { 0x8000, 0, 0, 0 }, 133 0, { 0, 0 } 134 }, 135 { 136 "MAGMA_Sp", "MAGMA,21HS_Sp", "Magma 2+1 Sp", 2, 1, 137 1, 0xa000, 0xc000, 0xe000, { 0x4000, 0, 0, 0 }, 138 1, { 0x6000, 0 } 139 }, 140 { 141 "MAGMA_Sp", "MAGMA,41_Sp", "Magma 4+1 Sp", 4, 1, 142 1, 0xa000, 0xc000, 0xe000, { 0x4000, 0, 0, 0 }, 143 1, { 0x6000, 0 } 144 }, 145 { 146 "MAGMA_Sp", "MAGMA,82_Sp", "Magma 8+2 Sp", 8, 2, 147 2, 0xd000, 0xe000, 0xf000, { 0x8000, 0x9000, 0, 0 }, 148 2, { 0xa000, 0xb000 } 149 }, 150 { 151 "MAGMA_Sp", "MAGMA,P1_Sp", "Magma P1 Sp", 0, 1, 152 0, 0, 0, 0, { 0, 0, 0, 0 }, 153 1, { 0x8000, 0 } 154 }, 155 { 156 "MAGMA_Sp", "MAGMA,P2_Sp", "Magma P2 Sp", 0, 2, 157 0, 0, 0, 0, { 0, 0, 0, 0 }, 158 2, { 0x4000, 0x8000 } 159 }, 160 { 161 "MAGMA 2+1HS Sp", "", "Magma 2+1HS Sp", 2, 0, 162 1, 0xa000, 0xc000, 0xe000, { 0x4000, 0, 0, 0 }, 163 1, { 0x8000, 0 } 164 }, 165 { 166 NULL, NULL, NULL, 0, 0, 167 0, 0, 0, 0, { 0, 0, 0, 0 }, 168 0, { 0, 0 } 169 } 170 }; 171 172 /************************************************************************ 173 * 174 * Autoconfig Stuff 175 */ 176 177 CFATTACH_DECL(magma, sizeof(struct magma_softc), 178 magma_match, magma_attach, NULL, NULL); 179 180 CFATTACH_DECL(mtty, sizeof(struct mtty_softc), 181 mtty_match, mtty_attach, NULL, NULL); 182 183 CFATTACH_DECL(mbpp, sizeof(struct mbpp_softc), 184 mbpp_match, mbpp_attach, NULL, NULL); 185 186 extern struct cfdriver mtty_cd; 187 extern struct cfdriver mbpp_cd; 188 189 dev_type_open(mttyopen); 190 dev_type_close(mttyclose); 191 dev_type_read(mttyread); 192 dev_type_write(mttywrite); 193 dev_type_ioctl(mttyioctl); 194 dev_type_stop(mttystop); 195 dev_type_tty(mttytty); 196 dev_type_poll(mttypoll); 197 198 const struct cdevsw mtty_cdevsw = { 199 mttyopen, mttyclose, mttyread, mttywrite, mttyioctl, 200 mttystop, mttytty, mttypoll, nommap, ttykqfilter, D_TTY 201 }; 202 203 dev_type_open(mbppopen); 204 dev_type_close(mbppclose); 205 dev_type_read(mbpp_rw); 206 dev_type_ioctl(mbppioctl); 207 208 const struct cdevsw mbpp_cdevsw = { 209 mbppopen, mbppclose, mbpp_rw, mbpp_rw, mbppioctl, 210 nostop, notty, nopoll, nommap, nokqfilter, 211 }; 212 213 /************************************************************************ 214 * 215 * CD1400 Routines 216 * 217 * cd1400_compute_baud calculate COR/BPR register values 218 * cd1400_write_ccr write a value to CD1400 ccr 219 * cd1400_read_reg read from a CD1400 register 220 * cd1400_write_reg write to a CD1400 register 221 * cd1400_enable_transmitter enable transmitting on CD1400 channel 222 */ 223 224 /* 225 * compute the bpr/cor pair for any baud rate 226 * returns 0 for success, 1 for failure 227 */ 228 int 229 cd1400_compute_baud(speed, clock, cor, bpr) 230 speed_t speed; 231 int clock; 232 int *cor, *bpr; 233 { 234 int c, co, br; 235 236 if( speed < 50 || speed > 150000 ) 237 return(1); 238 239 for( c = 0, co = 8 ; co <= 2048 ; co <<= 2, c++ ) { 240 br = ((clock * 1000000) + (co * speed) / 2) / (co * speed); 241 if( br < 0x100 ) { 242 *bpr = br; 243 *cor = c; 244 return(0); 245 } 246 } 247 248 return(1); 249 } 250 251 /* 252 * Write a CD1400 channel command, should have a timeout? 253 */ 254 inline void 255 cd1400_write_ccr(cd, cmd) 256 struct cd1400 *cd; 257 u_char cmd; 258 { 259 while( cd1400_read_reg(cd, CD1400_CCR) ) 260 ; 261 262 cd1400_write_reg(cd, CD1400_CCR, cmd); 263 } 264 265 /* 266 * read a value from a cd1400 register 267 */ 268 inline u_char 269 cd1400_read_reg(cd, reg) 270 struct cd1400 *cd; 271 int reg; 272 { 273 return(cd->cd_reg[reg]); 274 } 275 276 /* 277 * write a value to a cd1400 register 278 */ 279 inline void 280 cd1400_write_reg(cd, reg, value) 281 struct cd1400 *cd; 282 int reg; 283 u_char value; 284 { 285 cd->cd_reg[reg] = value; 286 } 287 288 /* 289 * enable transmit service requests for cd1400 channel 290 */ 291 void 292 cd1400_enable_transmitter(cd, channel) 293 struct cd1400 *cd; 294 int channel; 295 { 296 int s, srer; 297 298 s = spltty(); 299 cd1400_write_reg(cd, CD1400_CAR, channel); 300 srer = cd1400_read_reg(cd, CD1400_SRER); 301 SET(srer, CD1400_SRER_TXRDY); 302 cd1400_write_reg(cd, CD1400_SRER, srer); 303 splx(s); 304 } 305 306 /************************************************************************ 307 * 308 * CD1190 Routines 309 */ 310 311 /* well, there are none yet */ 312 313 /************************************************************************ 314 * 315 * Magma Routines 316 * 317 * magma_match reports if we have a magma board available 318 * magma_attach attaches magma boards to the sbus 319 * magma_hard hardware level interrupt routine 320 * magma_soft software level interrupt routine 321 */ 322 323 int 324 magma_match(parent, cf, aux) 325 struct device *parent; 326 struct cfdata *cf; 327 void *aux; 328 { 329 struct sbus_attach_args *sa = aux; 330 struct magma_board_info *card; 331 332 /* See if we support this device */ 333 for (card = supported_cards; ; card++) { 334 if (card->mb_sbusname == NULL) 335 /* End of table: no match */ 336 return (0); 337 if (strcmp(sa->sa_name, card->mb_sbusname) == 0) 338 break; 339 } 340 341 dprintf(("magma: matched `%s'\n", sa->sa_name)); 342 dprintf(("magma: magma_prom `%s'\n", 343 prom_getpropstring(sa->sa_node, "magma_prom"))); 344 dprintf(("magma: intlevels `%s'\n", 345 prom_getpropstring(sa->sa_node, "intlevels"))); 346 dprintf(("magma: chiprev `%s'\n", 347 prom_getpropstring(sa->sa_node, "chiprev"))); 348 dprintf(("magma: clock `%s'\n", 349 prom_getpropstring(sa->sa_node, "clock"))); 350 351 return (1); 352 } 353 354 void 355 magma_attach(parent, self, aux) 356 struct device *parent; 357 struct device *self; 358 void *aux; 359 { 360 struct sbus_attach_args *sa = aux; 361 struct magma_softc *sc = (struct magma_softc *)self; 362 struct magma_board_info *card; 363 bus_space_handle_t bh; 364 char *magma_prom, *clockstr; 365 int cd_clock; 366 int node, chip; 367 368 node = sa->sa_node; 369 370 /* 371 * Find the card model. 372 * Older models all have sbus node name `MAGMA_Sp' (see 373 * `supported_cards[]' above), and must be distinguished 374 * by the `magma_prom' property. 375 */ 376 magma_prom = prom_getpropstring(node, "magma_prom"); 377 378 for (card = supported_cards; card->mb_name != NULL; card++) { 379 if (strcmp(sa->sa_name, card->mb_sbusname) != 0) 380 /* Sbus node name doesn't match */ 381 continue; 382 if (strcmp(magma_prom, card->mb_name) == 0) 383 /* Model name match */ 384 break; 385 } 386 387 if( card->mb_name == NULL ) { 388 printf(": %s (unsupported)\n", magma_prom); 389 return; 390 } 391 392 dprintf((" addr %p", sc)); 393 printf(": %s\n", card->mb_realname); 394 395 sc->ms_board = card; 396 sc->ms_ncd1400 = card->mb_ncd1400; 397 sc->ms_ncd1190 = card->mb_ncd1190; 398 399 if (sbus_bus_map(sa->sa_bustag, 400 sa->sa_slot, sa->sa_offset, sa->sa_size, 401 BUS_SPACE_MAP_LINEAR, &bh) != 0) { 402 printf("%s @ sbus: cannot map registers\n", self->dv_xname); 403 return; 404 } 405 406 /* the SVCACK* lines are daisychained */ 407 sc->ms_svcackr = (caddr_t)bus_space_vaddr(sa->sa_bustag, bh) 408 + card->mb_svcackr; 409 sc->ms_svcackt = (caddr_t)bus_space_vaddr(sa->sa_bustag, bh) 410 + card->mb_svcackt; 411 sc->ms_svcackm = (caddr_t)bus_space_vaddr(sa->sa_bustag, bh) 412 + card->mb_svcackm; 413 414 /* 415 * Find the clock speed; it's the same for all CD1400 chips 416 * on the board. 417 */ 418 clockstr = prom_getpropstring(node, "clock"); 419 if (*clockstr == '\0') 420 /* Default to 25MHz */ 421 cd_clock = 25; 422 else { 423 cd_clock = 0; 424 while (*clockstr != '\0') 425 cd_clock = (cd_clock * 10) + (*clockstr++ - '0'); 426 } 427 428 /* init the cd1400 chips */ 429 for( chip = 0 ; chip < card->mb_ncd1400 ; chip++ ) { 430 struct cd1400 *cd = &sc->ms_cd1400[chip]; 431 432 cd->cd_clock = cd_clock; 433 cd->cd_reg = (caddr_t)bh + card->mb_cd1400[chip]; 434 435 /* prom_getpropstring(node, "chiprev"); */ 436 /* seemingly the Magma drivers just ignore the propstring */ 437 cd->cd_chiprev = cd1400_read_reg(cd, CD1400_GFRCR); 438 439 dprintf(("%s attach CD1400 %d addr %p rev %x clock %dMHz\n", 440 sc->ms_dev.dv_xname, chip, 441 cd->cd_reg, cd->cd_chiprev, cd->cd_clock)); 442 443 /* clear GFRCR */ 444 cd1400_write_reg(cd, CD1400_GFRCR, 0x00); 445 446 /* reset whole chip */ 447 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET | CD1400_CCR_FULLRESET); 448 449 /* wait for revision code to be restored */ 450 while( cd1400_read_reg(cd, CD1400_GFRCR) != cd->cd_chiprev ) 451 ; 452 453 /* set the Prescaler Period Register to tick at 1ms */ 454 cd1400_write_reg(cd, CD1400_PPR, 455 ((cd->cd_clock * 1000000 / CD1400_PPR_PRESCALER + 500) / 1000)); 456 457 /* The LC2+1Sp card is the only card that doesn't have 458 * a CD1190 for the parallel port, but uses channel 0 of 459 * the CD1400, so we make a note of it for later and set up 460 * the CD1400 for parallel mode operation. 461 */ 462 if( card->mb_npar && card->mb_ncd1190 == 0 ) { 463 cd1400_write_reg(cd, CD1400_GCR, CD1400_GCR_PARALLEL); 464 cd->cd_parmode = 1; 465 } 466 } 467 468 /* init the cd1190 chips */ 469 for( chip = 0 ; chip < card->mb_ncd1190 ; chip++ ) { 470 struct cd1190 *cd = &sc->ms_cd1190[chip]; 471 472 cd->cd_reg = (caddr_t)bh + card->mb_cd1190[chip]; 473 474 /* XXX don't know anything about these chips yet */ 475 printf("%s: CD1190 %d addr %p (unsupported)\n", 476 self->dv_xname, chip, cd->cd_reg); 477 } 478 479 sbus_establish(&sc->ms_sd, &sc->ms_dev); 480 481 /* configure the children */ 482 (void)config_found(self, mtty_match, NULL); 483 (void)config_found(self, mbpp_match, NULL); 484 485 /* 486 * Establish the interrupt handlers. 487 */ 488 if (sa->sa_nintr == 0) 489 return; /* No interrupts to service!? */ 490 491 (void)bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_SERIAL, 492 magma_hard, sc); 493 sc->ms_sicookie = softintr_establish(IPL_SOFTSERIAL, magma_soft, sc); 494 if (sc->ms_sicookie == NULL) { 495 printf("\n%s: cannot establish soft int handler\n", 496 sc->ms_dev.dv_xname); 497 return; 498 } 499 evcnt_attach_dynamic(&sc->ms_intrcnt, EVCNT_TYPE_INTR, NULL, 500 sc->ms_dev.dv_xname, "intr"); 501 } 502 503 /* 504 * hard interrupt routine 505 * 506 * returns 1 if it handled it, otherwise 0 507 * 508 * runs at interrupt priority 509 */ 510 int 511 magma_hard(arg) 512 void *arg; 513 { 514 struct magma_softc *sc = arg; 515 struct cd1400 *cd; 516 int chip, status = 0; 517 int serviced = 0; 518 int needsoftint = 0; 519 520 /* 521 * check status of all the CD1400 chips 522 */ 523 for( chip = 0 ; chip < sc->ms_ncd1400 ; chip++ ) 524 status |= cd1400_read_reg(&sc->ms_cd1400[chip], CD1400_SVRR); 525 526 if( ISSET(status, CD1400_SVRR_RXRDY) ) { 527 u_char rivr = *sc->ms_svcackr; /* enter rx service context */ 528 int port = rivr >> 4; 529 530 if( rivr & (1<<3) ) { /* parallel port */ 531 struct mbpp_port *mbpp; 532 int n_chars; 533 534 mbpp = &sc->ms_mbpp->ms_port[port]; 535 cd = mbpp->mp_cd1400; 536 537 /* don't think we have to handle exceptions */ 538 n_chars = cd1400_read_reg(cd, CD1400_RDCR); 539 while (n_chars--) { 540 if( mbpp->mp_cnt == 0 ) { 541 SET(mbpp->mp_flags, MBPPF_WAKEUP); 542 needsoftint = 1; 543 break; 544 } 545 *mbpp->mp_ptr = cd1400_read_reg(cd,CD1400_RDSR); 546 mbpp->mp_ptr++; 547 mbpp->mp_cnt--; 548 } 549 } else { /* serial port */ 550 struct mtty_port *mtty; 551 u_char *ptr, n_chars, line_stat; 552 553 mtty = &sc->ms_mtty->ms_port[port]; 554 cd = mtty->mp_cd1400; 555 556 if( ISSET(rivr, CD1400_RIVR_EXCEPTION) ) { 557 line_stat = cd1400_read_reg(cd, CD1400_RDSR); 558 n_chars = 1; 559 } else { /* no exception, received data OK */ 560 line_stat = 0; 561 n_chars = cd1400_read_reg(cd, CD1400_RDCR); 562 } 563 564 ptr = mtty->mp_rput; 565 while( n_chars-- ) { 566 *ptr++ = line_stat; 567 *ptr++ = cd1400_read_reg(cd, CD1400_RDSR); 568 if( ptr == mtty->mp_rend ) ptr = mtty->mp_rbuf; 569 if( ptr == mtty->mp_rget ) { 570 if( ptr == mtty->mp_rbuf ) 571 ptr = mtty->mp_rend; 572 ptr -= 2; 573 SET(mtty->mp_flags, MTTYF_RING_OVERFLOW); 574 break; 575 } 576 } 577 mtty->mp_rput = ptr; 578 579 needsoftint = 1; 580 } 581 582 cd1400_write_reg(cd, CD1400_EOSRR, 0); /* end service context */ 583 serviced = 1; 584 } /* if(rx_service...) */ 585 586 if( ISSET(status, CD1400_SVRR_MDMCH) ) { 587 u_char mivr = *sc->ms_svcackm; /* enter mdm service context */ 588 int port = mivr >> 4; 589 struct mtty_port *mtty; 590 int carrier; 591 u_char msvr; 592 593 /* 594 * Handle CD (LC2+1Sp = DSR) changes. 595 */ 596 mtty = &sc->ms_mtty->ms_port[port]; 597 cd = mtty->mp_cd1400; 598 msvr = cd1400_read_reg(cd, CD1400_MSVR2); 599 carrier = ISSET(msvr, cd->cd_parmode ? CD1400_MSVR2_DSR : CD1400_MSVR2_CD); 600 601 if( mtty->mp_carrier != carrier ) { 602 SET(mtty->mp_flags, MTTYF_CARRIER_CHANGED); 603 mtty->mp_carrier = carrier; 604 needsoftint = 1; 605 } 606 607 cd1400_write_reg(cd, CD1400_EOSRR, 0); /* end service context */ 608 serviced = 1; 609 } /* if(mdm_service...) */ 610 611 if( ISSET(status, CD1400_SVRR_TXRDY) ) { 612 u_char tivr = *sc->ms_svcackt; /* enter tx service context */ 613 int port = tivr >> 4; 614 615 if( tivr & (1<<3) ) { /* parallel port */ 616 struct mbpp_port *mbpp; 617 618 mbpp = &sc->ms_mbpp->ms_port[port]; 619 cd = mbpp->mp_cd1400; 620 621 if( mbpp->mp_cnt ) { 622 int count = 0; 623 624 /* fill the fifo */ 625 while (mbpp->mp_cnt && 626 count++ < CD1400_PAR_FIFO_SIZE) { 627 cd1400_write_reg(cd, CD1400_TDR, 628 *mbpp->mp_ptr); 629 mbpp->mp_ptr++; 630 mbpp->mp_cnt--; 631 } 632 } else { 633 /* 634 * fifo is empty and we got no more data 635 * to send, so shut off interrupts and 636 * signal for a wakeup, which can't be 637 * done here in case we beat mbpp_send to 638 * the tsleep call (we are running at >spltty) 639 */ 640 cd1400_write_reg(cd, CD1400_SRER, 0); 641 SET(mbpp->mp_flags, MBPPF_WAKEUP); 642 needsoftint = 1; 643 } 644 } else { /* serial port */ 645 struct mtty_port *mtty; 646 struct tty *tp; 647 648 mtty = &sc->ms_mtty->ms_port[port]; 649 cd = mtty->mp_cd1400; 650 tp = mtty->mp_tty; 651 652 if( !ISSET(mtty->mp_flags, MTTYF_STOP) ) { 653 int count = 0; 654 655 /* check if we should start/stop a break */ 656 if( ISSET(mtty->mp_flags, MTTYF_SET_BREAK) ) { 657 cd1400_write_reg(cd, CD1400_TDR, 0); 658 cd1400_write_reg(cd, CD1400_TDR, 0x81); 659 /* should we delay too? */ 660 CLR(mtty->mp_flags, MTTYF_SET_BREAK); 661 count += 2; 662 } 663 664 if( ISSET(mtty->mp_flags, MTTYF_CLR_BREAK) ) { 665 cd1400_write_reg(cd, CD1400_TDR, 0); 666 cd1400_write_reg(cd, CD1400_TDR, 0x83); 667 CLR(mtty->mp_flags, MTTYF_CLR_BREAK); 668 count += 2; 669 } 670 671 /* I don't quite fill the fifo in case the last one is a 672 * NULL which I have to double up because its the escape 673 * code for embedded transmit characters. 674 */ 675 while( mtty->mp_txc > 0 && count < CD1400_TX_FIFO_SIZE - 1 ) { 676 u_char ch; 677 678 ch = *mtty->mp_txp; 679 680 mtty->mp_txc--; 681 mtty->mp_txp++; 682 683 if( ch == 0 ) { 684 cd1400_write_reg(cd, CD1400_TDR, ch); 685 count++; 686 } 687 688 cd1400_write_reg(cd, CD1400_TDR, ch); 689 count++; 690 } 691 } 692 693 /* if we ran out of work or are requested to STOP then 694 * shut off the txrdy interrupts and signal DONE to flush 695 * out the chars we have sent. 696 */ 697 if( mtty->mp_txc == 0 || ISSET(mtty->mp_flags, MTTYF_STOP) ) { 698 register int srer; 699 700 srer = cd1400_read_reg(cd, CD1400_SRER); 701 CLR(srer, CD1400_SRER_TXRDY); 702 cd1400_write_reg(cd, CD1400_SRER, srer); 703 CLR(mtty->mp_flags, MTTYF_STOP); 704 705 SET(mtty->mp_flags, MTTYF_DONE); 706 needsoftint = 1; 707 } 708 } 709 710 cd1400_write_reg(cd, CD1400_EOSRR, 0); /* end service context */ 711 serviced = 1; 712 } /* if(tx_service...) */ 713 714 /* XXX service CD1190 interrupts too 715 for( chip = 0 ; chip < sc->ms_ncd1190 ; chip++ ) { 716 } 717 */ 718 719 if (needsoftint) 720 /* trigger the soft interrupt */ 721 softintr_schedule(sc->ms_sicookie); 722 723 return(serviced); 724 } 725 726 /* 727 * magma soft interrupt handler 728 * 729 * returns 1 if it handled it, 0 otherwise 730 * 731 * runs at spltty() 732 */ 733 void 734 magma_soft(arg) 735 void *arg; 736 { 737 struct magma_softc *sc = arg; 738 struct mtty_softc *mtty = sc->ms_mtty; 739 struct mbpp_softc *mbpp = sc->ms_mbpp; 740 int port; 741 int s, flags; 742 743 if (mtty == NULL) 744 goto chkbpp; 745 746 /* 747 * check the tty ports to see what needs doing 748 */ 749 for( port = 0 ; port < mtty->ms_nports ; port++ ) { 750 struct mtty_port *mp = &mtty->ms_port[port]; 751 struct tty *tp = mp->mp_tty; 752 753 if( !ISSET(tp->t_state, TS_ISOPEN) ) 754 continue; 755 756 /* 757 * handle any received data 758 */ 759 while( mp->mp_rget != mp->mp_rput ) { 760 u_char stat; 761 int data; 762 763 stat = mp->mp_rget[0]; 764 data = mp->mp_rget[1]; 765 mp->mp_rget = ((mp->mp_rget + 2) == mp->mp_rend) 766 ? mp->mp_rbuf : (mp->mp_rget + 2); 767 768 if( stat & (CD1400_RDSR_BREAK | CD1400_RDSR_FE) ) 769 data |= TTY_FE; 770 if( stat & CD1400_RDSR_PE ) 771 data |= TTY_PE; 772 773 if( stat & CD1400_RDSR_OE ) 774 log(LOG_WARNING, "%s%x: fifo overflow\n", 775 mtty->ms_dev.dv_xname, port); 776 777 (*tp->t_linesw->l_rint)(data, tp); 778 } 779 780 s = splhigh(); /* block out hard interrupt routine */ 781 flags = mp->mp_flags; 782 CLR(mp->mp_flags, MTTYF_DONE | MTTYF_CARRIER_CHANGED | MTTYF_RING_OVERFLOW); 783 splx(s); /* ok */ 784 785 if( ISSET(flags, MTTYF_CARRIER_CHANGED) ) { 786 dprintf(("%s%x: cd %s\n", mtty->ms_dev.dv_xname, 787 port, mp->mp_carrier ? "on" : "off")); 788 (*tp->t_linesw->l_modem)(tp, mp->mp_carrier); 789 } 790 791 if( ISSET(flags, MTTYF_RING_OVERFLOW) ) { 792 log(LOG_WARNING, "%s%x: ring buffer overflow\n", 793 mtty->ms_dev.dv_xname, port); 794 } 795 796 if( ISSET(flags, MTTYF_DONE) ) { 797 ndflush(&tp->t_outq, mp->mp_txp - tp->t_outq.c_cf); 798 CLR(tp->t_state, TS_BUSY); 799 (*tp->t_linesw->l_start)(tp); /* might be some more */ 800 } 801 } /* for(each mtty...) */ 802 803 804 chkbpp: 805 /* 806 * Check the bpp ports (if any) to see what needs doing 807 */ 808 if (mbpp == NULL) 809 return; 810 811 for( port = 0 ; port < mbpp->ms_nports ; port++ ) { 812 struct mbpp_port *mp = &mbpp->ms_port[port]; 813 814 if( !ISSET(mp->mp_flags, MBPPF_OPEN) ) 815 continue; 816 817 s = splhigh(); 818 flags = mp->mp_flags; 819 CLR(mp->mp_flags, MBPPF_WAKEUP); 820 splx(s); 821 822 if( ISSET(flags, MBPPF_WAKEUP) ) { 823 wakeup(mp); 824 } 825 826 } /* for(each mbpp...) */ 827 } 828 829 /************************************************************************ 830 * 831 * MTTY Routines 832 * 833 * mtty_match match one mtty device 834 * mtty_attach attach mtty devices 835 * mttyopen open mtty device 836 * mttyclose close mtty device 837 * mttyread read from mtty 838 * mttywrite write to mtty 839 * mttyioctl do ioctl on mtty 840 * mttytty return tty pointer for mtty 841 * mttystop stop mtty device 842 * mtty_start start mtty device 843 * mtty_param set mtty parameters 844 * mtty_modem_control set modem control lines 845 */ 846 847 int 848 mtty_match(parent, cf, args) 849 struct device *parent; 850 struct cfdata *cf; 851 void *args; 852 { 853 struct magma_softc *sc = (struct magma_softc *)parent; 854 855 return( args == mtty_match && sc->ms_board->mb_nser && sc->ms_mtty == NULL ); 856 } 857 858 void 859 mtty_attach(parent, dev, args) 860 struct device *parent; 861 struct device *dev; 862 void *args; 863 { 864 struct magma_softc *sc = (struct magma_softc *)parent; 865 struct mtty_softc *ms = (struct mtty_softc *)dev; 866 int port, chip, chan; 867 868 sc->ms_mtty = ms; 869 dprintf((" addr %p", ms)); 870 871 for( port = 0, chip = 0, chan = 0 ; port < sc->ms_board->mb_nser ; port++ ) { 872 struct mtty_port *mp = &ms->ms_port[port]; 873 struct tty *tp; 874 875 mp->mp_cd1400 = &sc->ms_cd1400[chip]; 876 if (mp->mp_cd1400->cd_parmode && chan == 0) 877 chan = 1; /* skip channel 0 if parmode */ 878 mp->mp_channel = chan; 879 880 tp = ttymalloc(); 881 if (tp == NULL) break; 882 tty_attach(tp); 883 tp->t_oproc = mtty_start; 884 tp->t_param = mtty_param; 885 886 mp->mp_tty = tp; 887 888 mp->mp_rbuf = malloc(MTTY_RBUF_SIZE, M_DEVBUF, M_NOWAIT); 889 if (mp->mp_rbuf == NULL) break; 890 891 mp->mp_rend = mp->mp_rbuf + MTTY_RBUF_SIZE; 892 893 chan = (chan + 1) % CD1400_NO_OF_CHANNELS; 894 if (chan == 0) 895 chip++; 896 } 897 898 ms->ms_nports = port; 899 printf(": %d tty%s\n", port, port == 1 ? "" : "s"); 900 } 901 902 /* 903 * open routine. returns zero if successful, else error code 904 */ 905 int 906 mttyopen(dev, flags, mode, l) 907 dev_t dev; 908 int flags; 909 int mode; 910 struct lwp *l; 911 { 912 int card = MAGMA_CARD(dev); 913 int port = MAGMA_PORT(dev); 914 struct mtty_softc *ms; 915 struct mtty_port *mp; 916 struct tty *tp; 917 struct cd1400 *cd; 918 int error, s; 919 920 if( card >= mtty_cd.cd_ndevs || 921 (ms = mtty_cd.cd_devs[card]) == NULL || port >= ms->ms_nports ) 922 return(ENXIO); /* device not configured */ 923 924 mp = &ms->ms_port[port]; 925 tp = mp->mp_tty; 926 tp->t_dev = dev; 927 928 if (ISSET(tp->t_state, TS_ISOPEN) && 929 ISSET(tp->t_state, TS_XCLUDE) && 930 kauth_authorize_generic(l->l_cred, KAUTH_GENERIC_ISSUSER, 931 &l->l_acflag) != 0) 932 return (EBUSY); 933 934 s = spltty(); 935 936 if( !ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 937 938 /* set defaults */ 939 ttychars(tp); 940 tp->t_iflag = TTYDEF_IFLAG; 941 tp->t_oflag = TTYDEF_OFLAG; 942 tp->t_cflag = TTYDEF_CFLAG; 943 if( ISSET(mp->mp_openflags, TIOCFLAG_CLOCAL) ) 944 SET(tp->t_cflag, CLOCAL); 945 if( ISSET(mp->mp_openflags, TIOCFLAG_CRTSCTS) ) 946 SET(tp->t_cflag, CRTSCTS); 947 if( ISSET(mp->mp_openflags, TIOCFLAG_MDMBUF) ) 948 SET(tp->t_cflag, MDMBUF); 949 tp->t_lflag = TTYDEF_LFLAG; 950 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 951 952 /* init ring buffer */ 953 mp->mp_rput = mp->mp_rget = mp->mp_rbuf; 954 955 /* reset CD1400 channel */ 956 cd = mp->mp_cd1400; 957 cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel); 958 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET); 959 960 /* encode the port number in top half of LIVR */ 961 cd1400_write_reg(cd, CD1400_LIVR, port << 4 ); 962 963 /* sets parameters and raises DTR */ 964 (void)mtty_param(tp, &tp->t_termios); 965 966 /* set tty watermarks */ 967 ttsetwater(tp); 968 969 /* enable service requests */ 970 cd1400_write_reg(cd, CD1400_SRER, 971 CD1400_SRER_RXDATA | CD1400_SRER_MDMCH); 972 973 /* tell the tty about the carrier status */ 974 if( ISSET(mp->mp_openflags, TIOCFLAG_SOFTCAR) || 975 mp->mp_carrier ) 976 SET(tp->t_state, TS_CARR_ON); 977 else 978 CLR(tp->t_state, TS_CARR_ON); 979 } 980 splx(s); 981 982 error = ttyopen(tp, MTTY_DIALOUT(dev), ISSET(flags, O_NONBLOCK)); 983 if (error != 0) 984 goto bad; 985 986 error = (*tp->t_linesw->l_open)(dev, tp); 987 if (error != 0) 988 goto bad; 989 990 bad: 991 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 992 /* 993 * We failed to open the device, and nobody else had it opened. 994 * Clean up the state as appropriate. 995 */ 996 /* XXX - do that here */ 997 } 998 999 return (error); 1000 } 1001 1002 /* 1003 * close routine. returns zero if successful, else error code 1004 */ 1005 int 1006 mttyclose(dev, flag, mode, l) 1007 dev_t dev; 1008 int flag; 1009 int mode; 1010 struct lwp *l; 1011 { 1012 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(dev)]; 1013 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1014 struct tty *tp = mp->mp_tty; 1015 int s; 1016 1017 (*tp->t_linesw->l_close)(tp, flag); 1018 ttyclose(tp); 1019 1020 s = spltty(); 1021 1022 /* if HUPCL is set, and the tty is no longer open 1023 * shut down the port 1024 */ 1025 if( ISSET(tp->t_cflag, HUPCL) || !ISSET(tp->t_state, TS_ISOPEN) ) { 1026 /* XXX wait until FIFO is empty before turning off the channel 1027 struct cd1400 *cd = mp->mp_cd1400; 1028 */ 1029 1030 /* drop DTR and RTS */ 1031 (void)mtty_modem_control(mp, 0, DMSET); 1032 1033 /* turn off the channel 1034 cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel); 1035 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET); 1036 */ 1037 } 1038 1039 splx(s); 1040 1041 return(0); 1042 } 1043 1044 /* 1045 * Read routine 1046 */ 1047 int 1048 mttyread(dev, uio, flags) 1049 dev_t dev; 1050 struct uio *uio; 1051 int flags; 1052 { 1053 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(dev)]; 1054 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1055 struct tty *tp = mp->mp_tty; 1056 1057 return( (*tp->t_linesw->l_read)(tp, uio, flags) ); 1058 } 1059 1060 /* 1061 * Write routine 1062 */ 1063 int 1064 mttywrite(dev, uio, flags) 1065 dev_t dev; 1066 struct uio *uio; 1067 int flags; 1068 { 1069 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(dev)]; 1070 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1071 struct tty *tp = mp->mp_tty; 1072 1073 return( (*tp->t_linesw->l_write)(tp, uio, flags) ); 1074 } 1075 1076 /* 1077 * Poll routine 1078 */ 1079 int 1080 mttypoll(dev, events, l) 1081 dev_t dev; 1082 int events; 1083 struct lwp *l; 1084 { 1085 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(dev)]; 1086 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1087 struct tty *tp = mp->mp_tty; 1088 1089 return ((*tp->t_linesw->l_poll)(tp, events, l)); 1090 } 1091 1092 /* 1093 * return tty pointer 1094 */ 1095 struct tty * 1096 mttytty(dev) 1097 dev_t dev; 1098 { 1099 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(dev)]; 1100 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1101 1102 return(mp->mp_tty); 1103 } 1104 1105 /* 1106 * ioctl routine 1107 */ 1108 int 1109 mttyioctl(dev, cmd, data, flags, l) 1110 dev_t dev; 1111 u_long cmd; 1112 caddr_t data; 1113 int flags; 1114 struct lwp *l; 1115 { 1116 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(dev)]; 1117 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1118 struct tty *tp = mp->mp_tty; 1119 int error; 1120 1121 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flags, l); 1122 if( error != EPASSTHROUGH ) return(error); 1123 1124 error = ttioctl(tp, cmd, data, flags, l); 1125 if( error != EPASSTHROUGH ) return(error); 1126 1127 error = 0; 1128 1129 switch(cmd) { 1130 case TIOCSBRK: /* set break */ 1131 SET(mp->mp_flags, MTTYF_SET_BREAK); 1132 cd1400_enable_transmitter(mp->mp_cd1400, mp->mp_channel); 1133 break; 1134 1135 case TIOCCBRK: /* clear break */ 1136 SET(mp->mp_flags, MTTYF_CLR_BREAK); 1137 cd1400_enable_transmitter(mp->mp_cd1400, mp->mp_channel); 1138 break; 1139 1140 case TIOCSDTR: /* set DTR */ 1141 mtty_modem_control(mp, TIOCM_DTR, DMBIS); 1142 break; 1143 1144 case TIOCCDTR: /* clear DTR */ 1145 mtty_modem_control(mp, TIOCM_DTR, DMBIC); 1146 break; 1147 1148 case TIOCMSET: /* set modem lines */ 1149 mtty_modem_control(mp, *((int *)data), DMSET); 1150 break; 1151 1152 case TIOCMBIS: /* bit set modem lines */ 1153 mtty_modem_control(mp, *((int *)data), DMBIS); 1154 break; 1155 1156 case TIOCMBIC: /* bit clear modem lines */ 1157 mtty_modem_control(mp, *((int *)data), DMBIC); 1158 break; 1159 1160 case TIOCMGET: /* get modem lines */ 1161 *((int *)data) = mtty_modem_control(mp, 0, DMGET); 1162 break; 1163 1164 case TIOCGFLAGS: 1165 *((int *)data) = mp->mp_openflags; 1166 break; 1167 1168 case TIOCSFLAGS: 1169 if (kauth_authorize_generic(l->l_cred, KAUTH_GENERIC_ISSUSER, 1170 &l->l_acflag) ) 1171 error = EPERM; 1172 else 1173 mp->mp_openflags = *((int *)data) & 1174 (TIOCFLAG_SOFTCAR | TIOCFLAG_CLOCAL | 1175 TIOCFLAG_CRTSCTS | TIOCFLAG_MDMBUF); 1176 break; 1177 1178 default: 1179 error = EPASSTHROUGH; 1180 } 1181 1182 return(error); 1183 } 1184 1185 /* 1186 * Stop output, e.g., for ^S or output flush. 1187 */ 1188 void 1189 mttystop(tp, flags) 1190 struct tty *tp; 1191 int flags; 1192 { 1193 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(tp->t_dev)]; 1194 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(tp->t_dev)]; 1195 int s; 1196 1197 s = spltty(); 1198 1199 if( ISSET(tp->t_state, TS_BUSY) ) { 1200 if( !ISSET(tp->t_state, TS_TTSTOP) ) 1201 SET(tp->t_state, TS_FLUSH); 1202 1203 /* 1204 * the transmit interrupt routine will disable transmit when it 1205 * notices that MTTYF_STOP has been set. 1206 */ 1207 SET(mp->mp_flags, MTTYF_STOP); 1208 } 1209 1210 splx(s); 1211 } 1212 1213 /* 1214 * Start output, after a stop. 1215 */ 1216 void 1217 mtty_start(tp) 1218 struct tty *tp; 1219 { 1220 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(tp->t_dev)]; 1221 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(tp->t_dev)]; 1222 int s; 1223 1224 s = spltty(); 1225 1226 /* we only need to do something if we are not already busy 1227 * or delaying or stopped 1228 */ 1229 if( !ISSET(tp->t_state, TS_TTSTOP | TS_TIMEOUT | TS_BUSY) ) { 1230 1231 /* if we are sleeping and output has drained below 1232 * low water mark, awaken 1233 */ 1234 if( tp->t_outq.c_cc <= tp->t_lowat ) { 1235 if( ISSET(tp->t_state, TS_ASLEEP) ) { 1236 CLR(tp->t_state, TS_ASLEEP); 1237 wakeup(&tp->t_outq); 1238 } 1239 1240 selwakeup(&tp->t_wsel); 1241 } 1242 1243 /* if something to send, start transmitting 1244 */ 1245 if( tp->t_outq.c_cc ) { 1246 mp->mp_txc = ndqb(&tp->t_outq, 0); 1247 mp->mp_txp = tp->t_outq.c_cf; 1248 SET(tp->t_state, TS_BUSY); 1249 cd1400_enable_transmitter(mp->mp_cd1400, mp->mp_channel); 1250 } 1251 } 1252 1253 splx(s); 1254 } 1255 1256 /* 1257 * set/get modem line status 1258 * 1259 * bits can be: TIOCM_DTR, TIOCM_RTS, TIOCM_CTS, TIOCM_CD, TIOCM_RI, TIOCM_DSR 1260 * 1261 * note that DTR and RTS lines are exchanged, and that DSR is 1262 * not available on the LC2+1Sp card (used as CD) 1263 * 1264 * only let them fiddle with RTS if CRTSCTS is not enabled 1265 */ 1266 int 1267 mtty_modem_control(mp, bits, howto) 1268 struct mtty_port *mp; 1269 int bits; 1270 int howto; 1271 { 1272 struct cd1400 *cd = mp->mp_cd1400; 1273 struct tty *tp = mp->mp_tty; 1274 int s, msvr; 1275 1276 s = spltty(); 1277 1278 cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel); 1279 1280 switch(howto) { 1281 case DMGET: /* get bits */ 1282 bits = 0; 1283 1284 bits |= TIOCM_LE; 1285 1286 msvr = cd1400_read_reg(cd, CD1400_MSVR1); 1287 if( msvr & CD1400_MSVR1_RTS ) bits |= TIOCM_DTR; 1288 1289 msvr = cd1400_read_reg(cd, CD1400_MSVR2); 1290 if( msvr & CD1400_MSVR2_DTR ) bits |= TIOCM_RTS; 1291 if( msvr & CD1400_MSVR2_CTS ) bits |= TIOCM_CTS; 1292 if( msvr & CD1400_MSVR2_RI ) bits |= TIOCM_RI; 1293 if( msvr & CD1400_MSVR2_DSR ) bits |= (cd->cd_parmode ? TIOCM_CD : TIOCM_DSR); 1294 if( msvr & CD1400_MSVR2_CD ) bits |= (cd->cd_parmode ? 0 : TIOCM_CD); 1295 1296 break; 1297 1298 case DMSET: /* reset bits */ 1299 if( !ISSET(tp->t_cflag, CRTSCTS) ) 1300 cd1400_write_reg(cd, CD1400_MSVR2, ((bits & TIOCM_RTS) ? CD1400_MSVR2_DTR : 0)); 1301 1302 cd1400_write_reg(cd, CD1400_MSVR1, ((bits & TIOCM_DTR) ? CD1400_MSVR1_RTS : 0)); 1303 1304 break; 1305 1306 case DMBIS: /* set bits */ 1307 if( (bits & TIOCM_RTS) && !ISSET(tp->t_cflag, CRTSCTS) ) 1308 cd1400_write_reg(cd, CD1400_MSVR2, CD1400_MSVR2_DTR); 1309 1310 if( bits & TIOCM_DTR ) 1311 cd1400_write_reg(cd, CD1400_MSVR1, CD1400_MSVR1_RTS); 1312 1313 break; 1314 1315 case DMBIC: /* clear bits */ 1316 if( (bits & TIOCM_RTS) && !ISSET(tp->t_cflag, CRTSCTS) ) 1317 cd1400_write_reg(cd, CD1400_MSVR2, 0); 1318 1319 if( bits & TIOCM_DTR ) 1320 cd1400_write_reg(cd, CD1400_MSVR1, 0); 1321 1322 break; 1323 } 1324 1325 splx(s); 1326 return(bits); 1327 } 1328 1329 /* 1330 * Set tty parameters, returns error or 0 on success 1331 */ 1332 int 1333 mtty_param(tp, t) 1334 struct tty *tp; 1335 struct termios *t; 1336 { 1337 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(tp->t_dev)]; 1338 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(tp->t_dev)]; 1339 struct cd1400 *cd = mp->mp_cd1400; 1340 int rbpr, tbpr, rcor, tcor; 1341 u_char mcor1 = 0, mcor2 = 0; 1342 int s, opt; 1343 1344 if( t->c_ospeed && cd1400_compute_baud(t->c_ospeed, cd->cd_clock, &tcor, &tbpr) ) 1345 return(EINVAL); 1346 1347 if( t->c_ispeed && cd1400_compute_baud(t->c_ispeed, cd->cd_clock, &rcor, &rbpr) ) 1348 return(EINVAL); 1349 1350 s = spltty(); 1351 1352 /* hang up the line if ospeed is zero, else raise DTR */ 1353 (void)mtty_modem_control(mp, TIOCM_DTR, (t->c_ospeed == 0 ? DMBIC : DMBIS)); 1354 1355 /* select channel, done in mtty_modem_control() */ 1356 /* cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel); */ 1357 1358 /* set transmit speed */ 1359 if( t->c_ospeed ) { 1360 cd1400_write_reg(cd, CD1400_TCOR, tcor); 1361 cd1400_write_reg(cd, CD1400_TBPR, tbpr); 1362 } 1363 1364 /* set receive speed */ 1365 if( t->c_ispeed ) { 1366 cd1400_write_reg(cd, CD1400_RCOR, rcor); 1367 cd1400_write_reg(cd, CD1400_RBPR, rbpr); 1368 } 1369 1370 /* enable transmitting and receiving on this channel */ 1371 opt = CD1400_CCR_CMDCHANCTL | CD1400_CCR_XMTEN | CD1400_CCR_RCVEN; 1372 cd1400_write_ccr(cd, opt); 1373 1374 /* set parity, data and stop bits */ 1375 opt = 0; 1376 if( ISSET(t->c_cflag, PARENB) ) 1377 opt |= (ISSET(t->c_cflag, PARODD) ? CD1400_COR1_PARODD : CD1400_COR1_PARNORMAL); 1378 1379 if( !ISSET(t->c_iflag, INPCK) ) 1380 opt |= CD1400_COR1_NOINPCK; /* no parity checking */ 1381 1382 if( ISSET(t->c_cflag, CSTOPB) ) 1383 opt |= CD1400_COR1_STOP2; 1384 1385 switch( t->c_cflag & CSIZE ) { 1386 case CS5: 1387 opt |= CD1400_COR1_CS5; 1388 break; 1389 1390 case CS6: 1391 opt |= CD1400_COR1_CS6; 1392 break; 1393 1394 case CS7: 1395 opt |= CD1400_COR1_CS7; 1396 break; 1397 1398 default: 1399 opt |= CD1400_COR1_CS8; 1400 break; 1401 } 1402 1403 cd1400_write_reg(cd, CD1400_COR1, opt); 1404 1405 /* 1406 * enable Embedded Transmit Commands (for breaks) 1407 * use the CD1400 automatic CTS flow control if CRTSCTS is set 1408 */ 1409 opt = CD1400_COR2_ETC; 1410 if( ISSET(t->c_cflag, CRTSCTS) ) opt |= CD1400_COR2_CCTS_OFLOW; 1411 cd1400_write_reg(cd, CD1400_COR2, opt); 1412 1413 cd1400_write_reg(cd, CD1400_COR3, MTTY_RX_FIFO_THRESHOLD); 1414 1415 cd1400_write_ccr(cd, CD1400_CCR_CMDCORCHG | CD1400_CCR_COR1 | CD1400_CCR_COR2 | CD1400_CCR_COR3); 1416 1417 cd1400_write_reg(cd, CD1400_COR4, CD1400_COR4_PFO_EXCEPTION); 1418 cd1400_write_reg(cd, CD1400_COR5, 0); 1419 1420 /* 1421 * if automatic RTS handshaking enabled, set DTR threshold 1422 * (RTS and DTR lines are switched, CD1400 thinks its DTR) 1423 */ 1424 if( ISSET(t->c_cflag, CRTSCTS) ) 1425 mcor1 = MTTY_RX_DTR_THRESHOLD; 1426 1427 /* set up `carrier detect' interrupts */ 1428 if( cd->cd_parmode ) { 1429 SET(mcor1, CD1400_MCOR1_DSRzd); 1430 SET(mcor2, CD1400_MCOR2_DSRod); 1431 } else { 1432 SET(mcor1, CD1400_MCOR1_CDzd); 1433 SET(mcor2, CD1400_MCOR2_CDod); 1434 } 1435 1436 cd1400_write_reg(cd, CD1400_MCOR1, mcor1); 1437 cd1400_write_reg(cd, CD1400_MCOR2, mcor2); 1438 1439 /* receive timeout 2ms */ 1440 cd1400_write_reg(cd, CD1400_RTPR, 2); 1441 1442 splx(s); 1443 return(0); 1444 } 1445 1446 /************************************************************************ 1447 * 1448 * MBPP Routines 1449 * 1450 * mbpp_match match one mbpp device 1451 * mbpp_attach attach mbpp devices 1452 * mbppopen open mbpp device 1453 * mbppclose close mbpp device 1454 * mbppioctl do ioctl on mbpp 1455 * mbpp_rw general rw routine 1456 * mbpp_timeout rw timeout 1457 * mbpp_start rw start after delay 1458 * mbpp_send send data 1459 * mbpp_recv recv data 1460 */ 1461 1462 int 1463 mbpp_match(parent, cf, args) 1464 struct device *parent; 1465 struct cfdata *cf; 1466 void *args; 1467 { 1468 struct magma_softc *sc = (struct magma_softc *)parent; 1469 1470 return( args == mbpp_match && sc->ms_board->mb_npar && sc->ms_mbpp == NULL ); 1471 } 1472 1473 void 1474 mbpp_attach(parent, dev, args) 1475 struct device *parent; 1476 struct device *dev; 1477 void *args; 1478 { 1479 struct magma_softc *sc = (struct magma_softc *)parent; 1480 struct mbpp_softc *ms = (struct mbpp_softc *)dev; 1481 struct mbpp_port *mp; 1482 int port; 1483 1484 sc->ms_mbpp = ms; 1485 dprintf((" addr %p", ms)); 1486 1487 for( port = 0 ; port < sc->ms_board->mb_npar ; port++ ) { 1488 mp = &ms->ms_port[port]; 1489 1490 callout_init(&mp->mp_timeout_ch); 1491 callout_init(&mp->mp_start_ch); 1492 1493 if( sc->ms_ncd1190 ) 1494 mp->mp_cd1190 = &sc->ms_cd1190[port]; 1495 else 1496 mp->mp_cd1400 = &sc->ms_cd1400[0]; 1497 } 1498 1499 ms->ms_nports = port; 1500 printf(": %d port%s\n", port, port == 1 ? "" : "s"); 1501 } 1502 1503 /* 1504 * open routine. returns zero if successful, else error code 1505 */ 1506 int 1507 mbppopen(dev, flags, mode, l) 1508 dev_t dev; 1509 int flags; 1510 int mode; 1511 struct lwp *l; 1512 { 1513 int card = MAGMA_CARD(dev); 1514 int port = MAGMA_PORT(dev); 1515 struct mbpp_softc *ms; 1516 struct mbpp_port *mp; 1517 int s; 1518 1519 if( card >= mbpp_cd.cd_ndevs || 1520 (ms = mbpp_cd.cd_devs[card]) == NULL || port >= ms->ms_nports ) 1521 return(ENXIO); 1522 1523 mp = &ms->ms_port[port]; 1524 1525 s = spltty(); 1526 if( ISSET(mp->mp_flags, MBPPF_OPEN) ) { 1527 splx(s); 1528 return(EBUSY); 1529 } 1530 SET(mp->mp_flags, MBPPF_OPEN); 1531 splx(s); 1532 1533 /* set defaults */ 1534 mp->mp_burst = MBPP_BURST; 1535 mp->mp_timeout = mbpp_mstohz(MBPP_TIMEOUT); 1536 mp->mp_delay = mbpp_mstohz(MBPP_DELAY); 1537 1538 /* init chips */ 1539 if( mp->mp_cd1400 ) { /* CD1400 */ 1540 struct cd1400 *cd = mp->mp_cd1400; 1541 1542 /* set up CD1400 channel */ 1543 s = spltty(); 1544 cd1400_write_reg(cd, CD1400_CAR, 0); 1545 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET); 1546 cd1400_write_reg(cd, CD1400_LIVR, (1<<3)); 1547 splx(s); 1548 } else { /* CD1190 */ 1549 mp->mp_flags = 0; 1550 return (ENXIO); 1551 } 1552 1553 return (0); 1554 } 1555 1556 /* 1557 * close routine. returns zero if successful, else error code 1558 */ 1559 int 1560 mbppclose(dev, flag, mode, l) 1561 dev_t dev; 1562 int flag; 1563 int mode; 1564 struct lwp *l; 1565 { 1566 struct mbpp_softc *ms = mbpp_cd.cd_devs[MAGMA_CARD(dev)]; 1567 struct mbpp_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1568 1569 mp->mp_flags = 0; 1570 return(0); 1571 } 1572 1573 /* 1574 * ioctl routine 1575 */ 1576 int 1577 mbppioctl(dev, cmd, data, flags, l) 1578 dev_t dev; 1579 u_long cmd; 1580 caddr_t data; 1581 int flags; 1582 struct lwp *l; 1583 { 1584 struct mbpp_softc *ms = mbpp_cd.cd_devs[MAGMA_CARD(dev)]; 1585 struct mbpp_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1586 struct mbpp_param *bp; 1587 int error = 0; 1588 int s; 1589 1590 switch(cmd) { 1591 case MBPPIOCSPARAM: 1592 bp = (struct mbpp_param *)data; 1593 if( bp->bp_burst < MBPP_BURST_MIN || bp->bp_burst > MBPP_BURST_MAX || 1594 bp->bp_delay < MBPP_DELAY_MIN || bp->bp_delay > MBPP_DELAY_MIN ) { 1595 error = EINVAL; 1596 } else { 1597 mp->mp_burst = bp->bp_burst; 1598 mp->mp_timeout = mbpp_mstohz(bp->bp_timeout); 1599 mp->mp_delay = mbpp_mstohz(bp->bp_delay); 1600 } 1601 break; 1602 case MBPPIOCGPARAM: 1603 bp = (struct mbpp_param *)data; 1604 bp->bp_burst = mp->mp_burst; 1605 bp->bp_timeout = mbpp_hztoms(mp->mp_timeout); 1606 bp->bp_delay = mbpp_hztoms(mp->mp_delay); 1607 break; 1608 case MBPPIOCGSTAT: 1609 /* XXX make this more generic */ 1610 s = spltty(); 1611 cd1400_write_reg(mp->mp_cd1400, CD1400_CAR, 0); 1612 *(int *)data = cd1400_read_reg(mp->mp_cd1400, CD1400_PSVR); 1613 splx(s); 1614 break; 1615 default: 1616 error = ENOTTY; 1617 } 1618 1619 return(error); 1620 } 1621 1622 int 1623 mbpp_rw(dev, uio, flag) 1624 dev_t dev; 1625 struct uio *uio; 1626 int flag; 1627 { 1628 int card = MAGMA_CARD(dev); 1629 int port = MAGMA_PORT(dev); 1630 struct mbpp_softc *ms = mbpp_cd.cd_devs[card]; 1631 struct mbpp_port *mp = &ms->ms_port[port]; 1632 caddr_t buffer, ptr; 1633 int buflen, cnt, len; 1634 int s, error = 0; 1635 int gotdata = 0; 1636 1637 if( uio->uio_resid == 0 ) 1638 return(0); 1639 1640 buflen = min(uio->uio_resid, mp->mp_burst); 1641 buffer = malloc(buflen, M_DEVBUF, M_WAITOK); 1642 if( buffer == NULL ) 1643 return(ENOMEM); 1644 1645 SET(mp->mp_flags, MBPPF_UIO); 1646 1647 /* 1648 * start timeout, if needed 1649 */ 1650 if( mp->mp_timeout > 0 ) { 1651 SET(mp->mp_flags, MBPPF_TIMEOUT); 1652 callout_reset(&mp->mp_timeout_ch, mp->mp_timeout, 1653 mbpp_timeout, mp); 1654 } 1655 1656 len = cnt = 0; 1657 while( uio->uio_resid > 0 ) { 1658 len = min(buflen, uio->uio_resid); 1659 ptr = buffer; 1660 1661 if( uio->uio_rw == UIO_WRITE ) { 1662 error = uiomove(ptr, len, uio); 1663 if( error ) break; 1664 } 1665 again: /* goto bad */ 1666 /* timed out? */ 1667 if( !ISSET(mp->mp_flags, MBPPF_UIO) ) 1668 break; 1669 1670 /* 1671 * perform the operation 1672 */ 1673 if( uio->uio_rw == UIO_WRITE ) { 1674 cnt = mbpp_send(mp, ptr, len); 1675 } else { 1676 cnt = mbpp_recv(mp, ptr, len); 1677 } 1678 1679 if( uio->uio_rw == UIO_READ ) { 1680 if( cnt ) { 1681 error = uiomove(ptr, cnt, uio); 1682 if( error ) break; 1683 gotdata++; 1684 } 1685 else if( gotdata ) /* consider us done */ 1686 break; 1687 } 1688 1689 /* timed out? */ 1690 if( !ISSET(mp->mp_flags, MBPPF_UIO) ) 1691 break; 1692 1693 /* 1694 * poll delay? 1695 */ 1696 if( mp->mp_delay > 0 ) { 1697 s = splsoftclock(); 1698 SET(mp->mp_flags, MBPPF_DELAY); 1699 callout_reset(&mp->mp_start_ch, mp->mp_delay, 1700 mbpp_start, mp); 1701 error = tsleep(mp, PCATCH | PZERO, "mbppdelay", 0); 1702 splx(s); 1703 if( error ) break; 1704 } 1705 1706 /* 1707 * don't call uiomove again until we used all the data we grabbed 1708 */ 1709 if( uio->uio_rw == UIO_WRITE && cnt != len ) { 1710 ptr += cnt; 1711 len -= cnt; 1712 cnt = 0; 1713 goto again; 1714 } 1715 } 1716 1717 /* 1718 * clear timeouts 1719 */ 1720 s = splsoftclock(); 1721 if( ISSET(mp->mp_flags, MBPPF_TIMEOUT) ) { 1722 callout_stop(&mp->mp_timeout_ch); 1723 CLR(mp->mp_flags, MBPPF_TIMEOUT); 1724 } 1725 if( ISSET(mp->mp_flags, MBPPF_DELAY) ) { 1726 callout_stop(&mp->mp_start_ch); 1727 CLR(mp->mp_flags, MBPPF_DELAY); 1728 } 1729 splx(s); 1730 1731 /* 1732 * adjust for those chars that we uiomoved but never actually wrote 1733 */ 1734 if( uio->uio_rw == UIO_WRITE && cnt != len ) { 1735 uio->uio_resid += (len - cnt); 1736 } 1737 1738 free(buffer, M_DEVBUF); 1739 return(error); 1740 } 1741 1742 void 1743 mbpp_timeout(arg) 1744 void *arg; 1745 { 1746 struct mbpp_port *mp = arg; 1747 1748 CLR(mp->mp_flags, MBPPF_UIO | MBPPF_TIMEOUT); 1749 wakeup(mp); 1750 } 1751 1752 void 1753 mbpp_start(arg) 1754 void *arg; 1755 { 1756 struct mbpp_port *mp = arg; 1757 1758 CLR(mp->mp_flags, MBPPF_DELAY); 1759 wakeup(mp); 1760 } 1761 1762 int 1763 mbpp_send(mp, ptr, len) 1764 struct mbpp_port *mp; 1765 caddr_t ptr; 1766 int len; 1767 { 1768 int s; 1769 struct cd1400 *cd = mp->mp_cd1400; 1770 1771 /* set up io information */ 1772 mp->mp_ptr = ptr; 1773 mp->mp_cnt = len; 1774 1775 /* start transmitting */ 1776 s = spltty(); 1777 if( cd ) { 1778 cd1400_write_reg(cd, CD1400_CAR, 0); 1779 1780 /* output strobe width ~1microsecond */ 1781 cd1400_write_reg(cd, CD1400_TBPR, 10); 1782 1783 /* enable channel */ 1784 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_XMTEN); 1785 cd1400_write_reg(cd, CD1400_SRER, CD1400_SRER_TXRDY); 1786 } 1787 1788 /* ZZzzz... */ 1789 tsleep(mp, PCATCH | PZERO, "mbpp_send", 0); 1790 1791 /* stop transmitting */ 1792 if( cd ) { 1793 cd1400_write_reg(cd, CD1400_CAR, 0); 1794 1795 /* disable transmitter */ 1796 cd1400_write_reg(cd, CD1400_SRER, 0); 1797 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_XMTDIS); 1798 1799 /* flush fifo */ 1800 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET | CD1400_CCR_FTF); 1801 } 1802 splx(s); 1803 1804 /* return number of chars sent */ 1805 return(len - mp->mp_cnt); 1806 } 1807 1808 int 1809 mbpp_recv(mp, ptr, len) 1810 struct mbpp_port *mp; 1811 caddr_t ptr; 1812 int len; 1813 { 1814 int s; 1815 struct cd1400 *cd = mp->mp_cd1400; 1816 1817 /* set up io information */ 1818 mp->mp_ptr = ptr; 1819 mp->mp_cnt = len; 1820 1821 /* start receiving */ 1822 s = spltty(); 1823 if( cd ) { 1824 int rcor, rbpr; 1825 1826 cd1400_write_reg(cd, CD1400_CAR, 0); 1827 1828 /* input strobe at 100kbaud (10microseconds) */ 1829 cd1400_compute_baud(100000, cd->cd_clock, &rcor, &rbpr); 1830 cd1400_write_reg(cd, CD1400_RCOR, rcor); 1831 cd1400_write_reg(cd, CD1400_RBPR, rbpr); 1832 1833 /* rx threshold */ 1834 cd1400_write_reg(cd, CD1400_COR3, MBPP_RX_FIFO_THRESHOLD); 1835 cd1400_write_ccr(cd, CD1400_CCR_CMDCORCHG | CD1400_CCR_COR3); 1836 1837 /* enable channel */ 1838 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_RCVEN); 1839 cd1400_write_reg(cd, CD1400_SRER, CD1400_SRER_RXDATA); 1840 } 1841 1842 /* ZZzzz... */ 1843 tsleep(mp, PCATCH | PZERO, "mbpp_recv", 0); 1844 1845 /* stop receiving */ 1846 if( cd ) { 1847 cd1400_write_reg(cd, CD1400_CAR, 0); 1848 1849 /* disable receiving */ 1850 cd1400_write_reg(cd, CD1400_SRER, 0); 1851 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_RCVDIS); 1852 } 1853 splx(s); 1854 1855 /* return number of chars received */ 1856 return(len - mp->mp_cnt); 1857 } 1858 1859 int 1860 mbpp_hztoms(h) 1861 int h; 1862 { 1863 int m = h; 1864 1865 if( m > 0 ) 1866 m = m * 1000 / hz; 1867 return(m); 1868 } 1869 1870 int 1871 mbpp_mstohz(m) 1872 int m; 1873 { 1874 int h = m; 1875 1876 if( h > 0 ) { 1877 h = h * hz / 1000; 1878 if( h == 0 ) 1879 h = 1000 / hz; 1880 } 1881 return(h); 1882 } 1883 1884 #endif /* NMAGMA */ 1885
Indexes created Thu Oct 02 10:09:58 GMT 2025