magma.c revision 1.36
1 /* $NetBSD: magma.c,v 1.36 2006/09/23 04:45:49 jmcneill Exp $ */ 2 /* 3 * magma.c 4 * 5 * Copyright (c) 1998 Iain Hibbert 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Iain Hibbert 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35 /* 36 * Driver for Magma SBus Serial/Parallel cards using the Cirrus Logic 37 * CD1400 & CD1190 chips 38 */ 39 40 #include <sys/cdefs.h> 41 __KERNEL_RCSID(0, "$NetBSD: magma.c,v 1.36 2006/09/23 04:45:49 jmcneill Exp $"); 42 43 #if 0 44 #define MAGMA_DEBUG 45 #endif 46 47 #include "magma.h" 48 #if NMAGMA > 0 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/proc.h> 53 #include <sys/device.h> 54 #include <sys/file.h> 55 #include <sys/ioctl.h> 56 #include <sys/malloc.h> 57 #include <sys/tty.h> 58 #include <sys/time.h> 59 #include <sys/kernel.h> 60 #include <sys/syslog.h> 61 #include <sys/conf.h> 62 #include <sys/errno.h> 63 #include <sys/kauth.h> 64 65 #include <machine/bus.h> 66 #include <machine/intr.h> 67 #include <machine/autoconf.h> 68 69 #include <dev/sbus/sbusvar.h> 70 71 #include <dev/ic/cd1400reg.h> 72 #include <dev/ic/cd1190reg.h> 73 74 #include <dev/sbus/mbppio.h> 75 #include <dev/sbus/magmareg.h> 76 77 /* supported cards 78 * 79 * The table below lists the cards that this driver is likely to 80 * be able to support. 81 * 82 * Cards with parallel ports: except for the LC2+1Sp, they all use 83 * the CD1190 chip which I know nothing about. I've tried to leave 84 * hooks for it so it shouldn't be too hard to add support later. 85 * (I think somebody is working on this separately) 86 * 87 * Thanks to Bruce at Magma for telling me the hardware offsets. 88 */ 89 static struct magma_board_info supported_cards[] = { 90 { 91 "MAGMA_Sp", "MAGMA,4_Sp", "Magma 4 Sp", 4, 0, 92 1, 0xa000, 0xc000, 0xe000, { 0x8000, 0, 0, 0 }, 93 0, { 0, 0 } 94 }, 95 { 96 "MAGMA_Sp", "MAGMA,8_Sp", "Magma 8 Sp", 8, 0, 97 2, 0xa000, 0xc000, 0xe000, { 0x4000, 0x6000, 0, 0 }, 98 0, { 0, 0 } 99 }, 100 { 101 "MAGMA_Sp", "MAGMA,_8HS_Sp", "Magma Fast 8 Sp", 8, 0, 102 2, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0, 0 }, 103 0, { 0, 0 } 104 }, 105 { 106 "MAGMA_Sp", "MAGMA,_8SP_422", "Magma 8 Sp - 422", 8, 0, 107 2, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0, 0 }, 108 0, { 0, 0 } 109 }, 110 { 111 "MAGMA_Sp", "MAGMA,12_Sp", "Magma 12 Sp", 12, 0, 112 3, 0xa000, 0xc000, 0xe000, { 0x2000, 0x4000, 0x6000, 0 }, 113 0, { 0, 0 } 114 }, 115 { 116 "MAGMA_Sp", "MAGMA,16_Sp", "Magma 16 Sp", 16, 0, 117 4, 0xd000, 0xe000, 0xf000, { 0x8000, 0x9000, 0xa000, 0xb000 }, 118 0, { 0, 0 } 119 }, 120 { 121 "MAGMA_Sp", "MAGMA,16_Sp_2", "Magma 16 Sp", 16, 0, 122 4, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0xc000, 0xe000 }, 123 0, { 0, 0 } 124 }, 125 { 126 "MAGMA_Sp", "MAGMA,16HS_Sp", "Magma Fast 16 Sp", 16, 0, 127 4, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0xc000, 0xe000 }, 128 0, { 0, 0 } 129 }, 130 { 131 "MAGMA_Sp", "MAGMA,21_Sp", "Magma LC 2+1 Sp", 2, 1, 132 1, 0xa000, 0xc000, 0xe000, { 0x8000, 0, 0, 0 }, 133 0, { 0, 0 } 134 }, 135 { 136 "MAGMA_Sp", "MAGMA,21HS_Sp", "Magma 2+1 Sp", 2, 1, 137 1, 0xa000, 0xc000, 0xe000, { 0x4000, 0, 0, 0 }, 138 1, { 0x6000, 0 } 139 }, 140 { 141 "MAGMA_Sp", "MAGMA,41_Sp", "Magma 4+1 Sp", 4, 1, 142 1, 0xa000, 0xc000, 0xe000, { 0x4000, 0, 0, 0 }, 143 1, { 0x6000, 0 } 144 }, 145 { 146 "MAGMA_Sp", "MAGMA,82_Sp", "Magma 8+2 Sp", 8, 2, 147 2, 0xd000, 0xe000, 0xf000, { 0x8000, 0x9000, 0, 0 }, 148 2, { 0xa000, 0xb000 } 149 }, 150 { 151 "MAGMA_Sp", "MAGMA,P1_Sp", "Magma P1 Sp", 0, 1, 152 0, 0, 0, 0, { 0, 0, 0, 0 }, 153 1, { 0x8000, 0 } 154 }, 155 { 156 "MAGMA_Sp", "MAGMA,P2_Sp", "Magma P2 Sp", 0, 2, 157 0, 0, 0, 0, { 0, 0, 0, 0 }, 158 2, { 0x4000, 0x8000 } 159 }, 160 { 161 "MAGMA 2+1HS Sp", "", "Magma 2+1HS Sp", 2, 0, 162 1, 0xa000, 0xc000, 0xe000, { 0x4000, 0, 0, 0 }, 163 1, { 0x8000, 0 } 164 }, 165 { 166 NULL, NULL, NULL, 0, 0, 167 0, 0, 0, 0, { 0, 0, 0, 0 }, 168 0, { 0, 0 } 169 } 170 }; 171 172 /************************************************************************ 173 * 174 * Autoconfig Stuff 175 */ 176 177 CFATTACH_DECL(magma, sizeof(struct magma_softc), 178 magma_match, magma_attach, NULL, NULL); 179 180 CFATTACH_DECL(mtty, sizeof(struct mtty_softc), 181 mtty_match, mtty_attach, NULL, NULL); 182 183 CFATTACH_DECL(mbpp, sizeof(struct mbpp_softc), 184 mbpp_match, mbpp_attach, NULL, NULL); 185 186 extern struct cfdriver mtty_cd; 187 extern struct cfdriver mbpp_cd; 188 189 dev_type_open(mttyopen); 190 dev_type_close(mttyclose); 191 dev_type_read(mttyread); 192 dev_type_write(mttywrite); 193 dev_type_ioctl(mttyioctl); 194 dev_type_stop(mttystop); 195 dev_type_tty(mttytty); 196 dev_type_poll(mttypoll); 197 198 const struct cdevsw mtty_cdevsw = { 199 mttyopen, mttyclose, mttyread, mttywrite, mttyioctl, 200 mttystop, mttytty, mttypoll, nommap, ttykqfilter, D_TTY 201 }; 202 203 dev_type_open(mbppopen); 204 dev_type_close(mbppclose); 205 dev_type_read(mbpp_rw); 206 dev_type_ioctl(mbppioctl); 207 208 const struct cdevsw mbpp_cdevsw = { 209 mbppopen, mbppclose, mbpp_rw, mbpp_rw, mbppioctl, 210 nostop, notty, nopoll, nommap, nokqfilter, 211 }; 212 213 /************************************************************************ 214 * 215 * CD1400 Routines 216 * 217 * cd1400_compute_baud calculate COR/BPR register values 218 * cd1400_write_ccr write a value to CD1400 ccr 219 * cd1400_read_reg read from a CD1400 register 220 * cd1400_write_reg write to a CD1400 register 221 * cd1400_enable_transmitter enable transmitting on CD1400 channel 222 */ 223 224 /* 225 * compute the bpr/cor pair for any baud rate 226 * returns 0 for success, 1 for failure 227 */ 228 int 229 cd1400_compute_baud(speed, clock, cor, bpr) 230 speed_t speed; 231 int clock; 232 int *cor, *bpr; 233 { 234 int c, co, br; 235 236 if( speed < 50 || speed > 150000 ) 237 return(1); 238 239 for( c = 0, co = 8 ; co <= 2048 ; co <<= 2, c++ ) { 240 br = ((clock * 1000000) + (co * speed) / 2) / (co * speed); 241 if( br < 0x100 ) { 242 *bpr = br; 243 *cor = c; 244 return(0); 245 } 246 } 247 248 return(1); 249 } 250 251 /* 252 * Write a CD1400 channel command, should have a timeout? 253 */ 254 inline void 255 cd1400_write_ccr(cd, cmd) 256 struct cd1400 *cd; 257 u_char cmd; 258 { 259 while( cd1400_read_reg(cd, CD1400_CCR) ) 260 ; 261 262 cd1400_write_reg(cd, CD1400_CCR, cmd); 263 } 264 265 /* 266 * read a value from a cd1400 register 267 */ 268 inline u_char 269 cd1400_read_reg(cd, reg) 270 struct cd1400 *cd; 271 int reg; 272 { 273 return(cd->cd_reg[reg]); 274 } 275 276 /* 277 * write a value to a cd1400 register 278 */ 279 inline void 280 cd1400_write_reg(cd, reg, value) 281 struct cd1400 *cd; 282 int reg; 283 u_char value; 284 { 285 cd->cd_reg[reg] = value; 286 } 287 288 /* 289 * enable transmit service requests for cd1400 channel 290 */ 291 void 292 cd1400_enable_transmitter(cd, channel) 293 struct cd1400 *cd; 294 int channel; 295 { 296 int s, srer; 297 298 s = spltty(); 299 cd1400_write_reg(cd, CD1400_CAR, channel); 300 srer = cd1400_read_reg(cd, CD1400_SRER); 301 SET(srer, CD1400_SRER_TXRDY); 302 cd1400_write_reg(cd, CD1400_SRER, srer); 303 splx(s); 304 } 305 306 /************************************************************************ 307 * 308 * CD1190 Routines 309 */ 310 311 /* well, there are none yet */ 312 313 /************************************************************************ 314 * 315 * Magma Routines 316 * 317 * magma_match reports if we have a magma board available 318 * magma_attach attaches magma boards to the sbus 319 * magma_hard hardware level interrupt routine 320 * magma_soft software level interrupt routine 321 */ 322 323 int 324 magma_match(parent, cf, aux) 325 struct device *parent; 326 struct cfdata *cf; 327 void *aux; 328 { 329 struct sbus_attach_args *sa = aux; 330 struct magma_board_info *card; 331 332 /* See if we support this device */ 333 for (card = supported_cards; ; card++) { 334 if (card->mb_sbusname == NULL) 335 /* End of table: no match */ 336 return (0); 337 if (strcmp(sa->sa_name, card->mb_sbusname) == 0) 338 break; 339 } 340 341 dprintf(("magma: matched `%s'\n", sa->sa_name)); 342 dprintf(("magma: magma_prom `%s'\n", 343 prom_getpropstring(sa->sa_node, "magma_prom"))); 344 dprintf(("magma: intlevels `%s'\n", 345 prom_getpropstring(sa->sa_node, "intlevels"))); 346 dprintf(("magma: chiprev `%s'\n", 347 prom_getpropstring(sa->sa_node, "chiprev"))); 348 dprintf(("magma: clock `%s'\n", 349 prom_getpropstring(sa->sa_node, "clock"))); 350 351 return (1); 352 } 353 354 void 355 magma_attach(parent, self, aux) 356 struct device *parent; 357 struct device *self; 358 void *aux; 359 { 360 struct sbus_attach_args *sa = aux; 361 struct magma_softc *sc = (struct magma_softc *)self; 362 struct magma_board_info *card; 363 bus_space_handle_t bh; 364 char *magma_prom, *clockstr; 365 int cd_clock; 366 int node, chip; 367 368 node = sa->sa_node; 369 370 /* 371 * Find the card model. 372 * Older models all have sbus node name `MAGMA_Sp' (see 373 * `supported_cards[]' above), and must be distinguished 374 * by the `magma_prom' property. 375 */ 376 magma_prom = prom_getpropstring(node, "magma_prom"); 377 378 for (card = supported_cards; card->mb_name != NULL; card++) { 379 if (strcmp(sa->sa_name, card->mb_sbusname) != 0) 380 /* Sbus node name doesn't match */ 381 continue; 382 if (strcmp(magma_prom, card->mb_name) == 0) 383 /* Model name match */ 384 break; 385 } 386 387 if( card->mb_name == NULL ) { 388 printf(": %s (unsupported)\n", magma_prom); 389 return; 390 } 391 392 dprintf((" addr %p", sc)); 393 printf(": %s\n", card->mb_realname); 394 395 sc->ms_board = card; 396 sc->ms_ncd1400 = card->mb_ncd1400; 397 sc->ms_ncd1190 = card->mb_ncd1190; 398 399 if (sbus_bus_map(sa->sa_bustag, 400 sa->sa_slot, sa->sa_offset, sa->sa_size, 401 BUS_SPACE_MAP_LINEAR, &bh) != 0) { 402 printf("%s @ sbus: cannot map registers\n", self->dv_xname); 403 return; 404 } 405 406 /* the SVCACK* lines are daisychained */ 407 sc->ms_svcackr = (caddr_t)bus_space_vaddr(sa->sa_bustag, bh) 408 + card->mb_svcackr; 409 sc->ms_svcackt = (caddr_t)bus_space_vaddr(sa->sa_bustag, bh) 410 + card->mb_svcackt; 411 sc->ms_svcackm = (caddr_t)bus_space_vaddr(sa->sa_bustag, bh) 412 + card->mb_svcackm; 413 414 /* 415 * Find the clock speed; it's the same for all CD1400 chips 416 * on the board. 417 */ 418 clockstr = prom_getpropstring(node, "clock"); 419 if (*clockstr == '\0') 420 /* Default to 25MHz */ 421 cd_clock = 25; 422 else { 423 cd_clock = 0; 424 while (*clockstr != '\0') 425 cd_clock = (cd_clock * 10) + (*clockstr++ - '0'); 426 } 427 428 /* init the cd1400 chips */ 429 for( chip = 0 ; chip < card->mb_ncd1400 ; chip++ ) { 430 struct cd1400 *cd = &sc->ms_cd1400[chip]; 431 432 cd->cd_clock = cd_clock; 433 cd->cd_reg = (caddr_t)bh + card->mb_cd1400[chip]; 434 435 /* prom_getpropstring(node, "chiprev"); */ 436 /* seemingly the Magma drivers just ignore the propstring */ 437 cd->cd_chiprev = cd1400_read_reg(cd, CD1400_GFRCR); 438 439 dprintf(("%s attach CD1400 %d addr %p rev %x clock %dMHz\n", 440 sc->ms_dev.dv_xname, chip, 441 cd->cd_reg, cd->cd_chiprev, cd->cd_clock)); 442 443 /* clear GFRCR */ 444 cd1400_write_reg(cd, CD1400_GFRCR, 0x00); 445 446 /* reset whole chip */ 447 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET | CD1400_CCR_FULLRESET); 448 449 /* wait for revision code to be restored */ 450 while( cd1400_read_reg(cd, CD1400_GFRCR) != cd->cd_chiprev ) 451 ; 452 453 /* set the Prescaler Period Register to tick at 1ms */ 454 cd1400_write_reg(cd, CD1400_PPR, 455 ((cd->cd_clock * 1000000 / CD1400_PPR_PRESCALER + 500) / 1000)); 456 457 /* The LC2+1Sp card is the only card that doesn't have 458 * a CD1190 for the parallel port, but uses channel 0 of 459 * the CD1400, so we make a note of it for later and set up 460 * the CD1400 for parallel mode operation. 461 */ 462 if( card->mb_npar && card->mb_ncd1190 == 0 ) { 463 cd1400_write_reg(cd, CD1400_GCR, CD1400_GCR_PARALLEL); 464 cd->cd_parmode = 1; 465 } 466 } 467 468 /* init the cd1190 chips */ 469 for( chip = 0 ; chip < card->mb_ncd1190 ; chip++ ) { 470 struct cd1190 *cd = &sc->ms_cd1190[chip]; 471 472 cd->cd_reg = (caddr_t)bh + card->mb_cd1190[chip]; 473 474 /* XXX don't know anything about these chips yet */ 475 printf("%s: CD1190 %d addr %p (unsupported)\n", 476 self->dv_xname, chip, cd->cd_reg); 477 } 478 479 sbus_establish(&sc->ms_sd, &sc->ms_dev); 480 481 /* configure the children */ 482 (void)config_found(self, mtty_match, NULL); 483 (void)config_found(self, mbpp_match, NULL); 484 485 /* 486 * Establish the interrupt handlers. 487 */ 488 if (sa->sa_nintr == 0) 489 return; /* No interrupts to service!? */ 490 491 (void)bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_SERIAL, 492 magma_hard, sc); 493 sc->ms_sicookie = softintr_establish(IPL_SOFTSERIAL, magma_soft, sc); 494 if (sc->ms_sicookie == NULL) { 495 printf("\n%s: cannot establish soft int handler\n", 496 sc->ms_dev.dv_xname); 497 return; 498 } 499 evcnt_attach_dynamic(&sc->ms_intrcnt, EVCNT_TYPE_INTR, NULL, 500 sc->ms_dev.dv_xname, "intr"); 501 } 502 503 /* 504 * hard interrupt routine 505 * 506 * returns 1 if it handled it, otherwise 0 507 * 508 * runs at IPL_SERIAL 509 */ 510 int 511 magma_hard(arg) 512 void *arg; 513 { 514 struct magma_softc *sc = arg; 515 struct cd1400 *cd; 516 int chip, status = 0; 517 int serviced = 0; 518 int needsoftint = 0; 519 520 /* 521 * check status of all the CD1400 chips 522 */ 523 for( chip = 0 ; chip < sc->ms_ncd1400 ; chip++ ) 524 status |= cd1400_read_reg(&sc->ms_cd1400[chip], CD1400_SVRR); 525 526 if( ISSET(status, CD1400_SVRR_RXRDY) ) { 527 u_char rivr = *sc->ms_svcackr; /* enter rx service context */ 528 int port = rivr >> 4; 529 530 if( rivr & (1<<3) ) { /* parallel port */ 531 struct mbpp_port *mbpp; 532 int n_chars; 533 534 mbpp = &sc->ms_mbpp->ms_port[port]; 535 cd = mbpp->mp_cd1400; 536 537 /* don't think we have to handle exceptions */ 538 n_chars = cd1400_read_reg(cd, CD1400_RDCR); 539 while (n_chars--) { 540 if( mbpp->mp_cnt == 0 ) { 541 SET(mbpp->mp_flags, MBPPF_WAKEUP); 542 needsoftint = 1; 543 break; 544 } 545 *mbpp->mp_ptr = cd1400_read_reg(cd,CD1400_RDSR); 546 mbpp->mp_ptr++; 547 mbpp->mp_cnt--; 548 } 549 } else { /* serial port */ 550 struct mtty_port *mtty; 551 u_char *ptr, n_chars, line_stat; 552 553 mtty = &sc->ms_mtty->ms_port[port]; 554 cd = mtty->mp_cd1400; 555 556 if( ISSET(rivr, CD1400_RIVR_EXCEPTION) ) { 557 line_stat = cd1400_read_reg(cd, CD1400_RDSR); 558 n_chars = 1; 559 } else { /* no exception, received data OK */ 560 line_stat = 0; 561 n_chars = cd1400_read_reg(cd, CD1400_RDCR); 562 } 563 564 ptr = mtty->mp_rput; 565 while( n_chars-- ) { 566 *ptr++ = line_stat; 567 *ptr++ = cd1400_read_reg(cd, CD1400_RDSR); 568 if( ptr == mtty->mp_rend ) ptr = mtty->mp_rbuf; 569 if( ptr == mtty->mp_rget ) { 570 if( ptr == mtty->mp_rbuf ) 571 ptr = mtty->mp_rend; 572 ptr -= 2; 573 SET(mtty->mp_flags, MTTYF_RING_OVERFLOW); 574 break; 575 } 576 } 577 mtty->mp_rput = ptr; 578 579 needsoftint = 1; 580 } 581 582 cd1400_write_reg(cd, CD1400_EOSRR, 0); /* end service context */ 583 serviced = 1; 584 } /* if(rx_service...) */ 585 586 if( ISSET(status, CD1400_SVRR_MDMCH) ) { 587 u_char mivr = *sc->ms_svcackm; /* enter mdm service context */ 588 int port = mivr >> 4; 589 struct mtty_port *mtty; 590 int carrier; 591 u_char msvr; 592 593 /* 594 * Handle CD (LC2+1Sp = DSR) changes. 595 */ 596 mtty = &sc->ms_mtty->ms_port[port]; 597 cd = mtty->mp_cd1400; 598 msvr = cd1400_read_reg(cd, CD1400_MSVR2); 599 carrier = ISSET(msvr, cd->cd_parmode ? CD1400_MSVR2_DSR : CD1400_MSVR2_CD); 600 601 if( mtty->mp_carrier != carrier ) { 602 SET(mtty->mp_flags, MTTYF_CARRIER_CHANGED); 603 mtty->mp_carrier = carrier; 604 needsoftint = 1; 605 } 606 607 cd1400_write_reg(cd, CD1400_EOSRR, 0); /* end service context */ 608 serviced = 1; 609 } /* if(mdm_service...) */ 610 611 if( ISSET(status, CD1400_SVRR_TXRDY) ) { 612 u_char tivr = *sc->ms_svcackt; /* enter tx service context */ 613 int port = tivr >> 4; 614 615 if( tivr & (1<<3) ) { /* parallel port */ 616 struct mbpp_port *mbpp; 617 618 mbpp = &sc->ms_mbpp->ms_port[port]; 619 cd = mbpp->mp_cd1400; 620 621 if( mbpp->mp_cnt ) { 622 int count = 0; 623 624 /* fill the fifo */ 625 while (mbpp->mp_cnt && 626 count++ < CD1400_PAR_FIFO_SIZE) { 627 cd1400_write_reg(cd, CD1400_TDR, 628 *mbpp->mp_ptr); 629 mbpp->mp_ptr++; 630 mbpp->mp_cnt--; 631 } 632 } else { 633 /* 634 * fifo is empty and we got no more data 635 * to send, so shut off interrupts and 636 * signal for a wakeup, which can't be 637 * done here in case we beat mbpp_send to 638 * the tsleep call (we are running at >spltty) 639 */ 640 cd1400_write_reg(cd, CD1400_SRER, 0); 641 SET(mbpp->mp_flags, MBPPF_WAKEUP); 642 needsoftint = 1; 643 } 644 } else { /* serial port */ 645 struct mtty_port *mtty; 646 struct tty *tp; 647 648 mtty = &sc->ms_mtty->ms_port[port]; 649 cd = mtty->mp_cd1400; 650 tp = mtty->mp_tty; 651 652 if( !ISSET(mtty->mp_flags, MTTYF_STOP) ) { 653 int count = 0; 654 655 /* check if we should start/stop a break */ 656 if( ISSET(mtty->mp_flags, MTTYF_SET_BREAK) ) { 657 cd1400_write_reg(cd, CD1400_TDR, 0); 658 cd1400_write_reg(cd, CD1400_TDR, 0x81); 659 /* should we delay too? */ 660 CLR(mtty->mp_flags, MTTYF_SET_BREAK); 661 count += 2; 662 } 663 664 if( ISSET(mtty->mp_flags, MTTYF_CLR_BREAK) ) { 665 cd1400_write_reg(cd, CD1400_TDR, 0); 666 cd1400_write_reg(cd, CD1400_TDR, 0x83); 667 CLR(mtty->mp_flags, MTTYF_CLR_BREAK); 668 count += 2; 669 } 670 671 /* I don't quite fill the fifo in case the last one is a 672 * NULL which I have to double up because its the escape 673 * code for embedded transmit characters. 674 */ 675 while( mtty->mp_txc > 0 && count < CD1400_TX_FIFO_SIZE - 1 ) { 676 u_char ch; 677 678 ch = *mtty->mp_txp; 679 680 mtty->mp_txc--; 681 mtty->mp_txp++; 682 683 if( ch == 0 ) { 684 cd1400_write_reg(cd, CD1400_TDR, ch); 685 count++; 686 } 687 688 cd1400_write_reg(cd, CD1400_TDR, ch); 689 count++; 690 } 691 } 692 693 /* if we ran out of work or are requested to STOP then 694 * shut off the txrdy interrupts and signal DONE to flush 695 * out the chars we have sent. 696 */ 697 if( mtty->mp_txc == 0 || ISSET(mtty->mp_flags, MTTYF_STOP) ) { 698 register int srer; 699 700 srer = cd1400_read_reg(cd, CD1400_SRER); 701 CLR(srer, CD1400_SRER_TXRDY); 702 cd1400_write_reg(cd, CD1400_SRER, srer); 703 CLR(mtty->mp_flags, MTTYF_STOP); 704 705 SET(mtty->mp_flags, MTTYF_DONE); 706 needsoftint = 1; 707 } 708 } 709 710 cd1400_write_reg(cd, CD1400_EOSRR, 0); /* end service context */ 711 serviced = 1; 712 } /* if(tx_service...) */ 713 714 /* XXX service CD1190 interrupts too 715 for( chip = 0 ; chip < sc->ms_ncd1190 ; chip++ ) { 716 } 717 */ 718 719 if (needsoftint) 720 /* trigger the soft interrupt */ 721 softintr_schedule(sc->ms_sicookie); 722 723 return(serviced); 724 } 725 726 /* 727 * magma soft interrupt handler 728 * 729 * runs at IPL_SOFTSERIAL 730 */ 731 void 732 magma_soft(arg) 733 void *arg; 734 { 735 struct magma_softc *sc = arg; 736 struct mtty_softc *mtty = sc->ms_mtty; 737 struct mbpp_softc *mbpp = sc->ms_mbpp; 738 int port; 739 int s, flags; 740 741 if (mtty == NULL) 742 goto chkbpp; 743 744 /* 745 * check the tty ports to see what needs doing 746 */ 747 for( port = 0 ; port < mtty->ms_nports ; port++ ) { 748 struct mtty_port *mp = &mtty->ms_port[port]; 749 struct tty *tp = mp->mp_tty; 750 751 if( !ISSET(tp->t_state, TS_ISOPEN) ) 752 continue; 753 754 /* 755 * handle any received data 756 */ 757 while( mp->mp_rget != mp->mp_rput ) { 758 u_char stat; 759 int data; 760 761 stat = mp->mp_rget[0]; 762 data = mp->mp_rget[1]; 763 mp->mp_rget = ((mp->mp_rget + 2) == mp->mp_rend) 764 ? mp->mp_rbuf : (mp->mp_rget + 2); 765 766 if( stat & (CD1400_RDSR_BREAK | CD1400_RDSR_FE) ) 767 data |= TTY_FE; 768 if( stat & CD1400_RDSR_PE ) 769 data |= TTY_PE; 770 771 if( stat & CD1400_RDSR_OE ) 772 log(LOG_WARNING, "%s%x: fifo overflow\n", 773 mtty->ms_dev.dv_xname, port); 774 775 (*tp->t_linesw->l_rint)(data, tp); 776 } 777 778 s = splserial(); /* block out hard interrupt routine */ 779 flags = mp->mp_flags; 780 CLR(mp->mp_flags, MTTYF_DONE | MTTYF_CARRIER_CHANGED | MTTYF_RING_OVERFLOW); 781 splx(s); /* ok */ 782 783 if( ISSET(flags, MTTYF_CARRIER_CHANGED) ) { 784 dprintf(("%s%x: cd %s\n", mtty->ms_dev.dv_xname, 785 port, mp->mp_carrier ? "on" : "off")); 786 (*tp->t_linesw->l_modem)(tp, mp->mp_carrier); 787 } 788 789 if( ISSET(flags, MTTYF_RING_OVERFLOW) ) { 790 log(LOG_WARNING, "%s%x: ring buffer overflow\n", 791 mtty->ms_dev.dv_xname, port); 792 } 793 794 if( ISSET(flags, MTTYF_DONE) ) { 795 ndflush(&tp->t_outq, mp->mp_txp - tp->t_outq.c_cf); 796 CLR(tp->t_state, TS_BUSY); 797 (*tp->t_linesw->l_start)(tp); /* might be some more */ 798 } 799 } /* for(each mtty...) */ 800 801 802 chkbpp: 803 /* 804 * Check the bpp ports (if any) to see what needs doing 805 */ 806 if (mbpp == NULL) 807 return; 808 809 for( port = 0 ; port < mbpp->ms_nports ; port++ ) { 810 struct mbpp_port *mp = &mbpp->ms_port[port]; 811 812 if( !ISSET(mp->mp_flags, MBPPF_OPEN) ) 813 continue; 814 815 s = splserial(); 816 flags = mp->mp_flags; 817 CLR(mp->mp_flags, MBPPF_WAKEUP); 818 splx(s); 819 820 if( ISSET(flags, MBPPF_WAKEUP) ) { 821 wakeup(mp); 822 } 823 824 } /* for(each mbpp...) */ 825 } 826 827 /************************************************************************ 828 * 829 * MTTY Routines 830 * 831 * mtty_match match one mtty device 832 * mtty_attach attach mtty devices 833 * mttyopen open mtty device 834 * mttyclose close mtty device 835 * mttyread read from mtty 836 * mttywrite write to mtty 837 * mttyioctl do ioctl on mtty 838 * mttytty return tty pointer for mtty 839 * mttystop stop mtty device 840 * mtty_start start mtty device 841 * mtty_param set mtty parameters 842 * mtty_modem_control set modem control lines 843 */ 844 845 int 846 mtty_match(parent, cf, args) 847 struct device *parent; 848 struct cfdata *cf; 849 void *args; 850 { 851 struct magma_softc *sc = (struct magma_softc *)parent; 852 853 return( args == mtty_match && sc->ms_board->mb_nser && sc->ms_mtty == NULL ); 854 } 855 856 void 857 mtty_attach(parent, dev, args) 858 struct device *parent; 859 struct device *dev; 860 void *args; 861 { 862 struct magma_softc *sc = (struct magma_softc *)parent; 863 struct mtty_softc *ms = (struct mtty_softc *)dev; 864 int port, chip, chan; 865 866 sc->ms_mtty = ms; 867 dprintf((" addr %p", ms)); 868 869 for( port = 0, chip = 0, chan = 0 ; port < sc->ms_board->mb_nser ; port++ ) { 870 struct mtty_port *mp = &ms->ms_port[port]; 871 struct tty *tp; 872 873 mp->mp_cd1400 = &sc->ms_cd1400[chip]; 874 if (mp->mp_cd1400->cd_parmode && chan == 0) 875 chan = 1; /* skip channel 0 if parmode */ 876 mp->mp_channel = chan; 877 878 tp = ttymalloc(); 879 if (tp == NULL) break; 880 tty_attach(tp); 881 tp->t_oproc = mtty_start; 882 tp->t_param = mtty_param; 883 884 mp->mp_tty = tp; 885 886 mp->mp_rbuf = malloc(MTTY_RBUF_SIZE, M_DEVBUF, M_NOWAIT); 887 if (mp->mp_rbuf == NULL) break; 888 889 mp->mp_rend = mp->mp_rbuf + MTTY_RBUF_SIZE; 890 891 chan = (chan + 1) % CD1400_NO_OF_CHANNELS; 892 if (chan == 0) 893 chip++; 894 } 895 896 ms->ms_nports = port; 897 printf(": %d tty%s\n", port, port == 1 ? "" : "s"); 898 } 899 900 /* 901 * open routine. returns zero if successful, else error code 902 */ 903 int 904 mttyopen(dev, flags, mode, l) 905 dev_t dev; 906 int flags; 907 int mode; 908 struct lwp *l; 909 { 910 int card = MAGMA_CARD(dev); 911 int port = MAGMA_PORT(dev); 912 struct mtty_softc *ms; 913 struct mtty_port *mp; 914 struct tty *tp; 915 struct cd1400 *cd; 916 int error, s; 917 918 if( card >= mtty_cd.cd_ndevs || 919 (ms = mtty_cd.cd_devs[card]) == NULL || port >= ms->ms_nports ) 920 return(ENXIO); /* device not configured */ 921 922 mp = &ms->ms_port[port]; 923 tp = mp->mp_tty; 924 tp->t_dev = dev; 925 926 if (ISSET(tp->t_state, TS_ISOPEN) && 927 ISSET(tp->t_state, TS_XCLUDE) && 928 kauth_authorize_generic(l->l_cred, KAUTH_GENERIC_ISSUSER, 929 &l->l_acflag) != 0) 930 return (EBUSY); 931 932 s = spltty(); 933 934 if( !ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 935 936 /* set defaults */ 937 ttychars(tp); 938 tp->t_iflag = TTYDEF_IFLAG; 939 tp->t_oflag = TTYDEF_OFLAG; 940 tp->t_cflag = TTYDEF_CFLAG; 941 if( ISSET(mp->mp_openflags, TIOCFLAG_CLOCAL) ) 942 SET(tp->t_cflag, CLOCAL); 943 if( ISSET(mp->mp_openflags, TIOCFLAG_CRTSCTS) ) 944 SET(tp->t_cflag, CRTSCTS); 945 if( ISSET(mp->mp_openflags, TIOCFLAG_MDMBUF) ) 946 SET(tp->t_cflag, MDMBUF); 947 tp->t_lflag = TTYDEF_LFLAG; 948 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 949 950 /* init ring buffer */ 951 mp->mp_rput = mp->mp_rget = mp->mp_rbuf; 952 953 /* reset CD1400 channel */ 954 cd = mp->mp_cd1400; 955 cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel); 956 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET); 957 958 /* encode the port number in top half of LIVR */ 959 cd1400_write_reg(cd, CD1400_LIVR, port << 4 ); 960 961 /* sets parameters and raises DTR */ 962 (void)mtty_param(tp, &tp->t_termios); 963 964 /* set tty watermarks */ 965 ttsetwater(tp); 966 967 /* enable service requests */ 968 cd1400_write_reg(cd, CD1400_SRER, 969 CD1400_SRER_RXDATA | CD1400_SRER_MDMCH); 970 971 /* tell the tty about the carrier status */ 972 if( ISSET(mp->mp_openflags, TIOCFLAG_SOFTCAR) || 973 mp->mp_carrier ) 974 SET(tp->t_state, TS_CARR_ON); 975 else 976 CLR(tp->t_state, TS_CARR_ON); 977 } 978 splx(s); 979 980 error = ttyopen(tp, MTTY_DIALOUT(dev), ISSET(flags, O_NONBLOCK)); 981 if (error != 0) 982 goto bad; 983 984 error = (*tp->t_linesw->l_open)(dev, tp); 985 if (error != 0) 986 goto bad; 987 988 bad: 989 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 990 /* 991 * We failed to open the device, and nobody else had it opened. 992 * Clean up the state as appropriate. 993 */ 994 /* XXX - do that here */ 995 } 996 997 return (error); 998 } 999 1000 /* 1001 * close routine. returns zero if successful, else error code 1002 */ 1003 int 1004 mttyclose(dev, flag, mode, l) 1005 dev_t dev; 1006 int flag; 1007 int mode; 1008 struct lwp *l; 1009 { 1010 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(dev)]; 1011 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1012 struct tty *tp = mp->mp_tty; 1013 int s; 1014 1015 (*tp->t_linesw->l_close)(tp, flag); 1016 ttyclose(tp); 1017 1018 s = spltty(); 1019 1020 /* if HUPCL is set, and the tty is no longer open 1021 * shut down the port 1022 */ 1023 if( ISSET(tp->t_cflag, HUPCL) || !ISSET(tp->t_state, TS_ISOPEN) ) { 1024 /* XXX wait until FIFO is empty before turning off the channel 1025 struct cd1400 *cd = mp->mp_cd1400; 1026 */ 1027 1028 /* drop DTR and RTS */ 1029 (void)mtty_modem_control(mp, 0, DMSET); 1030 1031 /* turn off the channel 1032 cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel); 1033 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET); 1034 */ 1035 } 1036 1037 splx(s); 1038 1039 return(0); 1040 } 1041 1042 /* 1043 * Read routine 1044 */ 1045 int 1046 mttyread(dev, uio, flags) 1047 dev_t dev; 1048 struct uio *uio; 1049 int flags; 1050 { 1051 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(dev)]; 1052 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1053 struct tty *tp = mp->mp_tty; 1054 1055 return( (*tp->t_linesw->l_read)(tp, uio, flags) ); 1056 } 1057 1058 /* 1059 * Write routine 1060 */ 1061 int 1062 mttywrite(dev, uio, flags) 1063 dev_t dev; 1064 struct uio *uio; 1065 int flags; 1066 { 1067 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(dev)]; 1068 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1069 struct tty *tp = mp->mp_tty; 1070 1071 return( (*tp->t_linesw->l_write)(tp, uio, flags) ); 1072 } 1073 1074 /* 1075 * Poll routine 1076 */ 1077 int 1078 mttypoll(dev, events, l) 1079 dev_t dev; 1080 int events; 1081 struct lwp *l; 1082 { 1083 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(dev)]; 1084 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1085 struct tty *tp = mp->mp_tty; 1086 1087 return ((*tp->t_linesw->l_poll)(tp, events, l)); 1088 } 1089 1090 /* 1091 * return tty pointer 1092 */ 1093 struct tty * 1094 mttytty(dev) 1095 dev_t dev; 1096 { 1097 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(dev)]; 1098 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1099 1100 return(mp->mp_tty); 1101 } 1102 1103 /* 1104 * ioctl routine 1105 */ 1106 int 1107 mttyioctl(dev, cmd, data, flags, l) 1108 dev_t dev; 1109 u_long cmd; 1110 caddr_t data; 1111 int flags; 1112 struct lwp *l; 1113 { 1114 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(dev)]; 1115 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1116 struct tty *tp = mp->mp_tty; 1117 int error; 1118 1119 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flags, l); 1120 if( error != EPASSTHROUGH ) return(error); 1121 1122 error = ttioctl(tp, cmd, data, flags, l); 1123 if( error != EPASSTHROUGH ) return(error); 1124 1125 error = 0; 1126 1127 switch(cmd) { 1128 case TIOCSBRK: /* set break */ 1129 SET(mp->mp_flags, MTTYF_SET_BREAK); 1130 cd1400_enable_transmitter(mp->mp_cd1400, mp->mp_channel); 1131 break; 1132 1133 case TIOCCBRK: /* clear break */ 1134 SET(mp->mp_flags, MTTYF_CLR_BREAK); 1135 cd1400_enable_transmitter(mp->mp_cd1400, mp->mp_channel); 1136 break; 1137 1138 case TIOCSDTR: /* set DTR */ 1139 mtty_modem_control(mp, TIOCM_DTR, DMBIS); 1140 break; 1141 1142 case TIOCCDTR: /* clear DTR */ 1143 mtty_modem_control(mp, TIOCM_DTR, DMBIC); 1144 break; 1145 1146 case TIOCMSET: /* set modem lines */ 1147 mtty_modem_control(mp, *((int *)data), DMSET); 1148 break; 1149 1150 case TIOCMBIS: /* bit set modem lines */ 1151 mtty_modem_control(mp, *((int *)data), DMBIS); 1152 break; 1153 1154 case TIOCMBIC: /* bit clear modem lines */ 1155 mtty_modem_control(mp, *((int *)data), DMBIC); 1156 break; 1157 1158 case TIOCMGET: /* get modem lines */ 1159 *((int *)data) = mtty_modem_control(mp, 0, DMGET); 1160 break; 1161 1162 case TIOCGFLAGS: 1163 *((int *)data) = mp->mp_openflags; 1164 break; 1165 1166 case TIOCSFLAGS: 1167 if (kauth_authorize_generic(l->l_cred, KAUTH_GENERIC_ISSUSER, 1168 &l->l_acflag) ) 1169 error = EPERM; 1170 else 1171 mp->mp_openflags = *((int *)data) & 1172 (TIOCFLAG_SOFTCAR | TIOCFLAG_CLOCAL | 1173 TIOCFLAG_CRTSCTS | TIOCFLAG_MDMBUF); 1174 break; 1175 1176 default: 1177 error = EPASSTHROUGH; 1178 } 1179 1180 return(error); 1181 } 1182 1183 /* 1184 * Stop output, e.g., for ^S or output flush. 1185 */ 1186 void 1187 mttystop(tp, flags) 1188 struct tty *tp; 1189 int flags; 1190 { 1191 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(tp->t_dev)]; 1192 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(tp->t_dev)]; 1193 int s; 1194 1195 s = spltty(); 1196 1197 if( ISSET(tp->t_state, TS_BUSY) ) { 1198 if( !ISSET(tp->t_state, TS_TTSTOP) ) 1199 SET(tp->t_state, TS_FLUSH); 1200 1201 /* 1202 * the transmit interrupt routine will disable transmit when it 1203 * notices that MTTYF_STOP has been set. 1204 */ 1205 SET(mp->mp_flags, MTTYF_STOP); 1206 } 1207 1208 splx(s); 1209 } 1210 1211 /* 1212 * Start output, after a stop. 1213 */ 1214 void 1215 mtty_start(tp) 1216 struct tty *tp; 1217 { 1218 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(tp->t_dev)]; 1219 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(tp->t_dev)]; 1220 int s; 1221 1222 s = spltty(); 1223 1224 /* we only need to do something if we are not already busy 1225 * or delaying or stopped 1226 */ 1227 if( !ISSET(tp->t_state, TS_TTSTOP | TS_TIMEOUT | TS_BUSY) ) { 1228 1229 /* if we are sleeping and output has drained below 1230 * low water mark, awaken 1231 */ 1232 if( tp->t_outq.c_cc <= tp->t_lowat ) { 1233 if( ISSET(tp->t_state, TS_ASLEEP) ) { 1234 CLR(tp->t_state, TS_ASLEEP); 1235 wakeup(&tp->t_outq); 1236 } 1237 1238 selwakeup(&tp->t_wsel); 1239 } 1240 1241 /* if something to send, start transmitting 1242 */ 1243 if( tp->t_outq.c_cc ) { 1244 mp->mp_txc = ndqb(&tp->t_outq, 0); 1245 mp->mp_txp = tp->t_outq.c_cf; 1246 SET(tp->t_state, TS_BUSY); 1247 cd1400_enable_transmitter(mp->mp_cd1400, mp->mp_channel); 1248 } 1249 } 1250 1251 splx(s); 1252 } 1253 1254 /* 1255 * set/get modem line status 1256 * 1257 * bits can be: TIOCM_DTR, TIOCM_RTS, TIOCM_CTS, TIOCM_CD, TIOCM_RI, TIOCM_DSR 1258 * 1259 * note that DTR and RTS lines are exchanged, and that DSR is 1260 * not available on the LC2+1Sp card (used as CD) 1261 * 1262 * only let them fiddle with RTS if CRTSCTS is not enabled 1263 */ 1264 int 1265 mtty_modem_control(mp, bits, howto) 1266 struct mtty_port *mp; 1267 int bits; 1268 int howto; 1269 { 1270 struct cd1400 *cd = mp->mp_cd1400; 1271 struct tty *tp = mp->mp_tty; 1272 int s, msvr; 1273 1274 s = spltty(); 1275 1276 cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel); 1277 1278 switch(howto) { 1279 case DMGET: /* get bits */ 1280 bits = 0; 1281 1282 bits |= TIOCM_LE; 1283 1284 msvr = cd1400_read_reg(cd, CD1400_MSVR1); 1285 if( msvr & CD1400_MSVR1_RTS ) bits |= TIOCM_DTR; 1286 1287 msvr = cd1400_read_reg(cd, CD1400_MSVR2); 1288 if( msvr & CD1400_MSVR2_DTR ) bits |= TIOCM_RTS; 1289 if( msvr & CD1400_MSVR2_CTS ) bits |= TIOCM_CTS; 1290 if( msvr & CD1400_MSVR2_RI ) bits |= TIOCM_RI; 1291 if( msvr & CD1400_MSVR2_DSR ) bits |= (cd->cd_parmode ? TIOCM_CD : TIOCM_DSR); 1292 if( msvr & CD1400_MSVR2_CD ) bits |= (cd->cd_parmode ? 0 : TIOCM_CD); 1293 1294 break; 1295 1296 case DMSET: /* reset bits */ 1297 if( !ISSET(tp->t_cflag, CRTSCTS) ) 1298 cd1400_write_reg(cd, CD1400_MSVR2, ((bits & TIOCM_RTS) ? CD1400_MSVR2_DTR : 0)); 1299 1300 cd1400_write_reg(cd, CD1400_MSVR1, ((bits & TIOCM_DTR) ? CD1400_MSVR1_RTS : 0)); 1301 1302 break; 1303 1304 case DMBIS: /* set bits */ 1305 if( (bits & TIOCM_RTS) && !ISSET(tp->t_cflag, CRTSCTS) ) 1306 cd1400_write_reg(cd, CD1400_MSVR2, CD1400_MSVR2_DTR); 1307 1308 if( bits & TIOCM_DTR ) 1309 cd1400_write_reg(cd, CD1400_MSVR1, CD1400_MSVR1_RTS); 1310 1311 break; 1312 1313 case DMBIC: /* clear bits */ 1314 if( (bits & TIOCM_RTS) && !ISSET(tp->t_cflag, CRTSCTS) ) 1315 cd1400_write_reg(cd, CD1400_MSVR2, 0); 1316 1317 if( bits & TIOCM_DTR ) 1318 cd1400_write_reg(cd, CD1400_MSVR1, 0); 1319 1320 break; 1321 } 1322 1323 splx(s); 1324 return(bits); 1325 } 1326 1327 /* 1328 * Set tty parameters, returns error or 0 on success 1329 */ 1330 int 1331 mtty_param(tp, t) 1332 struct tty *tp; 1333 struct termios *t; 1334 { 1335 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(tp->t_dev)]; 1336 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(tp->t_dev)]; 1337 struct cd1400 *cd = mp->mp_cd1400; 1338 int rbpr, tbpr, rcor, tcor; 1339 u_char mcor1 = 0, mcor2 = 0; 1340 int s, opt; 1341 1342 if( t->c_ospeed && cd1400_compute_baud(t->c_ospeed, cd->cd_clock, &tcor, &tbpr) ) 1343 return(EINVAL); 1344 1345 if( t->c_ispeed && cd1400_compute_baud(t->c_ispeed, cd->cd_clock, &rcor, &rbpr) ) 1346 return(EINVAL); 1347 1348 s = spltty(); 1349 1350 /* hang up the line if ospeed is zero, else raise DTR */ 1351 (void)mtty_modem_control(mp, TIOCM_DTR, (t->c_ospeed == 0 ? DMBIC : DMBIS)); 1352 1353 /* select channel, done in mtty_modem_control() */ 1354 /* cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel); */ 1355 1356 /* set transmit speed */ 1357 if( t->c_ospeed ) { 1358 cd1400_write_reg(cd, CD1400_TCOR, tcor); 1359 cd1400_write_reg(cd, CD1400_TBPR, tbpr); 1360 } 1361 1362 /* set receive speed */ 1363 if( t->c_ispeed ) { 1364 cd1400_write_reg(cd, CD1400_RCOR, rcor); 1365 cd1400_write_reg(cd, CD1400_RBPR, rbpr); 1366 } 1367 1368 /* enable transmitting and receiving on this channel */ 1369 opt = CD1400_CCR_CMDCHANCTL | CD1400_CCR_XMTEN | CD1400_CCR_RCVEN; 1370 cd1400_write_ccr(cd, opt); 1371 1372 /* set parity, data and stop bits */ 1373 opt = 0; 1374 if( ISSET(t->c_cflag, PARENB) ) 1375 opt |= (ISSET(t->c_cflag, PARODD) ? CD1400_COR1_PARODD : CD1400_COR1_PARNORMAL); 1376 1377 if( !ISSET(t->c_iflag, INPCK) ) 1378 opt |= CD1400_COR1_NOINPCK; /* no parity checking */ 1379 1380 if( ISSET(t->c_cflag, CSTOPB) ) 1381 opt |= CD1400_COR1_STOP2; 1382 1383 switch( t->c_cflag & CSIZE ) { 1384 case CS5: 1385 opt |= CD1400_COR1_CS5; 1386 break; 1387 1388 case CS6: 1389 opt |= CD1400_COR1_CS6; 1390 break; 1391 1392 case CS7: 1393 opt |= CD1400_COR1_CS7; 1394 break; 1395 1396 default: 1397 opt |= CD1400_COR1_CS8; 1398 break; 1399 } 1400 1401 cd1400_write_reg(cd, CD1400_COR1, opt); 1402 1403 /* 1404 * enable Embedded Transmit Commands (for breaks) 1405 * use the CD1400 automatic CTS flow control if CRTSCTS is set 1406 */ 1407 opt = CD1400_COR2_ETC; 1408 if( ISSET(t->c_cflag, CRTSCTS) ) opt |= CD1400_COR2_CCTS_OFLOW; 1409 cd1400_write_reg(cd, CD1400_COR2, opt); 1410 1411 cd1400_write_reg(cd, CD1400_COR3, MTTY_RX_FIFO_THRESHOLD); 1412 1413 cd1400_write_ccr(cd, CD1400_CCR_CMDCORCHG | CD1400_CCR_COR1 | CD1400_CCR_COR2 | CD1400_CCR_COR3); 1414 1415 cd1400_write_reg(cd, CD1400_COR4, CD1400_COR4_PFO_EXCEPTION); 1416 cd1400_write_reg(cd, CD1400_COR5, 0); 1417 1418 /* 1419 * if automatic RTS handshaking enabled, set DTR threshold 1420 * (RTS and DTR lines are switched, CD1400 thinks its DTR) 1421 */ 1422 if( ISSET(t->c_cflag, CRTSCTS) ) 1423 mcor1 = MTTY_RX_DTR_THRESHOLD; 1424 1425 /* set up `carrier detect' interrupts */ 1426 if( cd->cd_parmode ) { 1427 SET(mcor1, CD1400_MCOR1_DSRzd); 1428 SET(mcor2, CD1400_MCOR2_DSRod); 1429 } else { 1430 SET(mcor1, CD1400_MCOR1_CDzd); 1431 SET(mcor2, CD1400_MCOR2_CDod); 1432 } 1433 1434 cd1400_write_reg(cd, CD1400_MCOR1, mcor1); 1435 cd1400_write_reg(cd, CD1400_MCOR2, mcor2); 1436 1437 /* receive timeout 2ms */ 1438 cd1400_write_reg(cd, CD1400_RTPR, 2); 1439 1440 splx(s); 1441 return(0); 1442 } 1443 1444 /************************************************************************ 1445 * 1446 * MBPP Routines 1447 * 1448 * mbpp_match match one mbpp device 1449 * mbpp_attach attach mbpp devices 1450 * mbppopen open mbpp device 1451 * mbppclose close mbpp device 1452 * mbppioctl do ioctl on mbpp 1453 * mbpp_rw general rw routine 1454 * mbpp_timeout rw timeout 1455 * mbpp_start rw start after delay 1456 * mbpp_send send data 1457 * mbpp_recv recv data 1458 */ 1459 1460 int 1461 mbpp_match(parent, cf, args) 1462 struct device *parent; 1463 struct cfdata *cf; 1464 void *args; 1465 { 1466 struct magma_softc *sc = (struct magma_softc *)parent; 1467 1468 return( args == mbpp_match && sc->ms_board->mb_npar && sc->ms_mbpp == NULL ); 1469 } 1470 1471 void 1472 mbpp_attach(parent, dev, args) 1473 struct device *parent; 1474 struct device *dev; 1475 void *args; 1476 { 1477 struct magma_softc *sc = (struct magma_softc *)parent; 1478 struct mbpp_softc *ms = (struct mbpp_softc *)dev; 1479 struct mbpp_port *mp; 1480 int port; 1481 1482 sc->ms_mbpp = ms; 1483 dprintf((" addr %p", ms)); 1484 1485 for( port = 0 ; port < sc->ms_board->mb_npar ; port++ ) { 1486 mp = &ms->ms_port[port]; 1487 1488 callout_init(&mp->mp_timeout_ch); 1489 callout_init(&mp->mp_start_ch); 1490 1491 if( sc->ms_ncd1190 ) 1492 mp->mp_cd1190 = &sc->ms_cd1190[port]; 1493 else 1494 mp->mp_cd1400 = &sc->ms_cd1400[0]; 1495 } 1496 1497 ms->ms_nports = port; 1498 printf(": %d port%s\n", port, port == 1 ? "" : "s"); 1499 } 1500 1501 /* 1502 * open routine. returns zero if successful, else error code 1503 */ 1504 int 1505 mbppopen(dev, flags, mode, l) 1506 dev_t dev; 1507 int flags; 1508 int mode; 1509 struct lwp *l; 1510 { 1511 int card = MAGMA_CARD(dev); 1512 int port = MAGMA_PORT(dev); 1513 struct mbpp_softc *ms; 1514 struct mbpp_port *mp; 1515 int s; 1516 1517 if( card >= mbpp_cd.cd_ndevs || 1518 (ms = mbpp_cd.cd_devs[card]) == NULL || port >= ms->ms_nports ) 1519 return(ENXIO); 1520 1521 mp = &ms->ms_port[port]; 1522 1523 s = spltty(); 1524 if( ISSET(mp->mp_flags, MBPPF_OPEN) ) { 1525 splx(s); 1526 return(EBUSY); 1527 } 1528 SET(mp->mp_flags, MBPPF_OPEN); 1529 splx(s); 1530 1531 /* set defaults */ 1532 mp->mp_burst = MBPP_BURST; 1533 mp->mp_timeout = mbpp_mstohz(MBPP_TIMEOUT); 1534 mp->mp_delay = mbpp_mstohz(MBPP_DELAY); 1535 1536 /* init chips */ 1537 if( mp->mp_cd1400 ) { /* CD1400 */ 1538 struct cd1400 *cd = mp->mp_cd1400; 1539 1540 /* set up CD1400 channel */ 1541 s = spltty(); 1542 cd1400_write_reg(cd, CD1400_CAR, 0); 1543 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET); 1544 cd1400_write_reg(cd, CD1400_LIVR, (1<<3)); 1545 splx(s); 1546 } else { /* CD1190 */ 1547 mp->mp_flags = 0; 1548 return (ENXIO); 1549 } 1550 1551 return (0); 1552 } 1553 1554 /* 1555 * close routine. returns zero if successful, else error code 1556 */ 1557 int 1558 mbppclose(dev, flag, mode, l) 1559 dev_t dev; 1560 int flag; 1561 int mode; 1562 struct lwp *l; 1563 { 1564 struct mbpp_softc *ms = mbpp_cd.cd_devs[MAGMA_CARD(dev)]; 1565 struct mbpp_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1566 1567 mp->mp_flags = 0; 1568 return(0); 1569 } 1570 1571 /* 1572 * ioctl routine 1573 */ 1574 int 1575 mbppioctl(dev, cmd, data, flags, l) 1576 dev_t dev; 1577 u_long cmd; 1578 caddr_t data; 1579 int flags; 1580 struct lwp *l; 1581 { 1582 struct mbpp_softc *ms = mbpp_cd.cd_devs[MAGMA_CARD(dev)]; 1583 struct mbpp_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1584 struct mbpp_param *bp; 1585 int error = 0; 1586 int s; 1587 1588 switch(cmd) { 1589 case MBPPIOCSPARAM: 1590 bp = (struct mbpp_param *)data; 1591 if( bp->bp_burst < MBPP_BURST_MIN || bp->bp_burst > MBPP_BURST_MAX || 1592 bp->bp_delay < MBPP_DELAY_MIN || bp->bp_delay > MBPP_DELAY_MIN ) { 1593 error = EINVAL; 1594 } else { 1595 mp->mp_burst = bp->bp_burst; 1596 mp->mp_timeout = mbpp_mstohz(bp->bp_timeout); 1597 mp->mp_delay = mbpp_mstohz(bp->bp_delay); 1598 } 1599 break; 1600 case MBPPIOCGPARAM: 1601 bp = (struct mbpp_param *)data; 1602 bp->bp_burst = mp->mp_burst; 1603 bp->bp_timeout = mbpp_hztoms(mp->mp_timeout); 1604 bp->bp_delay = mbpp_hztoms(mp->mp_delay); 1605 break; 1606 case MBPPIOCGSTAT: 1607 /* XXX make this more generic */ 1608 s = spltty(); 1609 cd1400_write_reg(mp->mp_cd1400, CD1400_CAR, 0); 1610 *(int *)data = cd1400_read_reg(mp->mp_cd1400, CD1400_PSVR); 1611 splx(s); 1612 break; 1613 default: 1614 error = ENOTTY; 1615 } 1616 1617 return(error); 1618 } 1619 1620 int 1621 mbpp_rw(dev, uio, flag) 1622 dev_t dev; 1623 struct uio *uio; 1624 int flag; 1625 { 1626 int card = MAGMA_CARD(dev); 1627 int port = MAGMA_PORT(dev); 1628 struct mbpp_softc *ms = mbpp_cd.cd_devs[card]; 1629 struct mbpp_port *mp = &ms->ms_port[port]; 1630 caddr_t buffer, ptr; 1631 int buflen, cnt, len; 1632 int s, error = 0; 1633 int gotdata = 0; 1634 1635 if( uio->uio_resid == 0 ) 1636 return(0); 1637 1638 buflen = min(uio->uio_resid, mp->mp_burst); 1639 buffer = malloc(buflen, M_DEVBUF, M_WAITOK); 1640 if( buffer == NULL ) 1641 return(ENOMEM); 1642 1643 SET(mp->mp_flags, MBPPF_UIO); 1644 1645 /* 1646 * start timeout, if needed 1647 */ 1648 if( mp->mp_timeout > 0 ) { 1649 SET(mp->mp_flags, MBPPF_TIMEOUT); 1650 callout_reset(&mp->mp_timeout_ch, mp->mp_timeout, 1651 mbpp_timeout, mp); 1652 } 1653 1654 len = cnt = 0; 1655 while( uio->uio_resid > 0 ) { 1656 len = min(buflen, uio->uio_resid); 1657 ptr = buffer; 1658 1659 if( uio->uio_rw == UIO_WRITE ) { 1660 error = uiomove(ptr, len, uio); 1661 if( error ) break; 1662 } 1663 again: /* goto bad */ 1664 /* timed out? */ 1665 if( !ISSET(mp->mp_flags, MBPPF_UIO) ) 1666 break; 1667 1668 /* 1669 * perform the operation 1670 */ 1671 if( uio->uio_rw == UIO_WRITE ) { 1672 cnt = mbpp_send(mp, ptr, len); 1673 } else { 1674 cnt = mbpp_recv(mp, ptr, len); 1675 } 1676 1677 if( uio->uio_rw == UIO_READ ) { 1678 if( cnt ) { 1679 error = uiomove(ptr, cnt, uio); 1680 if( error ) break; 1681 gotdata++; 1682 } 1683 else if( gotdata ) /* consider us done */ 1684 break; 1685 } 1686 1687 /* timed out? */ 1688 if( !ISSET(mp->mp_flags, MBPPF_UIO) ) 1689 break; 1690 1691 /* 1692 * poll delay? 1693 */ 1694 if( mp->mp_delay > 0 ) { 1695 s = splsoftclock(); 1696 SET(mp->mp_flags, MBPPF_DELAY); 1697 callout_reset(&mp->mp_start_ch, mp->mp_delay, 1698 mbpp_start, mp); 1699 error = tsleep(mp, PCATCH | PZERO, "mbppdelay", 0); 1700 splx(s); 1701 if( error ) break; 1702 } 1703 1704 /* 1705 * don't call uiomove again until we used all the data we grabbed 1706 */ 1707 if( uio->uio_rw == UIO_WRITE && cnt != len ) { 1708 ptr += cnt; 1709 len -= cnt; 1710 cnt = 0; 1711 goto again; 1712 } 1713 } 1714 1715 /* 1716 * clear timeouts 1717 */ 1718 s = splsoftclock(); 1719 if( ISSET(mp->mp_flags, MBPPF_TIMEOUT) ) { 1720 callout_stop(&mp->mp_timeout_ch); 1721 CLR(mp->mp_flags, MBPPF_TIMEOUT); 1722 } 1723 if( ISSET(mp->mp_flags, MBPPF_DELAY) ) { 1724 callout_stop(&mp->mp_start_ch); 1725 CLR(mp->mp_flags, MBPPF_DELAY); 1726 } 1727 splx(s); 1728 1729 /* 1730 * adjust for those chars that we uiomoved but never actually wrote 1731 */ 1732 if( uio->uio_rw == UIO_WRITE && cnt != len ) { 1733 uio->uio_resid += (len - cnt); 1734 } 1735 1736 free(buffer, M_DEVBUF); 1737 return(error); 1738 } 1739 1740 void 1741 mbpp_timeout(arg) 1742 void *arg; 1743 { 1744 struct mbpp_port *mp = arg; 1745 1746 CLR(mp->mp_flags, MBPPF_UIO | MBPPF_TIMEOUT); 1747 wakeup(mp); 1748 } 1749 1750 void 1751 mbpp_start(arg) 1752 void *arg; 1753 { 1754 struct mbpp_port *mp = arg; 1755 1756 CLR(mp->mp_flags, MBPPF_DELAY); 1757 wakeup(mp); 1758 } 1759 1760 int 1761 mbpp_send(mp, ptr, len) 1762 struct mbpp_port *mp; 1763 caddr_t ptr; 1764 int len; 1765 { 1766 int s; 1767 struct cd1400 *cd = mp->mp_cd1400; 1768 1769 /* set up io information */ 1770 mp->mp_ptr = ptr; 1771 mp->mp_cnt = len; 1772 1773 /* start transmitting */ 1774 s = spltty(); 1775 if( cd ) { 1776 cd1400_write_reg(cd, CD1400_CAR, 0); 1777 1778 /* output strobe width ~1microsecond */ 1779 cd1400_write_reg(cd, CD1400_TBPR, 10); 1780 1781 /* enable channel */ 1782 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_XMTEN); 1783 cd1400_write_reg(cd, CD1400_SRER, CD1400_SRER_TXRDY); 1784 } 1785 1786 /* ZZzzz... */ 1787 tsleep(mp, PCATCH | PZERO, "mbpp_send", 0); 1788 1789 /* stop transmitting */ 1790 if( cd ) { 1791 cd1400_write_reg(cd, CD1400_CAR, 0); 1792 1793 /* disable transmitter */ 1794 cd1400_write_reg(cd, CD1400_SRER, 0); 1795 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_XMTDIS); 1796 1797 /* flush fifo */ 1798 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET | CD1400_CCR_FTF); 1799 } 1800 splx(s); 1801 1802 /* return number of chars sent */ 1803 return(len - mp->mp_cnt); 1804 } 1805 1806 int 1807 mbpp_recv(mp, ptr, len) 1808 struct mbpp_port *mp; 1809 caddr_t ptr; 1810 int len; 1811 { 1812 int s; 1813 struct cd1400 *cd = mp->mp_cd1400; 1814 1815 /* set up io information */ 1816 mp->mp_ptr = ptr; 1817 mp->mp_cnt = len; 1818 1819 /* start receiving */ 1820 s = spltty(); 1821 if( cd ) { 1822 int rcor, rbpr; 1823 1824 cd1400_write_reg(cd, CD1400_CAR, 0); 1825 1826 /* input strobe at 100kbaud (10microseconds) */ 1827 cd1400_compute_baud(100000, cd->cd_clock, &rcor, &rbpr); 1828 cd1400_write_reg(cd, CD1400_RCOR, rcor); 1829 cd1400_write_reg(cd, CD1400_RBPR, rbpr); 1830 1831 /* rx threshold */ 1832 cd1400_write_reg(cd, CD1400_COR3, MBPP_RX_FIFO_THRESHOLD); 1833 cd1400_write_ccr(cd, CD1400_CCR_CMDCORCHG | CD1400_CCR_COR3); 1834 1835 /* enable channel */ 1836 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_RCVEN); 1837 cd1400_write_reg(cd, CD1400_SRER, CD1400_SRER_RXDATA); 1838 } 1839 1840 /* ZZzzz... */ 1841 tsleep(mp, PCATCH | PZERO, "mbpp_recv", 0); 1842 1843 /* stop receiving */ 1844 if( cd ) { 1845 cd1400_write_reg(cd, CD1400_CAR, 0); 1846 1847 /* disable receiving */ 1848 cd1400_write_reg(cd, CD1400_SRER, 0); 1849 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_RCVDIS); 1850 } 1851 splx(s); 1852 1853 /* return number of chars received */ 1854 return(len - mp->mp_cnt); 1855 } 1856 1857 int 1858 mbpp_hztoms(h) 1859 int h; 1860 { 1861 int m = h; 1862 1863 if( m > 0 ) 1864 m = m * 1000 / hz; 1865 return(m); 1866 } 1867 1868 int 1869 mbpp_mstohz(m) 1870 int m; 1871 { 1872 int h = m; 1873 1874 if( h > 0 ) { 1875 h = h * hz / 1000; 1876 if( h == 0 ) 1877 h = 1000 / hz; 1878 } 1879 return(h); 1880 } 1881 1882 #endif /* NMAGMA */ 1883
Indexes created Mon Sep 22 13:09:51 GMT 2025