magma.c revision 1.4
1 /* $NetBSD: magma.c,v 1.4 1998/07/28 00:31:42 pk Exp $ */ 2 /* 3 * magma.c 4 * 5 * Copyright (c) 1998 Iain Hibbert 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Iain Hibbert 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 #if 0 35 #define MAGMA_DEBUG 36 #endif 37 38 /* 39 * Driver for Magma SBus Serial/Parallel cards using the Cirrus Logic 40 * CD1400 & CD1190 chips 41 */ 42 43 #include "magma.h" 44 #if NMAGMA > 0 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/proc.h> 49 #include <sys/device.h> 50 #include <sys/file.h> 51 #include <sys/ioctl.h> 52 #include <sys/malloc.h> 53 #include <sys/tty.h> 54 #include <sys/time.h> 55 #include <sys/kernel.h> 56 #include <sys/syslog.h> 57 #include <sys/conf.h> 58 #include <sys/errno.h> 59 60 #include <machine/conf.h> 61 #include <machine/bus.h> 62 #include <machine/autoconf.h> 63 #include <dev/sbus/sbusvar.h> 64 65 #include <dev/ic/cd1400reg.h> 66 #include <dev/ic/cd1190reg.h> 67 68 #include <dev/sbus/mbppio.h> 69 #include <dev/sbus/magmareg.h> 70 71 /* 72 * Select tty soft interrupt bit based on TTY ipl. (stole from zs.c) 73 */ 74 #if PIL_TTY == 1 75 # define IE_MSOFT IE_L1 76 #elif PIL_TTY == 4 77 # define IE_MSOFT IE_L4 78 #elif PIL_TTY == 6 79 # define IE_MSOFT IE_L6 80 #else 81 # error "no suitable software interrupt bit" 82 #endif 83 84 /* supported cards 85 * 86 * The table below lists the cards that this driver is likely to 87 * be able to support. 88 * 89 * Cards with parallel ports: except for the LC2+1Sp, they all use 90 * the CD1190 chip which I know nothing about. I've tried to leave 91 * hooks for it so it shouldn't be too hard to add support later. 92 * (I think somebody is working on this separately) 93 * 94 * Thanks to Bruce at Magma for telling me the hardware offsets. 95 */ 96 static struct magma_board_info supported_cards[] = { 97 { 98 "MAGMA,4_Sp", "Magma 4 Sp", 4, 0, 99 1, 0xa000, 0xc000, 0xe000, { 0x8000, 0, 0, 0 }, 100 0, { 0, 0 } 101 }, 102 { 103 "MAGMA,8_Sp", "Magma 8 Sp", 8, 0, 104 2, 0xa000, 0xc000, 0xe000, { 0x4000, 0x6000, 0, 0 }, 105 0, { 0, 0 } 106 }, 107 { 108 "MAGMA,_8HS_Sp", "Magma Fast 8 Sp", 8, 0, 109 2, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0, 0 }, 110 0, { 0, 0 } 111 }, 112 { 113 "MAGMA,_8SP_422", "Magma 8 Sp - 422", 8, 0, 114 2, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0, 0 }, 115 0, { 0, 0 } 116 }, 117 { 118 "MAGMA,12_Sp", "Magma 12 Sp", 12, 0, 119 3, 0xa000, 0xc000, 0xe000, { 0x2000, 0x4000, 0x6000, 0 }, 120 0, { 0, 0 } 121 }, 122 { 123 "MAGMA,16_Sp", "Magma 16 Sp", 16, 0, 124 4, 0xd000, 0xe000, 0xf000, { 0x8000, 0x9000, 0xa000, 0xb000 }, 125 0, { 0, 0 } 126 }, 127 { 128 "MAGMA,16_Sp_2", "Magma 16 Sp", 16, 0, 129 4, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0xc000, 0xe000 }, 130 0, { 0, 0 } 131 }, 132 { 133 "MAGMA,16HS_Sp", "Magma Fast 16 Sp", 16, 0, 134 4, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0xc000, 0xe000 }, 135 0, { 0, 0 } 136 }, 137 { 138 "MAGMA,21_Sp", "Magma LC 2+1 Sp", 2, 1, 139 1, 0xa000, 0xc000, 0xe000, { 0x8000, 0, 0, 0 }, 140 0, { 0, 0 } 141 }, 142 { 143 "MAGMA,21HS_Sp", "Magma 2+1 Sp", 2, 1, 144 1, 0xa000, 0xc000, 0xe000, { 0x4000, 0, 0, 0 }, 145 1, { 0x6000, 0 } 146 }, 147 { 148 "MAGMA,41_Sp", "Magma 4+1 Sp", 4, 1, 149 1, 0xa000, 0xc000, 0xe000, { 0x4000, 0, 0, 0 }, 150 1, { 0x6000, 0 } 151 }, 152 { 153 "MAGMA,82_Sp", "Magma 8+2 Sp", 8, 2, 154 2, 0xd000, 0xe000, 0xf000, { 0x8000, 0x9000, 0, 0 }, 155 2, { 0xa000, 0xb000 } 156 }, 157 { 158 "MAGMA,P1_Sp", "Magma P1 Sp", 0, 1, 159 0, 0, 0, 0, { 0, 0, 0, 0 }, 160 1, { 0x8000, 0 } 161 }, 162 { 163 "MAGMA,P2_Sp", "Magma P2 Sp", 0, 2, 164 0, 0, 0, 0, { 0, 0, 0, 0 }, 165 2, { 0x4000, 0x8000 } 166 }, 167 { 168 NULL, NULL, 0, 0, 169 0, 0, 0, 0, { 0, 0, 0, 0 }, 170 0, { 0, 0 } 171 } 172 }; 173 174 /************************************************************************ 175 * 176 * Autoconfig Stuff 177 */ 178 179 struct cfattach magma_ca = { 180 sizeof(struct magma_softc), magma_match, magma_attach 181 }; 182 183 struct cfattach mtty_ca = { 184 sizeof(struct mtty_softc), mtty_match, mtty_attach 185 }; 186 187 struct cfattach mbpp_ca = { 188 sizeof(struct mbpp_softc), mbpp_match, mbpp_attach 189 }; 190 191 extern struct cfdriver mtty_cd; 192 extern struct cfdriver mbpp_cd; 193 194 /************************************************************************ 195 * 196 * CD1400 Routines 197 * 198 * cd1400_compute_baud calculate COR/BPR register values 199 * cd1400_write_ccr write a value to CD1400 ccr 200 * cd1400_read_reg read from a CD1400 register 201 * cd1400_write_reg write to a CD1400 register 202 * cd1400_enable_transmitter enable transmitting on CD1400 channel 203 */ 204 205 /* 206 * compute the bpr/cor pair for any baud rate 207 * returns 0 for success, 1 for failure 208 */ 209 int 210 cd1400_compute_baud(speed, clock, cor, bpr) 211 speed_t speed; 212 int clock; 213 int *cor, *bpr; 214 { 215 int c, co, br; 216 217 if( speed < 50 || speed > 150000 ) 218 return(1); 219 220 for( c = 0, co = 8 ; co <= 2048 ; co <<= 2, c++ ) { 221 br = ((clock * 1000000) + (co * speed) / 2) / (co * speed); 222 if( br < 0x100 ) { 223 *bpr = br; 224 *cor = c; 225 return(0); 226 } 227 } 228 229 return(1); 230 } 231 232 /* 233 * Write a CD1400 channel command, should have a timeout? 234 */ 235 __inline void 236 cd1400_write_ccr(cd, cmd) 237 struct cd1400 *cd; 238 u_char cmd; 239 { 240 while( cd1400_read_reg(cd, CD1400_CCR) ) 241 ; 242 243 cd1400_write_reg(cd, CD1400_CCR, cmd); 244 } 245 246 /* 247 * read a value from a cd1400 register 248 */ 249 __inline u_char 250 cd1400_read_reg(cd, reg) 251 struct cd1400 *cd; 252 int reg; 253 { 254 return(cd->cd_reg[reg]); 255 } 256 257 /* 258 * write a value to a cd1400 register 259 */ 260 __inline void 261 cd1400_write_reg(cd, reg, value) 262 struct cd1400 *cd; 263 int reg; 264 u_char value; 265 { 266 cd->cd_reg[reg] = value; 267 } 268 269 /* 270 * enable transmit service requests for cd1400 channel 271 */ 272 void 273 cd1400_enable_transmitter(cd, channel) 274 struct cd1400 *cd; 275 int channel; 276 { 277 int s, srer; 278 279 s = spltty(); 280 cd1400_write_reg(cd, CD1400_CAR, channel); 281 srer = cd1400_read_reg(cd, CD1400_SRER); 282 SET(srer, CD1400_SRER_TXRDY); 283 cd1400_write_reg(cd, CD1400_SRER, srer); 284 splx(s); 285 } 286 287 /************************************************************************ 288 * 289 * CD1190 Routines 290 */ 291 292 /* well, there are none yet */ 293 294 /************************************************************************ 295 * 296 * Magma Routines 297 * 298 * magma_match reports if we have a magma board available 299 * magma_attach attaches magma boards to the sbus 300 * magma_hard hardware level interrupt routine 301 * magma_soft software level interrupt routine 302 */ 303 304 int 305 magma_match(parent, cf, aux) 306 struct device *parent; 307 struct cfdata *cf; 308 void *aux; 309 { 310 struct sbus_attach_args *sa = aux; 311 312 /* is it a magma Sp card? */ 313 if( strcmp(sa->sa_name, "MAGMA_Sp") != 0 ) 314 return(0); 315 316 dprintf(("magma: matched `%s'\n", sa->sa_name)); 317 dprintf(("magma: magma_prom `%s'\n", 318 getpropstring(sa->sa_node, "magma_prom"))); 319 dprintf(("magma: intlevels `%s'\n", 320 getpropstring(sa->sa_node, "intlevels"))); 321 dprintf(("magma: chiprev `%s'\n", 322 getpropstring(sa->sa_node, "chiprev"))); 323 dprintf(("magma: clock `%s'\n", 324 getpropstring(sa->sa_node, "clock"))); 325 326 return (1); 327 } 328 329 void 330 magma_attach(parent, self, aux) 331 struct device *parent; 332 struct device *self; 333 void *aux; 334 { 335 struct sbus_attach_args *sa = aux; 336 struct magma_softc *sc = (struct magma_softc *)self; 337 struct magma_board_info *card = supported_cards; 338 bus_space_handle_t bh; 339 char *magma_prom; 340 int node, chip; 341 342 node = sa->sa_node; 343 magma_prom = getpropstring(node, "magma_prom"); 344 345 /* find the card type */ 346 while (card->mb_name && strcmp(magma_prom, card->mb_name) != 0) 347 card++; 348 349 dprintf((" addr %p", sc)); 350 printf(" softpri %d:", PIL_TTY); 351 352 if( card->mb_name == NULL ) { 353 printf(" %s (unsupported)\n", magma_prom); 354 return; 355 } 356 357 printf(" %s\n", card->mb_realname); 358 359 sc->ms_board = card; 360 sc->ms_ncd1400 = card->mb_ncd1400; 361 sc->ms_ncd1190 = card->mb_ncd1190; 362 363 if (sbus_bus_map(sa->sa_bustag, 364 sa->sa_slot, 365 sa->sa_offset, 366 sa->sa_size, 367 BUS_SPACE_MAP_LINEAR, 368 0, &bh) != 0) { 369 printf("%s @ sbus: cannot map registers\n", self->dv_xname); 370 return; 371 } 372 373 /* the SVCACK* lines are daisychained */ 374 sc->ms_svcackr = (caddr_t)bh + card->mb_svcackr; 375 sc->ms_svcackt = (caddr_t)bh + card->mb_svcackt; 376 sc->ms_svcackm = (caddr_t)bh + card->mb_svcackm; 377 378 /* init the cd1400 chips */ 379 for( chip = 0 ; chip < card->mb_ncd1400 ; chip++ ) { 380 struct cd1400 *cd = &sc->ms_cd1400[chip]; 381 382 cd->cd_reg = (caddr_t)bh + card->mb_cd1400[chip]; 383 384 /* XXX getpropstring(node, "clock") */ 385 cd->cd_clock = 25; 386 387 /* getpropstring(node, "chiprev"); */ 388 /* seemingly the Magma drivers just ignore the propstring */ 389 cd->cd_chiprev = cd1400_read_reg(cd, CD1400_GFRCR); 390 391 dprintf(("%s attach CD1400 %d addr %p rev %x clock %dMhz\n", 392 sc->ms_dev.dv_xname, chip, 393 cd->cd_reg, cd->cd_chiprev, cd->cd_clock)); 394 395 /* clear GFRCR */ 396 cd1400_write_reg(cd, CD1400_GFRCR, 0x00); 397 398 /* reset whole chip */ 399 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET | CD1400_CCR_FULLRESET); 400 401 /* wait for revision code to be restored */ 402 while( cd1400_read_reg(cd, CD1400_GFRCR) != cd->cd_chiprev ) 403 ; 404 405 /* set the Prescaler Period Register to tick at 1ms */ 406 cd1400_write_reg(cd, CD1400_PPR, 407 ((cd->cd_clock * 1000000 / CD1400_PPR_PRESCALER + 500) / 1000)); 408 409 /* The LC2+1Sp card is the only card that doesn't have 410 * a CD1190 for the parallel port, but uses channel 0 of 411 * the CD1400, so we make a note of it for later and set up 412 * the CD1400 for parallel mode operation. 413 */ 414 if( card->mb_npar && card->mb_ncd1190 == 0 ) { 415 cd1400_write_reg(cd, CD1400_GCR, CD1400_GCR_PARALLEL); 416 cd->cd_parmode = 1; 417 } 418 } 419 420 /* init the cd1190 chips */ 421 for( chip = 0 ; chip < card->mb_ncd1190 ; chip++ ) { 422 struct cd1190 *cd = &sc->ms_cd1190[chip]; 423 424 cd->cd_reg = (caddr_t)bh + card->mb_cd1190[chip]; 425 dprintf(("%s attach CD1190 %d addr %p (failed)\n", 426 self->dv_xname, chip, cd->cd_reg)); 427 /* XXX don't know anything about these chips yet */ 428 } 429 430 sbus_establish(&sc->ms_sd, &sc->ms_dev); 431 432 /* configure the children */ 433 (void)config_found(self, mtty_match, NULL); 434 (void)config_found(self, mbpp_match, NULL); 435 436 /* 437 * Establish the interrupt handlers. 438 */ 439 (void)bus_intr_establish(sa->sa_bustag, sa->sa_pri, 0, magma_hard, sc); 440 (void)bus_intr_establish(sa->sa_bustag, PIL_TTY, 441 BUS_INTR_ESTABLISH_SOFTINTR, 442 magma_soft, sc); 443 evcnt_attach(&sc->ms_dev, "intr", &sc->ms_intrcnt); 444 } 445 446 /* 447 * hard interrupt routine 448 * 449 * returns 1 if it handled it, otherwise 0 450 * 451 * runs at interrupt priority 452 */ 453 int 454 magma_hard(arg) 455 void *arg; 456 { 457 struct magma_softc *sc = arg; 458 struct cd1400 *cd; 459 int chip, status = 0; 460 int serviced = 0; 461 int needsoftint = 0; 462 463 /* 464 * check status of all the CD1400 chips 465 */ 466 for( chip = 0 ; chip < sc->ms_ncd1400 ; chip++ ) 467 status |= cd1400_read_reg(&sc->ms_cd1400[chip], CD1400_SVRR); 468 469 if( ISSET(status, CD1400_SVRR_RXRDY) ) { 470 u_char rivr = *sc->ms_svcackr; /* enter rx service context */ 471 int port = rivr >> 4; 472 473 if( rivr & (1<<3) ) { /* parallel port */ 474 struct mbpp_port *mbpp; 475 int n_chars; 476 477 mbpp = &sc->ms_mbpp->ms_port[port]; 478 cd = mbpp->mp_cd1400; 479 480 /* don't think we have to handle exceptions */ 481 n_chars = cd1400_read_reg(cd, CD1400_RDCR); 482 while (n_chars--) { 483 if( mbpp->mp_cnt == 0 ) { 484 SET(mbpp->mp_flags, MBPPF_WAKEUP); 485 needsoftint = 1; 486 break; 487 } 488 *mbpp->mp_ptr = cd1400_read_reg(cd,CD1400_RDSR); 489 mbpp->mp_ptr++; 490 mbpp->mp_cnt--; 491 } 492 } else { /* serial port */ 493 struct mtty_port *mtty; 494 u_char *ptr, n_chars, line_stat; 495 496 mtty = &sc->ms_mtty->ms_port[port]; 497 cd = mtty->mp_cd1400; 498 499 if( ISSET(rivr, CD1400_RIVR_EXCEPTION) ) { 500 line_stat = cd1400_read_reg(cd, CD1400_RDSR); 501 n_chars = 1; 502 } else { /* no exception, received data OK */ 503 line_stat = 0; 504 n_chars = cd1400_read_reg(cd, CD1400_RDCR); 505 } 506 507 ptr = mtty->mp_rput; 508 while( n_chars-- ) { 509 *ptr++ = line_stat; 510 *ptr++ = cd1400_read_reg(cd, CD1400_RDSR); 511 if( ptr == mtty->mp_rend ) ptr = mtty->mp_rbuf; 512 if( ptr == mtty->mp_rget ) { 513 if( ptr == mtty->mp_rbuf ) 514 ptr = mtty->mp_rend; 515 ptr -= 2; 516 SET(mtty->mp_flags, MTTYF_RING_OVERFLOW); 517 break; 518 } 519 } 520 mtty->mp_rput = ptr; 521 522 needsoftint = 1; 523 } 524 525 cd1400_write_reg(cd, CD1400_EOSRR, 0); /* end service context */ 526 serviced = 1; 527 } /* if(rx_service...) */ 528 529 if( ISSET(status, CD1400_SVRR_MDMCH) ) { 530 u_char mivr = *sc->ms_svcackm; /* enter mdm service context */ 531 int port = mivr >> 4; 532 struct mtty_port *mtty; 533 int carrier; 534 u_char msvr; 535 536 /* 537 * Handle CD (LC2+1Sp = DSR) changes. 538 */ 539 mtty = &sc->ms_mtty->ms_port[port]; 540 cd = mtty->mp_cd1400; 541 msvr = cd1400_read_reg(cd, CD1400_MSVR2); 542 carrier = ISSET(msvr, cd->cd_parmode ? CD1400_MSVR2_DSR : CD1400_MSVR2_CD); 543 544 if( mtty->mp_carrier != carrier ) { 545 SET(mtty->mp_flags, MTTYF_CARRIER_CHANGED); 546 mtty->mp_carrier = carrier; 547 needsoftint = 1; 548 } 549 550 cd1400_write_reg(cd, CD1400_EOSRR, 0); /* end service context */ 551 serviced = 1; 552 } /* if(mdm_service...) */ 553 554 if( ISSET(status, CD1400_SVRR_TXRDY) ) { 555 u_char tivr = *sc->ms_svcackt; /* enter tx service context */ 556 int port = tivr >> 4; 557 558 if( tivr & (1<<3) ) { /* parallel port */ 559 struct mbpp_port *mbpp; 560 561 mbpp = &sc->ms_mbpp->ms_port[port]; 562 cd = mbpp->mp_cd1400; 563 564 if( mbpp->mp_cnt ) { 565 int count = 0; 566 567 /* fill the fifo */ 568 while (mbpp->mp_cnt && 569 count++ < CD1400_PAR_FIFO_SIZE) { 570 cd1400_write_reg(cd, CD1400_TDR, 571 *mbpp->mp_ptr); 572 mbpp->mp_ptr++; 573 mbpp->mp_cnt--; 574 } 575 } else { 576 /* 577 * fifo is empty and we got no more data 578 * to send, so shut off interrupts and 579 * signal for a wakeup, which can't be 580 * done here in case we beat mbpp_send to 581 * the tsleep call (we are running at >spltty) 582 */ 583 cd1400_write_reg(cd, CD1400_SRER, 0); 584 SET(mbpp->mp_flags, MBPPF_WAKEUP); 585 needsoftint = 1; 586 } 587 } else { /* serial port */ 588 struct mtty_port *mtty; 589 struct tty *tp; 590 591 mtty = &sc->ms_mtty->ms_port[port]; 592 cd = mtty->mp_cd1400; 593 tp = mtty->mp_tty; 594 595 if( !ISSET(mtty->mp_flags, MTTYF_STOP) ) { 596 int count = 0; 597 598 /* check if we should start/stop a break */ 599 if( ISSET(mtty->mp_flags, MTTYF_SET_BREAK) ) { 600 cd1400_write_reg(cd, CD1400_TDR, 0); 601 cd1400_write_reg(cd, CD1400_TDR, 0x81); 602 /* should we delay too? */ 603 CLR(mtty->mp_flags, MTTYF_SET_BREAK); 604 count += 2; 605 } 606 607 if( ISSET(mtty->mp_flags, MTTYF_CLR_BREAK) ) { 608 cd1400_write_reg(cd, CD1400_TDR, 0); 609 cd1400_write_reg(cd, CD1400_TDR, 0x83); 610 CLR(mtty->mp_flags, MTTYF_CLR_BREAK); 611 count += 2; 612 } 613 614 /* I don't quite fill the fifo in case the last one is a 615 * NULL which I have to double up because its the escape 616 * code for embedded transmit characters. 617 */ 618 while( mtty->mp_txc > 0 && count < CD1400_TX_FIFO_SIZE - 1 ) { 619 u_char ch; 620 621 ch = *mtty->mp_txp; 622 623 mtty->mp_txc--; 624 mtty->mp_txp++; 625 626 if( ch == 0 ) { 627 cd1400_write_reg(cd, CD1400_TDR, ch); 628 count++; 629 } 630 631 cd1400_write_reg(cd, CD1400_TDR, ch); 632 count++; 633 } 634 } 635 636 /* if we ran out of work or are requested to STOP then 637 * shut off the txrdy interrupts and signal DONE to flush 638 * out the chars we have sent. 639 */ 640 if( mtty->mp_txc == 0 || ISSET(mtty->mp_flags, MTTYF_STOP) ) { 641 register int srer; 642 643 srer = cd1400_read_reg(cd, CD1400_SRER); 644 CLR(srer, CD1400_SRER_TXRDY); 645 cd1400_write_reg(cd, CD1400_SRER, srer); 646 CLR(mtty->mp_flags, MTTYF_STOP); 647 648 SET(mtty->mp_flags, MTTYF_DONE); 649 needsoftint = 1; 650 } 651 } 652 653 cd1400_write_reg(cd, CD1400_EOSRR, 0); /* end service context */ 654 serviced = 1; 655 } /* if(tx_service...) */ 656 657 /* XXX service CD1190 interrupts too 658 for( chip = 0 ; chip < sc->ms_ncd1190 ; chip++ ) { 659 } 660 */ 661 662 if( needsoftint ) { /* trigger the soft interrupt */ 663 #if defined(SUN4M) 664 if( CPU_ISSUN4M ) 665 raise(0, PIL_TTY); 666 else 667 #endif 668 ienab_bis(IE_MSOFT); 669 } 670 671 return(serviced); 672 } 673 674 /* 675 * magma soft interrupt handler 676 * 677 * returns 1 if it handled it, 0 otherwise 678 * 679 * runs at spltty() 680 */ 681 int 682 magma_soft(arg) 683 void *arg; 684 { 685 struct magma_softc *sc = arg; 686 struct mtty_softc *mtty = sc->ms_mtty; 687 struct mbpp_softc *mbpp = sc->ms_mbpp; 688 int port; 689 int serviced = 0; 690 int s, flags; 691 692 if (mtty == NULL) 693 goto chkbpp; 694 695 /* 696 * check the tty ports to see what needs doing 697 */ 698 for( port = 0 ; port < mtty->ms_nports ; port++ ) { 699 struct mtty_port *mp = &mtty->ms_port[port]; 700 struct tty *tp = mp->mp_tty; 701 702 if( !ISSET(tp->t_state, TS_ISOPEN) ) 703 continue; 704 705 /* 706 * handle any received data 707 */ 708 while( mp->mp_rget != mp->mp_rput ) { 709 u_char stat; 710 int data; 711 712 stat = mp->mp_rget[0]; 713 data = mp->mp_rget[1]; 714 mp->mp_rget = ((mp->mp_rget + 2) == mp->mp_rend) 715 ? mp->mp_rbuf : (mp->mp_rget + 2); 716 717 if( stat & (CD1400_RDSR_BREAK | CD1400_RDSR_FE) ) 718 data |= TTY_FE; 719 if( stat & CD1400_RDSR_PE ) 720 data |= TTY_PE; 721 722 if( stat & CD1400_RDSR_OE ) 723 log(LOG_WARNING, "%s%x: fifo overflow\n", 724 mtty->ms_dev.dv_xname, port); 725 726 (*linesw[tp->t_line].l_rint)(data, tp); 727 serviced = 1; 728 } 729 730 s = splhigh(); /* block out hard interrupt routine */ 731 flags = mp->mp_flags; 732 CLR(mp->mp_flags, MTTYF_DONE | MTTYF_CARRIER_CHANGED | MTTYF_RING_OVERFLOW); 733 splx(s); /* ok */ 734 735 if( ISSET(flags, MTTYF_CARRIER_CHANGED) ) { 736 dprintf(("%s%x: cd %s\n", mtty->ms_dev.dv_xname, 737 port, mp->mp_carrier ? "on" : "off")); 738 (*linesw[tp->t_line].l_modem)(tp, mp->mp_carrier); 739 serviced = 1; 740 } 741 742 if( ISSET(flags, MTTYF_RING_OVERFLOW) ) { 743 log(LOG_WARNING, "%s%x: ring buffer overflow\n", 744 mtty->ms_dev.dv_xname, port); 745 serviced = 1; 746 } 747 748 if( ISSET(flags, MTTYF_DONE) ) { 749 ndflush(&tp->t_outq, mp->mp_txp - tp->t_outq.c_cf); 750 CLR(tp->t_state, TS_BUSY); 751 (*linesw[tp->t_line].l_start)(tp); /* might be some more */ 752 serviced = 1; 753 } 754 } /* for(each mtty...) */ 755 756 757 chkbpp: 758 /* 759 * Check the bpp ports (if any) to see what needs doing 760 */ 761 if (mbpp == NULL) 762 return (serviced); 763 764 for( port = 0 ; port < mbpp->ms_nports ; port++ ) { 765 struct mbpp_port *mp = &mbpp->ms_port[port]; 766 767 if( !ISSET(mp->mp_flags, MBPPF_OPEN) ) 768 continue; 769 770 s = splhigh(); 771 flags = mp->mp_flags; 772 CLR(mp->mp_flags, MBPPF_WAKEUP); 773 splx(s); 774 775 if( ISSET(flags, MBPPF_WAKEUP) ) { 776 wakeup(mp); 777 serviced = 1; 778 } 779 780 } /* for(each mbpp...) */ 781 782 return(serviced); 783 } 784 785 /************************************************************************ 786 * 787 * MTTY Routines 788 * 789 * mtty_match match one mtty device 790 * mtty_attach attach mtty devices 791 * mttyopen open mtty device 792 * mttyclose close mtty device 793 * mttyread read from mtty 794 * mttywrite write to mtty 795 * mttyioctl do ioctl on mtty 796 * mttytty return tty pointer for mtty 797 * mttystop stop mtty device 798 * mtty_start start mtty device 799 * mtty_param set mtty parameters 800 * mtty_modem_control set modem control lines 801 */ 802 803 int 804 mtty_match(parent, cf, args) 805 struct device *parent; 806 struct cfdata *cf; 807 void *args; 808 { 809 struct magma_softc *sc = (struct magma_softc *)parent; 810 811 return( args == mtty_match && sc->ms_board->mb_nser && sc->ms_mtty == NULL ); 812 } 813 814 void 815 mtty_attach(parent, dev, args) 816 struct device *parent; 817 struct device *dev; 818 void *args; 819 { 820 struct magma_softc *sc = (struct magma_softc *)parent; 821 struct mtty_softc *ms = (struct mtty_softc *)dev; 822 int port, chip, chan; 823 824 sc->ms_mtty = ms; 825 dprintf((" addr %p", ms)); 826 827 for( port = 0, chip = 0, chan = 0 ; port < sc->ms_board->mb_nser ; port++ ) { 828 struct mtty_port *mp = &ms->ms_port[port]; 829 struct tty *tp; 830 831 mp->mp_cd1400 = &sc->ms_cd1400[chip]; 832 if( mp->mp_cd1400->cd_parmode && chan == 0 ) 833 chan = 1; /* skip channel 0 if parmode */ 834 mp->mp_channel = chan; 835 836 tp = ttymalloc(); 837 if( tp == NULL ) break; 838 tty_attach(tp); 839 tp->t_oproc = mtty_start; 840 tp->t_param = mtty_param; 841 842 mp->mp_tty = tp; 843 844 mp->mp_rbuf = malloc(MTTY_RBUF_SIZE, M_DEVBUF, M_NOWAIT); 845 if( mp->mp_rbuf == NULL ) break; 846 847 mp->mp_rend = mp->mp_rbuf + MTTY_RBUF_SIZE; 848 849 chan = (chan + 1) % CD1400_NO_OF_CHANNELS; 850 if( chan == 0 ) chip++; 851 } 852 853 ms->ms_nports = port; 854 printf(": %d tty%s\n", port, port == 1 ? "" : "s"); 855 } 856 857 /* 858 * open routine. returns zero if successful, else error code 859 */ 860 int 861 mttyopen(dev, flags, mode, p) 862 dev_t dev; 863 int flags; 864 int mode; 865 struct proc *p; 866 { 867 int card = MAGMA_CARD(dev); 868 int port = MAGMA_PORT(dev); 869 struct mtty_softc *ms; 870 struct mtty_port *mp; 871 struct tty *tp; 872 struct cd1400 *cd; 873 int error, s; 874 875 if( card >= mtty_cd.cd_ndevs || 876 (ms = mtty_cd.cd_devs[card]) == NULL || port >= ms->ms_nports ) 877 return(ENXIO); /* device not configured */ 878 879 mp = &ms->ms_port[port]; 880 tp = mp->mp_tty; 881 tp->t_dev = dev; 882 883 if (ISSET(tp->t_state, TS_ISOPEN) && 884 ISSET(tp->t_state, TS_XCLUDE) && 885 p->p_ucred->cr_uid != 0) 886 return (EBUSY); 887 888 s = spltty(); 889 890 if( !ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 891 892 /* set defaults */ 893 ttychars(tp); 894 tp->t_iflag = TTYDEF_IFLAG; 895 tp->t_oflag = TTYDEF_OFLAG; 896 tp->t_cflag = TTYDEF_CFLAG; 897 if( ISSET(mp->mp_openflags, TIOCFLAG_CLOCAL) ) 898 SET(tp->t_cflag, CLOCAL); 899 if( ISSET(mp->mp_openflags, TIOCFLAG_CRTSCTS) ) 900 SET(tp->t_cflag, CRTSCTS); 901 if( ISSET(mp->mp_openflags, TIOCFLAG_MDMBUF) ) 902 SET(tp->t_cflag, MDMBUF); 903 tp->t_lflag = TTYDEF_LFLAG; 904 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 905 906 /* init ring buffer */ 907 mp->mp_rput = mp->mp_rget = mp->mp_rbuf; 908 909 /* reset CD1400 channel */ 910 cd = mp->mp_cd1400; 911 cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel); 912 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET); 913 914 /* encode the port number in top half of LIVR */ 915 cd1400_write_reg(cd, CD1400_LIVR, port << 4 ); 916 917 /* sets parameters and raises DTR */ 918 (void)mtty_param(tp, &tp->t_termios); 919 920 /* set tty watermarks */ 921 ttsetwater(tp); 922 923 /* enable service requests */ 924 cd1400_write_reg(cd, CD1400_SRER, 925 CD1400_SRER_RXDATA | CD1400_SRER_MDMCH); 926 927 /* tell the tty about the carrier status */ 928 if( ISSET(mp->mp_openflags, TIOCFLAG_SOFTCAR) || 929 mp->mp_carrier ) 930 SET(tp->t_state, TS_CARR_ON); 931 else 932 CLR(tp->t_state, TS_CARR_ON); 933 } 934 splx(s); 935 936 error = ttyopen(tp, MTTY_DIALOUT(dev), ISSET(flags, O_NONBLOCK)); 937 if (error != 0) 938 goto bad; 939 940 error = (*linesw[tp->t_line].l_open)(dev, tp); 941 if (error != 0) 942 goto bad; 943 944 bad: 945 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 946 /* 947 * We failed to open the device, and nobody else had it opened. 948 * Clean up the state as appropriate. 949 */ 950 /* XXX - do that here */ 951 } 952 953 return (error); 954 } 955 956 /* 957 * close routine. returns zero if successful, else error code 958 */ 959 int 960 mttyclose(dev, flag, mode, p) 961 dev_t dev; 962 int flag; 963 int mode; 964 struct proc *p; 965 { 966 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(dev)]; 967 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 968 struct tty *tp = mp->mp_tty; 969 int s; 970 971 (*linesw[tp->t_line].l_close)(tp, flag); 972 ttyclose(tp); 973 974 s = spltty(); 975 976 /* if HUPCL is set, and the tty is no longer open 977 * shut down the port 978 */ 979 if( ISSET(tp->t_cflag, HUPCL) || !ISSET(tp->t_state, TS_ISOPEN) ) { 980 /* XXX wait until FIFO is empty before turning off the channel 981 struct cd1400 *cd = mp->mp_cd1400; 982 */ 983 984 /* drop DTR and RTS */ 985 (void)mtty_modem_control(mp, 0, DMSET); 986 987 /* turn off the channel 988 cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel); 989 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET); 990 */ 991 } 992 993 splx(s); 994 995 return(0); 996 } 997 998 /* 999 * Read routine 1000 */ 1001 int 1002 mttyread(dev, uio, flags) 1003 dev_t dev; 1004 struct uio *uio; 1005 int flags; 1006 { 1007 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(dev)]; 1008 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1009 struct tty *tp = mp->mp_tty; 1010 1011 return( (*linesw[tp->t_line].l_read)(tp, uio, flags) ); 1012 } 1013 1014 /* 1015 * Write routine 1016 */ 1017 int 1018 mttywrite(dev, uio, flags) 1019 dev_t dev; 1020 struct uio *uio; 1021 int flags; 1022 { 1023 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(dev)]; 1024 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1025 struct tty *tp = mp->mp_tty; 1026 1027 return( (*linesw[tp->t_line].l_write)(tp, uio, flags) ); 1028 } 1029 1030 /* 1031 * return tty pointer 1032 */ 1033 struct tty * 1034 mttytty(dev) 1035 dev_t dev; 1036 { 1037 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(dev)]; 1038 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1039 1040 return(mp->mp_tty); 1041 } 1042 1043 /* 1044 * ioctl routine 1045 */ 1046 int 1047 mttyioctl(dev, cmd, data, flags, p) 1048 dev_t dev; 1049 u_long cmd; 1050 caddr_t data; 1051 int flags; 1052 struct proc *p; 1053 { 1054 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(dev)]; 1055 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1056 struct tty *tp = mp->mp_tty; 1057 int error; 1058 1059 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flags, p); 1060 if( error >= 0 ) return(error); 1061 1062 error = ttioctl(tp, cmd, data, flags, p); 1063 if( error >= 0 ) return(error); 1064 1065 error = 0; 1066 1067 switch(cmd) { 1068 case TIOCSBRK: /* set break */ 1069 SET(mp->mp_flags, MTTYF_SET_BREAK); 1070 cd1400_enable_transmitter(mp->mp_cd1400, mp->mp_channel); 1071 break; 1072 1073 case TIOCCBRK: /* clear break */ 1074 SET(mp->mp_flags, MTTYF_CLR_BREAK); 1075 cd1400_enable_transmitter(mp->mp_cd1400, mp->mp_channel); 1076 break; 1077 1078 case TIOCSDTR: /* set DTR */ 1079 mtty_modem_control(mp, TIOCM_DTR, DMBIS); 1080 break; 1081 1082 case TIOCCDTR: /* clear DTR */ 1083 mtty_modem_control(mp, TIOCM_DTR, DMBIC); 1084 break; 1085 1086 case TIOCMSET: /* set modem lines */ 1087 mtty_modem_control(mp, *((int *)data), DMSET); 1088 break; 1089 1090 case TIOCMBIS: /* bit set modem lines */ 1091 mtty_modem_control(mp, *((int *)data), DMBIS); 1092 break; 1093 1094 case TIOCMBIC: /* bit clear modem lines */ 1095 mtty_modem_control(mp, *((int *)data), DMBIC); 1096 break; 1097 1098 case TIOCMGET: /* get modem lines */ 1099 *((int *)data) = mtty_modem_control(mp, 0, DMGET); 1100 break; 1101 1102 case TIOCGFLAGS: 1103 *((int *)data) = mp->mp_openflags; 1104 break; 1105 1106 case TIOCSFLAGS: 1107 if( suser(p->p_ucred, &p->p_acflag) ) 1108 error = EPERM; 1109 else 1110 mp->mp_openflags = *((int *)data) & 1111 (TIOCFLAG_SOFTCAR | TIOCFLAG_CLOCAL | 1112 TIOCFLAG_CRTSCTS | TIOCFLAG_MDMBUF); 1113 break; 1114 1115 default: 1116 error = ENOTTY; 1117 } 1118 1119 return(error); 1120 } 1121 1122 /* 1123 * Stop output, e.g., for ^S or output flush. 1124 */ 1125 void 1126 mttystop(tp, flags) 1127 struct tty *tp; 1128 int flags; 1129 { 1130 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(tp->t_dev)]; 1131 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(tp->t_dev)]; 1132 int s; 1133 1134 s = spltty(); 1135 1136 if( ISSET(tp->t_state, TS_BUSY) ) { 1137 if( !ISSET(tp->t_state, TS_TTSTOP) ) 1138 SET(tp->t_state, TS_FLUSH); 1139 1140 /* 1141 * the transmit interrupt routine will disable transmit when it 1142 * notices that MTTYF_STOP has been set. 1143 */ 1144 SET(mp->mp_flags, MTTYF_STOP); 1145 } 1146 1147 splx(s); 1148 } 1149 1150 /* 1151 * Start output, after a stop. 1152 */ 1153 void 1154 mtty_start(tp) 1155 struct tty *tp; 1156 { 1157 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(tp->t_dev)]; 1158 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(tp->t_dev)]; 1159 int s; 1160 1161 s = spltty(); 1162 1163 /* we only need to do something if we are not already busy 1164 * or delaying or stopped 1165 */ 1166 if( !ISSET(tp->t_state, TS_TTSTOP | TS_TIMEOUT | TS_BUSY) ) { 1167 1168 /* if we are sleeping and output has drained below 1169 * low water mark, awaken 1170 */ 1171 if( tp->t_outq.c_cc <= tp->t_lowat ) { 1172 if( ISSET(tp->t_state, TS_ASLEEP) ) { 1173 CLR(tp->t_state, TS_ASLEEP); 1174 wakeup(&tp->t_outq); 1175 } 1176 1177 selwakeup(&tp->t_wsel); 1178 } 1179 1180 /* if something to send, start transmitting 1181 */ 1182 if( tp->t_outq.c_cc ) { 1183 mp->mp_txc = ndqb(&tp->t_outq, 0); 1184 mp->mp_txp = tp->t_outq.c_cf; 1185 SET(tp->t_state, TS_BUSY); 1186 cd1400_enable_transmitter(mp->mp_cd1400, mp->mp_channel); 1187 } 1188 } 1189 1190 splx(s); 1191 } 1192 1193 /* 1194 * set/get modem line status 1195 * 1196 * bits can be: TIOCM_DTR, TIOCM_RTS, TIOCM_CTS, TIOCM_CD, TIOCM_RI, TIOCM_DSR 1197 * 1198 * note that DTR and RTS lines are exchanged, and that DSR is 1199 * not available on the LC2+1Sp card (used as CD) 1200 * 1201 * only let them fiddle with RTS if CRTSCTS is not enabled 1202 */ 1203 int 1204 mtty_modem_control(mp, bits, howto) 1205 struct mtty_port *mp; 1206 int bits; 1207 int howto; 1208 { 1209 struct cd1400 *cd = mp->mp_cd1400; 1210 struct tty *tp = mp->mp_tty; 1211 int s, msvr; 1212 1213 s = spltty(); 1214 1215 cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel); 1216 1217 switch(howto) { 1218 case DMGET: /* get bits */ 1219 bits = 0; 1220 1221 bits |= TIOCM_LE; 1222 1223 msvr = cd1400_read_reg(cd, CD1400_MSVR1); 1224 if( msvr & CD1400_MSVR1_RTS ) bits |= TIOCM_DTR; 1225 1226 msvr = cd1400_read_reg(cd, CD1400_MSVR2); 1227 if( msvr & CD1400_MSVR2_DTR ) bits |= TIOCM_RTS; 1228 if( msvr & CD1400_MSVR2_CTS ) bits |= TIOCM_CTS; 1229 if( msvr & CD1400_MSVR2_RI ) bits |= TIOCM_RI; 1230 if( msvr & CD1400_MSVR2_DSR ) bits |= (cd->cd_parmode ? TIOCM_CD : TIOCM_DSR); 1231 if( msvr & CD1400_MSVR2_CD ) bits |= (cd->cd_parmode ? 0 : TIOCM_CD); 1232 1233 break; 1234 1235 case DMSET: /* reset bits */ 1236 if( !ISSET(tp->t_cflag, CRTSCTS) ) 1237 cd1400_write_reg(cd, CD1400_MSVR2, ((bits & TIOCM_RTS) ? CD1400_MSVR2_DTR : 0)); 1238 1239 cd1400_write_reg(cd, CD1400_MSVR1, ((bits & TIOCM_DTR) ? CD1400_MSVR1_RTS : 0)); 1240 1241 break; 1242 1243 case DMBIS: /* set bits */ 1244 if( (bits & TIOCM_RTS) && !ISSET(tp->t_cflag, CRTSCTS) ) 1245 cd1400_write_reg(cd, CD1400_MSVR2, CD1400_MSVR2_DTR); 1246 1247 if( bits & TIOCM_DTR ) 1248 cd1400_write_reg(cd, CD1400_MSVR1, CD1400_MSVR1_RTS); 1249 1250 break; 1251 1252 case DMBIC: /* clear bits */ 1253 if( (bits & TIOCM_RTS) && !ISSET(tp->t_cflag, CRTSCTS) ) 1254 cd1400_write_reg(cd, CD1400_MSVR2, 0); 1255 1256 if( bits & TIOCM_DTR ) 1257 cd1400_write_reg(cd, CD1400_MSVR1, 0); 1258 1259 break; 1260 } 1261 1262 splx(s); 1263 return(bits); 1264 } 1265 1266 /* 1267 * Set tty parameters, returns error or 0 on success 1268 */ 1269 int 1270 mtty_param(tp, t) 1271 struct tty *tp; 1272 struct termios *t; 1273 { 1274 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(tp->t_dev)]; 1275 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(tp->t_dev)]; 1276 struct cd1400 *cd = mp->mp_cd1400; 1277 int rbpr, tbpr, rcor, tcor; 1278 u_char mcor1 = 0, mcor2 = 0; 1279 int s, opt; 1280 1281 if( t->c_ospeed && cd1400_compute_baud(t->c_ospeed, cd->cd_clock, &tcor, &tbpr) ) 1282 return(EINVAL); 1283 1284 if( t->c_ispeed && cd1400_compute_baud(t->c_ispeed, cd->cd_clock, &rcor, &rbpr) ) 1285 return(EINVAL); 1286 1287 s = spltty(); 1288 1289 /* hang up the line if ospeed is zero, else raise DTR */ 1290 (void)mtty_modem_control(mp, TIOCM_DTR, (t->c_ospeed == 0 ? DMBIC : DMBIS)); 1291 1292 /* select channel, done in mtty_modem_control() */ 1293 /* cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel); */ 1294 1295 /* set transmit speed */ 1296 if( t->c_ospeed ) { 1297 cd1400_write_reg(cd, CD1400_TCOR, tcor); 1298 cd1400_write_reg(cd, CD1400_TBPR, tbpr); 1299 } 1300 1301 /* set receive speed */ 1302 if( t->c_ispeed ) { 1303 cd1400_write_reg(cd, CD1400_RCOR, rcor); 1304 cd1400_write_reg(cd, CD1400_RBPR, rbpr); 1305 } 1306 1307 /* enable transmitting and receiving on this channel */ 1308 opt = CD1400_CCR_CMDCHANCTL | CD1400_CCR_XMTEN | CD1400_CCR_RCVEN; 1309 cd1400_write_ccr(cd, opt); 1310 1311 /* set parity, data and stop bits */ 1312 opt = 0; 1313 if( ISSET(t->c_cflag, PARENB) ) 1314 opt |= (ISSET(t->c_cflag, PARODD) ? CD1400_COR1_PARODD : CD1400_COR1_PARNORMAL); 1315 1316 if( !ISSET(t->c_iflag, INPCK) ) 1317 opt |= CD1400_COR1_NOINPCK; /* no parity checking */ 1318 1319 if( ISSET(t->c_cflag, CSTOPB) ) 1320 opt |= CD1400_COR1_STOP2; 1321 1322 switch( t->c_cflag & CSIZE ) { 1323 case CS5: 1324 opt |= CD1400_COR1_CS5; 1325 break; 1326 1327 case CS6: 1328 opt |= CD1400_COR1_CS6; 1329 break; 1330 1331 case CS7: 1332 opt |= CD1400_COR1_CS7; 1333 break; 1334 1335 default: 1336 opt |= CD1400_COR1_CS8; 1337 break; 1338 } 1339 1340 cd1400_write_reg(cd, CD1400_COR1, opt); 1341 1342 /* 1343 * enable Embedded Transmit Commands (for breaks) 1344 * use the CD1400 automatic CTS flow control if CRTSCTS is set 1345 */ 1346 opt = CD1400_COR2_ETC; 1347 if( ISSET(t->c_cflag, CRTSCTS) ) opt |= CD1400_COR2_CCTS_OFLOW; 1348 cd1400_write_reg(cd, CD1400_COR2, opt); 1349 1350 cd1400_write_reg(cd, CD1400_COR3, MTTY_RX_FIFO_THRESHOLD); 1351 1352 cd1400_write_ccr(cd, CD1400_CCR_CMDCORCHG | CD1400_CCR_COR1 | CD1400_CCR_COR2 | CD1400_CCR_COR3); 1353 1354 cd1400_write_reg(cd, CD1400_COR4, CD1400_COR4_PFO_EXCEPTION); 1355 cd1400_write_reg(cd, CD1400_COR5, 0); 1356 1357 /* 1358 * if automatic RTS handshaking enabled, set DTR threshold 1359 * (RTS and DTR lines are switched, CD1400 thinks its DTR) 1360 */ 1361 if( ISSET(t->c_cflag, CRTSCTS) ) 1362 mcor1 = MTTY_RX_DTR_THRESHOLD; 1363 1364 /* set up `carrier detect' interrupts */ 1365 if( cd->cd_parmode ) { 1366 SET(mcor1, CD1400_MCOR1_DSRzd); 1367 SET(mcor2, CD1400_MCOR2_DSRod); 1368 } else { 1369 SET(mcor1, CD1400_MCOR1_CDzd); 1370 SET(mcor2, CD1400_MCOR2_CDod); 1371 } 1372 1373 cd1400_write_reg(cd, CD1400_MCOR1, mcor1); 1374 cd1400_write_reg(cd, CD1400_MCOR2, mcor2); 1375 1376 /* receive timeout 2ms */ 1377 cd1400_write_reg(cd, CD1400_RTPR, 2); 1378 1379 splx(s); 1380 return(0); 1381 } 1382 1383 /************************************************************************ 1384 * 1385 * MBPP Routines 1386 * 1387 * mbpp_match match one mbpp device 1388 * mbpp_attach attach mbpp devices 1389 * mbppopen open mbpp device 1390 * mbppclose close mbpp device 1391 * mbppread read from mbpp 1392 * mbppwrite write to mbpp 1393 * mbppioctl do ioctl on mbpp 1394 * mbppselect do select on mbpp 1395 * mbpp_rw general rw routine 1396 * mbpp_timeout rw timeout 1397 * mbpp_start rw start after delay 1398 * mbpp_send send data 1399 * mbpp_recv recv data 1400 */ 1401 1402 int 1403 mbpp_match(parent, cf, args) 1404 struct device *parent; 1405 struct cfdata *cf; 1406 void *args; 1407 { 1408 struct magma_softc *sc = (struct magma_softc *)parent; 1409 1410 return( args == mbpp_match && sc->ms_board->mb_npar && sc->ms_mbpp == NULL ); 1411 } 1412 1413 void 1414 mbpp_attach(parent, dev, args) 1415 struct device *parent; 1416 struct device *dev; 1417 void *args; 1418 { 1419 struct magma_softc *sc = (struct magma_softc *)parent; 1420 struct mbpp_softc *ms = (struct mbpp_softc *)dev; 1421 struct mbpp_port *mp; 1422 int port; 1423 1424 sc->ms_mbpp = ms; 1425 dprintf((" addr %p", ms)); 1426 1427 for( port = 0 ; port < sc->ms_board->mb_npar ; port++ ) { 1428 mp = &ms->ms_port[port]; 1429 1430 if( sc->ms_ncd1190 ) 1431 mp->mp_cd1190 = &sc->ms_cd1190[port]; 1432 else 1433 mp->mp_cd1400 = &sc->ms_cd1400[0]; 1434 } 1435 1436 ms->ms_nports = port; 1437 printf(": %d port%s\n", port, port == 1 ? "" : "s"); 1438 } 1439 1440 /* 1441 * open routine. returns zero if successful, else error code 1442 */ 1443 int 1444 mbppopen(dev, flags, mode, p) 1445 dev_t dev; 1446 int flags; 1447 int mode; 1448 struct proc *p; 1449 { 1450 int card = MAGMA_CARD(dev); 1451 int port = MAGMA_PORT(dev); 1452 struct mbpp_softc *ms; 1453 struct mbpp_port *mp; 1454 int s; 1455 1456 if( card >= mbpp_cd.cd_ndevs || 1457 (ms = mbpp_cd.cd_devs[card]) == NULL || port >= ms->ms_nports ) 1458 return(ENXIO); 1459 1460 mp = &ms->ms_port[port]; 1461 1462 s = spltty(); 1463 if( ISSET(mp->mp_flags, MBPPF_OPEN) ) { 1464 splx(s); 1465 return(EBUSY); 1466 } 1467 SET(mp->mp_flags, MBPPF_OPEN); 1468 splx(s); 1469 1470 /* set defaults */ 1471 mp->mp_burst = MBPP_BURST; 1472 mp->mp_timeout = mbpp_mstohz(MBPP_TIMEOUT); 1473 mp->mp_delay = mbpp_mstohz(MBPP_DELAY); 1474 1475 /* init chips */ 1476 if( mp->mp_cd1400 ) { /* CD1400 */ 1477 struct cd1400 *cd = mp->mp_cd1400; 1478 1479 /* set up CD1400 channel */ 1480 s = spltty(); 1481 cd1400_write_reg(cd, CD1400_CAR, 0); 1482 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET); 1483 cd1400_write_reg(cd, CD1400_LIVR, (1<<3)); 1484 splx(s); 1485 } else { /* CD1190 */ 1486 mp->mp_flags = 0; 1487 return (ENXIO); 1488 } 1489 1490 return (0); 1491 } 1492 1493 /* 1494 * close routine. returns zero if successful, else error code 1495 */ 1496 int 1497 mbppclose(dev, flag, mode, p) 1498 dev_t dev; 1499 int flag; 1500 int mode; 1501 struct proc *p; 1502 { 1503 struct mbpp_softc *ms = mbpp_cd.cd_devs[MAGMA_CARD(dev)]; 1504 struct mbpp_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1505 1506 mp->mp_flags = 0; 1507 return(0); 1508 } 1509 1510 /* 1511 * Read routine 1512 */ 1513 int 1514 mbppread(dev, uio, flags) 1515 dev_t dev; 1516 struct uio *uio; 1517 int flags; 1518 { 1519 1520 return( mbpp_rw(dev, uio) ); 1521 } 1522 1523 /* 1524 * Write routine 1525 */ 1526 int 1527 mbppwrite(dev, uio, flags) 1528 dev_t dev; 1529 struct uio *uio; 1530 int flags; 1531 { 1532 1533 return( mbpp_rw(dev, uio) ); 1534 } 1535 1536 /* 1537 * ioctl routine 1538 */ 1539 int 1540 mbppioctl(dev, cmd, data, flags, p) 1541 dev_t dev; 1542 u_long cmd; 1543 caddr_t data; 1544 int flags; 1545 struct proc *p; 1546 { 1547 struct mbpp_softc *ms = mbpp_cd.cd_devs[MAGMA_CARD(dev)]; 1548 struct mbpp_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1549 struct mbpp_param *bp; 1550 int error = 0; 1551 int s; 1552 1553 switch(cmd) { 1554 case MBPPIOCSPARAM: 1555 bp = (struct mbpp_param *)data; 1556 if( bp->bp_burst < MBPP_BURST_MIN || bp->bp_burst > MBPP_BURST_MAX || 1557 bp->bp_delay < MBPP_DELAY_MIN || bp->bp_delay > MBPP_DELAY_MIN ) { 1558 error = EINVAL; 1559 } else { 1560 mp->mp_burst = bp->bp_burst; 1561 mp->mp_timeout = mbpp_mstohz(bp->bp_timeout); 1562 mp->mp_delay = mbpp_mstohz(bp->bp_delay); 1563 } 1564 break; 1565 case MBPPIOCGPARAM: 1566 bp = (struct mbpp_param *)data; 1567 bp->bp_burst = mp->mp_burst; 1568 bp->bp_timeout = mbpp_hztoms(mp->mp_timeout); 1569 bp->bp_delay = mbpp_hztoms(mp->mp_delay); 1570 break; 1571 case MBPPIOCGSTAT: 1572 /* XXX make this more generic */ 1573 s = spltty(); 1574 cd1400_write_reg(mp->mp_cd1400, CD1400_CAR, 0); 1575 *(int *)data = cd1400_read_reg(mp->mp_cd1400, CD1400_PSVR); 1576 splx(s); 1577 break; 1578 default: 1579 error = ENOTTY; 1580 } 1581 1582 return(error); 1583 } 1584 1585 /* 1586 * poll routine 1587 */ 1588 int 1589 mbpppoll(dev, rw, p) 1590 dev_t dev; 1591 int rw; 1592 struct proc *p; 1593 { 1594 1595 return(ENODEV); 1596 } 1597 1598 int 1599 mbpp_rw(dev, uio) 1600 dev_t dev; 1601 struct uio *uio; 1602 { 1603 int card = MAGMA_CARD(dev); 1604 int port = MAGMA_PORT(dev); 1605 struct mbpp_softc *ms = mbpp_cd.cd_devs[card]; 1606 struct mbpp_port *mp = &ms->ms_port[port]; 1607 caddr_t buffer, ptr; 1608 int buflen, cnt, len; 1609 int s, error = 0; 1610 int gotdata = 0; 1611 1612 if( uio->uio_resid == 0 ) 1613 return(0); 1614 1615 buflen = min(uio->uio_resid, mp->mp_burst); 1616 buffer = malloc(buflen, M_DEVBUF, M_WAITOK); 1617 if( buffer == NULL ) 1618 return(ENOMEM); 1619 1620 SET(mp->mp_flags, MBPPF_UIO); 1621 1622 /* 1623 * start timeout, if needed 1624 */ 1625 if( mp->mp_timeout > 0 ) { 1626 SET(mp->mp_flags, MBPPF_TIMEOUT); 1627 timeout(mbpp_timeout, mp, mp->mp_timeout); 1628 } 1629 1630 len = cnt = 0; 1631 while( uio->uio_resid > 0 ) { 1632 len = min(buflen, uio->uio_resid); 1633 ptr = buffer; 1634 1635 if( uio->uio_rw == UIO_WRITE ) { 1636 error = uiomove(ptr, len, uio); 1637 if( error ) break; 1638 } 1639 again: /* goto bad */ 1640 /* timed out? */ 1641 if( !ISSET(mp->mp_flags, MBPPF_UIO) ) 1642 break; 1643 1644 /* 1645 * perform the operation 1646 */ 1647 if( uio->uio_rw == UIO_WRITE ) { 1648 cnt = mbpp_send(mp, ptr, len); 1649 } else { 1650 cnt = mbpp_recv(mp, ptr, len); 1651 } 1652 1653 if( uio->uio_rw == UIO_READ ) { 1654 if( cnt ) { 1655 error = uiomove(ptr, cnt, uio); 1656 if( error ) break; 1657 gotdata++; 1658 } 1659 else if( gotdata ) /* consider us done */ 1660 break; 1661 } 1662 1663 /* timed out? */ 1664 if( !ISSET(mp->mp_flags, MBPPF_UIO) ) 1665 break; 1666 1667 /* 1668 * poll delay? 1669 */ 1670 if( mp->mp_delay > 0 ) { 1671 s = splsoftclock(); 1672 SET(mp->mp_flags, MBPPF_DELAY); 1673 timeout(mbpp_start, mp, mp->mp_delay); 1674 error = tsleep(mp, PCATCH | PZERO, "mbppdelay", 0); 1675 splx(s); 1676 if( error ) break; 1677 } 1678 1679 /* 1680 * don't call uiomove again until we used all the data we grabbed 1681 */ 1682 if( uio->uio_rw == UIO_WRITE && cnt != len ) { 1683 ptr += cnt; 1684 len -= cnt; 1685 cnt = 0; 1686 goto again; 1687 } 1688 } 1689 1690 /* 1691 * clear timeouts 1692 */ 1693 s = splsoftclock(); 1694 if( ISSET(mp->mp_flags, MBPPF_TIMEOUT) ) { 1695 untimeout(mbpp_timeout, mp); 1696 CLR(mp->mp_flags, MBPPF_TIMEOUT); 1697 } 1698 if( ISSET(mp->mp_flags, MBPPF_DELAY) ) { 1699 untimeout(mbpp_start, mp); 1700 CLR(mp->mp_flags, MBPPF_DELAY); 1701 } 1702 splx(s); 1703 1704 /* 1705 * adjust for those chars that we uiomoved but never actually wrote 1706 */ 1707 if( uio->uio_rw == UIO_WRITE && cnt != len ) { 1708 uio->uio_resid += (len - cnt); 1709 } 1710 1711 free(buffer, M_DEVBUF); 1712 return(error); 1713 } 1714 1715 void 1716 mbpp_timeout(arg) 1717 void *arg; 1718 { 1719 struct mbpp_port *mp = arg; 1720 1721 CLR(mp->mp_flags, MBPPF_UIO | MBPPF_TIMEOUT); 1722 wakeup(mp); 1723 } 1724 1725 void 1726 mbpp_start(arg) 1727 void *arg; 1728 { 1729 struct mbpp_port *mp = arg; 1730 1731 CLR(mp->mp_flags, MBPPF_DELAY); 1732 wakeup(mp); 1733 } 1734 1735 int 1736 mbpp_send(mp, ptr, len) 1737 struct mbpp_port *mp; 1738 caddr_t ptr; 1739 int len; 1740 { 1741 int s; 1742 struct cd1400 *cd = mp->mp_cd1400; 1743 1744 /* set up io information */ 1745 mp->mp_ptr = ptr; 1746 mp->mp_cnt = len; 1747 1748 /* start transmitting */ 1749 s = spltty(); 1750 if( cd ) { 1751 cd1400_write_reg(cd, CD1400_CAR, 0); 1752 1753 /* output strobe width ~1microsecond */ 1754 cd1400_write_reg(cd, CD1400_TBPR, 10); 1755 1756 /* enable channel */ 1757 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_XMTEN); 1758 cd1400_write_reg(cd, CD1400_SRER, CD1400_SRER_TXRDY); 1759 } 1760 1761 /* ZZzzz... */ 1762 tsleep(mp, PCATCH | PZERO, "mbpp_send", 0); 1763 1764 /* stop transmitting */ 1765 if( cd ) { 1766 cd1400_write_reg(cd, CD1400_CAR, 0); 1767 1768 /* disable transmitter */ 1769 cd1400_write_reg(cd, CD1400_SRER, 0); 1770 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_XMTDIS); 1771 1772 /* flush fifo */ 1773 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET | CD1400_CCR_FTF); 1774 } 1775 splx(s); 1776 1777 /* return number of chars sent */ 1778 return(len - mp->mp_cnt); 1779 } 1780 1781 int 1782 mbpp_recv(mp, ptr, len) 1783 struct mbpp_port *mp; 1784 caddr_t ptr; 1785 int len; 1786 { 1787 int s; 1788 struct cd1400 *cd = mp->mp_cd1400; 1789 1790 /* set up io information */ 1791 mp->mp_ptr = ptr; 1792 mp->mp_cnt = len; 1793 1794 /* start receiving */ 1795 s = spltty(); 1796 if( cd ) { 1797 int rcor, rbpr; 1798 1799 cd1400_write_reg(cd, CD1400_CAR, 0); 1800 1801 /* input strobe at 100kbaud (10microseconds) */ 1802 cd1400_compute_baud(100000, cd->cd_clock, &rcor, &rbpr); 1803 cd1400_write_reg(cd, CD1400_RCOR, rcor); 1804 cd1400_write_reg(cd, CD1400_RBPR, rbpr); 1805 1806 /* rx threshold */ 1807 cd1400_write_reg(cd, CD1400_COR3, MBPP_RX_FIFO_THRESHOLD); 1808 cd1400_write_ccr(cd, CD1400_CCR_CMDCORCHG | CD1400_CCR_COR3); 1809 1810 /* enable channel */ 1811 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_RCVEN); 1812 cd1400_write_reg(cd, CD1400_SRER, CD1400_SRER_RXDATA); 1813 } 1814 1815 /* ZZzzz... */ 1816 tsleep(mp, PCATCH | PZERO, "mbpp_recv", 0); 1817 1818 /* stop receiving */ 1819 if( cd ) { 1820 cd1400_write_reg(cd, CD1400_CAR, 0); 1821 1822 /* disable receiving */ 1823 cd1400_write_reg(cd, CD1400_SRER, 0); 1824 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_RCVDIS); 1825 } 1826 splx(s); 1827 1828 /* return number of chars received */ 1829 return(len - mp->mp_cnt); 1830 } 1831 1832 int 1833 mbpp_hztoms(h) 1834 int h; 1835 { 1836 int m = h; 1837 1838 if( m > 0 ) 1839 m = m * 1000 / hz; 1840 return(m); 1841 } 1842 1843 int 1844 mbpp_mstohz(m) 1845 int m; 1846 { 1847 int h = m; 1848 1849 if( h > 0 ) { 1850 h = h * hz / 1000; 1851 if( h == 0 ) 1852 h = 1000 / hz; 1853 } 1854 return(h); 1855 } 1856 1857 #endif /* NMAGMA */ 1858
Indexes created Thu Oct 02 10:09:58 GMT 2025