magma.c revision 1.42
1 /* $NetBSD: magma.c,v 1.42 2007/08/12 17:53:01 macallan Exp $ */ 2 /* 3 * magma.c 4 * 5 * Copyright (c) 1998 Iain Hibbert 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Iain Hibbert 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35 /* 36 * Driver for Magma SBus Serial/Parallel cards using the Cirrus Logic 37 * CD1400 & CD1190 chips 38 */ 39 40 #include <sys/cdefs.h> 41 __KERNEL_RCSID(0, "$NetBSD: magma.c,v 1.42 2007/08/12 17:53:01 macallan Exp $"); 42 43 #if 0 44 #define MAGMA_DEBUG 45 #endif 46 47 #include "magma.h" 48 #if NMAGMA > 0 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/proc.h> 53 #include <sys/device.h> 54 #include <sys/file.h> 55 #include <sys/ioctl.h> 56 #include <sys/malloc.h> 57 #include <sys/tty.h> 58 #include <sys/time.h> 59 #include <sys/kernel.h> 60 #include <sys/syslog.h> 61 #include <sys/conf.h> 62 #include <sys/errno.h> 63 #include <sys/kauth.h> 64 65 #include <machine/bus.h> 66 #include <machine/intr.h> 67 #include <machine/autoconf.h> 68 69 #include <dev/sbus/sbusvar.h> 70 71 #include <dev/ic/cd1400reg.h> 72 #include <dev/ic/cd1190reg.h> 73 74 #include <dev/sbus/mbppio.h> 75 #include <dev/sbus/magmareg.h> 76 77 /* supported cards 78 * 79 * The table below lists the cards that this driver is likely to 80 * be able to support. 81 * 82 * Cards with parallel ports: except for the LC2+1Sp, they all use 83 * the CD1190 chip which I know nothing about. I've tried to leave 84 * hooks for it so it shouldn't be too hard to add support later. 85 * (I think somebody is working on this separately) 86 * 87 * Thanks to Bruce at Magma for telling me the hardware offsets. 88 */ 89 static struct magma_board_info supported_cards[] = { 90 { 91 "MAGMA_Sp", "MAGMA,4_Sp", "Magma 4 Sp", 4, 0, 92 1, 0xa000, 0xc000, 0xe000, { 0x8000, 0, 0, 0 }, 93 0, { 0, 0 } 94 }, 95 { 96 "MAGMA_Sp", "MAGMA,8_Sp", "Magma 8 Sp", 8, 0, 97 2, 0xa000, 0xc000, 0xe000, { 0x4000, 0x6000, 0, 0 }, 98 0, { 0, 0 } 99 }, 100 { 101 "MAGMA_Sp", "MAGMA,_8HS_Sp", "Magma Fast 8 Sp", 8, 0, 102 2, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0, 0 }, 103 0, { 0, 0 } 104 }, 105 { 106 "MAGMA_Sp", "MAGMA,_8SP_422", "Magma 8 Sp - 422", 8, 0, 107 2, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0, 0 }, 108 0, { 0, 0 } 109 }, 110 { 111 "MAGMA_Sp", "MAGMA,12_Sp", "Magma 12 Sp", 12, 0, 112 3, 0xa000, 0xc000, 0xe000, { 0x2000, 0x4000, 0x6000, 0 }, 113 0, { 0, 0 } 114 }, 115 { 116 "MAGMA_Sp", "MAGMA,16_Sp", "Magma 16 Sp", 16, 0, 117 4, 0xd000, 0xe000, 0xf000, { 0x8000, 0x9000, 0xa000, 0xb000 }, 118 0, { 0, 0 } 119 }, 120 { 121 "MAGMA_Sp", "MAGMA,16_Sp_2", "Magma 16 Sp", 16, 0, 122 4, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0xc000, 0xe000 }, 123 0, { 0, 0 } 124 }, 125 { 126 "MAGMA_Sp", "MAGMA,16HS_Sp", "Magma Fast 16 Sp", 16, 0, 127 4, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0xc000, 0xe000 }, 128 0, { 0, 0 } 129 }, 130 { 131 "MAGMA_Sp", "MAGMA,21_Sp", "Magma LC 2+1 Sp", 2, 1, 132 1, 0xa000, 0xc000, 0xe000, { 0x8000, 0, 0, 0 }, 133 0, { 0, 0 } 134 }, 135 { 136 "MAGMA_Sp", "MAGMA,21HS_Sp", "Magma 2+1 Sp", 2, 1, 137 1, 0xa000, 0xc000, 0xe000, { 0x4000, 0, 0, 0 }, 138 1, { 0x6000, 0 } 139 }, 140 { 141 "MAGMA_Sp", "MAGMA,41_Sp", "Magma 4+1 Sp", 4, 1, 142 1, 0xa000, 0xc000, 0xe000, { 0x4000, 0, 0, 0 }, 143 1, { 0x6000, 0 } 144 }, 145 { 146 "MAGMA_Sp", "MAGMA,82_Sp", "Magma 8+2 Sp", 8, 2, 147 2, 0xd000, 0xe000, 0xf000, { 0x8000, 0x9000, 0, 0 }, 148 2, { 0xa000, 0xb000 } 149 }, 150 { 151 "MAGMA_Sp", "MAGMA,P1_Sp", "Magma P1 Sp", 0, 1, 152 0, 0, 0, 0, { 0, 0, 0, 0 }, 153 1, { 0x8000, 0 } 154 }, 155 { 156 "MAGMA_Sp", "MAGMA,P2_Sp", "Magma P2 Sp", 0, 2, 157 0, 0, 0, 0, { 0, 0, 0, 0 }, 158 2, { 0x4000, 0x8000 } 159 }, 160 { 161 "MAGMA 2+1HS Sp", "", "Magma 2+1HS Sp", 2, 0, 162 1, 0xa000, 0xc000, 0xe000, { 0x4000, 0, 0, 0 }, 163 1, { 0x8000, 0 } 164 }, 165 { 166 NULL, NULL, NULL, 0, 0, 167 0, 0, 0, 0, { 0, 0, 0, 0 }, 168 0, { 0, 0 } 169 } 170 }; 171 172 /************************************************************************ 173 * 174 * Autoconfig Stuff 175 */ 176 177 CFATTACH_DECL(magma, sizeof(struct magma_softc), 178 magma_match, magma_attach, NULL, NULL); 179 180 CFATTACH_DECL(mtty, sizeof(struct mtty_softc), 181 mtty_match, mtty_attach, NULL, NULL); 182 183 CFATTACH_DECL(mbpp, sizeof(struct mbpp_softc), 184 mbpp_match, mbpp_attach, NULL, NULL); 185 186 extern struct cfdriver mtty_cd; 187 extern struct cfdriver mbpp_cd; 188 189 dev_type_open(mttyopen); 190 dev_type_close(mttyclose); 191 dev_type_read(mttyread); 192 dev_type_write(mttywrite); 193 dev_type_ioctl(mttyioctl); 194 dev_type_stop(mttystop); 195 dev_type_tty(mttytty); 196 dev_type_poll(mttypoll); 197 198 const struct cdevsw mtty_cdevsw = { 199 mttyopen, mttyclose, mttyread, mttywrite, mttyioctl, 200 mttystop, mttytty, mttypoll, nommap, ttykqfilter, D_TTY 201 }; 202 203 dev_type_open(mbppopen); 204 dev_type_close(mbppclose); 205 dev_type_read(mbpp_rw); 206 dev_type_ioctl(mbppioctl); 207 208 const struct cdevsw mbpp_cdevsw = { 209 mbppopen, mbppclose, mbpp_rw, mbpp_rw, mbppioctl, 210 nostop, notty, nopoll, nommap, nokqfilter, D_OTHER 211 }; 212 213 /************************************************************************ 214 * 215 * CD1400 Routines 216 * 217 * cd1400_compute_baud calculate COR/BPR register values 218 * cd1400_write_ccr write a value to CD1400 ccr 219 * cd1400_read_reg read from a CD1400 register 220 * cd1400_write_reg write to a CD1400 register 221 * cd1400_enable_transmitter enable transmitting on CD1400 channel 222 */ 223 224 /* 225 * compute the bpr/cor pair for any baud rate 226 * returns 0 for success, 1 for failure 227 */ 228 int 229 cd1400_compute_baud(speed, clock, cor, bpr) 230 speed_t speed; 231 int clock; 232 int *cor, *bpr; 233 { 234 int c, co, br; 235 236 if( speed < 50 || speed > 150000 ) 237 return(1); 238 239 for( c = 0, co = 8 ; co <= 2048 ; co <<= 2, c++ ) { 240 br = ((clock * 1000000) + (co * speed) / 2) / (co * speed); 241 if( br < 0x100 ) { 242 *bpr = br; 243 *cor = c; 244 return(0); 245 } 246 } 247 248 return(1); 249 } 250 251 /* 252 * Write a CD1400 channel command, should have a timeout? 253 */ 254 inline void 255 cd1400_write_ccr(cd, cmd) 256 struct cd1400 *cd; 257 u_char cmd; 258 { 259 while( cd1400_read_reg(cd, CD1400_CCR) ) 260 ; 261 262 cd1400_write_reg(cd, CD1400_CCR, cmd); 263 } 264 265 /* 266 * read a value from a cd1400 register 267 */ 268 inline u_char 269 cd1400_read_reg(cd, reg) 270 struct cd1400 *cd; 271 int reg; 272 { 273 return(cd->cd_reg[reg]); 274 } 275 276 /* 277 * write a value to a cd1400 register 278 */ 279 inline void 280 cd1400_write_reg(cd, reg, value) 281 struct cd1400 *cd; 282 int reg; 283 u_char value; 284 { 285 cd->cd_reg[reg] = value; 286 } 287 288 /* 289 * enable transmit service requests for cd1400 channel 290 */ 291 void 292 cd1400_enable_transmitter(cd, channel) 293 struct cd1400 *cd; 294 int channel; 295 { 296 int s, srer; 297 298 s = spltty(); 299 cd1400_write_reg(cd, CD1400_CAR, channel); 300 srer = cd1400_read_reg(cd, CD1400_SRER); 301 SET(srer, CD1400_SRER_TXRDY); 302 cd1400_write_reg(cd, CD1400_SRER, srer); 303 splx(s); 304 } 305 306 /************************************************************************ 307 * 308 * CD1190 Routines 309 */ 310 311 /* well, there are none yet */ 312 313 /************************************************************************ 314 * 315 * Magma Routines 316 * 317 * magma_match reports if we have a magma board available 318 * magma_attach attaches magma boards to the sbus 319 * magma_hard hardware level interrupt routine 320 * magma_soft software level interrupt routine 321 */ 322 323 int 324 magma_match(parent, cf, aux) 325 struct device *parent; 326 struct cfdata *cf; 327 void *aux; 328 { 329 struct sbus_attach_args *sa = aux; 330 struct magma_board_info *card; 331 332 /* See if we support this device */ 333 for (card = supported_cards; ; card++) { 334 if (card->mb_sbusname == NULL) 335 /* End of table: no match */ 336 return (0); 337 if (strcmp(sa->sa_name, card->mb_sbusname) == 0) 338 break; 339 } 340 341 dprintf(("magma: matched `%s'\n", sa->sa_name)); 342 dprintf(("magma: magma_prom `%s'\n", 343 prom_getpropstring(sa->sa_node, "magma_prom"))); 344 dprintf(("magma: intlevels `%s'\n", 345 prom_getpropstring(sa->sa_node, "intlevels"))); 346 dprintf(("magma: chiprev `%s'\n", 347 prom_getpropstring(sa->sa_node, "chiprev"))); 348 dprintf(("magma: clock `%s'\n", 349 prom_getpropstring(sa->sa_node, "clock"))); 350 351 return (1); 352 } 353 354 void 355 magma_attach(parent, self, aux) 356 struct device *parent; 357 struct device *self; 358 void *aux; 359 { 360 struct sbus_attach_args *sa = aux; 361 struct magma_softc *sc = (struct magma_softc *)self; 362 struct magma_board_info *card; 363 bus_space_handle_t bh; 364 char *magma_prom, *clockstr; 365 int cd_clock; 366 int node, chip; 367 368 node = sa->sa_node; 369 370 /* 371 * Find the card model. 372 * Older models all have sbus node name `MAGMA_Sp' (see 373 * `supported_cards[]' above), and must be distinguished 374 * by the `magma_prom' property. 375 */ 376 magma_prom = prom_getpropstring(node, "magma_prom"); 377 378 for (card = supported_cards; card->mb_name != NULL; card++) { 379 if (strcmp(sa->sa_name, card->mb_sbusname) != 0) 380 /* Sbus node name doesn't match */ 381 continue; 382 if (strcmp(magma_prom, card->mb_name) == 0) 383 /* Model name match */ 384 break; 385 } 386 387 if( card->mb_name == NULL ) { 388 printf(": %s (unsupported)\n", magma_prom); 389 return; 390 } 391 392 dprintf((" addr %p", sc)); 393 printf(": %s\n", card->mb_realname); 394 395 sc->ms_board = card; 396 sc->ms_ncd1400 = card->mb_ncd1400; 397 sc->ms_ncd1190 = card->mb_ncd1190; 398 399 if (sbus_bus_map(sa->sa_bustag, 400 sa->sa_slot, sa->sa_offset, sa->sa_size, 401 BUS_SPACE_MAP_LINEAR, &bh) != 0) { 402 printf("%s @ sbus: cannot map registers\n", self->dv_xname); 403 return; 404 } 405 406 /* the SVCACK* lines are daisychained */ 407 sc->ms_svcackr = (char *)bus_space_vaddr(sa->sa_bustag, bh) 408 + card->mb_svcackr; 409 sc->ms_svcackt = (char *)bus_space_vaddr(sa->sa_bustag, bh) 410 + card->mb_svcackt; 411 sc->ms_svcackm = (char *)bus_space_vaddr(sa->sa_bustag, bh) 412 + card->mb_svcackm; 413 414 /* 415 * Find the clock speed; it's the same for all CD1400 chips 416 * on the board. 417 */ 418 clockstr = prom_getpropstring(node, "clock"); 419 if (*clockstr == '\0') 420 /* Default to 25MHz */ 421 cd_clock = 25; 422 else { 423 cd_clock = 0; 424 while (*clockstr != '\0') 425 cd_clock = (cd_clock * 10) + (*clockstr++ - '0'); 426 } 427 428 /* init the cd1400 chips */ 429 for( chip = 0 ; chip < card->mb_ncd1400 ; chip++ ) { 430 struct cd1400 *cd = &sc->ms_cd1400[chip]; 431 432 cd->cd_clock = cd_clock; 433 cd->cd_reg = (char *)bus_space_vaddr(sa->sa_bustag, bh) + 434 card->mb_cd1400[chip]; 435 436 /* prom_getpropstring(node, "chiprev"); */ 437 /* seemingly the Magma drivers just ignore the propstring */ 438 cd->cd_chiprev = cd1400_read_reg(cd, CD1400_GFRCR); 439 440 dprintf(("%s attach CD1400 %d addr %p rev %x clock %dMHz\n", 441 sc->ms_dev.dv_xname, chip, 442 cd->cd_reg, cd->cd_chiprev, cd->cd_clock)); 443 444 /* clear GFRCR */ 445 cd1400_write_reg(cd, CD1400_GFRCR, 0x00); 446 447 /* reset whole chip */ 448 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET | CD1400_CCR_FULLRESET); 449 450 /* wait for revision code to be restored */ 451 while( cd1400_read_reg(cd, CD1400_GFRCR) != cd->cd_chiprev ) 452 ; 453 454 /* set the Prescaler Period Register to tick at 1ms */ 455 cd1400_write_reg(cd, CD1400_PPR, 456 ((cd->cd_clock * 1000000 / CD1400_PPR_PRESCALER + 500) / 1000)); 457 458 /* The LC2+1Sp card is the only card that doesn't have 459 * a CD1190 for the parallel port, but uses channel 0 of 460 * the CD1400, so we make a note of it for later and set up 461 * the CD1400 for parallel mode operation. 462 */ 463 if( card->mb_npar && card->mb_ncd1190 == 0 ) { 464 cd1400_write_reg(cd, CD1400_GCR, CD1400_GCR_PARALLEL); 465 cd->cd_parmode = 1; 466 } 467 } 468 469 /* init the cd1190 chips */ 470 for( chip = 0 ; chip < card->mb_ncd1190 ; chip++ ) { 471 struct cd1190 *cd = &sc->ms_cd1190[chip]; 472 473 cd->cd_reg = (char *)bus_space_vaddr(sa->sa_bustag, bh) + 474 card->mb_cd1190[chip]; 475 476 /* XXX don't know anything about these chips yet */ 477 printf("%s: CD1190 %d addr %p (unsupported)\n", 478 self->dv_xname, chip, cd->cd_reg); 479 } 480 481 sbus_establish(&sc->ms_sd, &sc->ms_dev); 482 483 /* configure the children */ 484 (void)config_found(self, mtty_match, NULL); 485 (void)config_found(self, mbpp_match, NULL); 486 487 /* 488 * Establish the interrupt handlers. 489 */ 490 if (sa->sa_nintr == 0) 491 return; /* No interrupts to service!? */ 492 493 (void)bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_SERIAL, 494 magma_hard, sc); 495 sc->ms_sicookie = softintr_establish(IPL_SOFTSERIAL, magma_soft, sc); 496 if (sc->ms_sicookie == NULL) { 497 printf("\n%s: cannot establish soft int handler\n", 498 sc->ms_dev.dv_xname); 499 return; 500 } 501 evcnt_attach_dynamic(&sc->ms_intrcnt, EVCNT_TYPE_INTR, NULL, 502 sc->ms_dev.dv_xname, "intr"); 503 } 504 505 /* 506 * hard interrupt routine 507 * 508 * returns 1 if it handled it, otherwise 0 509 * 510 * runs at IPL_SERIAL 511 */ 512 int 513 magma_hard(arg) 514 void *arg; 515 { 516 struct magma_softc *sc = arg; 517 struct cd1400 *cd; 518 int chip, status = 0; 519 int serviced = 0; 520 int needsoftint = 0; 521 522 /* 523 * check status of all the CD1400 chips 524 */ 525 for( chip = 0 ; chip < sc->ms_ncd1400 ; chip++ ) 526 status |= cd1400_read_reg(&sc->ms_cd1400[chip], CD1400_SVRR); 527 528 if( ISSET(status, CD1400_SVRR_RXRDY) ) { 529 u_char rivr = *sc->ms_svcackr; /* enter rx service context */ 530 int port = rivr >> 4; 531 532 if( rivr & (1<<3) ) { /* parallel port */ 533 struct mbpp_port *mbpp; 534 int n_chars; 535 536 mbpp = &sc->ms_mbpp->ms_port[port]; 537 cd = mbpp->mp_cd1400; 538 539 /* don't think we have to handle exceptions */ 540 n_chars = cd1400_read_reg(cd, CD1400_RDCR); 541 while (n_chars--) { 542 if( mbpp->mp_cnt == 0 ) { 543 SET(mbpp->mp_flags, MBPPF_WAKEUP); 544 needsoftint = 1; 545 break; 546 } 547 *mbpp->mp_ptr = cd1400_read_reg(cd,CD1400_RDSR); 548 mbpp->mp_ptr++; 549 mbpp->mp_cnt--; 550 } 551 } else { /* serial port */ 552 struct mtty_port *mtty; 553 u_char *ptr, n_chars, line_stat; 554 555 mtty = &sc->ms_mtty->ms_port[port]; 556 cd = mtty->mp_cd1400; 557 558 if( ISSET(rivr, CD1400_RIVR_EXCEPTION) ) { 559 line_stat = cd1400_read_reg(cd, CD1400_RDSR); 560 n_chars = 1; 561 } else { /* no exception, received data OK */ 562 line_stat = 0; 563 n_chars = cd1400_read_reg(cd, CD1400_RDCR); 564 } 565 566 ptr = mtty->mp_rput; 567 while( n_chars-- ) { 568 *ptr++ = line_stat; 569 *ptr++ = cd1400_read_reg(cd, CD1400_RDSR); 570 if( ptr == mtty->mp_rend ) ptr = mtty->mp_rbuf; 571 if( ptr == mtty->mp_rget ) { 572 if( ptr == mtty->mp_rbuf ) 573 ptr = mtty->mp_rend; 574 ptr -= 2; 575 SET(mtty->mp_flags, MTTYF_RING_OVERFLOW); 576 break; 577 } 578 } 579 mtty->mp_rput = ptr; 580 581 needsoftint = 1; 582 } 583 584 cd1400_write_reg(cd, CD1400_EOSRR, 0); /* end service context */ 585 serviced = 1; 586 } /* if(rx_service...) */ 587 588 if( ISSET(status, CD1400_SVRR_MDMCH) ) { 589 u_char mivr = *sc->ms_svcackm; /* enter mdm service context */ 590 int port = mivr >> 4; 591 struct mtty_port *mtty; 592 int carrier; 593 u_char msvr; 594 595 /* 596 * Handle CD (LC2+1Sp = DSR) changes. 597 */ 598 mtty = &sc->ms_mtty->ms_port[port]; 599 cd = mtty->mp_cd1400; 600 msvr = cd1400_read_reg(cd, CD1400_MSVR2); 601 carrier = ISSET(msvr, cd->cd_parmode ? CD1400_MSVR2_DSR : CD1400_MSVR2_CD); 602 603 if( mtty->mp_carrier != carrier ) { 604 SET(mtty->mp_flags, MTTYF_CARRIER_CHANGED); 605 mtty->mp_carrier = carrier; 606 needsoftint = 1; 607 } 608 609 cd1400_write_reg(cd, CD1400_EOSRR, 0); /* end service context */ 610 serviced = 1; 611 } /* if(mdm_service...) */ 612 613 if( ISSET(status, CD1400_SVRR_TXRDY) ) { 614 u_char tivr = *sc->ms_svcackt; /* enter tx service context */ 615 int port = tivr >> 4; 616 617 if( tivr & (1<<3) ) { /* parallel port */ 618 struct mbpp_port *mbpp; 619 620 mbpp = &sc->ms_mbpp->ms_port[port]; 621 cd = mbpp->mp_cd1400; 622 623 if( mbpp->mp_cnt ) { 624 int count = 0; 625 626 /* fill the fifo */ 627 while (mbpp->mp_cnt && 628 count++ < CD1400_PAR_FIFO_SIZE) { 629 cd1400_write_reg(cd, CD1400_TDR, 630 *mbpp->mp_ptr); 631 mbpp->mp_ptr++; 632 mbpp->mp_cnt--; 633 } 634 } else { 635 /* 636 * fifo is empty and we got no more data 637 * to send, so shut off interrupts and 638 * signal for a wakeup, which can't be 639 * done here in case we beat mbpp_send to 640 * the tsleep call (we are running at >spltty) 641 */ 642 cd1400_write_reg(cd, CD1400_SRER, 0); 643 SET(mbpp->mp_flags, MBPPF_WAKEUP); 644 needsoftint = 1; 645 } 646 } else { /* serial port */ 647 struct mtty_port *mtty; 648 struct tty *tp; 649 650 mtty = &sc->ms_mtty->ms_port[port]; 651 cd = mtty->mp_cd1400; 652 tp = mtty->mp_tty; 653 654 if( !ISSET(mtty->mp_flags, MTTYF_STOP) ) { 655 int count = 0; 656 657 /* check if we should start/stop a break */ 658 if( ISSET(mtty->mp_flags, MTTYF_SET_BREAK) ) { 659 cd1400_write_reg(cd, CD1400_TDR, 0); 660 cd1400_write_reg(cd, CD1400_TDR, 0x81); 661 /* should we delay too? */ 662 CLR(mtty->mp_flags, MTTYF_SET_BREAK); 663 count += 2; 664 } 665 666 if( ISSET(mtty->mp_flags, MTTYF_CLR_BREAK) ) { 667 cd1400_write_reg(cd, CD1400_TDR, 0); 668 cd1400_write_reg(cd, CD1400_TDR, 0x83); 669 CLR(mtty->mp_flags, MTTYF_CLR_BREAK); 670 count += 2; 671 } 672 673 /* I don't quite fill the fifo in case the last one is a 674 * NULL which I have to double up because its the escape 675 * code for embedded transmit characters. 676 */ 677 while( mtty->mp_txc > 0 && count < CD1400_TX_FIFO_SIZE - 1 ) { 678 u_char ch; 679 680 ch = *mtty->mp_txp; 681 682 mtty->mp_txc--; 683 mtty->mp_txp++; 684 685 if( ch == 0 ) { 686 cd1400_write_reg(cd, CD1400_TDR, ch); 687 count++; 688 } 689 690 cd1400_write_reg(cd, CD1400_TDR, ch); 691 count++; 692 } 693 } 694 695 /* if we ran out of work or are requested to STOP then 696 * shut off the txrdy interrupts and signal DONE to flush 697 * out the chars we have sent. 698 */ 699 if( mtty->mp_txc == 0 || ISSET(mtty->mp_flags, MTTYF_STOP) ) { 700 register int srer; 701 702 srer = cd1400_read_reg(cd, CD1400_SRER); 703 CLR(srer, CD1400_SRER_TXRDY); 704 cd1400_write_reg(cd, CD1400_SRER, srer); 705 CLR(mtty->mp_flags, MTTYF_STOP); 706 707 SET(mtty->mp_flags, MTTYF_DONE); 708 needsoftint = 1; 709 } 710 } 711 712 cd1400_write_reg(cd, CD1400_EOSRR, 0); /* end service context */ 713 serviced = 1; 714 } /* if(tx_service...) */ 715 716 /* XXX service CD1190 interrupts too 717 for( chip = 0 ; chip < sc->ms_ncd1190 ; chip++ ) { 718 } 719 */ 720 721 if (needsoftint) 722 /* trigger the soft interrupt */ 723 softintr_schedule(sc->ms_sicookie); 724 725 return(serviced); 726 } 727 728 /* 729 * magma soft interrupt handler 730 * 731 * runs at IPL_SOFTSERIAL 732 */ 733 void 734 magma_soft(arg) 735 void *arg; 736 { 737 struct magma_softc *sc = arg; 738 struct mtty_softc *mtty = sc->ms_mtty; 739 struct mbpp_softc *mbpp = sc->ms_mbpp; 740 int port; 741 int s, flags; 742 743 if (mtty == NULL) 744 goto chkbpp; 745 746 /* 747 * check the tty ports to see what needs doing 748 */ 749 for( port = 0 ; port < mtty->ms_nports ; port++ ) { 750 struct mtty_port *mp = &mtty->ms_port[port]; 751 struct tty *tp = mp->mp_tty; 752 753 if( !ISSET(tp->t_state, TS_ISOPEN) ) 754 continue; 755 756 /* 757 * handle any received data 758 */ 759 while( mp->mp_rget != mp->mp_rput ) { 760 u_char stat; 761 int data; 762 763 stat = mp->mp_rget[0]; 764 data = mp->mp_rget[1]; 765 mp->mp_rget = ((mp->mp_rget + 2) == mp->mp_rend) 766 ? mp->mp_rbuf : (mp->mp_rget + 2); 767 768 if( stat & (CD1400_RDSR_BREAK | CD1400_RDSR_FE) ) 769 data |= TTY_FE; 770 if( stat & CD1400_RDSR_PE ) 771 data |= TTY_PE; 772 773 if( stat & CD1400_RDSR_OE ) 774 log(LOG_WARNING, "%s%x: fifo overflow\n", 775 mtty->ms_dev.dv_xname, port); 776 777 (*tp->t_linesw->l_rint)(data, tp); 778 } 779 780 s = splserial(); /* block out hard interrupt routine */ 781 flags = mp->mp_flags; 782 CLR(mp->mp_flags, MTTYF_DONE | MTTYF_CARRIER_CHANGED | MTTYF_RING_OVERFLOW); 783 splx(s); /* ok */ 784 785 if( ISSET(flags, MTTYF_CARRIER_CHANGED) ) { 786 dprintf(("%s%x: cd %s\n", mtty->ms_dev.dv_xname, 787 port, mp->mp_carrier ? "on" : "off")); 788 (*tp->t_linesw->l_modem)(tp, mp->mp_carrier); 789 } 790 791 if( ISSET(flags, MTTYF_RING_OVERFLOW) ) { 792 log(LOG_WARNING, "%s%x: ring buffer overflow\n", 793 mtty->ms_dev.dv_xname, port); 794 } 795 796 if( ISSET(flags, MTTYF_DONE) ) { 797 ndflush(&tp->t_outq, mp->mp_txp - tp->t_outq.c_cf); 798 CLR(tp->t_state, TS_BUSY); 799 (*tp->t_linesw->l_start)(tp); /* might be some more */ 800 } 801 } /* for(each mtty...) */ 802 803 804 chkbpp: 805 /* 806 * Check the bpp ports (if any) to see what needs doing 807 */ 808 if (mbpp == NULL) 809 return; 810 811 for( port = 0 ; port < mbpp->ms_nports ; port++ ) { 812 struct mbpp_port *mp = &mbpp->ms_port[port]; 813 814 if( !ISSET(mp->mp_flags, MBPPF_OPEN) ) 815 continue; 816 817 s = splserial(); 818 flags = mp->mp_flags; 819 CLR(mp->mp_flags, MBPPF_WAKEUP); 820 splx(s); 821 822 if( ISSET(flags, MBPPF_WAKEUP) ) { 823 wakeup(mp); 824 } 825 826 } /* for(each mbpp...) */ 827 } 828 829 /************************************************************************ 830 * 831 * MTTY Routines 832 * 833 * mtty_match match one mtty device 834 * mtty_attach attach mtty devices 835 * mttyopen open mtty device 836 * mttyclose close mtty device 837 * mttyread read from mtty 838 * mttywrite write to mtty 839 * mttyioctl do ioctl on mtty 840 * mttytty return tty pointer for mtty 841 * mttystop stop mtty device 842 * mtty_start start mtty device 843 * mtty_param set mtty parameters 844 * mtty_modem_control set modem control lines 845 */ 846 847 int 848 mtty_match(parent, cf, args) 849 struct device *parent; 850 struct cfdata *cf; 851 void *args; 852 { 853 struct magma_softc *sc = (struct magma_softc *)parent; 854 855 return( args == mtty_match && sc->ms_board->mb_nser && sc->ms_mtty == NULL ); 856 } 857 858 void 859 mtty_attach(parent, dev, args) 860 struct device *parent; 861 struct device *dev; 862 void *args; 863 { 864 struct magma_softc *sc = (struct magma_softc *)parent; 865 struct mtty_softc *ms = (struct mtty_softc *)dev; 866 int port, chip, chan; 867 868 sc->ms_mtty = ms; 869 dprintf((" addr %p", ms)); 870 871 for( port = 0, chip = 0, chan = 0 ; port < sc->ms_board->mb_nser ; port++ ) { 872 struct mtty_port *mp = &ms->ms_port[port]; 873 struct tty *tp; 874 875 mp->mp_cd1400 = &sc->ms_cd1400[chip]; 876 if (mp->mp_cd1400->cd_parmode && chan == 0) 877 chan = 1; /* skip channel 0 if parmode */ 878 mp->mp_channel = chan; 879 880 tp = ttymalloc(); 881 if (tp == NULL) break; 882 tty_attach(tp); 883 tp->t_oproc = mtty_start; 884 tp->t_param = mtty_param; 885 886 mp->mp_tty = tp; 887 888 mp->mp_rbuf = malloc(MTTY_RBUF_SIZE, M_DEVBUF, M_NOWAIT); 889 if (mp->mp_rbuf == NULL) break; 890 891 mp->mp_rend = mp->mp_rbuf + MTTY_RBUF_SIZE; 892 893 chan = (chan + 1) % CD1400_NO_OF_CHANNELS; 894 if (chan == 0) 895 chip++; 896 } 897 898 ms->ms_nports = port; 899 printf(": %d tty%s\n", port, port == 1 ? "" : "s"); 900 } 901 902 /* 903 * open routine. returns zero if successful, else error code 904 */ 905 int 906 mttyopen(dev, flags, mode, l) 907 dev_t dev; 908 int flags; 909 int mode; 910 struct lwp *l; 911 { 912 int card = MAGMA_CARD(dev); 913 int port = MAGMA_PORT(dev); 914 struct mtty_softc *ms; 915 struct mtty_port *mp; 916 struct tty *tp; 917 struct cd1400 *cd; 918 int error, s; 919 920 if( card >= mtty_cd.cd_ndevs || 921 (ms = mtty_cd.cd_devs[card]) == NULL || port >= ms->ms_nports ) 922 return(ENXIO); /* device not configured */ 923 924 mp = &ms->ms_port[port]; 925 tp = mp->mp_tty; 926 tp->t_dev = dev; 927 928 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 929 return (EBUSY); 930 931 s = spltty(); 932 933 if( !ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 934 935 /* set defaults */ 936 ttychars(tp); 937 tp->t_iflag = TTYDEF_IFLAG; 938 tp->t_oflag = TTYDEF_OFLAG; 939 tp->t_cflag = TTYDEF_CFLAG; 940 if( ISSET(mp->mp_openflags, TIOCFLAG_CLOCAL) ) 941 SET(tp->t_cflag, CLOCAL); 942 if( ISSET(mp->mp_openflags, TIOCFLAG_CRTSCTS) ) 943 SET(tp->t_cflag, CRTSCTS); 944 if( ISSET(mp->mp_openflags, TIOCFLAG_MDMBUF) ) 945 SET(tp->t_cflag, MDMBUF); 946 tp->t_lflag = TTYDEF_LFLAG; 947 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 948 949 /* init ring buffer */ 950 mp->mp_rput = mp->mp_rget = mp->mp_rbuf; 951 952 /* reset CD1400 channel */ 953 cd = mp->mp_cd1400; 954 cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel); 955 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET); 956 957 /* encode the port number in top half of LIVR */ 958 cd1400_write_reg(cd, CD1400_LIVR, port << 4 ); 959 960 /* sets parameters and raises DTR */ 961 (void)mtty_param(tp, &tp->t_termios); 962 963 /* set tty watermarks */ 964 ttsetwater(tp); 965 966 /* enable service requests */ 967 cd1400_write_reg(cd, CD1400_SRER, 968 CD1400_SRER_RXDATA | CD1400_SRER_MDMCH); 969 970 /* tell the tty about the carrier status */ 971 if( ISSET(mp->mp_openflags, TIOCFLAG_SOFTCAR) || 972 mp->mp_carrier ) 973 SET(tp->t_state, TS_CARR_ON); 974 else 975 CLR(tp->t_state, TS_CARR_ON); 976 } 977 splx(s); 978 979 error = ttyopen(tp, MTTY_DIALOUT(dev), ISSET(flags, O_NONBLOCK)); 980 if (error != 0) 981 goto bad; 982 983 error = (*tp->t_linesw->l_open)(dev, tp); 984 if (error != 0) 985 goto bad; 986 987 bad: 988 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 989 /* 990 * We failed to open the device, and nobody else had it opened. 991 * Clean up the state as appropriate. 992 */ 993 /* XXX - do that here */ 994 } 995 996 return (error); 997 } 998 999 /* 1000 * close routine. returns zero if successful, else error code 1001 */ 1002 int 1003 mttyclose(dev, flag, mode, l) 1004 dev_t dev; 1005 int flag; 1006 int mode; 1007 struct lwp *l; 1008 { 1009 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(dev)]; 1010 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1011 struct tty *tp = mp->mp_tty; 1012 int s; 1013 1014 (*tp->t_linesw->l_close)(tp, flag); 1015 ttyclose(tp); 1016 1017 s = spltty(); 1018 1019 /* if HUPCL is set, and the tty is no longer open 1020 * shut down the port 1021 */ 1022 if( ISSET(tp->t_cflag, HUPCL) || !ISSET(tp->t_state, TS_ISOPEN) ) { 1023 /* XXX wait until FIFO is empty before turning off the channel 1024 struct cd1400 *cd = mp->mp_cd1400; 1025 */ 1026 1027 /* drop DTR and RTS */ 1028 (void)mtty_modem_control(mp, 0, DMSET); 1029 1030 /* turn off the channel 1031 cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel); 1032 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET); 1033 */ 1034 } 1035 1036 splx(s); 1037 1038 return(0); 1039 } 1040 1041 /* 1042 * Read routine 1043 */ 1044 int 1045 mttyread(dev, uio, flags) 1046 dev_t dev; 1047 struct uio *uio; 1048 int flags; 1049 { 1050 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(dev)]; 1051 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1052 struct tty *tp = mp->mp_tty; 1053 1054 return( (*tp->t_linesw->l_read)(tp, uio, flags) ); 1055 } 1056 1057 /* 1058 * Write routine 1059 */ 1060 int 1061 mttywrite(dev, uio, flags) 1062 dev_t dev; 1063 struct uio *uio; 1064 int flags; 1065 { 1066 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(dev)]; 1067 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1068 struct tty *tp = mp->mp_tty; 1069 1070 return( (*tp->t_linesw->l_write)(tp, uio, flags) ); 1071 } 1072 1073 /* 1074 * Poll routine 1075 */ 1076 int 1077 mttypoll(dev, events, l) 1078 dev_t dev; 1079 int events; 1080 struct lwp *l; 1081 { 1082 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(dev)]; 1083 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1084 struct tty *tp = mp->mp_tty; 1085 1086 return ((*tp->t_linesw->l_poll)(tp, events, l)); 1087 } 1088 1089 /* 1090 * return tty pointer 1091 */ 1092 struct tty * 1093 mttytty(dev) 1094 dev_t dev; 1095 { 1096 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(dev)]; 1097 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1098 1099 return(mp->mp_tty); 1100 } 1101 1102 /* 1103 * ioctl routine 1104 */ 1105 int 1106 mttyioctl(dev, cmd, data, flags, l) 1107 dev_t dev; 1108 u_long cmd; 1109 void *data; 1110 int flags; 1111 struct lwp *l; 1112 { 1113 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(dev)]; 1114 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1115 struct tty *tp = mp->mp_tty; 1116 int error; 1117 1118 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flags, l); 1119 if( error != EPASSTHROUGH ) return(error); 1120 1121 error = ttioctl(tp, cmd, data, flags, l); 1122 if( error != EPASSTHROUGH ) return(error); 1123 1124 error = 0; 1125 1126 switch(cmd) { 1127 case TIOCSBRK: /* set break */ 1128 SET(mp->mp_flags, MTTYF_SET_BREAK); 1129 cd1400_enable_transmitter(mp->mp_cd1400, mp->mp_channel); 1130 break; 1131 1132 case TIOCCBRK: /* clear break */ 1133 SET(mp->mp_flags, MTTYF_CLR_BREAK); 1134 cd1400_enable_transmitter(mp->mp_cd1400, mp->mp_channel); 1135 break; 1136 1137 case TIOCSDTR: /* set DTR */ 1138 mtty_modem_control(mp, TIOCM_DTR, DMBIS); 1139 break; 1140 1141 case TIOCCDTR: /* clear DTR */ 1142 mtty_modem_control(mp, TIOCM_DTR, DMBIC); 1143 break; 1144 1145 case TIOCMSET: /* set modem lines */ 1146 mtty_modem_control(mp, *((int *)data), DMSET); 1147 break; 1148 1149 case TIOCMBIS: /* bit set modem lines */ 1150 mtty_modem_control(mp, *((int *)data), DMBIS); 1151 break; 1152 1153 case TIOCMBIC: /* bit clear modem lines */ 1154 mtty_modem_control(mp, *((int *)data), DMBIC); 1155 break; 1156 1157 case TIOCMGET: /* get modem lines */ 1158 *((int *)data) = mtty_modem_control(mp, 0, DMGET); 1159 break; 1160 1161 case TIOCGFLAGS: 1162 *((int *)data) = mp->mp_openflags; 1163 break; 1164 1165 case TIOCSFLAGS: 1166 if (kauth_authorize_device_tty(l->l_cred, 1167 KAUTH_DEVICE_TTY_PRIVSET, tp)) 1168 error = EPERM; 1169 else 1170 mp->mp_openflags = *((int *)data) & 1171 (TIOCFLAG_SOFTCAR | TIOCFLAG_CLOCAL | 1172 TIOCFLAG_CRTSCTS | TIOCFLAG_MDMBUF); 1173 break; 1174 1175 default: 1176 error = EPASSTHROUGH; 1177 } 1178 1179 return(error); 1180 } 1181 1182 /* 1183 * Stop output, e.g., for ^S or output flush. 1184 */ 1185 void 1186 mttystop(tp, flags) 1187 struct tty *tp; 1188 int flags; 1189 { 1190 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(tp->t_dev)]; 1191 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(tp->t_dev)]; 1192 int s; 1193 1194 s = spltty(); 1195 1196 if( ISSET(tp->t_state, TS_BUSY) ) { 1197 if( !ISSET(tp->t_state, TS_TTSTOP) ) 1198 SET(tp->t_state, TS_FLUSH); 1199 1200 /* 1201 * the transmit interrupt routine will disable transmit when it 1202 * notices that MTTYF_STOP has been set. 1203 */ 1204 SET(mp->mp_flags, MTTYF_STOP); 1205 } 1206 1207 splx(s); 1208 } 1209 1210 /* 1211 * Start output, after a stop. 1212 */ 1213 void 1214 mtty_start(tp) 1215 struct tty *tp; 1216 { 1217 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(tp->t_dev)]; 1218 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(tp->t_dev)]; 1219 int s; 1220 1221 s = spltty(); 1222 1223 /* we only need to do something if we are not already busy 1224 * or delaying or stopped 1225 */ 1226 if( !ISSET(tp->t_state, TS_TTSTOP | TS_TIMEOUT | TS_BUSY) ) { 1227 1228 /* if we are sleeping and output has drained below 1229 * low water mark, awaken 1230 */ 1231 if( tp->t_outq.c_cc <= tp->t_lowat ) { 1232 if( ISSET(tp->t_state, TS_ASLEEP) ) { 1233 CLR(tp->t_state, TS_ASLEEP); 1234 wakeup(&tp->t_outq); 1235 } 1236 1237 selwakeup(&tp->t_wsel); 1238 } 1239 1240 /* if something to send, start transmitting 1241 */ 1242 if( tp->t_outq.c_cc ) { 1243 mp->mp_txc = ndqb(&tp->t_outq, 0); 1244 mp->mp_txp = tp->t_outq.c_cf; 1245 SET(tp->t_state, TS_BUSY); 1246 cd1400_enable_transmitter(mp->mp_cd1400, mp->mp_channel); 1247 } 1248 } 1249 1250 splx(s); 1251 } 1252 1253 /* 1254 * set/get modem line status 1255 * 1256 * bits can be: TIOCM_DTR, TIOCM_RTS, TIOCM_CTS, TIOCM_CD, TIOCM_RI, TIOCM_DSR 1257 * 1258 * note that DTR and RTS lines are exchanged, and that DSR is 1259 * not available on the LC2+1Sp card (used as CD) 1260 * 1261 * only let them fiddle with RTS if CRTSCTS is not enabled 1262 */ 1263 int 1264 mtty_modem_control(mp, bits, howto) 1265 struct mtty_port *mp; 1266 int bits; 1267 int howto; 1268 { 1269 struct cd1400 *cd = mp->mp_cd1400; 1270 struct tty *tp = mp->mp_tty; 1271 int s, msvr; 1272 1273 s = spltty(); 1274 1275 cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel); 1276 1277 switch(howto) { 1278 case DMGET: /* get bits */ 1279 bits = 0; 1280 1281 bits |= TIOCM_LE; 1282 1283 msvr = cd1400_read_reg(cd, CD1400_MSVR1); 1284 if( msvr & CD1400_MSVR1_RTS ) bits |= TIOCM_DTR; 1285 1286 msvr = cd1400_read_reg(cd, CD1400_MSVR2); 1287 if( msvr & CD1400_MSVR2_DTR ) bits |= TIOCM_RTS; 1288 if( msvr & CD1400_MSVR2_CTS ) bits |= TIOCM_CTS; 1289 if( msvr & CD1400_MSVR2_RI ) bits |= TIOCM_RI; 1290 if( msvr & CD1400_MSVR2_DSR ) bits |= (cd->cd_parmode ? TIOCM_CD : TIOCM_DSR); 1291 if( msvr & CD1400_MSVR2_CD ) bits |= (cd->cd_parmode ? 0 : TIOCM_CD); 1292 1293 break; 1294 1295 case DMSET: /* reset bits */ 1296 if( !ISSET(tp->t_cflag, CRTSCTS) ) 1297 cd1400_write_reg(cd, CD1400_MSVR2, ((bits & TIOCM_RTS) ? CD1400_MSVR2_DTR : 0)); 1298 1299 cd1400_write_reg(cd, CD1400_MSVR1, ((bits & TIOCM_DTR) ? CD1400_MSVR1_RTS : 0)); 1300 1301 break; 1302 1303 case DMBIS: /* set bits */ 1304 if( (bits & TIOCM_RTS) && !ISSET(tp->t_cflag, CRTSCTS) ) 1305 cd1400_write_reg(cd, CD1400_MSVR2, CD1400_MSVR2_DTR); 1306 1307 if( bits & TIOCM_DTR ) 1308 cd1400_write_reg(cd, CD1400_MSVR1, CD1400_MSVR1_RTS); 1309 1310 break; 1311 1312 case DMBIC: /* clear bits */ 1313 if( (bits & TIOCM_RTS) && !ISSET(tp->t_cflag, CRTSCTS) ) 1314 cd1400_write_reg(cd, CD1400_MSVR2, 0); 1315 1316 if( bits & TIOCM_DTR ) 1317 cd1400_write_reg(cd, CD1400_MSVR1, 0); 1318 1319 break; 1320 } 1321 1322 splx(s); 1323 return(bits); 1324 } 1325 1326 /* 1327 * Set tty parameters, returns error or 0 on success 1328 */ 1329 int 1330 mtty_param(tp, t) 1331 struct tty *tp; 1332 struct termios *t; 1333 { 1334 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(tp->t_dev)]; 1335 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(tp->t_dev)]; 1336 struct cd1400 *cd = mp->mp_cd1400; 1337 int rbpr, tbpr, rcor, tcor; 1338 u_char mcor1 = 0, mcor2 = 0; 1339 int s, opt; 1340 1341 if( t->c_ospeed && cd1400_compute_baud(t->c_ospeed, cd->cd_clock, &tcor, &tbpr) ) 1342 return(EINVAL); 1343 1344 if( t->c_ispeed && cd1400_compute_baud(t->c_ispeed, cd->cd_clock, &rcor, &rbpr) ) 1345 return(EINVAL); 1346 1347 s = spltty(); 1348 1349 /* hang up the line if ospeed is zero, else raise DTR */ 1350 (void)mtty_modem_control(mp, TIOCM_DTR, (t->c_ospeed == 0 ? DMBIC : DMBIS)); 1351 1352 /* select channel, done in mtty_modem_control() */ 1353 /* cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel); */ 1354 1355 /* set transmit speed */ 1356 if( t->c_ospeed ) { 1357 cd1400_write_reg(cd, CD1400_TCOR, tcor); 1358 cd1400_write_reg(cd, CD1400_TBPR, tbpr); 1359 } 1360 1361 /* set receive speed */ 1362 if( t->c_ispeed ) { 1363 cd1400_write_reg(cd, CD1400_RCOR, rcor); 1364 cd1400_write_reg(cd, CD1400_RBPR, rbpr); 1365 } 1366 1367 /* enable transmitting and receiving on this channel */ 1368 opt = CD1400_CCR_CMDCHANCTL | CD1400_CCR_XMTEN | CD1400_CCR_RCVEN; 1369 cd1400_write_ccr(cd, opt); 1370 1371 /* set parity, data and stop bits */ 1372 opt = 0; 1373 if( ISSET(t->c_cflag, PARENB) ) 1374 opt |= (ISSET(t->c_cflag, PARODD) ? CD1400_COR1_PARODD : CD1400_COR1_PARNORMAL); 1375 1376 if( !ISSET(t->c_iflag, INPCK) ) 1377 opt |= CD1400_COR1_NOINPCK; /* no parity checking */ 1378 1379 if( ISSET(t->c_cflag, CSTOPB) ) 1380 opt |= CD1400_COR1_STOP2; 1381 1382 switch( t->c_cflag & CSIZE ) { 1383 case CS5: 1384 opt |= CD1400_COR1_CS5; 1385 break; 1386 1387 case CS6: 1388 opt |= CD1400_COR1_CS6; 1389 break; 1390 1391 case CS7: 1392 opt |= CD1400_COR1_CS7; 1393 break; 1394 1395 default: 1396 opt |= CD1400_COR1_CS8; 1397 break; 1398 } 1399 1400 cd1400_write_reg(cd, CD1400_COR1, opt); 1401 1402 /* 1403 * enable Embedded Transmit Commands (for breaks) 1404 * use the CD1400 automatic CTS flow control if CRTSCTS is set 1405 */ 1406 opt = CD1400_COR2_ETC; 1407 if( ISSET(t->c_cflag, CRTSCTS) ) opt |= CD1400_COR2_CCTS_OFLOW; 1408 cd1400_write_reg(cd, CD1400_COR2, opt); 1409 1410 cd1400_write_reg(cd, CD1400_COR3, MTTY_RX_FIFO_THRESHOLD); 1411 1412 cd1400_write_ccr(cd, CD1400_CCR_CMDCORCHG | CD1400_CCR_COR1 | CD1400_CCR_COR2 | CD1400_CCR_COR3); 1413 1414 cd1400_write_reg(cd, CD1400_COR4, CD1400_COR4_PFO_EXCEPTION); 1415 cd1400_write_reg(cd, CD1400_COR5, 0); 1416 1417 /* 1418 * if automatic RTS handshaking enabled, set DTR threshold 1419 * (RTS and DTR lines are switched, CD1400 thinks its DTR) 1420 */ 1421 if( ISSET(t->c_cflag, CRTSCTS) ) 1422 mcor1 = MTTY_RX_DTR_THRESHOLD; 1423 1424 /* set up `carrier detect' interrupts */ 1425 if( cd->cd_parmode ) { 1426 SET(mcor1, CD1400_MCOR1_DSRzd); 1427 SET(mcor2, CD1400_MCOR2_DSRod); 1428 } else { 1429 SET(mcor1, CD1400_MCOR1_CDzd); 1430 SET(mcor2, CD1400_MCOR2_CDod); 1431 } 1432 1433 cd1400_write_reg(cd, CD1400_MCOR1, mcor1); 1434 cd1400_write_reg(cd, CD1400_MCOR2, mcor2); 1435 1436 /* receive timeout 2ms */ 1437 cd1400_write_reg(cd, CD1400_RTPR, 2); 1438 1439 splx(s); 1440 return(0); 1441 } 1442 1443 /************************************************************************ 1444 * 1445 * MBPP Routines 1446 * 1447 * mbpp_match match one mbpp device 1448 * mbpp_attach attach mbpp devices 1449 * mbppopen open mbpp device 1450 * mbppclose close mbpp device 1451 * mbppioctl do ioctl on mbpp 1452 * mbpp_rw general rw routine 1453 * mbpp_timeout rw timeout 1454 * mbpp_start rw start after delay 1455 * mbpp_send send data 1456 * mbpp_recv recv data 1457 */ 1458 1459 int 1460 mbpp_match(parent, cf, args) 1461 struct device *parent; 1462 struct cfdata *cf; 1463 void *args; 1464 { 1465 struct magma_softc *sc = (struct magma_softc *)parent; 1466 1467 return( args == mbpp_match && sc->ms_board->mb_npar && sc->ms_mbpp == NULL ); 1468 } 1469 1470 void 1471 mbpp_attach(parent, dev, args) 1472 struct device *parent; 1473 struct device *dev; 1474 void *args; 1475 { 1476 struct magma_softc *sc = (struct magma_softc *)parent; 1477 struct mbpp_softc *ms = (struct mbpp_softc *)dev; 1478 struct mbpp_port *mp; 1479 int port; 1480 1481 sc->ms_mbpp = ms; 1482 dprintf((" addr %p", ms)); 1483 1484 for( port = 0 ; port < sc->ms_board->mb_npar ; port++ ) { 1485 mp = &ms->ms_port[port]; 1486 1487 callout_init(&mp->mp_timeout_ch, 0); 1488 callout_init(&mp->mp_start_ch, 0); 1489 1490 if( sc->ms_ncd1190 ) 1491 mp->mp_cd1190 = &sc->ms_cd1190[port]; 1492 else 1493 mp->mp_cd1400 = &sc->ms_cd1400[0]; 1494 } 1495 1496 ms->ms_nports = port; 1497 printf(": %d port%s\n", port, port == 1 ? "" : "s"); 1498 } 1499 1500 /* 1501 * open routine. returns zero if successful, else error code 1502 */ 1503 int 1504 mbppopen(dev, flags, mode, l) 1505 dev_t dev; 1506 int flags; 1507 int mode; 1508 struct lwp *l; 1509 { 1510 int card = MAGMA_CARD(dev); 1511 int port = MAGMA_PORT(dev); 1512 struct mbpp_softc *ms; 1513 struct mbpp_port *mp; 1514 int s; 1515 1516 if( card >= mbpp_cd.cd_ndevs || 1517 (ms = mbpp_cd.cd_devs[card]) == NULL || port >= ms->ms_nports ) 1518 return(ENXIO); 1519 1520 mp = &ms->ms_port[port]; 1521 1522 s = spltty(); 1523 if( ISSET(mp->mp_flags, MBPPF_OPEN) ) { 1524 splx(s); 1525 return(EBUSY); 1526 } 1527 SET(mp->mp_flags, MBPPF_OPEN); 1528 splx(s); 1529 1530 /* set defaults */ 1531 mp->mp_burst = MBPP_BURST; 1532 mp->mp_timeout = mbpp_mstohz(MBPP_TIMEOUT); 1533 mp->mp_delay = mbpp_mstohz(MBPP_DELAY); 1534 1535 /* init chips */ 1536 if( mp->mp_cd1400 ) { /* CD1400 */ 1537 struct cd1400 *cd = mp->mp_cd1400; 1538 1539 /* set up CD1400 channel */ 1540 s = spltty(); 1541 cd1400_write_reg(cd, CD1400_CAR, 0); 1542 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET); 1543 cd1400_write_reg(cd, CD1400_LIVR, (1<<3)); 1544 splx(s); 1545 } else { /* CD1190 */ 1546 mp->mp_flags = 0; 1547 return (ENXIO); 1548 } 1549 1550 return (0); 1551 } 1552 1553 /* 1554 * close routine. returns zero if successful, else error code 1555 */ 1556 int 1557 mbppclose(dev, flag, mode, l) 1558 dev_t dev; 1559 int flag; 1560 int mode; 1561 struct lwp *l; 1562 { 1563 struct mbpp_softc *ms = mbpp_cd.cd_devs[MAGMA_CARD(dev)]; 1564 struct mbpp_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1565 1566 mp->mp_flags = 0; 1567 return(0); 1568 } 1569 1570 /* 1571 * ioctl routine 1572 */ 1573 int 1574 mbppioctl(dev, cmd, data, flags, l) 1575 dev_t dev; 1576 u_long cmd; 1577 void *data; 1578 int flags; 1579 struct lwp *l; 1580 { 1581 struct mbpp_softc *ms = mbpp_cd.cd_devs[MAGMA_CARD(dev)]; 1582 struct mbpp_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1583 struct mbpp_param *bp; 1584 int error = 0; 1585 int s; 1586 1587 switch(cmd) { 1588 case MBPPIOCSPARAM: 1589 bp = (struct mbpp_param *)data; 1590 if( bp->bp_burst < MBPP_BURST_MIN || bp->bp_burst > MBPP_BURST_MAX || 1591 bp->bp_delay < MBPP_DELAY_MIN || bp->bp_delay > MBPP_DELAY_MIN ) { 1592 error = EINVAL; 1593 } else { 1594 mp->mp_burst = bp->bp_burst; 1595 mp->mp_timeout = mbpp_mstohz(bp->bp_timeout); 1596 mp->mp_delay = mbpp_mstohz(bp->bp_delay); 1597 } 1598 break; 1599 case MBPPIOCGPARAM: 1600 bp = (struct mbpp_param *)data; 1601 bp->bp_burst = mp->mp_burst; 1602 bp->bp_timeout = mbpp_hztoms(mp->mp_timeout); 1603 bp->bp_delay = mbpp_hztoms(mp->mp_delay); 1604 break; 1605 case MBPPIOCGSTAT: 1606 /* XXX make this more generic */ 1607 s = spltty(); 1608 cd1400_write_reg(mp->mp_cd1400, CD1400_CAR, 0); 1609 *(int *)data = cd1400_read_reg(mp->mp_cd1400, CD1400_PSVR); 1610 splx(s); 1611 break; 1612 default: 1613 error = ENOTTY; 1614 } 1615 1616 return(error); 1617 } 1618 1619 int 1620 mbpp_rw(dev, uio, flag) 1621 dev_t dev; 1622 struct uio *uio; 1623 int flag; 1624 { 1625 int card = MAGMA_CARD(dev); 1626 int port = MAGMA_PORT(dev); 1627 struct mbpp_softc *ms = mbpp_cd.cd_devs[card]; 1628 struct mbpp_port *mp = &ms->ms_port[port]; 1629 char *buffer, *ptr; 1630 int buflen, cnt, len; 1631 int s, error = 0; 1632 int gotdata = 0; 1633 1634 if( uio->uio_resid == 0 ) 1635 return(0); 1636 1637 buflen = min(uio->uio_resid, mp->mp_burst); 1638 buffer = malloc(buflen, M_DEVBUF, M_WAITOK); 1639 if( buffer == NULL ) 1640 return(ENOMEM); 1641 1642 SET(mp->mp_flags, MBPPF_UIO); 1643 1644 /* 1645 * start timeout, if needed 1646 */ 1647 if( mp->mp_timeout > 0 ) { 1648 SET(mp->mp_flags, MBPPF_TIMEOUT); 1649 callout_reset(&mp->mp_timeout_ch, mp->mp_timeout, 1650 mbpp_timeout, mp); 1651 } 1652 1653 len = cnt = 0; 1654 while( uio->uio_resid > 0 ) { 1655 len = min(buflen, uio->uio_resid); 1656 ptr = buffer; 1657 1658 if( uio->uio_rw == UIO_WRITE ) { 1659 error = uiomove(ptr, len, uio); 1660 if( error ) break; 1661 } 1662 again: /* goto bad */ 1663 /* timed out? */ 1664 if( !ISSET(mp->mp_flags, MBPPF_UIO) ) 1665 break; 1666 1667 /* 1668 * perform the operation 1669 */ 1670 if( uio->uio_rw == UIO_WRITE ) { 1671 cnt = mbpp_send(mp, ptr, len); 1672 } else { 1673 cnt = mbpp_recv(mp, ptr, len); 1674 } 1675 1676 if( uio->uio_rw == UIO_READ ) { 1677 if( cnt ) { 1678 error = uiomove(ptr, cnt, uio); 1679 if( error ) break; 1680 gotdata++; 1681 } 1682 else if( gotdata ) /* consider us done */ 1683 break; 1684 } 1685 1686 /* timed out? */ 1687 if( !ISSET(mp->mp_flags, MBPPF_UIO) ) 1688 break; 1689 1690 /* 1691 * poll delay? 1692 */ 1693 if( mp->mp_delay > 0 ) { 1694 s = splsoftclock(); 1695 SET(mp->mp_flags, MBPPF_DELAY); 1696 callout_reset(&mp->mp_start_ch, mp->mp_delay, 1697 mbpp_start, mp); 1698 error = tsleep(mp, PCATCH | PZERO, "mbppdelay", 0); 1699 splx(s); 1700 if( error ) break; 1701 } 1702 1703 /* 1704 * don't call uiomove again until we used all the data we grabbed 1705 */ 1706 if( uio->uio_rw == UIO_WRITE && cnt != len ) { 1707 ptr += cnt; 1708 len -= cnt; 1709 cnt = 0; 1710 goto again; 1711 } 1712 } 1713 1714 /* 1715 * clear timeouts 1716 */ 1717 s = splsoftclock(); 1718 if( ISSET(mp->mp_flags, MBPPF_TIMEOUT) ) { 1719 callout_stop(&mp->mp_timeout_ch); 1720 CLR(mp->mp_flags, MBPPF_TIMEOUT); 1721 } 1722 if( ISSET(mp->mp_flags, MBPPF_DELAY) ) { 1723 callout_stop(&mp->mp_start_ch); 1724 CLR(mp->mp_flags, MBPPF_DELAY); 1725 } 1726 splx(s); 1727 1728 /* 1729 * adjust for those chars that we uiomoved but never actually wrote 1730 */ 1731 if( uio->uio_rw == UIO_WRITE && cnt != len ) { 1732 uio->uio_resid += (len - cnt); 1733 } 1734 1735 free(buffer, M_DEVBUF); 1736 return(error); 1737 } 1738 1739 void 1740 mbpp_timeout(arg) 1741 void *arg; 1742 { 1743 struct mbpp_port *mp = arg; 1744 1745 CLR(mp->mp_flags, MBPPF_UIO | MBPPF_TIMEOUT); 1746 wakeup(mp); 1747 } 1748 1749 void 1750 mbpp_start(arg) 1751 void *arg; 1752 { 1753 struct mbpp_port *mp = arg; 1754 1755 CLR(mp->mp_flags, MBPPF_DELAY); 1756 wakeup(mp); 1757 } 1758 1759 int 1760 mbpp_send(mp, ptr, len) 1761 struct mbpp_port *mp; 1762 void *ptr; 1763 int len; 1764 { 1765 int s; 1766 struct cd1400 *cd = mp->mp_cd1400; 1767 1768 /* set up io information */ 1769 mp->mp_ptr = ptr; 1770 mp->mp_cnt = len; 1771 1772 /* start transmitting */ 1773 s = spltty(); 1774 if( cd ) { 1775 cd1400_write_reg(cd, CD1400_CAR, 0); 1776 1777 /* output strobe width ~1microsecond */ 1778 cd1400_write_reg(cd, CD1400_TBPR, 10); 1779 1780 /* enable channel */ 1781 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_XMTEN); 1782 cd1400_write_reg(cd, CD1400_SRER, CD1400_SRER_TXRDY); 1783 } 1784 1785 /* ZZzzz... */ 1786 tsleep(mp, PCATCH | PZERO, "mbpp_send", 0); 1787 1788 /* stop transmitting */ 1789 if( cd ) { 1790 cd1400_write_reg(cd, CD1400_CAR, 0); 1791 1792 /* disable transmitter */ 1793 cd1400_write_reg(cd, CD1400_SRER, 0); 1794 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_XMTDIS); 1795 1796 /* flush fifo */ 1797 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET | CD1400_CCR_FTF); 1798 } 1799 splx(s); 1800 1801 /* return number of chars sent */ 1802 return(len - mp->mp_cnt); 1803 } 1804 1805 int 1806 mbpp_recv(mp, ptr, len) 1807 struct mbpp_port *mp; 1808 void *ptr; 1809 int len; 1810 { 1811 int s; 1812 struct cd1400 *cd = mp->mp_cd1400; 1813 1814 /* set up io information */ 1815 mp->mp_ptr = ptr; 1816 mp->mp_cnt = len; 1817 1818 /* start receiving */ 1819 s = spltty(); 1820 if( cd ) { 1821 int rcor, rbpr; 1822 1823 cd1400_write_reg(cd, CD1400_CAR, 0); 1824 1825 /* input strobe at 100kbaud (10microseconds) */ 1826 cd1400_compute_baud(100000, cd->cd_clock, &rcor, &rbpr); 1827 cd1400_write_reg(cd, CD1400_RCOR, rcor); 1828 cd1400_write_reg(cd, CD1400_RBPR, rbpr); 1829 1830 /* rx threshold */ 1831 cd1400_write_reg(cd, CD1400_COR3, MBPP_RX_FIFO_THRESHOLD); 1832 cd1400_write_ccr(cd, CD1400_CCR_CMDCORCHG | CD1400_CCR_COR3); 1833 1834 /* enable channel */ 1835 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_RCVEN); 1836 cd1400_write_reg(cd, CD1400_SRER, CD1400_SRER_RXDATA); 1837 } 1838 1839 /* ZZzzz... */ 1840 tsleep(mp, PCATCH | PZERO, "mbpp_recv", 0); 1841 1842 /* stop receiving */ 1843 if( cd ) { 1844 cd1400_write_reg(cd, CD1400_CAR, 0); 1845 1846 /* disable receiving */ 1847 cd1400_write_reg(cd, CD1400_SRER, 0); 1848 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_RCVDIS); 1849 } 1850 splx(s); 1851 1852 /* return number of chars received */ 1853 return(len - mp->mp_cnt); 1854 } 1855 1856 int 1857 mbpp_hztoms(h) 1858 int h; 1859 { 1860 int m = h; 1861 1862 if( m > 0 ) 1863 m = m * 1000 / hz; 1864 return(m); 1865 } 1866 1867 int 1868 mbpp_mstohz(m) 1869 int m; 1870 { 1871 int h = m; 1872 1873 if( h > 0 ) { 1874 h = h * hz / 1000; 1875 if( h == 0 ) 1876 h = 1000 / hz; 1877 } 1878 return(h); 1879 } 1880 1881 #endif /* NMAGMA */ 1882
Indexes created Tue Sep 23 02:09:52 GMT 2025