magma.c revision 1.45.14.1
1 /* $NetBSD: magma.c,v 1.45.14.1 2008/06/02 13:23:50 mjf Exp $ */ 2 /* 3 * magma.c 4 * 5 * Copyright (c) 1998 Iain Hibbert 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Iain Hibbert 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35 /* 36 * Driver for Magma SBus Serial/Parallel cards using the Cirrus Logic 37 * CD1400 & CD1190 chips 38 */ 39 40 #include <sys/cdefs.h> 41 __KERNEL_RCSID(0, "$NetBSD: magma.c,v 1.45.14.1 2008/06/02 13:23:50 mjf Exp $"); 42 43 #if 0 44 #define MAGMA_DEBUG 45 #endif 46 47 #include "magma.h" 48 #if NMAGMA > 0 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/proc.h> 53 #include <sys/device.h> 54 #include <sys/file.h> 55 #include <sys/ioctl.h> 56 #include <sys/malloc.h> 57 #include <sys/tty.h> 58 #include <sys/time.h> 59 #include <sys/kernel.h> 60 #include <sys/syslog.h> 61 #include <sys/conf.h> 62 #include <sys/errno.h> 63 #include <sys/kauth.h> 64 #include <sys/intr.h> 65 66 #include <sys/bus.h> 67 #include <machine/autoconf.h> 68 69 #include <dev/sbus/sbusvar.h> 70 71 #include <dev/ic/cd1400reg.h> 72 #include <dev/ic/cd1190reg.h> 73 74 #include <dev/sbus/mbppio.h> 75 #include <dev/sbus/magmareg.h> 76 77 /* supported cards 78 * 79 * The table below lists the cards that this driver is likely to 80 * be able to support. 81 * 82 * Cards with parallel ports: except for the LC2+1Sp, they all use 83 * the CD1190 chip which I know nothing about. I've tried to leave 84 * hooks for it so it shouldn't be too hard to add support later. 85 * (I think somebody is working on this separately) 86 * 87 * Thanks to Bruce at Magma for telling me the hardware offsets. 88 */ 89 static struct magma_board_info supported_cards[] = { 90 { 91 "MAGMA_Sp", "MAGMA,4_Sp", "Magma 4 Sp", 4, 0, 92 1, 0xa000, 0xc000, 0xe000, { 0x8000, 0, 0, 0 }, 93 0, { 0, 0 } 94 }, 95 { 96 "MAGMA_Sp", "MAGMA,8_Sp", "Magma 8 Sp", 8, 0, 97 2, 0xa000, 0xc000, 0xe000, { 0x4000, 0x6000, 0, 0 }, 98 0, { 0, 0 } 99 }, 100 { 101 "MAGMA_Sp", "MAGMA,_8HS_Sp", "Magma Fast 8 Sp", 8, 0, 102 2, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0, 0 }, 103 0, { 0, 0 } 104 }, 105 { 106 "MAGMA_Sp", "MAGMA,_8SP_422", "Magma 8 Sp - 422", 8, 0, 107 2, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0, 0 }, 108 0, { 0, 0 } 109 }, 110 { 111 "MAGMA_Sp", "MAGMA,12_Sp", "Magma 12 Sp", 12, 0, 112 3, 0xa000, 0xc000, 0xe000, { 0x2000, 0x4000, 0x6000, 0 }, 113 0, { 0, 0 } 114 }, 115 { 116 "MAGMA_Sp", "MAGMA,16_Sp", "Magma 16 Sp", 16, 0, 117 4, 0xd000, 0xe000, 0xf000, { 0x8000, 0x9000, 0xa000, 0xb000 }, 118 0, { 0, 0 } 119 }, 120 { 121 "MAGMA_Sp", "MAGMA,16_Sp_2", "Magma 16 Sp", 16, 0, 122 4, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0xc000, 0xe000 }, 123 0, { 0, 0 } 124 }, 125 { 126 "MAGMA_Sp", "MAGMA,16HS_Sp", "Magma Fast 16 Sp", 16, 0, 127 4, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0xc000, 0xe000 }, 128 0, { 0, 0 } 129 }, 130 { 131 "MAGMA_Sp", "MAGMA,21_Sp", "Magma LC 2+1 Sp", 2, 1, 132 1, 0xa000, 0xc000, 0xe000, { 0x8000, 0, 0, 0 }, 133 0, { 0, 0 } 134 }, 135 { 136 "MAGMA_Sp", "MAGMA,21HS_Sp", "Magma 2+1 Sp", 2, 1, 137 1, 0xa000, 0xc000, 0xe000, { 0x4000, 0, 0, 0 }, 138 1, { 0x6000, 0 } 139 }, 140 { 141 "MAGMA_Sp", "MAGMA,41_Sp", "Magma 4+1 Sp", 4, 1, 142 1, 0xa000, 0xc000, 0xe000, { 0x4000, 0, 0, 0 }, 143 1, { 0x6000, 0 } 144 }, 145 { 146 "MAGMA_Sp", "MAGMA,82_Sp", "Magma 8+2 Sp", 8, 2, 147 2, 0xd000, 0xe000, 0xf000, { 0x8000, 0x9000, 0, 0 }, 148 2, { 0xa000, 0xb000 } 149 }, 150 { 151 "MAGMA_Sp", "MAGMA,P1_Sp", "Magma P1 Sp", 0, 1, 152 0, 0, 0, 0, { 0, 0, 0, 0 }, 153 1, { 0x8000, 0 } 154 }, 155 { 156 "MAGMA_Sp", "MAGMA,P2_Sp", "Magma P2 Sp", 0, 2, 157 0, 0, 0, 0, { 0, 0, 0, 0 }, 158 2, { 0x4000, 0x8000 } 159 }, 160 { 161 "MAGMA 2+1HS Sp", "", "Magma 2+1HS Sp", 2, 0, 162 1, 0xa000, 0xc000, 0xe000, { 0x4000, 0, 0, 0 }, 163 1, { 0x8000, 0 } 164 }, 165 { 166 NULL, NULL, NULL, 0, 0, 167 0, 0, 0, 0, { 0, 0, 0, 0 }, 168 0, { 0, 0 } 169 } 170 }; 171 172 /************************************************************************ 173 * 174 * Autoconfig Stuff 175 */ 176 177 CFATTACH_DECL(magma, sizeof(struct magma_softc), 178 magma_match, magma_attach, NULL, NULL); 179 180 CFATTACH_DECL(mtty, sizeof(struct mtty_softc), 181 mtty_match, mtty_attach, NULL, NULL); 182 183 CFATTACH_DECL(mbpp, sizeof(struct mbpp_softc), 184 mbpp_match, mbpp_attach, NULL, NULL); 185 186 extern struct cfdriver mtty_cd; 187 extern struct cfdriver mbpp_cd; 188 189 dev_type_open(mttyopen); 190 dev_type_close(mttyclose); 191 dev_type_read(mttyread); 192 dev_type_write(mttywrite); 193 dev_type_ioctl(mttyioctl); 194 dev_type_stop(mttystop); 195 dev_type_tty(mttytty); 196 dev_type_poll(mttypoll); 197 198 const struct cdevsw mtty_cdevsw = { 199 mttyopen, mttyclose, mttyread, mttywrite, mttyioctl, 200 mttystop, mttytty, mttypoll, nommap, ttykqfilter, D_TTY 201 }; 202 203 dev_type_open(mbppopen); 204 dev_type_close(mbppclose); 205 dev_type_read(mbpp_rw); 206 dev_type_ioctl(mbppioctl); 207 208 const struct cdevsw mbpp_cdevsw = { 209 mbppopen, mbppclose, mbpp_rw, mbpp_rw, mbppioctl, 210 nostop, notty, nopoll, nommap, nokqfilter, D_OTHER 211 }; 212 213 /************************************************************************ 214 * 215 * CD1400 Routines 216 * 217 * cd1400_compute_baud calculate COR/BPR register values 218 * cd1400_write_ccr write a value to CD1400 ccr 219 * cd1400_read_reg read from a CD1400 register 220 * cd1400_write_reg write to a CD1400 register 221 * cd1400_enable_transmitter enable transmitting on CD1400 channel 222 */ 223 224 /* 225 * compute the bpr/cor pair for any baud rate 226 * returns 0 for success, 1 for failure 227 */ 228 int 229 cd1400_compute_baud(speed, clock, cor, bpr) 230 speed_t speed; 231 int clock; 232 int *cor, *bpr; 233 { 234 int c, co, br; 235 236 if( speed < 50 || speed > 150000 ) 237 return(1); 238 239 for( c = 0, co = 8 ; co <= 2048 ; co <<= 2, c++ ) { 240 br = ((clock * 1000000) + (co * speed) / 2) / (co * speed); 241 if( br < 0x100 ) { 242 *bpr = br; 243 *cor = c; 244 return(0); 245 } 246 } 247 248 return(1); 249 } 250 251 /* 252 * Write a CD1400 channel command, should have a timeout? 253 */ 254 inline void 255 cd1400_write_ccr(cd, cmd) 256 struct cd1400 *cd; 257 u_char cmd; 258 { 259 while( cd1400_read_reg(cd, CD1400_CCR) ) 260 ; 261 262 cd1400_write_reg(cd, CD1400_CCR, cmd); 263 } 264 265 /* 266 * read a value from a cd1400 register 267 */ 268 inline u_char 269 cd1400_read_reg(cd, reg) 270 struct cd1400 *cd; 271 int reg; 272 { 273 return(cd->cd_reg[reg]); 274 } 275 276 /* 277 * write a value to a cd1400 register 278 */ 279 inline void 280 cd1400_write_reg(cd, reg, value) 281 struct cd1400 *cd; 282 int reg; 283 u_char value; 284 { 285 cd->cd_reg[reg] = value; 286 } 287 288 /* 289 * enable transmit service requests for cd1400 channel 290 */ 291 void 292 cd1400_enable_transmitter(cd, channel) 293 struct cd1400 *cd; 294 int channel; 295 { 296 int s, srer; 297 298 s = spltty(); 299 cd1400_write_reg(cd, CD1400_CAR, channel); 300 srer = cd1400_read_reg(cd, CD1400_SRER); 301 SET(srer, CD1400_SRER_TXRDY); 302 cd1400_write_reg(cd, CD1400_SRER, srer); 303 splx(s); 304 } 305 306 /************************************************************************ 307 * 308 * CD1190 Routines 309 */ 310 311 /* well, there are none yet */ 312 313 /************************************************************************ 314 * 315 * Magma Routines 316 * 317 * magma_match reports if we have a magma board available 318 * magma_attach attaches magma boards to the sbus 319 * magma_hard hardware level interrupt routine 320 * magma_soft software level interrupt routine 321 */ 322 323 int 324 magma_match(parent, cf, aux) 325 struct device *parent; 326 struct cfdata *cf; 327 void *aux; 328 { 329 struct sbus_attach_args *sa = aux; 330 struct magma_board_info *card; 331 332 /* See if we support this device */ 333 for (card = supported_cards; ; card++) { 334 if (card->mb_sbusname == NULL) 335 /* End of table: no match */ 336 return (0); 337 if (strcmp(sa->sa_name, card->mb_sbusname) == 0) 338 break; 339 } 340 341 dprintf(("magma: matched `%s'\n", sa->sa_name)); 342 dprintf(("magma: magma_prom `%s'\n", 343 prom_getpropstring(sa->sa_node, "magma_prom"))); 344 dprintf(("magma: intlevels `%s'\n", 345 prom_getpropstring(sa->sa_node, "intlevels"))); 346 dprintf(("magma: chiprev `%s'\n", 347 prom_getpropstring(sa->sa_node, "chiprev"))); 348 dprintf(("magma: clock `%s'\n", 349 prom_getpropstring(sa->sa_node, "clock"))); 350 351 return (1); 352 } 353 354 void 355 magma_attach(parent, self, aux) 356 struct device *parent; 357 struct device *self; 358 void *aux; 359 { 360 struct sbus_attach_args *sa = aux; 361 struct magma_softc *sc = (struct magma_softc *)self; 362 struct magma_board_info *card; 363 bus_space_handle_t bh; 364 char *magma_prom, *clockstr; 365 int cd_clock; 366 int node, chip; 367 368 node = sa->sa_node; 369 370 /* 371 * Find the card model. 372 * Older models all have sbus node name `MAGMA_Sp' (see 373 * `supported_cards[]' above), and must be distinguished 374 * by the `magma_prom' property. 375 */ 376 magma_prom = prom_getpropstring(node, "magma_prom"); 377 378 for (card = supported_cards; card->mb_name != NULL; card++) { 379 if (strcmp(sa->sa_name, card->mb_sbusname) != 0) 380 /* Sbus node name doesn't match */ 381 continue; 382 if (strcmp(magma_prom, card->mb_name) == 0) 383 /* Model name match */ 384 break; 385 } 386 387 if( card->mb_name == NULL ) { 388 printf(": %s (unsupported)\n", magma_prom); 389 return; 390 } 391 392 dprintf((" addr %p", sc)); 393 printf(": %s\n", card->mb_realname); 394 395 sc->ms_board = card; 396 sc->ms_ncd1400 = card->mb_ncd1400; 397 sc->ms_ncd1190 = card->mb_ncd1190; 398 399 if (sbus_bus_map(sa->sa_bustag, 400 sa->sa_slot, sa->sa_offset, sa->sa_size, 401 BUS_SPACE_MAP_LINEAR, &bh) != 0) { 402 aprint_error("%s @ sbus: cannot map registers\n", 403 device_xname(self)); 404 return; 405 } 406 407 /* the SVCACK* lines are daisychained */ 408 sc->ms_svcackr = (char *)bus_space_vaddr(sa->sa_bustag, bh) 409 + card->mb_svcackr; 410 sc->ms_svcackt = (char *)bus_space_vaddr(sa->sa_bustag, bh) 411 + card->mb_svcackt; 412 sc->ms_svcackm = (char *)bus_space_vaddr(sa->sa_bustag, bh) 413 + card->mb_svcackm; 414 415 /* 416 * Find the clock speed; it's the same for all CD1400 chips 417 * on the board. 418 */ 419 clockstr = prom_getpropstring(node, "clock"); 420 if (*clockstr == '\0') 421 /* Default to 25MHz */ 422 cd_clock = 25; 423 else { 424 cd_clock = 0; 425 while (*clockstr != '\0') 426 cd_clock = (cd_clock * 10) + (*clockstr++ - '0'); 427 } 428 429 /* init the cd1400 chips */ 430 for( chip = 0 ; chip < card->mb_ncd1400 ; chip++ ) { 431 struct cd1400 *cd = &sc->ms_cd1400[chip]; 432 433 cd->cd_clock = cd_clock; 434 cd->cd_reg = (char *)bus_space_vaddr(sa->sa_bustag, bh) + 435 card->mb_cd1400[chip]; 436 437 /* prom_getpropstring(node, "chiprev"); */ 438 /* seemingly the Magma drivers just ignore the propstring */ 439 cd->cd_chiprev = cd1400_read_reg(cd, CD1400_GFRCR); 440 441 dprintf(("%s attach CD1400 %d addr %p rev %x clock %dMHz\n", 442 device_xname(&sc->ms_dev), chip, 443 cd->cd_reg, cd->cd_chiprev, cd->cd_clock)); 444 445 /* clear GFRCR */ 446 cd1400_write_reg(cd, CD1400_GFRCR, 0x00); 447 448 /* reset whole chip */ 449 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET | CD1400_CCR_FULLRESET); 450 451 /* wait for revision code to be restored */ 452 while( cd1400_read_reg(cd, CD1400_GFRCR) != cd->cd_chiprev ) 453 ; 454 455 /* set the Prescaler Period Register to tick at 1ms */ 456 cd1400_write_reg(cd, CD1400_PPR, 457 ((cd->cd_clock * 1000000 / CD1400_PPR_PRESCALER + 500) / 1000)); 458 459 /* The LC2+1Sp card is the only card that doesn't have 460 * a CD1190 for the parallel port, but uses channel 0 of 461 * the CD1400, so we make a note of it for later and set up 462 * the CD1400 for parallel mode operation. 463 */ 464 if( card->mb_npar && card->mb_ncd1190 == 0 ) { 465 cd1400_write_reg(cd, CD1400_GCR, CD1400_GCR_PARALLEL); 466 cd->cd_parmode = 1; 467 } 468 } 469 470 /* init the cd1190 chips */ 471 for( chip = 0 ; chip < card->mb_ncd1190 ; chip++ ) { 472 struct cd1190 *cd = &sc->ms_cd1190[chip]; 473 474 cd->cd_reg = (char *)bus_space_vaddr(sa->sa_bustag, bh) + 475 card->mb_cd1190[chip]; 476 477 /* XXX don't know anything about these chips yet */ 478 printf("%s: CD1190 %d addr %p (unsupported)\n", 479 device_xname(self), chip, cd->cd_reg); 480 } 481 482 sbus_establish(&sc->ms_sd, &sc->ms_dev); 483 484 /* configure the children */ 485 (void)config_found(self, mtty_match, NULL); 486 (void)config_found(self, mbpp_match, NULL); 487 488 /* 489 * Establish the interrupt handlers. 490 */ 491 if (sa->sa_nintr == 0) 492 return; /* No interrupts to service!? */ 493 494 (void)bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_SERIAL, 495 magma_hard, sc); 496 sc->ms_sicookie = softint_establish(SOFTINT_SERIAL, magma_soft, sc); 497 if (sc->ms_sicookie == NULL) { 498 aprint_normal("\n"); 499 aprint_error_dev(&sc->ms_dev, "cannot establish soft int handler\n"); 500 return; 501 } 502 evcnt_attach_dynamic(&sc->ms_intrcnt, EVCNT_TYPE_INTR, NULL, 503 device_xname(&sc->ms_dev), "intr"); 504 } 505 506 /* 507 * hard interrupt routine 508 * 509 * returns 1 if it handled it, otherwise 0 510 * 511 * runs at IPL_SERIAL 512 */ 513 int 514 magma_hard(arg) 515 void *arg; 516 { 517 struct magma_softc *sc = arg; 518 struct cd1400 *cd; 519 int chip, status = 0; 520 int serviced = 0; 521 int needsoftint = 0; 522 523 /* 524 * check status of all the CD1400 chips 525 */ 526 for( chip = 0 ; chip < sc->ms_ncd1400 ; chip++ ) 527 status |= cd1400_read_reg(&sc->ms_cd1400[chip], CD1400_SVRR); 528 529 if( ISSET(status, CD1400_SVRR_RXRDY) ) { 530 u_char rivr = *sc->ms_svcackr; /* enter rx service context */ 531 int port = rivr >> 4; 532 533 if( rivr & (1<<3) ) { /* parallel port */ 534 struct mbpp_port *mbpp; 535 int n_chars; 536 537 mbpp = &sc->ms_mbpp->ms_port[port]; 538 cd = mbpp->mp_cd1400; 539 540 /* don't think we have to handle exceptions */ 541 n_chars = cd1400_read_reg(cd, CD1400_RDCR); 542 while (n_chars--) { 543 if( mbpp->mp_cnt == 0 ) { 544 SET(mbpp->mp_flags, MBPPF_WAKEUP); 545 needsoftint = 1; 546 break; 547 } 548 *mbpp->mp_ptr = cd1400_read_reg(cd,CD1400_RDSR); 549 mbpp->mp_ptr++; 550 mbpp->mp_cnt--; 551 } 552 } else { /* serial port */ 553 struct mtty_port *mtty; 554 u_char *ptr, n_chars, line_stat; 555 556 mtty = &sc->ms_mtty->ms_port[port]; 557 cd = mtty->mp_cd1400; 558 559 if( ISSET(rivr, CD1400_RIVR_EXCEPTION) ) { 560 line_stat = cd1400_read_reg(cd, CD1400_RDSR); 561 n_chars = 1; 562 } else { /* no exception, received data OK */ 563 line_stat = 0; 564 n_chars = cd1400_read_reg(cd, CD1400_RDCR); 565 } 566 567 ptr = mtty->mp_rput; 568 while( n_chars-- ) { 569 *ptr++ = line_stat; 570 *ptr++ = cd1400_read_reg(cd, CD1400_RDSR); 571 if( ptr == mtty->mp_rend ) ptr = mtty->mp_rbuf; 572 if( ptr == mtty->mp_rget ) { 573 if( ptr == mtty->mp_rbuf ) 574 ptr = mtty->mp_rend; 575 ptr -= 2; 576 SET(mtty->mp_flags, MTTYF_RING_OVERFLOW); 577 break; 578 } 579 } 580 mtty->mp_rput = ptr; 581 582 needsoftint = 1; 583 } 584 585 cd1400_write_reg(cd, CD1400_EOSRR, 0); /* end service context */ 586 serviced = 1; 587 } /* if(rx_service...) */ 588 589 if( ISSET(status, CD1400_SVRR_MDMCH) ) { 590 u_char mivr = *sc->ms_svcackm; /* enter mdm service context */ 591 int port = mivr >> 4; 592 struct mtty_port *mtty; 593 int carrier; 594 u_char msvr; 595 596 /* 597 * Handle CD (LC2+1Sp = DSR) changes. 598 */ 599 mtty = &sc->ms_mtty->ms_port[port]; 600 cd = mtty->mp_cd1400; 601 msvr = cd1400_read_reg(cd, CD1400_MSVR2); 602 carrier = ISSET(msvr, cd->cd_parmode ? CD1400_MSVR2_DSR : CD1400_MSVR2_CD); 603 604 if( mtty->mp_carrier != carrier ) { 605 SET(mtty->mp_flags, MTTYF_CARRIER_CHANGED); 606 mtty->mp_carrier = carrier; 607 needsoftint = 1; 608 } 609 610 cd1400_write_reg(cd, CD1400_EOSRR, 0); /* end service context */ 611 serviced = 1; 612 } /* if(mdm_service...) */ 613 614 if( ISSET(status, CD1400_SVRR_TXRDY) ) { 615 u_char tivr = *sc->ms_svcackt; /* enter tx service context */ 616 int port = tivr >> 4; 617 618 if( tivr & (1<<3) ) { /* parallel port */ 619 struct mbpp_port *mbpp; 620 621 mbpp = &sc->ms_mbpp->ms_port[port]; 622 cd = mbpp->mp_cd1400; 623 624 if( mbpp->mp_cnt ) { 625 int count = 0; 626 627 /* fill the fifo */ 628 while (mbpp->mp_cnt && 629 count++ < CD1400_PAR_FIFO_SIZE) { 630 cd1400_write_reg(cd, CD1400_TDR, 631 *mbpp->mp_ptr); 632 mbpp->mp_ptr++; 633 mbpp->mp_cnt--; 634 } 635 } else { 636 /* 637 * fifo is empty and we got no more data 638 * to send, so shut off interrupts and 639 * signal for a wakeup, which can't be 640 * done here in case we beat mbpp_send to 641 * the tsleep call (we are running at >spltty) 642 */ 643 cd1400_write_reg(cd, CD1400_SRER, 0); 644 SET(mbpp->mp_flags, MBPPF_WAKEUP); 645 needsoftint = 1; 646 } 647 } else { /* serial port */ 648 struct mtty_port *mtty; 649 struct tty *tp; 650 651 mtty = &sc->ms_mtty->ms_port[port]; 652 cd = mtty->mp_cd1400; 653 tp = mtty->mp_tty; 654 655 if( !ISSET(mtty->mp_flags, MTTYF_STOP) ) { 656 int count = 0; 657 658 /* check if we should start/stop a break */ 659 if( ISSET(mtty->mp_flags, MTTYF_SET_BREAK) ) { 660 cd1400_write_reg(cd, CD1400_TDR, 0); 661 cd1400_write_reg(cd, CD1400_TDR, 0x81); 662 /* should we delay too? */ 663 CLR(mtty->mp_flags, MTTYF_SET_BREAK); 664 count += 2; 665 } 666 667 if( ISSET(mtty->mp_flags, MTTYF_CLR_BREAK) ) { 668 cd1400_write_reg(cd, CD1400_TDR, 0); 669 cd1400_write_reg(cd, CD1400_TDR, 0x83); 670 CLR(mtty->mp_flags, MTTYF_CLR_BREAK); 671 count += 2; 672 } 673 674 /* I don't quite fill the fifo in case the last one is a 675 * NULL which I have to double up because its the escape 676 * code for embedded transmit characters. 677 */ 678 while( mtty->mp_txc > 0 && count < CD1400_TX_FIFO_SIZE - 1 ) { 679 u_char ch; 680 681 ch = *mtty->mp_txp; 682 683 mtty->mp_txc--; 684 mtty->mp_txp++; 685 686 if( ch == 0 ) { 687 cd1400_write_reg(cd, CD1400_TDR, ch); 688 count++; 689 } 690 691 cd1400_write_reg(cd, CD1400_TDR, ch); 692 count++; 693 } 694 } 695 696 /* if we ran out of work or are requested to STOP then 697 * shut off the txrdy interrupts and signal DONE to flush 698 * out the chars we have sent. 699 */ 700 if( mtty->mp_txc == 0 || ISSET(mtty->mp_flags, MTTYF_STOP) ) { 701 register int srer; 702 703 srer = cd1400_read_reg(cd, CD1400_SRER); 704 CLR(srer, CD1400_SRER_TXRDY); 705 cd1400_write_reg(cd, CD1400_SRER, srer); 706 CLR(mtty->mp_flags, MTTYF_STOP); 707 708 SET(mtty->mp_flags, MTTYF_DONE); 709 needsoftint = 1; 710 } 711 } 712 713 cd1400_write_reg(cd, CD1400_EOSRR, 0); /* end service context */ 714 serviced = 1; 715 } /* if(tx_service...) */ 716 717 /* XXX service CD1190 interrupts too 718 for( chip = 0 ; chip < sc->ms_ncd1190 ; chip++ ) { 719 } 720 */ 721 722 if (needsoftint) 723 /* trigger the soft interrupt */ 724 softint_schedule(sc->ms_sicookie); 725 726 return(serviced); 727 } 728 729 /* 730 * magma soft interrupt handler 731 * 732 * runs at IPL_SOFTSERIAL 733 */ 734 void 735 magma_soft(arg) 736 void *arg; 737 { 738 struct magma_softc *sc = arg; 739 struct mtty_softc *mtty = sc->ms_mtty; 740 struct mbpp_softc *mbpp = sc->ms_mbpp; 741 int port; 742 int s, flags; 743 744 if (mtty == NULL) 745 goto chkbpp; 746 747 /* 748 * check the tty ports to see what needs doing 749 */ 750 for( port = 0 ; port < mtty->ms_nports ; port++ ) { 751 struct mtty_port *mp = &mtty->ms_port[port]; 752 struct tty *tp = mp->mp_tty; 753 754 if( !ISSET(tp->t_state, TS_ISOPEN) ) 755 continue; 756 757 /* 758 * handle any received data 759 */ 760 while( mp->mp_rget != mp->mp_rput ) { 761 u_char stat; 762 int data; 763 764 stat = mp->mp_rget[0]; 765 data = mp->mp_rget[1]; 766 mp->mp_rget = ((mp->mp_rget + 2) == mp->mp_rend) 767 ? mp->mp_rbuf : (mp->mp_rget + 2); 768 769 if( stat & (CD1400_RDSR_BREAK | CD1400_RDSR_FE) ) 770 data |= TTY_FE; 771 if( stat & CD1400_RDSR_PE ) 772 data |= TTY_PE; 773 774 if( stat & CD1400_RDSR_OE ) 775 log(LOG_WARNING, "%s%x: fifo overflow\n", 776 device_xname(&mtty->ms_dev), port); 777 778 (*tp->t_linesw->l_rint)(data, tp); 779 } 780 781 s = splserial(); /* block out hard interrupt routine */ 782 flags = mp->mp_flags; 783 CLR(mp->mp_flags, MTTYF_DONE | MTTYF_CARRIER_CHANGED | MTTYF_RING_OVERFLOW); 784 splx(s); /* ok */ 785 786 if( ISSET(flags, MTTYF_CARRIER_CHANGED) ) { 787 dprintf(("%s%x: cd %s\n", device_xname(&mtty->ms_dev), 788 port, mp->mp_carrier ? "on" : "off")); 789 (*tp->t_linesw->l_modem)(tp, mp->mp_carrier); 790 } 791 792 if( ISSET(flags, MTTYF_RING_OVERFLOW) ) { 793 log(LOG_WARNING, "%s%x: ring buffer overflow\n", 794 device_xname(&mtty->ms_dev), port); 795 } 796 797 if( ISSET(flags, MTTYF_DONE) ) { 798 ndflush(&tp->t_outq, mp->mp_txp - tp->t_outq.c_cf); 799 CLR(tp->t_state, TS_BUSY); 800 (*tp->t_linesw->l_start)(tp); /* might be some more */ 801 } 802 } /* for(each mtty...) */ 803 804 805 chkbpp: 806 /* 807 * Check the bpp ports (if any) to see what needs doing 808 */ 809 if (mbpp == NULL) 810 return; 811 812 for( port = 0 ; port < mbpp->ms_nports ; port++ ) { 813 struct mbpp_port *mp = &mbpp->ms_port[port]; 814 815 if( !ISSET(mp->mp_flags, MBPPF_OPEN) ) 816 continue; 817 818 s = splserial(); 819 flags = mp->mp_flags; 820 CLR(mp->mp_flags, MBPPF_WAKEUP); 821 splx(s); 822 823 if( ISSET(flags, MBPPF_WAKEUP) ) { 824 wakeup(mp); 825 } 826 827 } /* for(each mbpp...) */ 828 } 829 830 /************************************************************************ 831 * 832 * MTTY Routines 833 * 834 * mtty_match match one mtty device 835 * mtty_attach attach mtty devices 836 * mttyopen open mtty device 837 * mttyclose close mtty device 838 * mttyread read from mtty 839 * mttywrite write to mtty 840 * mttyioctl do ioctl on mtty 841 * mttytty return tty pointer for mtty 842 * mttystop stop mtty device 843 * mtty_start start mtty device 844 * mtty_param set mtty parameters 845 * mtty_modem_control set modem control lines 846 */ 847 848 int 849 mtty_match(parent, cf, args) 850 struct device *parent; 851 struct cfdata *cf; 852 void *args; 853 { 854 struct magma_softc *sc = (struct magma_softc *)parent; 855 856 return( args == mtty_match && sc->ms_board->mb_nser && sc->ms_mtty == NULL ); 857 } 858 859 void 860 mtty_attach(parent, dev, args) 861 struct device *parent; 862 struct device *dev; 863 void *args; 864 { 865 struct magma_softc *sc = (struct magma_softc *)parent; 866 struct mtty_softc *ms = (struct mtty_softc *)dev; 867 int port, chip, chan; 868 869 sc->ms_mtty = ms; 870 dprintf((" addr %p", ms)); 871 872 for( port = 0, chip = 0, chan = 0 ; port < sc->ms_board->mb_nser ; port++ ) { 873 struct mtty_port *mp = &ms->ms_port[port]; 874 struct tty *tp; 875 876 mp->mp_cd1400 = &sc->ms_cd1400[chip]; 877 if (mp->mp_cd1400->cd_parmode && chan == 0) 878 chan = 1; /* skip channel 0 if parmode */ 879 mp->mp_channel = chan; 880 881 tp = ttymalloc(); 882 if (tp == NULL) break; 883 tty_attach(tp); 884 tp->t_oproc = mtty_start; 885 tp->t_param = mtty_param; 886 887 mp->mp_tty = tp; 888 889 mp->mp_rbuf = malloc(MTTY_RBUF_SIZE, M_DEVBUF, M_NOWAIT); 890 if (mp->mp_rbuf == NULL) break; 891 892 mp->mp_rend = mp->mp_rbuf + MTTY_RBUF_SIZE; 893 894 chan = (chan + 1) % CD1400_NO_OF_CHANNELS; 895 if (chan == 0) 896 chip++; 897 } 898 899 ms->ms_nports = port; 900 printf(": %d tty%s\n", port, port == 1 ? "" : "s"); 901 } 902 903 /* 904 * open routine. returns zero if successful, else error code 905 */ 906 int 907 mttyopen(dev, flags, mode, l) 908 dev_t dev; 909 int flags; 910 int mode; 911 struct lwp *l; 912 { 913 int card = MAGMA_CARD(dev); 914 int port = MAGMA_PORT(dev); 915 struct mtty_softc *ms; 916 struct mtty_port *mp; 917 struct tty *tp; 918 struct cd1400 *cd; 919 int error, s; 920 921 if( card >= mtty_cd.cd_ndevs || 922 (ms = mtty_cd.cd_devs[card]) == NULL || port >= ms->ms_nports ) 923 return(ENXIO); /* device not configured */ 924 925 mp = &ms->ms_port[port]; 926 tp = mp->mp_tty; 927 tp->t_dev = dev; 928 929 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 930 return (EBUSY); 931 932 s = spltty(); 933 934 if( !ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 935 936 /* set defaults */ 937 ttychars(tp); 938 tp->t_iflag = TTYDEF_IFLAG; 939 tp->t_oflag = TTYDEF_OFLAG; 940 tp->t_cflag = TTYDEF_CFLAG; 941 if( ISSET(mp->mp_openflags, TIOCFLAG_CLOCAL) ) 942 SET(tp->t_cflag, CLOCAL); 943 if( ISSET(mp->mp_openflags, TIOCFLAG_CRTSCTS) ) 944 SET(tp->t_cflag, CRTSCTS); 945 if( ISSET(mp->mp_openflags, TIOCFLAG_MDMBUF) ) 946 SET(tp->t_cflag, MDMBUF); 947 tp->t_lflag = TTYDEF_LFLAG; 948 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 949 950 /* init ring buffer */ 951 mp->mp_rput = mp->mp_rget = mp->mp_rbuf; 952 953 /* reset CD1400 channel */ 954 cd = mp->mp_cd1400; 955 cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel); 956 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET); 957 958 /* encode the port number in top half of LIVR */ 959 cd1400_write_reg(cd, CD1400_LIVR, port << 4 ); 960 961 /* sets parameters and raises DTR */ 962 (void)mtty_param(tp, &tp->t_termios); 963 964 /* set tty watermarks */ 965 ttsetwater(tp); 966 967 /* enable service requests */ 968 cd1400_write_reg(cd, CD1400_SRER, 969 CD1400_SRER_RXDATA | CD1400_SRER_MDMCH); 970 971 /* tell the tty about the carrier status */ 972 if( ISSET(mp->mp_openflags, TIOCFLAG_SOFTCAR) || 973 mp->mp_carrier ) 974 SET(tp->t_state, TS_CARR_ON); 975 else 976 CLR(tp->t_state, TS_CARR_ON); 977 } 978 splx(s); 979 980 error = ttyopen(tp, MTTY_DIALOUT(dev), ISSET(flags, O_NONBLOCK)); 981 if (error != 0) 982 goto bad; 983 984 error = (*tp->t_linesw->l_open)(dev, tp); 985 if (error != 0) 986 goto bad; 987 988 bad: 989 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 990 /* 991 * We failed to open the device, and nobody else had it opened. 992 * Clean up the state as appropriate. 993 */ 994 /* XXX - do that here */ 995 } 996 997 return (error); 998 } 999 1000 /* 1001 * close routine. returns zero if successful, else error code 1002 */ 1003 int 1004 mttyclose(dev, flag, mode, l) 1005 dev_t dev; 1006 int flag; 1007 int mode; 1008 struct lwp *l; 1009 { 1010 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(dev)]; 1011 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1012 struct tty *tp = mp->mp_tty; 1013 int s; 1014 1015 (*tp->t_linesw->l_close)(tp, flag); 1016 ttyclose(tp); 1017 1018 s = spltty(); 1019 1020 /* if HUPCL is set, and the tty is no longer open 1021 * shut down the port 1022 */ 1023 if( ISSET(tp->t_cflag, HUPCL) || !ISSET(tp->t_state, TS_ISOPEN) ) { 1024 /* XXX wait until FIFO is empty before turning off the channel 1025 struct cd1400 *cd = mp->mp_cd1400; 1026 */ 1027 1028 /* drop DTR and RTS */ 1029 (void)mtty_modem_control(mp, 0, DMSET); 1030 1031 /* turn off the channel 1032 cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel); 1033 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET); 1034 */ 1035 } 1036 1037 splx(s); 1038 1039 return(0); 1040 } 1041 1042 /* 1043 * Read routine 1044 */ 1045 int 1046 mttyread(dev, uio, flags) 1047 dev_t dev; 1048 struct uio *uio; 1049 int flags; 1050 { 1051 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(dev)]; 1052 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1053 struct tty *tp = mp->mp_tty; 1054 1055 return( (*tp->t_linesw->l_read)(tp, uio, flags) ); 1056 } 1057 1058 /* 1059 * Write routine 1060 */ 1061 int 1062 mttywrite(dev, uio, flags) 1063 dev_t dev; 1064 struct uio *uio; 1065 int flags; 1066 { 1067 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(dev)]; 1068 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1069 struct tty *tp = mp->mp_tty; 1070 1071 return( (*tp->t_linesw->l_write)(tp, uio, flags) ); 1072 } 1073 1074 /* 1075 * Poll routine 1076 */ 1077 int 1078 mttypoll(dev, events, l) 1079 dev_t dev; 1080 int events; 1081 struct lwp *l; 1082 { 1083 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(dev)]; 1084 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1085 struct tty *tp = mp->mp_tty; 1086 1087 return ((*tp->t_linesw->l_poll)(tp, events, l)); 1088 } 1089 1090 /* 1091 * return tty pointer 1092 */ 1093 struct tty * 1094 mttytty(dev) 1095 dev_t dev; 1096 { 1097 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(dev)]; 1098 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1099 1100 return(mp->mp_tty); 1101 } 1102 1103 /* 1104 * ioctl routine 1105 */ 1106 int 1107 mttyioctl(dev, cmd, data, flags, l) 1108 dev_t dev; 1109 u_long cmd; 1110 void *data; 1111 int flags; 1112 struct lwp *l; 1113 { 1114 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(dev)]; 1115 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1116 struct tty *tp = mp->mp_tty; 1117 int error; 1118 1119 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flags, l); 1120 if( error != EPASSTHROUGH ) return(error); 1121 1122 error = ttioctl(tp, cmd, data, flags, l); 1123 if( error != EPASSTHROUGH ) return(error); 1124 1125 error = 0; 1126 1127 switch(cmd) { 1128 case TIOCSBRK: /* set break */ 1129 SET(mp->mp_flags, MTTYF_SET_BREAK); 1130 cd1400_enable_transmitter(mp->mp_cd1400, mp->mp_channel); 1131 break; 1132 1133 case TIOCCBRK: /* clear break */ 1134 SET(mp->mp_flags, MTTYF_CLR_BREAK); 1135 cd1400_enable_transmitter(mp->mp_cd1400, mp->mp_channel); 1136 break; 1137 1138 case TIOCSDTR: /* set DTR */ 1139 mtty_modem_control(mp, TIOCM_DTR, DMBIS); 1140 break; 1141 1142 case TIOCCDTR: /* clear DTR */ 1143 mtty_modem_control(mp, TIOCM_DTR, DMBIC); 1144 break; 1145 1146 case TIOCMSET: /* set modem lines */ 1147 mtty_modem_control(mp, *((int *)data), DMSET); 1148 break; 1149 1150 case TIOCMBIS: /* bit set modem lines */ 1151 mtty_modem_control(mp, *((int *)data), DMBIS); 1152 break; 1153 1154 case TIOCMBIC: /* bit clear modem lines */ 1155 mtty_modem_control(mp, *((int *)data), DMBIC); 1156 break; 1157 1158 case TIOCMGET: /* get modem lines */ 1159 *((int *)data) = mtty_modem_control(mp, 0, DMGET); 1160 break; 1161 1162 case TIOCGFLAGS: 1163 *((int *)data) = mp->mp_openflags; 1164 break; 1165 1166 case TIOCSFLAGS: 1167 if (kauth_authorize_device_tty(l->l_cred, 1168 KAUTH_DEVICE_TTY_PRIVSET, tp)) 1169 error = EPERM; 1170 else 1171 mp->mp_openflags = *((int *)data) & 1172 (TIOCFLAG_SOFTCAR | TIOCFLAG_CLOCAL | 1173 TIOCFLAG_CRTSCTS | TIOCFLAG_MDMBUF); 1174 break; 1175 1176 default: 1177 error = EPASSTHROUGH; 1178 } 1179 1180 return(error); 1181 } 1182 1183 /* 1184 * Stop output, e.g., for ^S or output flush. 1185 */ 1186 void 1187 mttystop(tp, flags) 1188 struct tty *tp; 1189 int flags; 1190 { 1191 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(tp->t_dev)]; 1192 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(tp->t_dev)]; 1193 int s; 1194 1195 s = spltty(); 1196 1197 if( ISSET(tp->t_state, TS_BUSY) ) { 1198 if( !ISSET(tp->t_state, TS_TTSTOP) ) 1199 SET(tp->t_state, TS_FLUSH); 1200 1201 /* 1202 * the transmit interrupt routine will disable transmit when it 1203 * notices that MTTYF_STOP has been set. 1204 */ 1205 SET(mp->mp_flags, MTTYF_STOP); 1206 } 1207 1208 splx(s); 1209 } 1210 1211 /* 1212 * Start output, after a stop. 1213 */ 1214 void 1215 mtty_start(tp) 1216 struct tty *tp; 1217 { 1218 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(tp->t_dev)]; 1219 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(tp->t_dev)]; 1220 int s; 1221 1222 s = spltty(); 1223 1224 /* we only need to do something if we are not already busy 1225 * or delaying or stopped 1226 */ 1227 if( !ISSET(tp->t_state, TS_TTSTOP | TS_TIMEOUT | TS_BUSY) ) { 1228 if (ttypull(tp)) { 1229 mp->mp_txc = ndqb(&tp->t_outq, 0); 1230 mp->mp_txp = tp->t_outq.c_cf; 1231 SET(tp->t_state, TS_BUSY); 1232 cd1400_enable_transmitter(mp->mp_cd1400, mp->mp_channel); 1233 } 1234 } 1235 1236 splx(s); 1237 } 1238 1239 /* 1240 * set/get modem line status 1241 * 1242 * bits can be: TIOCM_DTR, TIOCM_RTS, TIOCM_CTS, TIOCM_CD, TIOCM_RI, TIOCM_DSR 1243 * 1244 * note that DTR and RTS lines are exchanged, and that DSR is 1245 * not available on the LC2+1Sp card (used as CD) 1246 * 1247 * only let them fiddle with RTS if CRTSCTS is not enabled 1248 */ 1249 int 1250 mtty_modem_control(mp, bits, howto) 1251 struct mtty_port *mp; 1252 int bits; 1253 int howto; 1254 { 1255 struct cd1400 *cd = mp->mp_cd1400; 1256 struct tty *tp = mp->mp_tty; 1257 int s, msvr; 1258 1259 s = spltty(); 1260 1261 cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel); 1262 1263 switch(howto) { 1264 case DMGET: /* get bits */ 1265 bits = 0; 1266 1267 bits |= TIOCM_LE; 1268 1269 msvr = cd1400_read_reg(cd, CD1400_MSVR1); 1270 if( msvr & CD1400_MSVR1_RTS ) bits |= TIOCM_DTR; 1271 1272 msvr = cd1400_read_reg(cd, CD1400_MSVR2); 1273 if( msvr & CD1400_MSVR2_DTR ) bits |= TIOCM_RTS; 1274 if( msvr & CD1400_MSVR2_CTS ) bits |= TIOCM_CTS; 1275 if( msvr & CD1400_MSVR2_RI ) bits |= TIOCM_RI; 1276 if( msvr & CD1400_MSVR2_DSR ) bits |= (cd->cd_parmode ? TIOCM_CD : TIOCM_DSR); 1277 if( msvr & CD1400_MSVR2_CD ) bits |= (cd->cd_parmode ? 0 : TIOCM_CD); 1278 1279 break; 1280 1281 case DMSET: /* reset bits */ 1282 if( !ISSET(tp->t_cflag, CRTSCTS) ) 1283 cd1400_write_reg(cd, CD1400_MSVR2, ((bits & TIOCM_RTS) ? CD1400_MSVR2_DTR : 0)); 1284 1285 cd1400_write_reg(cd, CD1400_MSVR1, ((bits & TIOCM_DTR) ? CD1400_MSVR1_RTS : 0)); 1286 1287 break; 1288 1289 case DMBIS: /* set bits */ 1290 if( (bits & TIOCM_RTS) && !ISSET(tp->t_cflag, CRTSCTS) ) 1291 cd1400_write_reg(cd, CD1400_MSVR2, CD1400_MSVR2_DTR); 1292 1293 if( bits & TIOCM_DTR ) 1294 cd1400_write_reg(cd, CD1400_MSVR1, CD1400_MSVR1_RTS); 1295 1296 break; 1297 1298 case DMBIC: /* clear bits */ 1299 if( (bits & TIOCM_RTS) && !ISSET(tp->t_cflag, CRTSCTS) ) 1300 cd1400_write_reg(cd, CD1400_MSVR2, 0); 1301 1302 if( bits & TIOCM_DTR ) 1303 cd1400_write_reg(cd, CD1400_MSVR1, 0); 1304 1305 break; 1306 } 1307 1308 splx(s); 1309 return(bits); 1310 } 1311 1312 /* 1313 * Set tty parameters, returns error or 0 on success 1314 */ 1315 int 1316 mtty_param(tp, t) 1317 struct tty *tp; 1318 struct termios *t; 1319 { 1320 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(tp->t_dev)]; 1321 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(tp->t_dev)]; 1322 struct cd1400 *cd = mp->mp_cd1400; 1323 int rbpr, tbpr, rcor, tcor; 1324 u_char mcor1 = 0, mcor2 = 0; 1325 int s, opt; 1326 1327 if( t->c_ospeed && cd1400_compute_baud(t->c_ospeed, cd->cd_clock, &tcor, &tbpr) ) 1328 return(EINVAL); 1329 1330 if( t->c_ispeed && cd1400_compute_baud(t->c_ispeed, cd->cd_clock, &rcor, &rbpr) ) 1331 return(EINVAL); 1332 1333 s = spltty(); 1334 1335 /* hang up the line if ospeed is zero, else raise DTR */ 1336 (void)mtty_modem_control(mp, TIOCM_DTR, (t->c_ospeed == 0 ? DMBIC : DMBIS)); 1337 1338 /* select channel, done in mtty_modem_control() */ 1339 /* cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel); */ 1340 1341 /* set transmit speed */ 1342 if( t->c_ospeed ) { 1343 cd1400_write_reg(cd, CD1400_TCOR, tcor); 1344 cd1400_write_reg(cd, CD1400_TBPR, tbpr); 1345 } 1346 1347 /* set receive speed */ 1348 if( t->c_ispeed ) { 1349 cd1400_write_reg(cd, CD1400_RCOR, rcor); 1350 cd1400_write_reg(cd, CD1400_RBPR, rbpr); 1351 } 1352 1353 /* enable transmitting and receiving on this channel */ 1354 opt = CD1400_CCR_CMDCHANCTL | CD1400_CCR_XMTEN | CD1400_CCR_RCVEN; 1355 cd1400_write_ccr(cd, opt); 1356 1357 /* set parity, data and stop bits */ 1358 opt = 0; 1359 if( ISSET(t->c_cflag, PARENB) ) 1360 opt |= (ISSET(t->c_cflag, PARODD) ? CD1400_COR1_PARODD : CD1400_COR1_PARNORMAL); 1361 1362 if( !ISSET(t->c_iflag, INPCK) ) 1363 opt |= CD1400_COR1_NOINPCK; /* no parity checking */ 1364 1365 if( ISSET(t->c_cflag, CSTOPB) ) 1366 opt |= CD1400_COR1_STOP2; 1367 1368 switch( t->c_cflag & CSIZE ) { 1369 case CS5: 1370 opt |= CD1400_COR1_CS5; 1371 break; 1372 1373 case CS6: 1374 opt |= CD1400_COR1_CS6; 1375 break; 1376 1377 case CS7: 1378 opt |= CD1400_COR1_CS7; 1379 break; 1380 1381 default: 1382 opt |= CD1400_COR1_CS8; 1383 break; 1384 } 1385 1386 cd1400_write_reg(cd, CD1400_COR1, opt); 1387 1388 /* 1389 * enable Embedded Transmit Commands (for breaks) 1390 * use the CD1400 automatic CTS flow control if CRTSCTS is set 1391 */ 1392 opt = CD1400_COR2_ETC; 1393 if( ISSET(t->c_cflag, CRTSCTS) ) opt |= CD1400_COR2_CCTS_OFLOW; 1394 cd1400_write_reg(cd, CD1400_COR2, opt); 1395 1396 cd1400_write_reg(cd, CD1400_COR3, MTTY_RX_FIFO_THRESHOLD); 1397 1398 cd1400_write_ccr(cd, CD1400_CCR_CMDCORCHG | CD1400_CCR_COR1 | CD1400_CCR_COR2 | CD1400_CCR_COR3); 1399 1400 cd1400_write_reg(cd, CD1400_COR4, CD1400_COR4_PFO_EXCEPTION); 1401 cd1400_write_reg(cd, CD1400_COR5, 0); 1402 1403 /* 1404 * if automatic RTS handshaking enabled, set DTR threshold 1405 * (RTS and DTR lines are switched, CD1400 thinks its DTR) 1406 */ 1407 if( ISSET(t->c_cflag, CRTSCTS) ) 1408 mcor1 = MTTY_RX_DTR_THRESHOLD; 1409 1410 /* set up `carrier detect' interrupts */ 1411 if( cd->cd_parmode ) { 1412 SET(mcor1, CD1400_MCOR1_DSRzd); 1413 SET(mcor2, CD1400_MCOR2_DSRod); 1414 } else { 1415 SET(mcor1, CD1400_MCOR1_CDzd); 1416 SET(mcor2, CD1400_MCOR2_CDod); 1417 } 1418 1419 cd1400_write_reg(cd, CD1400_MCOR1, mcor1); 1420 cd1400_write_reg(cd, CD1400_MCOR2, mcor2); 1421 1422 /* receive timeout 2ms */ 1423 cd1400_write_reg(cd, CD1400_RTPR, 2); 1424 1425 splx(s); 1426 return(0); 1427 } 1428 1429 /************************************************************************ 1430 * 1431 * MBPP Routines 1432 * 1433 * mbpp_match match one mbpp device 1434 * mbpp_attach attach mbpp devices 1435 * mbppopen open mbpp device 1436 * mbppclose close mbpp device 1437 * mbppioctl do ioctl on mbpp 1438 * mbpp_rw general rw routine 1439 * mbpp_timeout rw timeout 1440 * mbpp_start rw start after delay 1441 * mbpp_send send data 1442 * mbpp_recv recv data 1443 */ 1444 1445 int 1446 mbpp_match(parent, cf, args) 1447 struct device *parent; 1448 struct cfdata *cf; 1449 void *args; 1450 { 1451 struct magma_softc *sc = (struct magma_softc *)parent; 1452 1453 return( args == mbpp_match && sc->ms_board->mb_npar && sc->ms_mbpp == NULL ); 1454 } 1455 1456 void 1457 mbpp_attach(parent, dev, args) 1458 struct device *parent; 1459 struct device *dev; 1460 void *args; 1461 { 1462 struct magma_softc *sc = (struct magma_softc *)parent; 1463 struct mbpp_softc *ms = (struct mbpp_softc *)dev; 1464 struct mbpp_port *mp; 1465 int port; 1466 1467 sc->ms_mbpp = ms; 1468 dprintf((" addr %p", ms)); 1469 1470 for( port = 0 ; port < sc->ms_board->mb_npar ; port++ ) { 1471 mp = &ms->ms_port[port]; 1472 1473 callout_init(&mp->mp_timeout_ch, 0); 1474 callout_init(&mp->mp_start_ch, 0); 1475 1476 if( sc->ms_ncd1190 ) 1477 mp->mp_cd1190 = &sc->ms_cd1190[port]; 1478 else 1479 mp->mp_cd1400 = &sc->ms_cd1400[0]; 1480 } 1481 1482 ms->ms_nports = port; 1483 printf(": %d port%s\n", port, port == 1 ? "" : "s"); 1484 } 1485 1486 /* 1487 * open routine. returns zero if successful, else error code 1488 */ 1489 int 1490 mbppopen(dev, flags, mode, l) 1491 dev_t dev; 1492 int flags; 1493 int mode; 1494 struct lwp *l; 1495 { 1496 int card = MAGMA_CARD(dev); 1497 int port = MAGMA_PORT(dev); 1498 struct mbpp_softc *ms; 1499 struct mbpp_port *mp; 1500 int s; 1501 1502 if( card >= mbpp_cd.cd_ndevs || 1503 (ms = mbpp_cd.cd_devs[card]) == NULL || port >= ms->ms_nports ) 1504 return(ENXIO); 1505 1506 mp = &ms->ms_port[port]; 1507 1508 s = spltty(); 1509 if( ISSET(mp->mp_flags, MBPPF_OPEN) ) { 1510 splx(s); 1511 return(EBUSY); 1512 } 1513 SET(mp->mp_flags, MBPPF_OPEN); 1514 splx(s); 1515 1516 /* set defaults */ 1517 mp->mp_burst = MBPP_BURST; 1518 mp->mp_timeout = mbpp_mstohz(MBPP_TIMEOUT); 1519 mp->mp_delay = mbpp_mstohz(MBPP_DELAY); 1520 1521 /* init chips */ 1522 if( mp->mp_cd1400 ) { /* CD1400 */ 1523 struct cd1400 *cd = mp->mp_cd1400; 1524 1525 /* set up CD1400 channel */ 1526 s = spltty(); 1527 cd1400_write_reg(cd, CD1400_CAR, 0); 1528 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET); 1529 cd1400_write_reg(cd, CD1400_LIVR, (1<<3)); 1530 splx(s); 1531 } else { /* CD1190 */ 1532 mp->mp_flags = 0; 1533 return (ENXIO); 1534 } 1535 1536 return (0); 1537 } 1538 1539 /* 1540 * close routine. returns zero if successful, else error code 1541 */ 1542 int 1543 mbppclose(dev, flag, mode, l) 1544 dev_t dev; 1545 int flag; 1546 int mode; 1547 struct lwp *l; 1548 { 1549 struct mbpp_softc *ms = mbpp_cd.cd_devs[MAGMA_CARD(dev)]; 1550 struct mbpp_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1551 1552 mp->mp_flags = 0; 1553 return(0); 1554 } 1555 1556 /* 1557 * ioctl routine 1558 */ 1559 int 1560 mbppioctl(dev, cmd, data, flags, l) 1561 dev_t dev; 1562 u_long cmd; 1563 void *data; 1564 int flags; 1565 struct lwp *l; 1566 { 1567 struct mbpp_softc *ms = mbpp_cd.cd_devs[MAGMA_CARD(dev)]; 1568 struct mbpp_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1569 struct mbpp_param *bp; 1570 int error = 0; 1571 int s; 1572 1573 switch(cmd) { 1574 case MBPPIOCSPARAM: 1575 bp = (struct mbpp_param *)data; 1576 if( bp->bp_burst < MBPP_BURST_MIN || bp->bp_burst > MBPP_BURST_MAX || 1577 bp->bp_delay < MBPP_DELAY_MIN || bp->bp_delay > MBPP_DELAY_MIN ) { 1578 error = EINVAL; 1579 } else { 1580 mp->mp_burst = bp->bp_burst; 1581 mp->mp_timeout = mbpp_mstohz(bp->bp_timeout); 1582 mp->mp_delay = mbpp_mstohz(bp->bp_delay); 1583 } 1584 break; 1585 case MBPPIOCGPARAM: 1586 bp = (struct mbpp_param *)data; 1587 bp->bp_burst = mp->mp_burst; 1588 bp->bp_timeout = mbpp_hztoms(mp->mp_timeout); 1589 bp->bp_delay = mbpp_hztoms(mp->mp_delay); 1590 break; 1591 case MBPPIOCGSTAT: 1592 /* XXX make this more generic */ 1593 s = spltty(); 1594 cd1400_write_reg(mp->mp_cd1400, CD1400_CAR, 0); 1595 *(int *)data = cd1400_read_reg(mp->mp_cd1400, CD1400_PSVR); 1596 splx(s); 1597 break; 1598 default: 1599 error = ENOTTY; 1600 } 1601 1602 return(error); 1603 } 1604 1605 int 1606 mbpp_rw(dev, uio, flag) 1607 dev_t dev; 1608 struct uio *uio; 1609 int flag; 1610 { 1611 int card = MAGMA_CARD(dev); 1612 int port = MAGMA_PORT(dev); 1613 struct mbpp_softc *ms = mbpp_cd.cd_devs[card]; 1614 struct mbpp_port *mp = &ms->ms_port[port]; 1615 char *buffer, *ptr; 1616 int buflen, cnt, len; 1617 int s, error = 0; 1618 int gotdata = 0; 1619 1620 if( uio->uio_resid == 0 ) 1621 return(0); 1622 1623 buflen = min(uio->uio_resid, mp->mp_burst); 1624 buffer = malloc(buflen, M_DEVBUF, M_WAITOK); 1625 if( buffer == NULL ) 1626 return(ENOMEM); 1627 1628 SET(mp->mp_flags, MBPPF_UIO); 1629 1630 /* 1631 * start timeout, if needed 1632 */ 1633 if( mp->mp_timeout > 0 ) { 1634 SET(mp->mp_flags, MBPPF_TIMEOUT); 1635 callout_reset(&mp->mp_timeout_ch, mp->mp_timeout, 1636 mbpp_timeout, mp); 1637 } 1638 1639 len = cnt = 0; 1640 while( uio->uio_resid > 0 ) { 1641 len = min(buflen, uio->uio_resid); 1642 ptr = buffer; 1643 1644 if( uio->uio_rw == UIO_WRITE ) { 1645 error = uiomove(ptr, len, uio); 1646 if( error ) break; 1647 } 1648 again: /* goto bad */ 1649 /* timed out? */ 1650 if( !ISSET(mp->mp_flags, MBPPF_UIO) ) 1651 break; 1652 1653 /* 1654 * perform the operation 1655 */ 1656 if( uio->uio_rw == UIO_WRITE ) { 1657 cnt = mbpp_send(mp, ptr, len); 1658 } else { 1659 cnt = mbpp_recv(mp, ptr, len); 1660 } 1661 1662 if( uio->uio_rw == UIO_READ ) { 1663 if( cnt ) { 1664 error = uiomove(ptr, cnt, uio); 1665 if( error ) break; 1666 gotdata++; 1667 } 1668 else if( gotdata ) /* consider us done */ 1669 break; 1670 } 1671 1672 /* timed out? */ 1673 if( !ISSET(mp->mp_flags, MBPPF_UIO) ) 1674 break; 1675 1676 /* 1677 * poll delay? 1678 */ 1679 if( mp->mp_delay > 0 ) { 1680 s = splsoftclock(); 1681 SET(mp->mp_flags, MBPPF_DELAY); 1682 callout_reset(&mp->mp_start_ch, mp->mp_delay, 1683 mbpp_start, mp); 1684 error = tsleep(mp, PCATCH | PZERO, "mbppdelay", 0); 1685 splx(s); 1686 if( error ) break; 1687 } 1688 1689 /* 1690 * don't call uiomove again until we used all the data we grabbed 1691 */ 1692 if( uio->uio_rw == UIO_WRITE && cnt != len ) { 1693 ptr += cnt; 1694 len -= cnt; 1695 cnt = 0; 1696 goto again; 1697 } 1698 } 1699 1700 /* 1701 * clear timeouts 1702 */ 1703 s = splsoftclock(); 1704 if( ISSET(mp->mp_flags, MBPPF_TIMEOUT) ) { 1705 callout_stop(&mp->mp_timeout_ch); 1706 CLR(mp->mp_flags, MBPPF_TIMEOUT); 1707 } 1708 if( ISSET(mp->mp_flags, MBPPF_DELAY) ) { 1709 callout_stop(&mp->mp_start_ch); 1710 CLR(mp->mp_flags, MBPPF_DELAY); 1711 } 1712 splx(s); 1713 1714 /* 1715 * adjust for those chars that we uiomoved but never actually wrote 1716 */ 1717 if( uio->uio_rw == UIO_WRITE && cnt != len ) { 1718 uio->uio_resid += (len - cnt); 1719 } 1720 1721 free(buffer, M_DEVBUF); 1722 return(error); 1723 } 1724 1725 void 1726 mbpp_timeout(arg) 1727 void *arg; 1728 { 1729 struct mbpp_port *mp = arg; 1730 1731 CLR(mp->mp_flags, MBPPF_UIO | MBPPF_TIMEOUT); 1732 wakeup(mp); 1733 } 1734 1735 void 1736 mbpp_start(arg) 1737 void *arg; 1738 { 1739 struct mbpp_port *mp = arg; 1740 1741 CLR(mp->mp_flags, MBPPF_DELAY); 1742 wakeup(mp); 1743 } 1744 1745 int 1746 mbpp_send(mp, ptr, len) 1747 struct mbpp_port *mp; 1748 void *ptr; 1749 int len; 1750 { 1751 int s; 1752 struct cd1400 *cd = mp->mp_cd1400; 1753 1754 /* set up io information */ 1755 mp->mp_ptr = ptr; 1756 mp->mp_cnt = len; 1757 1758 /* start transmitting */ 1759 s = spltty(); 1760 if( cd ) { 1761 cd1400_write_reg(cd, CD1400_CAR, 0); 1762 1763 /* output strobe width ~1microsecond */ 1764 cd1400_write_reg(cd, CD1400_TBPR, 10); 1765 1766 /* enable channel */ 1767 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_XMTEN); 1768 cd1400_write_reg(cd, CD1400_SRER, CD1400_SRER_TXRDY); 1769 } 1770 1771 /* ZZzzz... */ 1772 tsleep(mp, PCATCH | PZERO, "mbpp_send", 0); 1773 1774 /* stop transmitting */ 1775 if( cd ) { 1776 cd1400_write_reg(cd, CD1400_CAR, 0); 1777 1778 /* disable transmitter */ 1779 cd1400_write_reg(cd, CD1400_SRER, 0); 1780 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_XMTDIS); 1781 1782 /* flush fifo */ 1783 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET | CD1400_CCR_FTF); 1784 } 1785 splx(s); 1786 1787 /* return number of chars sent */ 1788 return(len - mp->mp_cnt); 1789 } 1790 1791 int 1792 mbpp_recv(mp, ptr, len) 1793 struct mbpp_port *mp; 1794 void *ptr; 1795 int len; 1796 { 1797 int s; 1798 struct cd1400 *cd = mp->mp_cd1400; 1799 1800 /* set up io information */ 1801 mp->mp_ptr = ptr; 1802 mp->mp_cnt = len; 1803 1804 /* start receiving */ 1805 s = spltty(); 1806 if( cd ) { 1807 int rcor, rbpr; 1808 1809 cd1400_write_reg(cd, CD1400_CAR, 0); 1810 1811 /* input strobe at 100kbaud (10microseconds) */ 1812 cd1400_compute_baud(100000, cd->cd_clock, &rcor, &rbpr); 1813 cd1400_write_reg(cd, CD1400_RCOR, rcor); 1814 cd1400_write_reg(cd, CD1400_RBPR, rbpr); 1815 1816 /* rx threshold */ 1817 cd1400_write_reg(cd, CD1400_COR3, MBPP_RX_FIFO_THRESHOLD); 1818 cd1400_write_ccr(cd, CD1400_CCR_CMDCORCHG | CD1400_CCR_COR3); 1819 1820 /* enable channel */ 1821 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_RCVEN); 1822 cd1400_write_reg(cd, CD1400_SRER, CD1400_SRER_RXDATA); 1823 } 1824 1825 /* ZZzzz... */ 1826 tsleep(mp, PCATCH | PZERO, "mbpp_recv", 0); 1827 1828 /* stop receiving */ 1829 if( cd ) { 1830 cd1400_write_reg(cd, CD1400_CAR, 0); 1831 1832 /* disable receiving */ 1833 cd1400_write_reg(cd, CD1400_SRER, 0); 1834 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_RCVDIS); 1835 } 1836 splx(s); 1837 1838 /* return number of chars received */ 1839 return(len - mp->mp_cnt); 1840 } 1841 1842 int 1843 mbpp_hztoms(h) 1844 int h; 1845 { 1846 int m = h; 1847 1848 if( m > 0 ) 1849 m = m * 1000 / hz; 1850 return(m); 1851 } 1852 1853 int 1854 mbpp_mstohz(m) 1855 int m; 1856 { 1857 int h = m; 1858 1859 if( h > 0 ) { 1860 h = h * hz / 1000; 1861 if( h == 0 ) 1862 h = 1000 / hz; 1863 } 1864 return(h); 1865 } 1866 1867 #endif /* NMAGMA */ 1868
Indexes created Thu Oct 02 10:09:58 GMT 2025