magma.c revision 1.49
1 /* $NetBSD: magma.c,v 1.49 2009/03/14 15:36:20 dsl Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 Iain Hibbert 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 /* 29 * Driver for Magma SBus Serial/Parallel cards using the Cirrus Logic 30 * CD1400 & CD1190 chips 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: magma.c,v 1.49 2009/03/14 15:36:20 dsl Exp $"); 35 36 #if 0 37 #define MAGMA_DEBUG 38 #endif 39 40 #include "magma.h" 41 #if NMAGMA > 0 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/proc.h> 46 #include <sys/device.h> 47 #include <sys/file.h> 48 #include <sys/ioctl.h> 49 #include <sys/malloc.h> 50 #include <sys/tty.h> 51 #include <sys/time.h> 52 #include <sys/kernel.h> 53 #include <sys/syslog.h> 54 #include <sys/conf.h> 55 #include <sys/errno.h> 56 #include <sys/kauth.h> 57 #include <sys/intr.h> 58 59 #include <sys/bus.h> 60 #include <machine/autoconf.h> 61 62 #include <dev/sbus/sbusvar.h> 63 64 #include <dev/ic/cd1400reg.h> 65 #include <dev/ic/cd1190reg.h> 66 67 #include <dev/sbus/mbppio.h> 68 #include <dev/sbus/magmareg.h> 69 70 /* supported cards 71 * 72 * The table below lists the cards that this driver is likely to 73 * be able to support. 74 * 75 * Cards with parallel ports: except for the LC2+1Sp, they all use 76 * the CD1190 chip which I know nothing about. I've tried to leave 77 * hooks for it so it shouldn't be too hard to add support later. 78 * (I think somebody is working on this separately) 79 * 80 * Thanks to Bruce at Magma for telling me the hardware offsets. 81 */ 82 static struct magma_board_info supported_cards[] = { 83 { 84 "MAGMA_Sp", "MAGMA,4_Sp", "Magma 4 Sp", 4, 0, 85 1, 0xa000, 0xc000, 0xe000, { 0x8000, 0, 0, 0 }, 86 0, { 0, 0 } 87 }, 88 { 89 "MAGMA_Sp", "MAGMA,8_Sp", "Magma 8 Sp", 8, 0, 90 2, 0xa000, 0xc000, 0xe000, { 0x4000, 0x6000, 0, 0 }, 91 0, { 0, 0 } 92 }, 93 { 94 "MAGMA_Sp", "MAGMA,_8HS_Sp", "Magma Fast 8 Sp", 8, 0, 95 2, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0, 0 }, 96 0, { 0, 0 } 97 }, 98 { 99 "MAGMA_Sp", "MAGMA,_8SP_422", "Magma 8 Sp - 422", 8, 0, 100 2, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0, 0 }, 101 0, { 0, 0 } 102 }, 103 { 104 "MAGMA_Sp", "MAGMA,12_Sp", "Magma 12 Sp", 12, 0, 105 3, 0xa000, 0xc000, 0xe000, { 0x2000, 0x4000, 0x6000, 0 }, 106 0, { 0, 0 } 107 }, 108 { 109 "MAGMA_Sp", "MAGMA,16_Sp", "Magma 16 Sp", 16, 0, 110 4, 0xd000, 0xe000, 0xf000, { 0x8000, 0x9000, 0xa000, 0xb000 }, 111 0, { 0, 0 } 112 }, 113 { 114 "MAGMA_Sp", "MAGMA,16_Sp_2", "Magma 16 Sp", 16, 0, 115 4, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0xc000, 0xe000 }, 116 0, { 0, 0 } 117 }, 118 { 119 "MAGMA_Sp", "MAGMA,16HS_Sp", "Magma Fast 16 Sp", 16, 0, 120 4, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0xc000, 0xe000 }, 121 0, { 0, 0 } 122 }, 123 { 124 "MAGMA_Sp", "MAGMA,21_Sp", "Magma LC 2+1 Sp", 2, 1, 125 1, 0xa000, 0xc000, 0xe000, { 0x8000, 0, 0, 0 }, 126 0, { 0, 0 } 127 }, 128 { 129 "MAGMA_Sp", "MAGMA,21HS_Sp", "Magma 2+1 Sp", 2, 1, 130 1, 0xa000, 0xc000, 0xe000, { 0x4000, 0, 0, 0 }, 131 1, { 0x6000, 0 } 132 }, 133 { 134 "MAGMA_Sp", "MAGMA,41_Sp", "Magma 4+1 Sp", 4, 1, 135 1, 0xa000, 0xc000, 0xe000, { 0x4000, 0, 0, 0 }, 136 1, { 0x6000, 0 } 137 }, 138 { 139 "MAGMA_Sp", "MAGMA,82_Sp", "Magma 8+2 Sp", 8, 2, 140 2, 0xd000, 0xe000, 0xf000, { 0x8000, 0x9000, 0, 0 }, 141 2, { 0xa000, 0xb000 } 142 }, 143 { 144 "MAGMA_Sp", "MAGMA,P1_Sp", "Magma P1 Sp", 0, 1, 145 0, 0, 0, 0, { 0, 0, 0, 0 }, 146 1, { 0x8000, 0 } 147 }, 148 { 149 "MAGMA_Sp", "MAGMA,P2_Sp", "Magma P2 Sp", 0, 2, 150 0, 0, 0, 0, { 0, 0, 0, 0 }, 151 2, { 0x4000, 0x8000 } 152 }, 153 { 154 "MAGMA 2+1HS Sp", "", "Magma 2+1HS Sp", 2, 0, 155 1, 0xa000, 0xc000, 0xe000, { 0x4000, 0, 0, 0 }, 156 1, { 0x8000, 0 } 157 }, 158 { 159 NULL, NULL, NULL, 0, 0, 160 0, 0, 0, 0, { 0, 0, 0, 0 }, 161 0, { 0, 0 } 162 } 163 }; 164 165 /************************************************************************ 166 * 167 * Autoconfig Stuff 168 */ 169 170 CFATTACH_DECL(magma, sizeof(struct magma_softc), 171 magma_match, magma_attach, NULL, NULL); 172 173 CFATTACH_DECL(mtty, sizeof(struct mtty_softc), 174 mtty_match, mtty_attach, NULL, NULL); 175 176 CFATTACH_DECL(mbpp, sizeof(struct mbpp_softc), 177 mbpp_match, mbpp_attach, NULL, NULL); 178 179 extern struct cfdriver mtty_cd; 180 extern struct cfdriver mbpp_cd; 181 182 dev_type_open(mttyopen); 183 dev_type_close(mttyclose); 184 dev_type_read(mttyread); 185 dev_type_write(mttywrite); 186 dev_type_ioctl(mttyioctl); 187 dev_type_stop(mttystop); 188 dev_type_tty(mttytty); 189 dev_type_poll(mttypoll); 190 191 const struct cdevsw mtty_cdevsw = { 192 mttyopen, mttyclose, mttyread, mttywrite, mttyioctl, 193 mttystop, mttytty, mttypoll, nommap, ttykqfilter, D_TTY 194 }; 195 196 dev_type_open(mbppopen); 197 dev_type_close(mbppclose); 198 dev_type_read(mbpp_rw); 199 dev_type_ioctl(mbppioctl); 200 201 const struct cdevsw mbpp_cdevsw = { 202 mbppopen, mbppclose, mbpp_rw, mbpp_rw, mbppioctl, 203 nostop, notty, nopoll, nommap, nokqfilter, D_OTHER 204 }; 205 206 /************************************************************************ 207 * 208 * CD1400 Routines 209 * 210 * cd1400_compute_baud calculate COR/BPR register values 211 * cd1400_write_ccr write a value to CD1400 ccr 212 * cd1400_read_reg read from a CD1400 register 213 * cd1400_write_reg write to a CD1400 register 214 * cd1400_enable_transmitter enable transmitting on CD1400 channel 215 */ 216 217 /* 218 * compute the bpr/cor pair for any baud rate 219 * returns 0 for success, 1 for failure 220 */ 221 int 222 cd1400_compute_baud(speed, clock, cor, bpr) 223 speed_t speed; 224 int clock; 225 int *cor, *bpr; 226 { 227 int c, co, br; 228 229 if( speed < 50 || speed > 150000 ) 230 return(1); 231 232 for( c = 0, co = 8 ; co <= 2048 ; co <<= 2, c++ ) { 233 br = ((clock * 1000000) + (co * speed) / 2) / (co * speed); 234 if( br < 0x100 ) { 235 *bpr = br; 236 *cor = c; 237 return(0); 238 } 239 } 240 241 return(1); 242 } 243 244 /* 245 * Write a CD1400 channel command, should have a timeout? 246 */ 247 inline void 248 cd1400_write_ccr(struct cd1400 *cd, u_char cmd) 249 { 250 while( cd1400_read_reg(cd, CD1400_CCR) ) 251 ; 252 253 cd1400_write_reg(cd, CD1400_CCR, cmd); 254 } 255 256 /* 257 * read a value from a cd1400 register 258 */ 259 inline u_char 260 cd1400_read_reg(struct cd1400 *cd, int reg) 261 { 262 return(cd->cd_reg[reg]); 263 } 264 265 /* 266 * write a value to a cd1400 register 267 */ 268 inline void 269 cd1400_write_reg(struct cd1400 *cd, int reg, u_char value) 270 { 271 cd->cd_reg[reg] = value; 272 } 273 274 /* 275 * enable transmit service requests for cd1400 channel 276 */ 277 void 278 cd1400_enable_transmitter(struct cd1400 *cd, int channel) 279 { 280 int s, srer; 281 282 s = spltty(); 283 cd1400_write_reg(cd, CD1400_CAR, channel); 284 srer = cd1400_read_reg(cd, CD1400_SRER); 285 SET(srer, CD1400_SRER_TXRDY); 286 cd1400_write_reg(cd, CD1400_SRER, srer); 287 splx(s); 288 } 289 290 /************************************************************************ 291 * 292 * CD1190 Routines 293 */ 294 295 /* well, there are none yet */ 296 297 /************************************************************************ 298 * 299 * Magma Routines 300 * 301 * magma_match reports if we have a magma board available 302 * magma_attach attaches magma boards to the sbus 303 * magma_hard hardware level interrupt routine 304 * magma_soft software level interrupt routine 305 */ 306 307 int 308 magma_match(struct device *parent, struct cfdata *cf, void *aux) 309 { 310 struct sbus_attach_args *sa = aux; 311 struct magma_board_info *card; 312 313 /* See if we support this device */ 314 for (card = supported_cards; ; card++) { 315 if (card->mb_sbusname == NULL) 316 /* End of table: no match */ 317 return (0); 318 if (strcmp(sa->sa_name, card->mb_sbusname) == 0) 319 break; 320 } 321 322 dprintf(("magma: matched `%s'\n", sa->sa_name)); 323 dprintf(("magma: magma_prom `%s'\n", 324 prom_getpropstring(sa->sa_node, "magma_prom"))); 325 dprintf(("magma: intlevels `%s'\n", 326 prom_getpropstring(sa->sa_node, "intlevels"))); 327 dprintf(("magma: chiprev `%s'\n", 328 prom_getpropstring(sa->sa_node, "chiprev"))); 329 dprintf(("magma: clock `%s'\n", 330 prom_getpropstring(sa->sa_node, "clock"))); 331 332 return (1); 333 } 334 335 void 336 magma_attach(struct device *parent, struct device *self, void *aux) 337 { 338 struct sbus_attach_args *sa = aux; 339 struct magma_softc *sc = device_private(self); 340 struct magma_board_info *card; 341 bus_space_handle_t bh; 342 char *magma_prom, *clockstr; 343 int cd_clock; 344 int node, chip; 345 346 node = sa->sa_node; 347 348 /* 349 * Find the card model. 350 * Older models all have sbus node name `MAGMA_Sp' (see 351 * `supported_cards[]' above), and must be distinguished 352 * by the `magma_prom' property. 353 */ 354 magma_prom = prom_getpropstring(node, "magma_prom"); 355 356 for (card = supported_cards; card->mb_name != NULL; card++) { 357 if (strcmp(sa->sa_name, card->mb_sbusname) != 0) 358 /* Sbus node name doesn't match */ 359 continue; 360 if (strcmp(magma_prom, card->mb_name) == 0) 361 /* Model name match */ 362 break; 363 } 364 365 if( card->mb_name == NULL ) { 366 printf(": %s (unsupported)\n", magma_prom); 367 return; 368 } 369 370 dprintf((" addr %p", sc)); 371 printf(": %s\n", card->mb_realname); 372 373 sc->ms_board = card; 374 sc->ms_ncd1400 = card->mb_ncd1400; 375 sc->ms_ncd1190 = card->mb_ncd1190; 376 377 if (sbus_bus_map(sa->sa_bustag, 378 sa->sa_slot, sa->sa_offset, sa->sa_size, 379 BUS_SPACE_MAP_LINEAR, &bh) != 0) { 380 aprint_error("%s @ sbus: cannot map registers\n", 381 device_xname(self)); 382 return; 383 } 384 385 /* the SVCACK* lines are daisychained */ 386 sc->ms_svcackr = (char *)bus_space_vaddr(sa->sa_bustag, bh) 387 + card->mb_svcackr; 388 sc->ms_svcackt = (char *)bus_space_vaddr(sa->sa_bustag, bh) 389 + card->mb_svcackt; 390 sc->ms_svcackm = (char *)bus_space_vaddr(sa->sa_bustag, bh) 391 + card->mb_svcackm; 392 393 /* 394 * Find the clock speed; it's the same for all CD1400 chips 395 * on the board. 396 */ 397 clockstr = prom_getpropstring(node, "clock"); 398 if (*clockstr == '\0') 399 /* Default to 25MHz */ 400 cd_clock = 25; 401 else { 402 cd_clock = 0; 403 while (*clockstr != '\0') 404 cd_clock = (cd_clock * 10) + (*clockstr++ - '0'); 405 } 406 407 /* init the cd1400 chips */ 408 for( chip = 0 ; chip < card->mb_ncd1400 ; chip++ ) { 409 struct cd1400 *cd = &sc->ms_cd1400[chip]; 410 411 cd->cd_clock = cd_clock; 412 cd->cd_reg = (char *)bus_space_vaddr(sa->sa_bustag, bh) + 413 card->mb_cd1400[chip]; 414 415 /* prom_getpropstring(node, "chiprev"); */ 416 /* seemingly the Magma drivers just ignore the propstring */ 417 cd->cd_chiprev = cd1400_read_reg(cd, CD1400_GFRCR); 418 419 dprintf(("%s attach CD1400 %d addr %p rev %x clock %dMHz\n", 420 device_xname(&sc->ms_dev), chip, 421 cd->cd_reg, cd->cd_chiprev, cd->cd_clock)); 422 423 /* clear GFRCR */ 424 cd1400_write_reg(cd, CD1400_GFRCR, 0x00); 425 426 /* reset whole chip */ 427 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET | CD1400_CCR_FULLRESET); 428 429 /* wait for revision code to be restored */ 430 while( cd1400_read_reg(cd, CD1400_GFRCR) != cd->cd_chiprev ) 431 ; 432 433 /* set the Prescaler Period Register to tick at 1ms */ 434 cd1400_write_reg(cd, CD1400_PPR, 435 ((cd->cd_clock * 1000000 / CD1400_PPR_PRESCALER + 500) / 1000)); 436 437 /* The LC2+1Sp card is the only card that doesn't have 438 * a CD1190 for the parallel port, but uses channel 0 of 439 * the CD1400, so we make a note of it for later and set up 440 * the CD1400 for parallel mode operation. 441 */ 442 if( card->mb_npar && card->mb_ncd1190 == 0 ) { 443 cd1400_write_reg(cd, CD1400_GCR, CD1400_GCR_PARALLEL); 444 cd->cd_parmode = 1; 445 } 446 } 447 448 /* init the cd1190 chips */ 449 for( chip = 0 ; chip < card->mb_ncd1190 ; chip++ ) { 450 struct cd1190 *cd = &sc->ms_cd1190[chip]; 451 452 cd->cd_reg = (char *)bus_space_vaddr(sa->sa_bustag, bh) + 453 card->mb_cd1190[chip]; 454 455 /* XXX don't know anything about these chips yet */ 456 printf("%s: CD1190 %d addr %p (unsupported)\n", 457 device_xname(self), chip, cd->cd_reg); 458 } 459 460 sbus_establish(&sc->ms_sd, &sc->ms_dev); 461 462 /* configure the children */ 463 (void)config_found(self, mtty_match, NULL); 464 (void)config_found(self, mbpp_match, NULL); 465 466 /* 467 * Establish the interrupt handlers. 468 */ 469 if (sa->sa_nintr == 0) 470 return; /* No interrupts to service!? */ 471 472 (void)bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_SERIAL, 473 magma_hard, sc); 474 sc->ms_sicookie = softint_establish(SOFTINT_SERIAL, magma_soft, sc); 475 if (sc->ms_sicookie == NULL) { 476 aprint_normal("\n"); 477 aprint_error_dev(&sc->ms_dev, "cannot establish soft int handler\n"); 478 return; 479 } 480 evcnt_attach_dynamic(&sc->ms_intrcnt, EVCNT_TYPE_INTR, NULL, 481 device_xname(&sc->ms_dev), "intr"); 482 } 483 484 /* 485 * hard interrupt routine 486 * 487 * returns 1 if it handled it, otherwise 0 488 * 489 * runs at IPL_SERIAL 490 */ 491 int 492 magma_hard(void *arg) 493 { 494 struct magma_softc *sc = arg; 495 struct cd1400 *cd; 496 int chip, status = 0; 497 int serviced = 0; 498 int needsoftint = 0; 499 500 /* 501 * check status of all the CD1400 chips 502 */ 503 for( chip = 0 ; chip < sc->ms_ncd1400 ; chip++ ) 504 status |= cd1400_read_reg(&sc->ms_cd1400[chip], CD1400_SVRR); 505 506 if( ISSET(status, CD1400_SVRR_RXRDY) ) { 507 u_char rivr = *sc->ms_svcackr; /* enter rx service context */ 508 int port = rivr >> 4; 509 510 if( rivr & (1<<3) ) { /* parallel port */ 511 struct mbpp_port *mbpp; 512 int n_chars; 513 514 mbpp = &sc->ms_mbpp->ms_port[port]; 515 cd = mbpp->mp_cd1400; 516 517 /* don't think we have to handle exceptions */ 518 n_chars = cd1400_read_reg(cd, CD1400_RDCR); 519 while (n_chars--) { 520 if( mbpp->mp_cnt == 0 ) { 521 SET(mbpp->mp_flags, MBPPF_WAKEUP); 522 needsoftint = 1; 523 break; 524 } 525 *mbpp->mp_ptr = cd1400_read_reg(cd,CD1400_RDSR); 526 mbpp->mp_ptr++; 527 mbpp->mp_cnt--; 528 } 529 } else { /* serial port */ 530 struct mtty_port *mtty; 531 u_char *ptr, n_chars, line_stat; 532 533 mtty = &sc->ms_mtty->ms_port[port]; 534 cd = mtty->mp_cd1400; 535 536 if( ISSET(rivr, CD1400_RIVR_EXCEPTION) ) { 537 line_stat = cd1400_read_reg(cd, CD1400_RDSR); 538 n_chars = 1; 539 } else { /* no exception, received data OK */ 540 line_stat = 0; 541 n_chars = cd1400_read_reg(cd, CD1400_RDCR); 542 } 543 544 ptr = mtty->mp_rput; 545 while( n_chars-- ) { 546 *ptr++ = line_stat; 547 *ptr++ = cd1400_read_reg(cd, CD1400_RDSR); 548 if( ptr == mtty->mp_rend ) ptr = mtty->mp_rbuf; 549 if( ptr == mtty->mp_rget ) { 550 if( ptr == mtty->mp_rbuf ) 551 ptr = mtty->mp_rend; 552 ptr -= 2; 553 SET(mtty->mp_flags, MTTYF_RING_OVERFLOW); 554 break; 555 } 556 } 557 mtty->mp_rput = ptr; 558 559 needsoftint = 1; 560 } 561 562 cd1400_write_reg(cd, CD1400_EOSRR, 0); /* end service context */ 563 serviced = 1; 564 } /* if(rx_service...) */ 565 566 if( ISSET(status, CD1400_SVRR_MDMCH) ) { 567 u_char mivr = *sc->ms_svcackm; /* enter mdm service context */ 568 int port = mivr >> 4; 569 struct mtty_port *mtty; 570 int carrier; 571 u_char msvr; 572 573 /* 574 * Handle CD (LC2+1Sp = DSR) changes. 575 */ 576 mtty = &sc->ms_mtty->ms_port[port]; 577 cd = mtty->mp_cd1400; 578 msvr = cd1400_read_reg(cd, CD1400_MSVR2); 579 carrier = ISSET(msvr, cd->cd_parmode ? CD1400_MSVR2_DSR : CD1400_MSVR2_CD); 580 581 if( mtty->mp_carrier != carrier ) { 582 SET(mtty->mp_flags, MTTYF_CARRIER_CHANGED); 583 mtty->mp_carrier = carrier; 584 needsoftint = 1; 585 } 586 587 cd1400_write_reg(cd, CD1400_EOSRR, 0); /* end service context */ 588 serviced = 1; 589 } /* if(mdm_service...) */ 590 591 if( ISSET(status, CD1400_SVRR_TXRDY) ) { 592 u_char tivr = *sc->ms_svcackt; /* enter tx service context */ 593 int port = tivr >> 4; 594 595 if( tivr & (1<<3) ) { /* parallel port */ 596 struct mbpp_port *mbpp; 597 598 mbpp = &sc->ms_mbpp->ms_port[port]; 599 cd = mbpp->mp_cd1400; 600 601 if( mbpp->mp_cnt ) { 602 int count = 0; 603 604 /* fill the fifo */ 605 while (mbpp->mp_cnt && 606 count++ < CD1400_PAR_FIFO_SIZE) { 607 cd1400_write_reg(cd, CD1400_TDR, 608 *mbpp->mp_ptr); 609 mbpp->mp_ptr++; 610 mbpp->mp_cnt--; 611 } 612 } else { 613 /* 614 * fifo is empty and we got no more data 615 * to send, so shut off interrupts and 616 * signal for a wakeup, which can't be 617 * done here in case we beat mbpp_send to 618 * the tsleep call (we are running at >spltty) 619 */ 620 cd1400_write_reg(cd, CD1400_SRER, 0); 621 SET(mbpp->mp_flags, MBPPF_WAKEUP); 622 needsoftint = 1; 623 } 624 } else { /* serial port */ 625 struct mtty_port *mtty; 626 struct tty *tp; 627 628 mtty = &sc->ms_mtty->ms_port[port]; 629 cd = mtty->mp_cd1400; 630 tp = mtty->mp_tty; 631 632 if( !ISSET(mtty->mp_flags, MTTYF_STOP) ) { 633 int count = 0; 634 635 /* check if we should start/stop a break */ 636 if( ISSET(mtty->mp_flags, MTTYF_SET_BREAK) ) { 637 cd1400_write_reg(cd, CD1400_TDR, 0); 638 cd1400_write_reg(cd, CD1400_TDR, 0x81); 639 /* should we delay too? */ 640 CLR(mtty->mp_flags, MTTYF_SET_BREAK); 641 count += 2; 642 } 643 644 if( ISSET(mtty->mp_flags, MTTYF_CLR_BREAK) ) { 645 cd1400_write_reg(cd, CD1400_TDR, 0); 646 cd1400_write_reg(cd, CD1400_TDR, 0x83); 647 CLR(mtty->mp_flags, MTTYF_CLR_BREAK); 648 count += 2; 649 } 650 651 /* I don't quite fill the fifo in case the last one is a 652 * NULL which I have to double up because its the escape 653 * code for embedded transmit characters. 654 */ 655 while( mtty->mp_txc > 0 && count < CD1400_TX_FIFO_SIZE - 1 ) { 656 u_char ch; 657 658 ch = *mtty->mp_txp; 659 660 mtty->mp_txc--; 661 mtty->mp_txp++; 662 663 if( ch == 0 ) { 664 cd1400_write_reg(cd, CD1400_TDR, ch); 665 count++; 666 } 667 668 cd1400_write_reg(cd, CD1400_TDR, ch); 669 count++; 670 } 671 } 672 673 /* if we ran out of work or are requested to STOP then 674 * shut off the txrdy interrupts and signal DONE to flush 675 * out the chars we have sent. 676 */ 677 if( mtty->mp_txc == 0 || ISSET(mtty->mp_flags, MTTYF_STOP) ) { 678 register int srer; 679 680 srer = cd1400_read_reg(cd, CD1400_SRER); 681 CLR(srer, CD1400_SRER_TXRDY); 682 cd1400_write_reg(cd, CD1400_SRER, srer); 683 CLR(mtty->mp_flags, MTTYF_STOP); 684 685 SET(mtty->mp_flags, MTTYF_DONE); 686 needsoftint = 1; 687 } 688 } 689 690 cd1400_write_reg(cd, CD1400_EOSRR, 0); /* end service context */ 691 serviced = 1; 692 } /* if(tx_service...) */ 693 694 /* XXX service CD1190 interrupts too 695 for( chip = 0 ; chip < sc->ms_ncd1190 ; chip++ ) { 696 } 697 */ 698 699 if (needsoftint) 700 /* trigger the soft interrupt */ 701 softint_schedule(sc->ms_sicookie); 702 703 return(serviced); 704 } 705 706 /* 707 * magma soft interrupt handler 708 * 709 * runs at IPL_SOFTSERIAL 710 */ 711 void 712 magma_soft(void *arg) 713 { 714 struct magma_softc *sc = arg; 715 struct mtty_softc *mtty = sc->ms_mtty; 716 struct mbpp_softc *mbpp = sc->ms_mbpp; 717 int port; 718 int s, flags; 719 720 if (mtty == NULL) 721 goto chkbpp; 722 723 /* 724 * check the tty ports to see what needs doing 725 */ 726 for( port = 0 ; port < mtty->ms_nports ; port++ ) { 727 struct mtty_port *mp = &mtty->ms_port[port]; 728 struct tty *tp = mp->mp_tty; 729 730 if( !ISSET(tp->t_state, TS_ISOPEN) ) 731 continue; 732 733 /* 734 * handle any received data 735 */ 736 while( mp->mp_rget != mp->mp_rput ) { 737 u_char stat; 738 int data; 739 740 stat = mp->mp_rget[0]; 741 data = mp->mp_rget[1]; 742 mp->mp_rget = ((mp->mp_rget + 2) == mp->mp_rend) 743 ? mp->mp_rbuf : (mp->mp_rget + 2); 744 745 if( stat & (CD1400_RDSR_BREAK | CD1400_RDSR_FE) ) 746 data |= TTY_FE; 747 if( stat & CD1400_RDSR_PE ) 748 data |= TTY_PE; 749 750 if( stat & CD1400_RDSR_OE ) 751 log(LOG_WARNING, "%s%x: fifo overflow\n", 752 device_xname(&mtty->ms_dev), port); 753 754 (*tp->t_linesw->l_rint)(data, tp); 755 } 756 757 s = splserial(); /* block out hard interrupt routine */ 758 flags = mp->mp_flags; 759 CLR(mp->mp_flags, MTTYF_DONE | MTTYF_CARRIER_CHANGED | MTTYF_RING_OVERFLOW); 760 splx(s); /* ok */ 761 762 if( ISSET(flags, MTTYF_CARRIER_CHANGED) ) { 763 dprintf(("%s%x: cd %s\n", device_xname(&mtty->ms_dev), 764 port, mp->mp_carrier ? "on" : "off")); 765 (*tp->t_linesw->l_modem)(tp, mp->mp_carrier); 766 } 767 768 if( ISSET(flags, MTTYF_RING_OVERFLOW) ) { 769 log(LOG_WARNING, "%s%x: ring buffer overflow\n", 770 device_xname(&mtty->ms_dev), port); 771 } 772 773 if( ISSET(flags, MTTYF_DONE) ) { 774 ndflush(&tp->t_outq, mp->mp_txp - tp->t_outq.c_cf); 775 CLR(tp->t_state, TS_BUSY); 776 (*tp->t_linesw->l_start)(tp); /* might be some more */ 777 } 778 } /* for(each mtty...) */ 779 780 781 chkbpp: 782 /* 783 * Check the bpp ports (if any) to see what needs doing 784 */ 785 if (mbpp == NULL) 786 return; 787 788 for( port = 0 ; port < mbpp->ms_nports ; port++ ) { 789 struct mbpp_port *mp = &mbpp->ms_port[port]; 790 791 if( !ISSET(mp->mp_flags, MBPPF_OPEN) ) 792 continue; 793 794 s = splserial(); 795 flags = mp->mp_flags; 796 CLR(mp->mp_flags, MBPPF_WAKEUP); 797 splx(s); 798 799 if( ISSET(flags, MBPPF_WAKEUP) ) { 800 wakeup(mp); 801 } 802 803 } /* for(each mbpp...) */ 804 } 805 806 /************************************************************************ 807 * 808 * MTTY Routines 809 * 810 * mtty_match match one mtty device 811 * mtty_attach attach mtty devices 812 * mttyopen open mtty device 813 * mttyclose close mtty device 814 * mttyread read from mtty 815 * mttywrite write to mtty 816 * mttyioctl do ioctl on mtty 817 * mttytty return tty pointer for mtty 818 * mttystop stop mtty device 819 * mtty_start start mtty device 820 * mtty_param set mtty parameters 821 * mtty_modem_control set modem control lines 822 */ 823 824 int 825 mtty_match(struct device *parent, struct cfdata *cf, void *args) 826 { 827 struct magma_softc *sc = device_private(parent); 828 829 return( args == mtty_match && sc->ms_board->mb_nser && sc->ms_mtty == NULL ); 830 } 831 832 void 833 mtty_attach(struct device *parent, struct device *dev, void *args) 834 { 835 struct magma_softc *sc = device_private(parent); 836 struct mtty_softc *ms = device_private(dev); 837 int port, chip, chan; 838 839 sc->ms_mtty = ms; 840 dprintf((" addr %p", ms)); 841 842 for( port = 0, chip = 0, chan = 0 ; port < sc->ms_board->mb_nser ; port++ ) { 843 struct mtty_port *mp = &ms->ms_port[port]; 844 struct tty *tp; 845 846 mp->mp_cd1400 = &sc->ms_cd1400[chip]; 847 if (mp->mp_cd1400->cd_parmode && chan == 0) 848 chan = 1; /* skip channel 0 if parmode */ 849 mp->mp_channel = chan; 850 851 tp = ttymalloc(); 852 if (tp == NULL) break; 853 tty_attach(tp); 854 tp->t_oproc = mtty_start; 855 tp->t_param = mtty_param; 856 857 mp->mp_tty = tp; 858 859 mp->mp_rbuf = malloc(MTTY_RBUF_SIZE, M_DEVBUF, M_NOWAIT); 860 if (mp->mp_rbuf == NULL) break; 861 862 mp->mp_rend = mp->mp_rbuf + MTTY_RBUF_SIZE; 863 864 chan = (chan + 1) % CD1400_NO_OF_CHANNELS; 865 if (chan == 0) 866 chip++; 867 } 868 869 ms->ms_nports = port; 870 printf(": %d tty%s\n", port, port == 1 ? "" : "s"); 871 } 872 873 /* 874 * open routine. returns zero if successful, else error code 875 */ 876 int 877 mttyopen(dev_t dev, int flags, int mode, struct lwp *l) 878 { 879 int card = MAGMA_CARD(dev); 880 int port = MAGMA_PORT(dev); 881 struct mtty_softc *ms; 882 struct mtty_port *mp; 883 struct tty *tp; 884 struct cd1400 *cd; 885 int error, s; 886 887 if ((ms = device_lookup_private(&mtty_cd, card)) == NULL 888 || port >= ms->ms_nports ) 889 return(ENXIO); /* device not configured */ 890 891 mp = &ms->ms_port[port]; 892 tp = mp->mp_tty; 893 tp->t_dev = dev; 894 895 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 896 return (EBUSY); 897 898 s = spltty(); 899 900 if( !ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 901 902 /* set defaults */ 903 ttychars(tp); 904 tp->t_iflag = TTYDEF_IFLAG; 905 tp->t_oflag = TTYDEF_OFLAG; 906 tp->t_cflag = TTYDEF_CFLAG; 907 if( ISSET(mp->mp_openflags, TIOCFLAG_CLOCAL) ) 908 SET(tp->t_cflag, CLOCAL); 909 if( ISSET(mp->mp_openflags, TIOCFLAG_CRTSCTS) ) 910 SET(tp->t_cflag, CRTSCTS); 911 if( ISSET(mp->mp_openflags, TIOCFLAG_MDMBUF) ) 912 SET(tp->t_cflag, MDMBUF); 913 tp->t_lflag = TTYDEF_LFLAG; 914 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 915 916 /* init ring buffer */ 917 mp->mp_rput = mp->mp_rget = mp->mp_rbuf; 918 919 /* reset CD1400 channel */ 920 cd = mp->mp_cd1400; 921 cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel); 922 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET); 923 924 /* encode the port number in top half of LIVR */ 925 cd1400_write_reg(cd, CD1400_LIVR, port << 4 ); 926 927 /* sets parameters and raises DTR */ 928 (void)mtty_param(tp, &tp->t_termios); 929 930 /* set tty watermarks */ 931 ttsetwater(tp); 932 933 /* enable service requests */ 934 cd1400_write_reg(cd, CD1400_SRER, 935 CD1400_SRER_RXDATA | CD1400_SRER_MDMCH); 936 937 /* tell the tty about the carrier status */ 938 if( ISSET(mp->mp_openflags, TIOCFLAG_SOFTCAR) || 939 mp->mp_carrier ) 940 SET(tp->t_state, TS_CARR_ON); 941 else 942 CLR(tp->t_state, TS_CARR_ON); 943 } 944 splx(s); 945 946 error = ttyopen(tp, MTTY_DIALOUT(dev), ISSET(flags, O_NONBLOCK)); 947 if (error != 0) 948 goto bad; 949 950 error = (*tp->t_linesw->l_open)(dev, tp); 951 if (error != 0) 952 goto bad; 953 954 bad: 955 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 956 /* 957 * We failed to open the device, and nobody else had it opened. 958 * Clean up the state as appropriate. 959 */ 960 /* XXX - do that here */ 961 } 962 963 return (error); 964 } 965 966 /* 967 * close routine. returns zero if successful, else error code 968 */ 969 int 970 mttyclose(dev_t dev, int flag, int mode, struct lwp *l) 971 { 972 struct mtty_softc *ms = device_lookup_private(&mtty_cd, 973 MAGMA_CARD(dev)); 974 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 975 struct tty *tp = mp->mp_tty; 976 int s; 977 978 (*tp->t_linesw->l_close)(tp, flag); 979 ttyclose(tp); 980 981 s = spltty(); 982 983 /* if HUPCL is set, and the tty is no longer open 984 * shut down the port 985 */ 986 if( ISSET(tp->t_cflag, HUPCL) || !ISSET(tp->t_state, TS_ISOPEN) ) { 987 /* XXX wait until FIFO is empty before turning off the channel 988 struct cd1400 *cd = mp->mp_cd1400; 989 */ 990 991 /* drop DTR and RTS */ 992 (void)mtty_modem_control(mp, 0, DMSET); 993 994 /* turn off the channel 995 cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel); 996 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET); 997 */ 998 } 999 1000 splx(s); 1001 1002 return(0); 1003 } 1004 1005 /* 1006 * Read routine 1007 */ 1008 int 1009 mttyread(dev_t dev, struct uio *uio, int flags) 1010 { 1011 struct mtty_softc *ms = device_lookup_private(&mtty_cd, 1012 MAGMA_CARD(dev)); 1013 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1014 struct tty *tp = mp->mp_tty; 1015 1016 return( (*tp->t_linesw->l_read)(tp, uio, flags) ); 1017 } 1018 1019 /* 1020 * Write routine 1021 */ 1022 int 1023 mttywrite(dev_t dev, struct uio *uio, int flags) 1024 { 1025 struct mtty_softc *ms = device_lookup_private(&mtty_cd, 1026 MAGMA_CARD(dev)); 1027 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1028 struct tty *tp = mp->mp_tty; 1029 1030 return( (*tp->t_linesw->l_write)(tp, uio, flags) ); 1031 } 1032 1033 /* 1034 * Poll routine 1035 */ 1036 int 1037 mttypoll(dev_t dev, int events, struct lwp *l) 1038 { 1039 struct mtty_softc *ms = device_lookup_private(&mtty_cd, 1040 MAGMA_CARD(dev)); 1041 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1042 struct tty *tp = mp->mp_tty; 1043 1044 return ((*tp->t_linesw->l_poll)(tp, events, l)); 1045 } 1046 1047 /* 1048 * return tty pointer 1049 */ 1050 struct tty * 1051 mttytty(dev_t dev) 1052 { 1053 struct mtty_softc *ms = device_lookup_private(&mtty_cd, 1054 MAGMA_CARD(dev)); 1055 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1056 1057 return(mp->mp_tty); 1058 } 1059 1060 /* 1061 * ioctl routine 1062 */ 1063 int 1064 mttyioctl(dev_t dev, u_long cmd, void *data, int flags, struct lwp *l) 1065 { 1066 struct mtty_softc *ms = device_lookup_private(&mtty_cd, 1067 MAGMA_CARD(dev)); 1068 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1069 struct tty *tp = mp->mp_tty; 1070 int error; 1071 1072 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flags, l); 1073 if( error != EPASSTHROUGH ) return(error); 1074 1075 error = ttioctl(tp, cmd, data, flags, l); 1076 if( error != EPASSTHROUGH ) return(error); 1077 1078 error = 0; 1079 1080 switch(cmd) { 1081 case TIOCSBRK: /* set break */ 1082 SET(mp->mp_flags, MTTYF_SET_BREAK); 1083 cd1400_enable_transmitter(mp->mp_cd1400, mp->mp_channel); 1084 break; 1085 1086 case TIOCCBRK: /* clear break */ 1087 SET(mp->mp_flags, MTTYF_CLR_BREAK); 1088 cd1400_enable_transmitter(mp->mp_cd1400, mp->mp_channel); 1089 break; 1090 1091 case TIOCSDTR: /* set DTR */ 1092 mtty_modem_control(mp, TIOCM_DTR, DMBIS); 1093 break; 1094 1095 case TIOCCDTR: /* clear DTR */ 1096 mtty_modem_control(mp, TIOCM_DTR, DMBIC); 1097 break; 1098 1099 case TIOCMSET: /* set modem lines */ 1100 mtty_modem_control(mp, *((int *)data), DMSET); 1101 break; 1102 1103 case TIOCMBIS: /* bit set modem lines */ 1104 mtty_modem_control(mp, *((int *)data), DMBIS); 1105 break; 1106 1107 case TIOCMBIC: /* bit clear modem lines */ 1108 mtty_modem_control(mp, *((int *)data), DMBIC); 1109 break; 1110 1111 case TIOCMGET: /* get modem lines */ 1112 *((int *)data) = mtty_modem_control(mp, 0, DMGET); 1113 break; 1114 1115 case TIOCGFLAGS: 1116 *((int *)data) = mp->mp_openflags; 1117 break; 1118 1119 case TIOCSFLAGS: 1120 if (kauth_authorize_device_tty(l->l_cred, 1121 KAUTH_DEVICE_TTY_PRIVSET, tp)) 1122 error = EPERM; 1123 else 1124 mp->mp_openflags = *((int *)data) & 1125 (TIOCFLAG_SOFTCAR | TIOCFLAG_CLOCAL | 1126 TIOCFLAG_CRTSCTS | TIOCFLAG_MDMBUF); 1127 break; 1128 1129 default: 1130 error = EPASSTHROUGH; 1131 } 1132 1133 return(error); 1134 } 1135 1136 /* 1137 * Stop output, e.g., for ^S or output flush. 1138 */ 1139 void 1140 mttystop(struct tty *tp, int flags) 1141 { 1142 struct mtty_softc *ms = device_lookup_private(&mtty_cd, 1143 MAGMA_CARD(tp->t_dev)); 1144 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(tp->t_dev)]; 1145 int s; 1146 1147 s = spltty(); 1148 1149 if( ISSET(tp->t_state, TS_BUSY) ) { 1150 if( !ISSET(tp->t_state, TS_TTSTOP) ) 1151 SET(tp->t_state, TS_FLUSH); 1152 1153 /* 1154 * the transmit interrupt routine will disable transmit when it 1155 * notices that MTTYF_STOP has been set. 1156 */ 1157 SET(mp->mp_flags, MTTYF_STOP); 1158 } 1159 1160 splx(s); 1161 } 1162 1163 /* 1164 * Start output, after a stop. 1165 */ 1166 void 1167 mtty_start(struct tty *tp) 1168 { 1169 struct mtty_softc *ms = device_lookup_private(&mtty_cd, 1170 MAGMA_CARD(tp->t_dev)); 1171 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(tp->t_dev)]; 1172 int s; 1173 1174 s = spltty(); 1175 1176 /* we only need to do something if we are not already busy 1177 * or delaying or stopped 1178 */ 1179 if( !ISSET(tp->t_state, TS_TTSTOP | TS_TIMEOUT | TS_BUSY) ) { 1180 if (ttypull(tp)) { 1181 mp->mp_txc = ndqb(&tp->t_outq, 0); 1182 mp->mp_txp = tp->t_outq.c_cf; 1183 SET(tp->t_state, TS_BUSY); 1184 cd1400_enable_transmitter(mp->mp_cd1400, mp->mp_channel); 1185 } 1186 } 1187 1188 splx(s); 1189 } 1190 1191 /* 1192 * set/get modem line status 1193 * 1194 * bits can be: TIOCM_DTR, TIOCM_RTS, TIOCM_CTS, TIOCM_CD, TIOCM_RI, TIOCM_DSR 1195 * 1196 * note that DTR and RTS lines are exchanged, and that DSR is 1197 * not available on the LC2+1Sp card (used as CD) 1198 * 1199 * only let them fiddle with RTS if CRTSCTS is not enabled 1200 */ 1201 int 1202 mtty_modem_control(struct mtty_port *mp, int bits, int howto) 1203 { 1204 struct cd1400 *cd = mp->mp_cd1400; 1205 struct tty *tp = mp->mp_tty; 1206 int s, msvr; 1207 1208 s = spltty(); 1209 1210 cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel); 1211 1212 switch(howto) { 1213 case DMGET: /* get bits */ 1214 bits = 0; 1215 1216 bits |= TIOCM_LE; 1217 1218 msvr = cd1400_read_reg(cd, CD1400_MSVR1); 1219 if( msvr & CD1400_MSVR1_RTS ) bits |= TIOCM_DTR; 1220 1221 msvr = cd1400_read_reg(cd, CD1400_MSVR2); 1222 if( msvr & CD1400_MSVR2_DTR ) bits |= TIOCM_RTS; 1223 if( msvr & CD1400_MSVR2_CTS ) bits |= TIOCM_CTS; 1224 if( msvr & CD1400_MSVR2_RI ) bits |= TIOCM_RI; 1225 if( msvr & CD1400_MSVR2_DSR ) bits |= (cd->cd_parmode ? TIOCM_CD : TIOCM_DSR); 1226 if( msvr & CD1400_MSVR2_CD ) bits |= (cd->cd_parmode ? 0 : TIOCM_CD); 1227 1228 break; 1229 1230 case DMSET: /* reset bits */ 1231 if( !ISSET(tp->t_cflag, CRTSCTS) ) 1232 cd1400_write_reg(cd, CD1400_MSVR2, ((bits & TIOCM_RTS) ? CD1400_MSVR2_DTR : 0)); 1233 1234 cd1400_write_reg(cd, CD1400_MSVR1, ((bits & TIOCM_DTR) ? CD1400_MSVR1_RTS : 0)); 1235 1236 break; 1237 1238 case DMBIS: /* set bits */ 1239 if( (bits & TIOCM_RTS) && !ISSET(tp->t_cflag, CRTSCTS) ) 1240 cd1400_write_reg(cd, CD1400_MSVR2, CD1400_MSVR2_DTR); 1241 1242 if( bits & TIOCM_DTR ) 1243 cd1400_write_reg(cd, CD1400_MSVR1, CD1400_MSVR1_RTS); 1244 1245 break; 1246 1247 case DMBIC: /* clear bits */ 1248 if( (bits & TIOCM_RTS) && !ISSET(tp->t_cflag, CRTSCTS) ) 1249 cd1400_write_reg(cd, CD1400_MSVR2, 0); 1250 1251 if( bits & TIOCM_DTR ) 1252 cd1400_write_reg(cd, CD1400_MSVR1, 0); 1253 1254 break; 1255 } 1256 1257 splx(s); 1258 return(bits); 1259 } 1260 1261 /* 1262 * Set tty parameters, returns error or 0 on success 1263 */ 1264 int 1265 mtty_param(struct tty *tp, struct termios *t) 1266 { 1267 struct mtty_softc *ms = device_lookup_private(&mtty_cd, 1268 MAGMA_CARD(tp->t_dev)); 1269 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(tp->t_dev)]; 1270 struct cd1400 *cd = mp->mp_cd1400; 1271 int rbpr, tbpr, rcor, tcor; 1272 u_char mcor1 = 0, mcor2 = 0; 1273 int s, opt; 1274 1275 if( t->c_ospeed && cd1400_compute_baud(t->c_ospeed, cd->cd_clock, &tcor, &tbpr) ) 1276 return(EINVAL); 1277 1278 if( t->c_ispeed && cd1400_compute_baud(t->c_ispeed, cd->cd_clock, &rcor, &rbpr) ) 1279 return(EINVAL); 1280 1281 s = spltty(); 1282 1283 /* hang up the line if ospeed is zero, else raise DTR */ 1284 (void)mtty_modem_control(mp, TIOCM_DTR, (t->c_ospeed == 0 ? DMBIC : DMBIS)); 1285 1286 /* select channel, done in mtty_modem_control() */ 1287 /* cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel); */ 1288 1289 /* set transmit speed */ 1290 if( t->c_ospeed ) { 1291 cd1400_write_reg(cd, CD1400_TCOR, tcor); 1292 cd1400_write_reg(cd, CD1400_TBPR, tbpr); 1293 } 1294 1295 /* set receive speed */ 1296 if( t->c_ispeed ) { 1297 cd1400_write_reg(cd, CD1400_RCOR, rcor); 1298 cd1400_write_reg(cd, CD1400_RBPR, rbpr); 1299 } 1300 1301 /* enable transmitting and receiving on this channel */ 1302 opt = CD1400_CCR_CMDCHANCTL | CD1400_CCR_XMTEN | CD1400_CCR_RCVEN; 1303 cd1400_write_ccr(cd, opt); 1304 1305 /* set parity, data and stop bits */ 1306 opt = 0; 1307 if( ISSET(t->c_cflag, PARENB) ) 1308 opt |= (ISSET(t->c_cflag, PARODD) ? CD1400_COR1_PARODD : CD1400_COR1_PARNORMAL); 1309 1310 if( !ISSET(t->c_iflag, INPCK) ) 1311 opt |= CD1400_COR1_NOINPCK; /* no parity checking */ 1312 1313 if( ISSET(t->c_cflag, CSTOPB) ) 1314 opt |= CD1400_COR1_STOP2; 1315 1316 switch( t->c_cflag & CSIZE ) { 1317 case CS5: 1318 opt |= CD1400_COR1_CS5; 1319 break; 1320 1321 case CS6: 1322 opt |= CD1400_COR1_CS6; 1323 break; 1324 1325 case CS7: 1326 opt |= CD1400_COR1_CS7; 1327 break; 1328 1329 default: 1330 opt |= CD1400_COR1_CS8; 1331 break; 1332 } 1333 1334 cd1400_write_reg(cd, CD1400_COR1, opt); 1335 1336 /* 1337 * enable Embedded Transmit Commands (for breaks) 1338 * use the CD1400 automatic CTS flow control if CRTSCTS is set 1339 */ 1340 opt = CD1400_COR2_ETC; 1341 if( ISSET(t->c_cflag, CRTSCTS) ) opt |= CD1400_COR2_CCTS_OFLOW; 1342 cd1400_write_reg(cd, CD1400_COR2, opt); 1343 1344 cd1400_write_reg(cd, CD1400_COR3, MTTY_RX_FIFO_THRESHOLD); 1345 1346 cd1400_write_ccr(cd, CD1400_CCR_CMDCORCHG | CD1400_CCR_COR1 | CD1400_CCR_COR2 | CD1400_CCR_COR3); 1347 1348 cd1400_write_reg(cd, CD1400_COR4, CD1400_COR4_PFO_EXCEPTION); 1349 cd1400_write_reg(cd, CD1400_COR5, 0); 1350 1351 /* 1352 * if automatic RTS handshaking enabled, set DTR threshold 1353 * (RTS and DTR lines are switched, CD1400 thinks its DTR) 1354 */ 1355 if( ISSET(t->c_cflag, CRTSCTS) ) 1356 mcor1 = MTTY_RX_DTR_THRESHOLD; 1357 1358 /* set up `carrier detect' interrupts */ 1359 if( cd->cd_parmode ) { 1360 SET(mcor1, CD1400_MCOR1_DSRzd); 1361 SET(mcor2, CD1400_MCOR2_DSRod); 1362 } else { 1363 SET(mcor1, CD1400_MCOR1_CDzd); 1364 SET(mcor2, CD1400_MCOR2_CDod); 1365 } 1366 1367 cd1400_write_reg(cd, CD1400_MCOR1, mcor1); 1368 cd1400_write_reg(cd, CD1400_MCOR2, mcor2); 1369 1370 /* receive timeout 2ms */ 1371 cd1400_write_reg(cd, CD1400_RTPR, 2); 1372 1373 splx(s); 1374 return(0); 1375 } 1376 1377 /************************************************************************ 1378 * 1379 * MBPP Routines 1380 * 1381 * mbpp_match match one mbpp device 1382 * mbpp_attach attach mbpp devices 1383 * mbppopen open mbpp device 1384 * mbppclose close mbpp device 1385 * mbppioctl do ioctl on mbpp 1386 * mbpp_rw general rw routine 1387 * mbpp_timeout rw timeout 1388 * mbpp_start rw start after delay 1389 * mbpp_send send data 1390 * mbpp_recv recv data 1391 */ 1392 1393 int 1394 mbpp_match(struct device *parent, struct cfdata *cf, void *args) 1395 { 1396 struct magma_softc *sc = device_private(parent); 1397 1398 return( args == mbpp_match && sc->ms_board->mb_npar && sc->ms_mbpp == NULL ); 1399 } 1400 1401 void 1402 mbpp_attach(struct device *parent, struct device *dev, void *args) 1403 { 1404 struct magma_softc *sc = device_private(parent); 1405 struct mbpp_softc *ms = device_private(dev); 1406 struct mbpp_port *mp; 1407 int port; 1408 1409 sc->ms_mbpp = ms; 1410 dprintf((" addr %p", ms)); 1411 1412 for( port = 0 ; port < sc->ms_board->mb_npar ; port++ ) { 1413 mp = &ms->ms_port[port]; 1414 1415 callout_init(&mp->mp_timeout_ch, 0); 1416 callout_init(&mp->mp_start_ch, 0); 1417 1418 if( sc->ms_ncd1190 ) 1419 mp->mp_cd1190 = &sc->ms_cd1190[port]; 1420 else 1421 mp->mp_cd1400 = &sc->ms_cd1400[0]; 1422 } 1423 1424 ms->ms_nports = port; 1425 printf(": %d port%s\n", port, port == 1 ? "" : "s"); 1426 } 1427 1428 /* 1429 * open routine. returns zero if successful, else error code 1430 */ 1431 int 1432 mbppopen(dev_t dev, int flags, int mode, struct lwp *l) 1433 { 1434 int card = MAGMA_CARD(dev); 1435 int port = MAGMA_PORT(dev); 1436 struct mbpp_softc *ms; 1437 struct mbpp_port *mp; 1438 int s; 1439 1440 if ((ms = device_lookup_private(&mbpp_cd, card)) == NULL 1441 || port >= ms->ms_nports ) 1442 return(ENXIO); 1443 1444 mp = &ms->ms_port[port]; 1445 1446 s = spltty(); 1447 if( ISSET(mp->mp_flags, MBPPF_OPEN) ) { 1448 splx(s); 1449 return(EBUSY); 1450 } 1451 SET(mp->mp_flags, MBPPF_OPEN); 1452 splx(s); 1453 1454 /* set defaults */ 1455 mp->mp_burst = MBPP_BURST; 1456 mp->mp_timeout = mbpp_mstohz(MBPP_TIMEOUT); 1457 mp->mp_delay = mbpp_mstohz(MBPP_DELAY); 1458 1459 /* init chips */ 1460 if( mp->mp_cd1400 ) { /* CD1400 */ 1461 struct cd1400 *cd = mp->mp_cd1400; 1462 1463 /* set up CD1400 channel */ 1464 s = spltty(); 1465 cd1400_write_reg(cd, CD1400_CAR, 0); 1466 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET); 1467 cd1400_write_reg(cd, CD1400_LIVR, (1<<3)); 1468 splx(s); 1469 } else { /* CD1190 */ 1470 mp->mp_flags = 0; 1471 return (ENXIO); 1472 } 1473 1474 return (0); 1475 } 1476 1477 /* 1478 * close routine. returns zero if successful, else error code 1479 */ 1480 int 1481 mbppclose(dev_t dev, int flag, int mode, struct lwp *l) 1482 { 1483 struct mbpp_softc *ms = device_lookup_private(&mbpp_cd, 1484 MAGMA_CARD(dev)); 1485 struct mbpp_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1486 1487 mp->mp_flags = 0; 1488 return(0); 1489 } 1490 1491 /* 1492 * ioctl routine 1493 */ 1494 int 1495 mbppioctl(dev_t dev, u_long cmd, void *data, int flags, struct lwp *l) 1496 { 1497 struct mbpp_softc *ms = device_lookup_private(&mbpp_cd, 1498 MAGMA_CARD(dev)); 1499 struct mbpp_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1500 struct mbpp_param *bp; 1501 int error = 0; 1502 int s; 1503 1504 switch(cmd) { 1505 case MBPPIOCSPARAM: 1506 bp = (struct mbpp_param *)data; 1507 if( bp->bp_burst < MBPP_BURST_MIN || bp->bp_burst > MBPP_BURST_MAX || 1508 bp->bp_delay < MBPP_DELAY_MIN || bp->bp_delay > MBPP_DELAY_MIN ) { 1509 error = EINVAL; 1510 } else { 1511 mp->mp_burst = bp->bp_burst; 1512 mp->mp_timeout = mbpp_mstohz(bp->bp_timeout); 1513 mp->mp_delay = mbpp_mstohz(bp->bp_delay); 1514 } 1515 break; 1516 case MBPPIOCGPARAM: 1517 bp = (struct mbpp_param *)data; 1518 bp->bp_burst = mp->mp_burst; 1519 bp->bp_timeout = mbpp_hztoms(mp->mp_timeout); 1520 bp->bp_delay = mbpp_hztoms(mp->mp_delay); 1521 break; 1522 case MBPPIOCGSTAT: 1523 /* XXX make this more generic */ 1524 s = spltty(); 1525 cd1400_write_reg(mp->mp_cd1400, CD1400_CAR, 0); 1526 *(int *)data = cd1400_read_reg(mp->mp_cd1400, CD1400_PSVR); 1527 splx(s); 1528 break; 1529 default: 1530 error = ENOTTY; 1531 } 1532 1533 return(error); 1534 } 1535 1536 int 1537 mbpp_rw(dev_t dev, struct uio *uio, int flag) 1538 { 1539 int card = MAGMA_CARD(dev); 1540 int port = MAGMA_PORT(dev); 1541 struct mbpp_softc *ms = device_lookup_private(&mbpp_cd, card); 1542 struct mbpp_port *mp = &ms->ms_port[port]; 1543 char *buffer, *ptr; 1544 int buflen, cnt, len; 1545 int s, error = 0; 1546 int gotdata = 0; 1547 1548 if( uio->uio_resid == 0 ) 1549 return(0); 1550 1551 buflen = min(uio->uio_resid, mp->mp_burst); 1552 buffer = malloc(buflen, M_DEVBUF, M_WAITOK); 1553 if( buffer == NULL ) 1554 return(ENOMEM); 1555 1556 SET(mp->mp_flags, MBPPF_UIO); 1557 1558 /* 1559 * start timeout, if needed 1560 */ 1561 if( mp->mp_timeout > 0 ) { 1562 SET(mp->mp_flags, MBPPF_TIMEOUT); 1563 callout_reset(&mp->mp_timeout_ch, mp->mp_timeout, 1564 mbpp_timeout, mp); 1565 } 1566 1567 len = cnt = 0; 1568 while( uio->uio_resid > 0 ) { 1569 len = min(buflen, uio->uio_resid); 1570 ptr = buffer; 1571 1572 if( uio->uio_rw == UIO_WRITE ) { 1573 error = uiomove(ptr, len, uio); 1574 if( error ) break; 1575 } 1576 again: /* goto bad */ 1577 /* timed out? */ 1578 if( !ISSET(mp->mp_flags, MBPPF_UIO) ) 1579 break; 1580 1581 /* 1582 * perform the operation 1583 */ 1584 if( uio->uio_rw == UIO_WRITE ) { 1585 cnt = mbpp_send(mp, ptr, len); 1586 } else { 1587 cnt = mbpp_recv(mp, ptr, len); 1588 } 1589 1590 if( uio->uio_rw == UIO_READ ) { 1591 if( cnt ) { 1592 error = uiomove(ptr, cnt, uio); 1593 if( error ) break; 1594 gotdata++; 1595 } 1596 else if( gotdata ) /* consider us done */ 1597 break; 1598 } 1599 1600 /* timed out? */ 1601 if( !ISSET(mp->mp_flags, MBPPF_UIO) ) 1602 break; 1603 1604 /* 1605 * poll delay? 1606 */ 1607 if( mp->mp_delay > 0 ) { 1608 s = splsoftclock(); 1609 SET(mp->mp_flags, MBPPF_DELAY); 1610 callout_reset(&mp->mp_start_ch, mp->mp_delay, 1611 mbpp_start, mp); 1612 error = tsleep(mp, PCATCH | PZERO, "mbppdelay", 0); 1613 splx(s); 1614 if( error ) break; 1615 } 1616 1617 /* 1618 * don't call uiomove again until we used all the data we grabbed 1619 */ 1620 if( uio->uio_rw == UIO_WRITE && cnt != len ) { 1621 ptr += cnt; 1622 len -= cnt; 1623 cnt = 0; 1624 goto again; 1625 } 1626 } 1627 1628 /* 1629 * clear timeouts 1630 */ 1631 s = splsoftclock(); 1632 if( ISSET(mp->mp_flags, MBPPF_TIMEOUT) ) { 1633 callout_stop(&mp->mp_timeout_ch); 1634 CLR(mp->mp_flags, MBPPF_TIMEOUT); 1635 } 1636 if( ISSET(mp->mp_flags, MBPPF_DELAY) ) { 1637 callout_stop(&mp->mp_start_ch); 1638 CLR(mp->mp_flags, MBPPF_DELAY); 1639 } 1640 splx(s); 1641 1642 /* 1643 * adjust for those chars that we uiomoved but never actually wrote 1644 */ 1645 if( uio->uio_rw == UIO_WRITE && cnt != len ) { 1646 uio->uio_resid += (len - cnt); 1647 } 1648 1649 free(buffer, M_DEVBUF); 1650 return(error); 1651 } 1652 1653 void 1654 mbpp_timeout(void *arg) 1655 { 1656 struct mbpp_port *mp = arg; 1657 1658 CLR(mp->mp_flags, MBPPF_UIO | MBPPF_TIMEOUT); 1659 wakeup(mp); 1660 } 1661 1662 void 1663 mbpp_start(void *arg) 1664 { 1665 struct mbpp_port *mp = arg; 1666 1667 CLR(mp->mp_flags, MBPPF_DELAY); 1668 wakeup(mp); 1669 } 1670 1671 int 1672 mbpp_send(struct mbpp_port *mp, void *ptr, int len) 1673 { 1674 int s; 1675 struct cd1400 *cd = mp->mp_cd1400; 1676 1677 /* set up io information */ 1678 mp->mp_ptr = ptr; 1679 mp->mp_cnt = len; 1680 1681 /* start transmitting */ 1682 s = spltty(); 1683 if( cd ) { 1684 cd1400_write_reg(cd, CD1400_CAR, 0); 1685 1686 /* output strobe width ~1microsecond */ 1687 cd1400_write_reg(cd, CD1400_TBPR, 10); 1688 1689 /* enable channel */ 1690 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_XMTEN); 1691 cd1400_write_reg(cd, CD1400_SRER, CD1400_SRER_TXRDY); 1692 } 1693 1694 /* ZZzzz... */ 1695 tsleep(mp, PCATCH | PZERO, "mbpp_send", 0); 1696 1697 /* stop transmitting */ 1698 if( cd ) { 1699 cd1400_write_reg(cd, CD1400_CAR, 0); 1700 1701 /* disable transmitter */ 1702 cd1400_write_reg(cd, CD1400_SRER, 0); 1703 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_XMTDIS); 1704 1705 /* flush fifo */ 1706 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET | CD1400_CCR_FTF); 1707 } 1708 splx(s); 1709 1710 /* return number of chars sent */ 1711 return(len - mp->mp_cnt); 1712 } 1713 1714 int 1715 mbpp_recv(struct mbpp_port *mp, void *ptr, int len) 1716 { 1717 int s; 1718 struct cd1400 *cd = mp->mp_cd1400; 1719 1720 /* set up io information */ 1721 mp->mp_ptr = ptr; 1722 mp->mp_cnt = len; 1723 1724 /* start receiving */ 1725 s = spltty(); 1726 if( cd ) { 1727 int rcor, rbpr; 1728 1729 cd1400_write_reg(cd, CD1400_CAR, 0); 1730 1731 /* input strobe at 100kbaud (10microseconds) */ 1732 cd1400_compute_baud(100000, cd->cd_clock, &rcor, &rbpr); 1733 cd1400_write_reg(cd, CD1400_RCOR, rcor); 1734 cd1400_write_reg(cd, CD1400_RBPR, rbpr); 1735 1736 /* rx threshold */ 1737 cd1400_write_reg(cd, CD1400_COR3, MBPP_RX_FIFO_THRESHOLD); 1738 cd1400_write_ccr(cd, CD1400_CCR_CMDCORCHG | CD1400_CCR_COR3); 1739 1740 /* enable channel */ 1741 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_RCVEN); 1742 cd1400_write_reg(cd, CD1400_SRER, CD1400_SRER_RXDATA); 1743 } 1744 1745 /* ZZzzz... */ 1746 tsleep(mp, PCATCH | PZERO, "mbpp_recv", 0); 1747 1748 /* stop receiving */ 1749 if( cd ) { 1750 cd1400_write_reg(cd, CD1400_CAR, 0); 1751 1752 /* disable receiving */ 1753 cd1400_write_reg(cd, CD1400_SRER, 0); 1754 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_RCVDIS); 1755 } 1756 splx(s); 1757 1758 /* return number of chars received */ 1759 return(len - mp->mp_cnt); 1760 } 1761 1762 int 1763 mbpp_hztoms(int h) 1764 { 1765 int m = h; 1766 1767 if( m > 0 ) 1768 m = m * 1000 / hz; 1769 return(m); 1770 } 1771 1772 int 1773 mbpp_mstohz(int m) 1774 { 1775 int h = m; 1776 1777 if( h > 0 ) { 1778 h = h * hz / 1000; 1779 if( h == 0 ) 1780 h = 1000 / hz; 1781 } 1782 return(h); 1783 } 1784 1785 #endif /* NMAGMA */ 1786
Indexes created Thu Oct 02 10:09:58 GMT 2025