magma.c revision 1.53
1 /* $NetBSD: magma.c,v 1.53 2009/09/17 16:28:12 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 Iain Hibbert 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 /* 29 * Driver for Magma SBus Serial/Parallel cards using the Cirrus Logic 30 * CD1400 & CD1190 chips 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: magma.c,v 1.53 2009/09/17 16:28:12 tsutsui Exp $"); 35 36 #if 0 37 #define MAGMA_DEBUG 38 #endif 39 40 #include "magma.h" 41 #if NMAGMA > 0 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/proc.h> 46 #include <sys/device.h> 47 #include <sys/file.h> 48 #include <sys/ioctl.h> 49 #include <sys/malloc.h> 50 #include <sys/tty.h> 51 #include <sys/time.h> 52 #include <sys/kernel.h> 53 #include <sys/syslog.h> 54 #include <sys/conf.h> 55 #include <sys/errno.h> 56 #include <sys/kauth.h> 57 #include <sys/intr.h> 58 59 #include <sys/bus.h> 60 #include <machine/autoconf.h> 61 62 #include <dev/sbus/sbusvar.h> 63 64 #include <dev/ic/cd1400reg.h> 65 #include <dev/ic/cd1190reg.h> 66 67 #include <dev/sbus/mbppio.h> 68 #include <dev/sbus/magmareg.h> 69 70 /* supported cards 71 * 72 * The table below lists the cards that this driver is likely to 73 * be able to support. 74 * 75 * Cards with parallel ports: except for the LC2+1Sp, they all use 76 * the CD1190 chip which I know nothing about. I've tried to leave 77 * hooks for it so it shouldn't be too hard to add support later. 78 * (I think somebody is working on this separately) 79 * 80 * Thanks to Bruce at Magma for telling me the hardware offsets. 81 */ 82 static struct magma_board_info supported_cards[] = { 83 { 84 "MAGMA_Sp", "MAGMA,4_Sp", "Magma 4 Sp", 4, 0, 85 1, 0xa000, 0xc000, 0xe000, { 0x8000, 0, 0, 0 }, 86 0, { 0, 0 } 87 }, 88 { 89 "MAGMA_Sp", "MAGMA,8_Sp", "Magma 8 Sp", 8, 0, 90 2, 0xa000, 0xc000, 0xe000, { 0x4000, 0x6000, 0, 0 }, 91 0, { 0, 0 } 92 }, 93 { 94 "MAGMA_Sp", "MAGMA,_8HS_Sp", "Magma Fast 8 Sp", 8, 0, 95 2, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0, 0 }, 96 0, { 0, 0 } 97 }, 98 { 99 "MAGMA_Sp", "MAGMA,_8SP_422", "Magma 8 Sp - 422", 8, 0, 100 2, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0, 0 }, 101 0, { 0, 0 } 102 }, 103 { 104 "MAGMA_Sp", "MAGMA,12_Sp", "Magma 12 Sp", 12, 0, 105 3, 0xa000, 0xc000, 0xe000, { 0x2000, 0x4000, 0x6000, 0 }, 106 0, { 0, 0 } 107 }, 108 { 109 "MAGMA_Sp", "MAGMA,16_Sp", "Magma 16 Sp", 16, 0, 110 4, 0xd000, 0xe000, 0xf000, { 0x8000, 0x9000, 0xa000, 0xb000 }, 111 0, { 0, 0 } 112 }, 113 { 114 "MAGMA_Sp", "MAGMA,16_Sp_2", "Magma 16 Sp", 16, 0, 115 4, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0xc000, 0xe000 }, 116 0, { 0, 0 } 117 }, 118 { 119 "MAGMA_Sp", "MAGMA,16HS_Sp", "Magma Fast 16 Sp", 16, 0, 120 4, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0xc000, 0xe000 }, 121 0, { 0, 0 } 122 }, 123 { 124 "MAGMA_Sp", "MAGMA,21_Sp", "Magma LC 2+1 Sp", 2, 1, 125 1, 0xa000, 0xc000, 0xe000, { 0x8000, 0, 0, 0 }, 126 0, { 0, 0 } 127 }, 128 { 129 "MAGMA_Sp", "MAGMA,21HS_Sp", "Magma 2+1 Sp", 2, 1, 130 1, 0xa000, 0xc000, 0xe000, { 0x4000, 0, 0, 0 }, 131 1, { 0x6000, 0 } 132 }, 133 { 134 "MAGMA_Sp", "MAGMA,41_Sp", "Magma 4+1 Sp", 4, 1, 135 1, 0xa000, 0xc000, 0xe000, { 0x4000, 0, 0, 0 }, 136 1, { 0x6000, 0 } 137 }, 138 { 139 "MAGMA_Sp", "MAGMA,82_Sp", "Magma 8+2 Sp", 8, 2, 140 2, 0xd000, 0xe000, 0xf000, { 0x8000, 0x9000, 0, 0 }, 141 2, { 0xa000, 0xb000 } 142 }, 143 { 144 "MAGMA_Sp", "MAGMA,P1_Sp", "Magma P1 Sp", 0, 1, 145 0, 0, 0, 0, { 0, 0, 0, 0 }, 146 1, { 0x8000, 0 } 147 }, 148 { 149 "MAGMA_Sp", "MAGMA,P2_Sp", "Magma P2 Sp", 0, 2, 150 0, 0, 0, 0, { 0, 0, 0, 0 }, 151 2, { 0x4000, 0x8000 } 152 }, 153 { 154 "MAGMA 2+1HS Sp", "", "Magma 2+1HS Sp", 2, 0, 155 1, 0xa000, 0xc000, 0xe000, { 0x4000, 0, 0, 0 }, 156 1, { 0x8000, 0 } 157 }, 158 { 159 NULL, NULL, NULL, 0, 0, 160 0, 0, 0, 0, { 0, 0, 0, 0 }, 161 0, { 0, 0 } 162 } 163 }; 164 165 /************************************************************************ 166 * 167 * Autoconfig Stuff 168 */ 169 170 CFATTACH_DECL(magma, sizeof(struct magma_softc), 171 magma_match, magma_attach, NULL, NULL); 172 173 CFATTACH_DECL(mtty, sizeof(struct mtty_softc), 174 mtty_match, mtty_attach, NULL, NULL); 175 176 CFATTACH_DECL(mbpp, sizeof(struct mbpp_softc), 177 mbpp_match, mbpp_attach, NULL, NULL); 178 179 extern struct cfdriver mtty_cd; 180 extern struct cfdriver mbpp_cd; 181 182 dev_type_open(mttyopen); 183 dev_type_close(mttyclose); 184 dev_type_read(mttyread); 185 dev_type_write(mttywrite); 186 dev_type_ioctl(mttyioctl); 187 dev_type_stop(mttystop); 188 dev_type_tty(mttytty); 189 dev_type_poll(mttypoll); 190 191 const struct cdevsw mtty_cdevsw = { 192 mttyopen, mttyclose, mttyread, mttywrite, mttyioctl, 193 mttystop, mttytty, mttypoll, nommap, ttykqfilter, D_TTY 194 }; 195 196 dev_type_open(mbppopen); 197 dev_type_close(mbppclose); 198 dev_type_read(mbpp_rw); 199 dev_type_ioctl(mbppioctl); 200 201 const struct cdevsw mbpp_cdevsw = { 202 mbppopen, mbppclose, mbpp_rw, mbpp_rw, mbppioctl, 203 nostop, notty, nopoll, nommap, nokqfilter, D_OTHER 204 }; 205 206 /************************************************************************ 207 * 208 * CD1400 Routines 209 * 210 * cd1400_compute_baud calculate COR/BPR register values 211 * cd1400_write_ccr write a value to CD1400 ccr 212 * cd1400_read_reg read from a CD1400 register 213 * cd1400_write_reg write to a CD1400 register 214 * cd1400_enable_transmitter enable transmitting on CD1400 channel 215 */ 216 217 /* 218 * compute the bpr/cor pair for any baud rate 219 * returns 0 for success, 1 for failure 220 */ 221 int 222 cd1400_compute_baud(speed_t speed, int clock, int *cor, int *bpr) 223 { 224 int c, co, br; 225 226 if( speed < 50 || speed > 150000 ) 227 return(1); 228 229 for( c = 0, co = 8 ; co <= 2048 ; co <<= 2, c++ ) { 230 br = ((clock * 1000000) + (co * speed) / 2) / (co * speed); 231 if( br < 0x100 ) { 232 *bpr = br; 233 *cor = c; 234 return(0); 235 } 236 } 237 238 return(1); 239 } 240 241 /* 242 * Write a CD1400 channel command, should have a timeout? 243 */ 244 inline void 245 cd1400_write_ccr(struct cd1400 *cd, u_char cmd) 246 { 247 while( cd1400_read_reg(cd, CD1400_CCR) ) 248 ; 249 250 cd1400_write_reg(cd, CD1400_CCR, cmd); 251 } 252 253 /* 254 * read a value from a cd1400 register 255 */ 256 inline u_char 257 cd1400_read_reg(struct cd1400 *cd, int reg) 258 { 259 return(cd->cd_reg[reg]); 260 } 261 262 /* 263 * write a value to a cd1400 register 264 */ 265 inline void 266 cd1400_write_reg(struct cd1400 *cd, int reg, u_char value) 267 { 268 cd->cd_reg[reg] = value; 269 } 270 271 /* 272 * enable transmit service requests for cd1400 channel 273 */ 274 void 275 cd1400_enable_transmitter(struct cd1400 *cd, int channel) 276 { 277 int s, srer; 278 279 s = spltty(); 280 cd1400_write_reg(cd, CD1400_CAR, channel); 281 srer = cd1400_read_reg(cd, CD1400_SRER); 282 SET(srer, CD1400_SRER_TXRDY); 283 cd1400_write_reg(cd, CD1400_SRER, srer); 284 splx(s); 285 } 286 287 /************************************************************************ 288 * 289 * CD1190 Routines 290 */ 291 292 /* well, there are none yet */ 293 294 /************************************************************************ 295 * 296 * Magma Routines 297 * 298 * magma_match reports if we have a magma board available 299 * magma_attach attaches magma boards to the sbus 300 * magma_hard hardware level interrupt routine 301 * magma_soft software level interrupt routine 302 */ 303 304 int 305 magma_match(device_t parent, cfdata_t cf, void *aux) 306 { 307 struct sbus_attach_args *sa = aux; 308 struct magma_board_info *card; 309 310 /* See if we support this device */ 311 for (card = supported_cards; ; card++) { 312 if (card->mb_sbusname == NULL) 313 /* End of table: no match */ 314 return (0); 315 if (strcmp(sa->sa_name, card->mb_sbusname) == 0) 316 break; 317 } 318 319 dprintf(("magma: matched `%s'\n", sa->sa_name)); 320 dprintf(("magma: magma_prom `%s'\n", 321 prom_getpropstring(sa->sa_node, "magma_prom"))); 322 dprintf(("magma: intlevels `%s'\n", 323 prom_getpropstring(sa->sa_node, "intlevels"))); 324 dprintf(("magma: chiprev `%s'\n", 325 prom_getpropstring(sa->sa_node, "chiprev"))); 326 dprintf(("magma: clock `%s'\n", 327 prom_getpropstring(sa->sa_node, "clock"))); 328 329 return (1); 330 } 331 332 void 333 magma_attach(device_t parent, device_t self, void *aux) 334 { 335 struct sbus_attach_args *sa = aux; 336 struct magma_softc *sc = device_private(self); 337 struct magma_board_info *card; 338 bus_space_handle_t bh; 339 char *magma_prom, *clockstr; 340 int cd_clock; 341 int node, chip; 342 343 node = sa->sa_node; 344 345 /* 346 * Find the card model. 347 * Older models all have sbus node name `MAGMA_Sp' (see 348 * `supported_cards[]' above), and must be distinguished 349 * by the `magma_prom' property. 350 */ 351 magma_prom = prom_getpropstring(node, "magma_prom"); 352 353 for (card = supported_cards; card->mb_name != NULL; card++) { 354 if (strcmp(sa->sa_name, card->mb_sbusname) != 0) 355 /* Sbus node name doesn't match */ 356 continue; 357 if (strcmp(magma_prom, card->mb_name) == 0) 358 /* Model name match */ 359 break; 360 } 361 362 if( card->mb_name == NULL ) { 363 printf(": %s (unsupported)\n", magma_prom); 364 return; 365 } 366 367 dprintf((" addr %p", sc)); 368 printf(": %s\n", card->mb_realname); 369 370 sc->ms_board = card; 371 sc->ms_ncd1400 = card->mb_ncd1400; 372 sc->ms_ncd1190 = card->mb_ncd1190; 373 374 if (sbus_bus_map(sa->sa_bustag, 375 sa->sa_slot, sa->sa_offset, sa->sa_size, 376 BUS_SPACE_MAP_LINEAR, &bh) != 0) { 377 aprint_error("%s @ sbus: cannot map registers\n", 378 device_xname(self)); 379 return; 380 } 381 382 /* the SVCACK* lines are daisychained */ 383 sc->ms_svcackr = (char *)bus_space_vaddr(sa->sa_bustag, bh) 384 + card->mb_svcackr; 385 sc->ms_svcackt = (char *)bus_space_vaddr(sa->sa_bustag, bh) 386 + card->mb_svcackt; 387 sc->ms_svcackm = (char *)bus_space_vaddr(sa->sa_bustag, bh) 388 + card->mb_svcackm; 389 390 /* 391 * Find the clock speed; it's the same for all CD1400 chips 392 * on the board. 393 */ 394 clockstr = prom_getpropstring(node, "clock"); 395 if (*clockstr == '\0') 396 /* Default to 25MHz */ 397 cd_clock = 25; 398 else { 399 cd_clock = 0; 400 while (*clockstr != '\0') 401 cd_clock = (cd_clock * 10) + (*clockstr++ - '0'); 402 } 403 404 /* init the cd1400 chips */ 405 for( chip = 0 ; chip < card->mb_ncd1400 ; chip++ ) { 406 struct cd1400 *cd = &sc->ms_cd1400[chip]; 407 408 cd->cd_clock = cd_clock; 409 cd->cd_reg = (char *)bus_space_vaddr(sa->sa_bustag, bh) + 410 card->mb_cd1400[chip]; 411 412 /* prom_getpropstring(node, "chiprev"); */ 413 /* seemingly the Magma drivers just ignore the propstring */ 414 cd->cd_chiprev = cd1400_read_reg(cd, CD1400_GFRCR); 415 416 dprintf(("%s attach CD1400 %d addr %p rev %x clock %dMHz\n", 417 device_xname(&sc->ms_dev), chip, 418 cd->cd_reg, cd->cd_chiprev, cd->cd_clock)); 419 420 /* clear GFRCR */ 421 cd1400_write_reg(cd, CD1400_GFRCR, 0x00); 422 423 /* reset whole chip */ 424 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET | CD1400_CCR_FULLRESET); 425 426 /* wait for revision code to be restored */ 427 while( cd1400_read_reg(cd, CD1400_GFRCR) != cd->cd_chiprev ) 428 ; 429 430 /* set the Prescaler Period Register to tick at 1ms */ 431 cd1400_write_reg(cd, CD1400_PPR, 432 ((cd->cd_clock * 1000000 / CD1400_PPR_PRESCALER + 500) / 1000)); 433 434 /* The LC2+1Sp card is the only card that doesn't have 435 * a CD1190 for the parallel port, but uses channel 0 of 436 * the CD1400, so we make a note of it for later and set up 437 * the CD1400 for parallel mode operation. 438 */ 439 if( card->mb_npar && card->mb_ncd1190 == 0 ) { 440 cd1400_write_reg(cd, CD1400_GCR, CD1400_GCR_PARALLEL); 441 cd->cd_parmode = 1; 442 } 443 } 444 445 /* init the cd1190 chips */ 446 for( chip = 0 ; chip < card->mb_ncd1190 ; chip++ ) { 447 struct cd1190 *cd = &sc->ms_cd1190[chip]; 448 449 cd->cd_reg = (char *)bus_space_vaddr(sa->sa_bustag, bh) + 450 card->mb_cd1190[chip]; 451 452 /* XXX don't know anything about these chips yet */ 453 printf("%s: CD1190 %d addr %p (unsupported)\n", 454 device_xname(self), chip, cd->cd_reg); 455 } 456 457 /* configure the children */ 458 (void)config_found(self, mtty_match, NULL); 459 (void)config_found(self, mbpp_match, NULL); 460 461 /* 462 * Establish the interrupt handlers. 463 */ 464 if (sa->sa_nintr == 0) 465 return; /* No interrupts to service!? */ 466 467 (void)bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_SERIAL, 468 magma_hard, sc); 469 sc->ms_sicookie = softint_establish(SOFTINT_SERIAL, magma_soft, sc); 470 if (sc->ms_sicookie == NULL) { 471 aprint_normal("\n"); 472 aprint_error_dev(&sc->ms_dev, "cannot establish soft int handler\n"); 473 return; 474 } 475 evcnt_attach_dynamic(&sc->ms_intrcnt, EVCNT_TYPE_INTR, NULL, 476 device_xname(&sc->ms_dev), "intr"); 477 } 478 479 /* 480 * hard interrupt routine 481 * 482 * returns 1 if it handled it, otherwise 0 483 * 484 * runs at IPL_SERIAL 485 */ 486 int 487 magma_hard(void *arg) 488 { 489 struct magma_softc *sc = arg; 490 struct cd1400 *cd; 491 int chip, status = 0; 492 int serviced = 0; 493 int needsoftint = 0; 494 495 /* 496 * check status of all the CD1400 chips 497 */ 498 for( chip = 0 ; chip < sc->ms_ncd1400 ; chip++ ) 499 status |= cd1400_read_reg(&sc->ms_cd1400[chip], CD1400_SVRR); 500 501 if( ISSET(status, CD1400_SVRR_RXRDY) ) { 502 u_char rivr = *sc->ms_svcackr; /* enter rx service context */ 503 int port = rivr >> 4; 504 505 if( rivr & (1<<3) ) { /* parallel port */ 506 struct mbpp_port *mbpp; 507 int n_chars; 508 509 mbpp = &sc->ms_mbpp->ms_port[port]; 510 cd = mbpp->mp_cd1400; 511 512 /* don't think we have to handle exceptions */ 513 n_chars = cd1400_read_reg(cd, CD1400_RDCR); 514 while (n_chars--) { 515 if( mbpp->mp_cnt == 0 ) { 516 SET(mbpp->mp_flags, MBPPF_WAKEUP); 517 needsoftint = 1; 518 break; 519 } 520 *mbpp->mp_ptr = cd1400_read_reg(cd,CD1400_RDSR); 521 mbpp->mp_ptr++; 522 mbpp->mp_cnt--; 523 } 524 } else { /* serial port */ 525 struct mtty_port *mtty; 526 u_char *ptr, n_chars, line_stat; 527 528 mtty = &sc->ms_mtty->ms_port[port]; 529 cd = mtty->mp_cd1400; 530 531 if( ISSET(rivr, CD1400_RIVR_EXCEPTION) ) { 532 line_stat = cd1400_read_reg(cd, CD1400_RDSR); 533 n_chars = 1; 534 } else { /* no exception, received data OK */ 535 line_stat = 0; 536 n_chars = cd1400_read_reg(cd, CD1400_RDCR); 537 } 538 539 ptr = mtty->mp_rput; 540 while( n_chars-- ) { 541 *ptr++ = line_stat; 542 *ptr++ = cd1400_read_reg(cd, CD1400_RDSR); 543 if( ptr == mtty->mp_rend ) ptr = mtty->mp_rbuf; 544 if( ptr == mtty->mp_rget ) { 545 if( ptr == mtty->mp_rbuf ) 546 ptr = mtty->mp_rend; 547 ptr -= 2; 548 SET(mtty->mp_flags, MTTYF_RING_OVERFLOW); 549 break; 550 } 551 } 552 mtty->mp_rput = ptr; 553 554 needsoftint = 1; 555 } 556 557 cd1400_write_reg(cd, CD1400_EOSRR, 0); /* end service context */ 558 serviced = 1; 559 } /* if(rx_service...) */ 560 561 if( ISSET(status, CD1400_SVRR_MDMCH) ) { 562 u_char mivr = *sc->ms_svcackm; /* enter mdm service context */ 563 int port = mivr >> 4; 564 struct mtty_port *mtty; 565 int carrier; 566 u_char msvr; 567 568 /* 569 * Handle CD (LC2+1Sp = DSR) changes. 570 */ 571 mtty = &sc->ms_mtty->ms_port[port]; 572 cd = mtty->mp_cd1400; 573 msvr = cd1400_read_reg(cd, CD1400_MSVR2); 574 carrier = ISSET(msvr, cd->cd_parmode ? CD1400_MSVR2_DSR : CD1400_MSVR2_CD); 575 576 if( mtty->mp_carrier != carrier ) { 577 SET(mtty->mp_flags, MTTYF_CARRIER_CHANGED); 578 mtty->mp_carrier = carrier; 579 needsoftint = 1; 580 } 581 582 cd1400_write_reg(cd, CD1400_EOSRR, 0); /* end service context */ 583 serviced = 1; 584 } /* if(mdm_service...) */ 585 586 if( ISSET(status, CD1400_SVRR_TXRDY) ) { 587 u_char tivr = *sc->ms_svcackt; /* enter tx service context */ 588 int port = tivr >> 4; 589 590 if( tivr & (1<<3) ) { /* parallel port */ 591 struct mbpp_port *mbpp; 592 593 mbpp = &sc->ms_mbpp->ms_port[port]; 594 cd = mbpp->mp_cd1400; 595 596 if( mbpp->mp_cnt ) { 597 int count = 0; 598 599 /* fill the fifo */ 600 while (mbpp->mp_cnt && 601 count++ < CD1400_PAR_FIFO_SIZE) { 602 cd1400_write_reg(cd, CD1400_TDR, 603 *mbpp->mp_ptr); 604 mbpp->mp_ptr++; 605 mbpp->mp_cnt--; 606 } 607 } else { 608 /* 609 * fifo is empty and we got no more data 610 * to send, so shut off interrupts and 611 * signal for a wakeup, which can't be 612 * done here in case we beat mbpp_send to 613 * the tsleep call (we are running at >spltty) 614 */ 615 cd1400_write_reg(cd, CD1400_SRER, 0); 616 SET(mbpp->mp_flags, MBPPF_WAKEUP); 617 needsoftint = 1; 618 } 619 } else { /* serial port */ 620 struct mtty_port *mtty; 621 struct tty *tp; 622 623 mtty = &sc->ms_mtty->ms_port[port]; 624 cd = mtty->mp_cd1400; 625 tp = mtty->mp_tty; 626 627 if( !ISSET(mtty->mp_flags, MTTYF_STOP) ) { 628 int count = 0; 629 630 /* check if we should start/stop a break */ 631 if( ISSET(mtty->mp_flags, MTTYF_SET_BREAK) ) { 632 cd1400_write_reg(cd, CD1400_TDR, 0); 633 cd1400_write_reg(cd, CD1400_TDR, 0x81); 634 /* should we delay too? */ 635 CLR(mtty->mp_flags, MTTYF_SET_BREAK); 636 count += 2; 637 } 638 639 if( ISSET(mtty->mp_flags, MTTYF_CLR_BREAK) ) { 640 cd1400_write_reg(cd, CD1400_TDR, 0); 641 cd1400_write_reg(cd, CD1400_TDR, 0x83); 642 CLR(mtty->mp_flags, MTTYF_CLR_BREAK); 643 count += 2; 644 } 645 646 /* I don't quite fill the fifo in case the last one is a 647 * NULL which I have to double up because its the escape 648 * code for embedded transmit characters. 649 */ 650 while( mtty->mp_txc > 0 && count < CD1400_TX_FIFO_SIZE - 1 ) { 651 u_char ch; 652 653 ch = *mtty->mp_txp; 654 655 mtty->mp_txc--; 656 mtty->mp_txp++; 657 658 if( ch == 0 ) { 659 cd1400_write_reg(cd, CD1400_TDR, ch); 660 count++; 661 } 662 663 cd1400_write_reg(cd, CD1400_TDR, ch); 664 count++; 665 } 666 } 667 668 /* if we ran out of work or are requested to STOP then 669 * shut off the txrdy interrupts and signal DONE to flush 670 * out the chars we have sent. 671 */ 672 if( mtty->mp_txc == 0 || ISSET(mtty->mp_flags, MTTYF_STOP) ) { 673 register int srer; 674 675 srer = cd1400_read_reg(cd, CD1400_SRER); 676 CLR(srer, CD1400_SRER_TXRDY); 677 cd1400_write_reg(cd, CD1400_SRER, srer); 678 CLR(mtty->mp_flags, MTTYF_STOP); 679 680 SET(mtty->mp_flags, MTTYF_DONE); 681 needsoftint = 1; 682 } 683 } 684 685 cd1400_write_reg(cd, CD1400_EOSRR, 0); /* end service context */ 686 serviced = 1; 687 } /* if(tx_service...) */ 688 689 /* XXX service CD1190 interrupts too 690 for( chip = 0 ; chip < sc->ms_ncd1190 ; chip++ ) { 691 } 692 */ 693 694 if (needsoftint) 695 /* trigger the soft interrupt */ 696 softint_schedule(sc->ms_sicookie); 697 698 return(serviced); 699 } 700 701 /* 702 * magma soft interrupt handler 703 * 704 * runs at IPL_SOFTSERIAL 705 */ 706 void 707 magma_soft(void *arg) 708 { 709 struct magma_softc *sc = arg; 710 struct mtty_softc *mtty = sc->ms_mtty; 711 struct mbpp_softc *mbpp = sc->ms_mbpp; 712 int port; 713 int s, flags; 714 715 if (mtty == NULL) 716 goto chkbpp; 717 718 /* 719 * check the tty ports to see what needs doing 720 */ 721 for( port = 0 ; port < mtty->ms_nports ; port++ ) { 722 struct mtty_port *mp = &mtty->ms_port[port]; 723 struct tty *tp = mp->mp_tty; 724 725 if( !ISSET(tp->t_state, TS_ISOPEN) ) 726 continue; 727 728 /* 729 * handle any received data 730 */ 731 while( mp->mp_rget != mp->mp_rput ) { 732 u_char stat; 733 int data; 734 735 stat = mp->mp_rget[0]; 736 data = mp->mp_rget[1]; 737 mp->mp_rget = ((mp->mp_rget + 2) == mp->mp_rend) 738 ? mp->mp_rbuf : (mp->mp_rget + 2); 739 740 if( stat & (CD1400_RDSR_BREAK | CD1400_RDSR_FE) ) 741 data |= TTY_FE; 742 if( stat & CD1400_RDSR_PE ) 743 data |= TTY_PE; 744 745 if( stat & CD1400_RDSR_OE ) 746 log(LOG_WARNING, "%s%x: fifo overflow\n", 747 device_xname(&mtty->ms_dev), port); 748 749 (*tp->t_linesw->l_rint)(data, tp); 750 } 751 752 s = splserial(); /* block out hard interrupt routine */ 753 flags = mp->mp_flags; 754 CLR(mp->mp_flags, MTTYF_DONE | MTTYF_CARRIER_CHANGED | MTTYF_RING_OVERFLOW); 755 splx(s); /* ok */ 756 757 if( ISSET(flags, MTTYF_CARRIER_CHANGED) ) { 758 dprintf(("%s%x: cd %s\n", device_xname(&mtty->ms_dev), 759 port, mp->mp_carrier ? "on" : "off")); 760 (*tp->t_linesw->l_modem)(tp, mp->mp_carrier); 761 } 762 763 if( ISSET(flags, MTTYF_RING_OVERFLOW) ) { 764 log(LOG_WARNING, "%s%x: ring buffer overflow\n", 765 device_xname(&mtty->ms_dev), port); 766 } 767 768 if( ISSET(flags, MTTYF_DONE) ) { 769 ndflush(&tp->t_outq, mp->mp_txp - tp->t_outq.c_cf); 770 CLR(tp->t_state, TS_BUSY); 771 (*tp->t_linesw->l_start)(tp); /* might be some more */ 772 } 773 } /* for(each mtty...) */ 774 775 776 chkbpp: 777 /* 778 * Check the bpp ports (if any) to see what needs doing 779 */ 780 if (mbpp == NULL) 781 return; 782 783 for( port = 0 ; port < mbpp->ms_nports ; port++ ) { 784 struct mbpp_port *mp = &mbpp->ms_port[port]; 785 786 if( !ISSET(mp->mp_flags, MBPPF_OPEN) ) 787 continue; 788 789 s = splserial(); 790 flags = mp->mp_flags; 791 CLR(mp->mp_flags, MBPPF_WAKEUP); 792 splx(s); 793 794 if( ISSET(flags, MBPPF_WAKEUP) ) { 795 wakeup(mp); 796 } 797 798 } /* for(each mbpp...) */ 799 } 800 801 /************************************************************************ 802 * 803 * MTTY Routines 804 * 805 * mtty_match match one mtty device 806 * mtty_attach attach mtty devices 807 * mttyopen open mtty device 808 * mttyclose close mtty device 809 * mttyread read from mtty 810 * mttywrite write to mtty 811 * mttyioctl do ioctl on mtty 812 * mttytty return tty pointer for mtty 813 * mttystop stop mtty device 814 * mtty_start start mtty device 815 * mtty_param set mtty parameters 816 * mtty_modem_control set modem control lines 817 */ 818 819 int 820 mtty_match(device_t parent, cfdata_t cf, void *args) 821 { 822 struct magma_softc *sc = device_private(parent); 823 824 return( args == mtty_match && sc->ms_board->mb_nser && sc->ms_mtty == NULL ); 825 } 826 827 void 828 mtty_attach(device_t parent, device_t dev, void *args) 829 { 830 struct magma_softc *sc = device_private(parent); 831 struct mtty_softc *ms = device_private(dev); 832 int port, chip, chan; 833 834 sc->ms_mtty = ms; 835 dprintf((" addr %p", ms)); 836 837 for( port = 0, chip = 0, chan = 0 ; port < sc->ms_board->mb_nser ; port++ ) { 838 struct mtty_port *mp = &ms->ms_port[port]; 839 struct tty *tp; 840 841 mp->mp_cd1400 = &sc->ms_cd1400[chip]; 842 if (mp->mp_cd1400->cd_parmode && chan == 0) 843 chan = 1; /* skip channel 0 if parmode */ 844 mp->mp_channel = chan; 845 846 tp = ttymalloc(); 847 if (tp == NULL) break; 848 tty_attach(tp); 849 tp->t_oproc = mtty_start; 850 tp->t_param = mtty_param; 851 852 mp->mp_tty = tp; 853 854 mp->mp_rbuf = malloc(MTTY_RBUF_SIZE, M_DEVBUF, M_NOWAIT); 855 if (mp->mp_rbuf == NULL) break; 856 857 mp->mp_rend = mp->mp_rbuf + MTTY_RBUF_SIZE; 858 859 chan = (chan + 1) % CD1400_NO_OF_CHANNELS; 860 if (chan == 0) 861 chip++; 862 } 863 864 ms->ms_nports = port; 865 printf(": %d tty%s\n", port, port == 1 ? "" : "s"); 866 } 867 868 /* 869 * open routine. returns zero if successful, else error code 870 */ 871 int 872 mttyopen(dev_t dev, int flags, int mode, struct lwp *l) 873 { 874 int card = MAGMA_CARD(dev); 875 int port = MAGMA_PORT(dev); 876 struct mtty_softc *ms; 877 struct mtty_port *mp; 878 struct tty *tp; 879 struct cd1400 *cd; 880 int error, s; 881 882 if ((ms = device_lookup_private(&mtty_cd, card)) == NULL 883 || port >= ms->ms_nports ) 884 return(ENXIO); /* device not configured */ 885 886 mp = &ms->ms_port[port]; 887 tp = mp->mp_tty; 888 tp->t_dev = dev; 889 890 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 891 return (EBUSY); 892 893 s = spltty(); 894 895 if( !ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 896 897 /* set defaults */ 898 ttychars(tp); 899 tp->t_iflag = TTYDEF_IFLAG; 900 tp->t_oflag = TTYDEF_OFLAG; 901 tp->t_cflag = TTYDEF_CFLAG; 902 if( ISSET(mp->mp_openflags, TIOCFLAG_CLOCAL) ) 903 SET(tp->t_cflag, CLOCAL); 904 if( ISSET(mp->mp_openflags, TIOCFLAG_CRTSCTS) ) 905 SET(tp->t_cflag, CRTSCTS); 906 if( ISSET(mp->mp_openflags, TIOCFLAG_MDMBUF) ) 907 SET(tp->t_cflag, MDMBUF); 908 tp->t_lflag = TTYDEF_LFLAG; 909 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 910 911 /* init ring buffer */ 912 mp->mp_rput = mp->mp_rget = mp->mp_rbuf; 913 914 /* reset CD1400 channel */ 915 cd = mp->mp_cd1400; 916 cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel); 917 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET); 918 919 /* encode the port number in top half of LIVR */ 920 cd1400_write_reg(cd, CD1400_LIVR, port << 4 ); 921 922 /* sets parameters and raises DTR */ 923 (void)mtty_param(tp, &tp->t_termios); 924 925 /* set tty watermarks */ 926 ttsetwater(tp); 927 928 /* enable service requests */ 929 cd1400_write_reg(cd, CD1400_SRER, 930 CD1400_SRER_RXDATA | CD1400_SRER_MDMCH); 931 932 /* tell the tty about the carrier status */ 933 if( ISSET(mp->mp_openflags, TIOCFLAG_SOFTCAR) || 934 mp->mp_carrier ) 935 SET(tp->t_state, TS_CARR_ON); 936 else 937 CLR(tp->t_state, TS_CARR_ON); 938 } 939 splx(s); 940 941 error = ttyopen(tp, MTTY_DIALOUT(dev), ISSET(flags, O_NONBLOCK)); 942 if (error != 0) 943 goto bad; 944 945 error = (*tp->t_linesw->l_open)(dev, tp); 946 if (error != 0) 947 goto bad; 948 949 bad: 950 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 951 /* 952 * We failed to open the device, and nobody else had it opened. 953 * Clean up the state as appropriate. 954 */ 955 /* XXX - do that here */ 956 } 957 958 return (error); 959 } 960 961 /* 962 * close routine. returns zero if successful, else error code 963 */ 964 int 965 mttyclose(dev_t dev, int flag, int mode, struct lwp *l) 966 { 967 struct mtty_softc *ms = device_lookup_private(&mtty_cd, 968 MAGMA_CARD(dev)); 969 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 970 struct tty *tp = mp->mp_tty; 971 int s; 972 973 (*tp->t_linesw->l_close)(tp, flag); 974 ttyclose(tp); 975 976 s = spltty(); 977 978 /* if HUPCL is set, and the tty is no longer open 979 * shut down the port 980 */ 981 if( ISSET(tp->t_cflag, HUPCL) || !ISSET(tp->t_state, TS_ISOPEN) ) { 982 /* XXX wait until FIFO is empty before turning off the channel 983 struct cd1400 *cd = mp->mp_cd1400; 984 */ 985 986 /* drop DTR and RTS */ 987 (void)mtty_modem_control(mp, 0, DMSET); 988 989 /* turn off the channel 990 cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel); 991 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET); 992 */ 993 } 994 995 splx(s); 996 997 return(0); 998 } 999 1000 /* 1001 * Read routine 1002 */ 1003 int 1004 mttyread(dev_t dev, struct uio *uio, int flags) 1005 { 1006 struct mtty_softc *ms = device_lookup_private(&mtty_cd, 1007 MAGMA_CARD(dev)); 1008 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1009 struct tty *tp = mp->mp_tty; 1010 1011 return( (*tp->t_linesw->l_read)(tp, uio, flags) ); 1012 } 1013 1014 /* 1015 * Write routine 1016 */ 1017 int 1018 mttywrite(dev_t dev, struct uio *uio, int flags) 1019 { 1020 struct mtty_softc *ms = device_lookup_private(&mtty_cd, 1021 MAGMA_CARD(dev)); 1022 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1023 struct tty *tp = mp->mp_tty; 1024 1025 return( (*tp->t_linesw->l_write)(tp, uio, flags) ); 1026 } 1027 1028 /* 1029 * Poll routine 1030 */ 1031 int 1032 mttypoll(dev_t dev, int events, struct lwp *l) 1033 { 1034 struct mtty_softc *ms = device_lookup_private(&mtty_cd, 1035 MAGMA_CARD(dev)); 1036 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1037 struct tty *tp = mp->mp_tty; 1038 1039 return ((*tp->t_linesw->l_poll)(tp, events, l)); 1040 } 1041 1042 /* 1043 * return tty pointer 1044 */ 1045 struct tty * 1046 mttytty(dev_t dev) 1047 { 1048 struct mtty_softc *ms = device_lookup_private(&mtty_cd, 1049 MAGMA_CARD(dev)); 1050 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1051 1052 return(mp->mp_tty); 1053 } 1054 1055 /* 1056 * ioctl routine 1057 */ 1058 int 1059 mttyioctl(dev_t dev, u_long cmd, void *data, int flags, struct lwp *l) 1060 { 1061 struct mtty_softc *ms = device_lookup_private(&mtty_cd, 1062 MAGMA_CARD(dev)); 1063 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1064 struct tty *tp = mp->mp_tty; 1065 int error; 1066 1067 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flags, l); 1068 if( error != EPASSTHROUGH ) return(error); 1069 1070 error = ttioctl(tp, cmd, data, flags, l); 1071 if( error != EPASSTHROUGH ) return(error); 1072 1073 error = 0; 1074 1075 switch(cmd) { 1076 case TIOCSBRK: /* set break */ 1077 SET(mp->mp_flags, MTTYF_SET_BREAK); 1078 cd1400_enable_transmitter(mp->mp_cd1400, mp->mp_channel); 1079 break; 1080 1081 case TIOCCBRK: /* clear break */ 1082 SET(mp->mp_flags, MTTYF_CLR_BREAK); 1083 cd1400_enable_transmitter(mp->mp_cd1400, mp->mp_channel); 1084 break; 1085 1086 case TIOCSDTR: /* set DTR */ 1087 mtty_modem_control(mp, TIOCM_DTR, DMBIS); 1088 break; 1089 1090 case TIOCCDTR: /* clear DTR */ 1091 mtty_modem_control(mp, TIOCM_DTR, DMBIC); 1092 break; 1093 1094 case TIOCMSET: /* set modem lines */ 1095 mtty_modem_control(mp, *((int *)data), DMSET); 1096 break; 1097 1098 case TIOCMBIS: /* bit set modem lines */ 1099 mtty_modem_control(mp, *((int *)data), DMBIS); 1100 break; 1101 1102 case TIOCMBIC: /* bit clear modem lines */ 1103 mtty_modem_control(mp, *((int *)data), DMBIC); 1104 break; 1105 1106 case TIOCMGET: /* get modem lines */ 1107 *((int *)data) = mtty_modem_control(mp, 0, DMGET); 1108 break; 1109 1110 case TIOCGFLAGS: 1111 *((int *)data) = mp->mp_openflags; 1112 break; 1113 1114 case TIOCSFLAGS: 1115 if (kauth_authorize_device_tty(l->l_cred, 1116 KAUTH_DEVICE_TTY_PRIVSET, tp)) 1117 error = EPERM; 1118 else 1119 mp->mp_openflags = *((int *)data) & 1120 (TIOCFLAG_SOFTCAR | TIOCFLAG_CLOCAL | 1121 TIOCFLAG_CRTSCTS | TIOCFLAG_MDMBUF); 1122 break; 1123 1124 default: 1125 error = EPASSTHROUGH; 1126 } 1127 1128 return(error); 1129 } 1130 1131 /* 1132 * Stop output, e.g., for ^S or output flush. 1133 */ 1134 void 1135 mttystop(struct tty *tp, int flags) 1136 { 1137 struct mtty_softc *ms = device_lookup_private(&mtty_cd, 1138 MAGMA_CARD(tp->t_dev)); 1139 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(tp->t_dev)]; 1140 int s; 1141 1142 s = spltty(); 1143 1144 if( ISSET(tp->t_state, TS_BUSY) ) { 1145 if( !ISSET(tp->t_state, TS_TTSTOP) ) 1146 SET(tp->t_state, TS_FLUSH); 1147 1148 /* 1149 * the transmit interrupt routine will disable transmit when it 1150 * notices that MTTYF_STOP has been set. 1151 */ 1152 SET(mp->mp_flags, MTTYF_STOP); 1153 } 1154 1155 splx(s); 1156 } 1157 1158 /* 1159 * Start output, after a stop. 1160 */ 1161 void 1162 mtty_start(struct tty *tp) 1163 { 1164 struct mtty_softc *ms = device_lookup_private(&mtty_cd, 1165 MAGMA_CARD(tp->t_dev)); 1166 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(tp->t_dev)]; 1167 int s; 1168 1169 s = spltty(); 1170 1171 /* we only need to do something if we are not already busy 1172 * or delaying or stopped 1173 */ 1174 if( !ISSET(tp->t_state, TS_TTSTOP | TS_TIMEOUT | TS_BUSY) ) { 1175 if (ttypull(tp)) { 1176 mp->mp_txc = ndqb(&tp->t_outq, 0); 1177 mp->mp_txp = tp->t_outq.c_cf; 1178 SET(tp->t_state, TS_BUSY); 1179 cd1400_enable_transmitter(mp->mp_cd1400, mp->mp_channel); 1180 } 1181 } 1182 1183 splx(s); 1184 } 1185 1186 /* 1187 * set/get modem line status 1188 * 1189 * bits can be: TIOCM_DTR, TIOCM_RTS, TIOCM_CTS, TIOCM_CD, TIOCM_RI, TIOCM_DSR 1190 * 1191 * note that DTR and RTS lines are exchanged, and that DSR is 1192 * not available on the LC2+1Sp card (used as CD) 1193 * 1194 * only let them fiddle with RTS if CRTSCTS is not enabled 1195 */ 1196 int 1197 mtty_modem_control(struct mtty_port *mp, int bits, int howto) 1198 { 1199 struct cd1400 *cd = mp->mp_cd1400; 1200 struct tty *tp = mp->mp_tty; 1201 int s, msvr; 1202 1203 s = spltty(); 1204 1205 cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel); 1206 1207 switch(howto) { 1208 case DMGET: /* get bits */ 1209 bits = 0; 1210 1211 bits |= TIOCM_LE; 1212 1213 msvr = cd1400_read_reg(cd, CD1400_MSVR1); 1214 if( msvr & CD1400_MSVR1_RTS ) bits |= TIOCM_DTR; 1215 1216 msvr = cd1400_read_reg(cd, CD1400_MSVR2); 1217 if( msvr & CD1400_MSVR2_DTR ) bits |= TIOCM_RTS; 1218 if( msvr & CD1400_MSVR2_CTS ) bits |= TIOCM_CTS; 1219 if( msvr & CD1400_MSVR2_RI ) bits |= TIOCM_RI; 1220 if( msvr & CD1400_MSVR2_DSR ) bits |= (cd->cd_parmode ? TIOCM_CD : TIOCM_DSR); 1221 if( msvr & CD1400_MSVR2_CD ) bits |= (cd->cd_parmode ? 0 : TIOCM_CD); 1222 1223 break; 1224 1225 case DMSET: /* reset bits */ 1226 if( !ISSET(tp->t_cflag, CRTSCTS) ) 1227 cd1400_write_reg(cd, CD1400_MSVR2, ((bits & TIOCM_RTS) ? CD1400_MSVR2_DTR : 0)); 1228 1229 cd1400_write_reg(cd, CD1400_MSVR1, ((bits & TIOCM_DTR) ? CD1400_MSVR1_RTS : 0)); 1230 1231 break; 1232 1233 case DMBIS: /* set bits */ 1234 if( (bits & TIOCM_RTS) && !ISSET(tp->t_cflag, CRTSCTS) ) 1235 cd1400_write_reg(cd, CD1400_MSVR2, CD1400_MSVR2_DTR); 1236 1237 if( bits & TIOCM_DTR ) 1238 cd1400_write_reg(cd, CD1400_MSVR1, CD1400_MSVR1_RTS); 1239 1240 break; 1241 1242 case DMBIC: /* clear bits */ 1243 if( (bits & TIOCM_RTS) && !ISSET(tp->t_cflag, CRTSCTS) ) 1244 cd1400_write_reg(cd, CD1400_MSVR2, 0); 1245 1246 if( bits & TIOCM_DTR ) 1247 cd1400_write_reg(cd, CD1400_MSVR1, 0); 1248 1249 break; 1250 } 1251 1252 splx(s); 1253 return(bits); 1254 } 1255 1256 /* 1257 * Set tty parameters, returns error or 0 on success 1258 */ 1259 int 1260 mtty_param(struct tty *tp, struct termios *t) 1261 { 1262 struct mtty_softc *ms = device_lookup_private(&mtty_cd, 1263 MAGMA_CARD(tp->t_dev)); 1264 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(tp->t_dev)]; 1265 struct cd1400 *cd = mp->mp_cd1400; 1266 int rbpr, tbpr, rcor, tcor; 1267 u_char mcor1 = 0, mcor2 = 0; 1268 int s, opt; 1269 1270 if( t->c_ospeed && cd1400_compute_baud(t->c_ospeed, cd->cd_clock, &tcor, &tbpr) ) 1271 return(EINVAL); 1272 1273 if( t->c_ispeed && cd1400_compute_baud(t->c_ispeed, cd->cd_clock, &rcor, &rbpr) ) 1274 return(EINVAL); 1275 1276 s = spltty(); 1277 1278 /* hang up the line if ospeed is zero, else raise DTR */ 1279 (void)mtty_modem_control(mp, TIOCM_DTR, (t->c_ospeed == 0 ? DMBIC : DMBIS)); 1280 1281 /* select channel, done in mtty_modem_control() */ 1282 /* cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel); */ 1283 1284 /* set transmit speed */ 1285 if( t->c_ospeed ) { 1286 cd1400_write_reg(cd, CD1400_TCOR, tcor); 1287 cd1400_write_reg(cd, CD1400_TBPR, tbpr); 1288 } 1289 1290 /* set receive speed */ 1291 if( t->c_ispeed ) { 1292 cd1400_write_reg(cd, CD1400_RCOR, rcor); 1293 cd1400_write_reg(cd, CD1400_RBPR, rbpr); 1294 } 1295 1296 /* enable transmitting and receiving on this channel */ 1297 opt = CD1400_CCR_CMDCHANCTL | CD1400_CCR_XMTEN | CD1400_CCR_RCVEN; 1298 cd1400_write_ccr(cd, opt); 1299 1300 /* set parity, data and stop bits */ 1301 opt = 0; 1302 if( ISSET(t->c_cflag, PARENB) ) 1303 opt |= (ISSET(t->c_cflag, PARODD) ? CD1400_COR1_PARODD : CD1400_COR1_PARNORMAL); 1304 1305 if( !ISSET(t->c_iflag, INPCK) ) 1306 opt |= CD1400_COR1_NOINPCK; /* no parity checking */ 1307 1308 if( ISSET(t->c_cflag, CSTOPB) ) 1309 opt |= CD1400_COR1_STOP2; 1310 1311 switch( t->c_cflag & CSIZE ) { 1312 case CS5: 1313 opt |= CD1400_COR1_CS5; 1314 break; 1315 1316 case CS6: 1317 opt |= CD1400_COR1_CS6; 1318 break; 1319 1320 case CS7: 1321 opt |= CD1400_COR1_CS7; 1322 break; 1323 1324 default: 1325 opt |= CD1400_COR1_CS8; 1326 break; 1327 } 1328 1329 cd1400_write_reg(cd, CD1400_COR1, opt); 1330 1331 /* 1332 * enable Embedded Transmit Commands (for breaks) 1333 * use the CD1400 automatic CTS flow control if CRTSCTS is set 1334 */ 1335 opt = CD1400_COR2_ETC; 1336 if( ISSET(t->c_cflag, CRTSCTS) ) opt |= CD1400_COR2_CCTS_OFLOW; 1337 cd1400_write_reg(cd, CD1400_COR2, opt); 1338 1339 cd1400_write_reg(cd, CD1400_COR3, MTTY_RX_FIFO_THRESHOLD); 1340 1341 cd1400_write_ccr(cd, CD1400_CCR_CMDCORCHG | CD1400_CCR_COR1 | CD1400_CCR_COR2 | CD1400_CCR_COR3); 1342 1343 cd1400_write_reg(cd, CD1400_COR4, CD1400_COR4_PFO_EXCEPTION); 1344 cd1400_write_reg(cd, CD1400_COR5, 0); 1345 1346 /* 1347 * if automatic RTS handshaking enabled, set DTR threshold 1348 * (RTS and DTR lines are switched, CD1400 thinks its DTR) 1349 */ 1350 if( ISSET(t->c_cflag, CRTSCTS) ) 1351 mcor1 = MTTY_RX_DTR_THRESHOLD; 1352 1353 /* set up `carrier detect' interrupts */ 1354 if( cd->cd_parmode ) { 1355 SET(mcor1, CD1400_MCOR1_DSRzd); 1356 SET(mcor2, CD1400_MCOR2_DSRod); 1357 } else { 1358 SET(mcor1, CD1400_MCOR1_CDzd); 1359 SET(mcor2, CD1400_MCOR2_CDod); 1360 } 1361 1362 cd1400_write_reg(cd, CD1400_MCOR1, mcor1); 1363 cd1400_write_reg(cd, CD1400_MCOR2, mcor2); 1364 1365 /* receive timeout 2ms */ 1366 cd1400_write_reg(cd, CD1400_RTPR, 2); 1367 1368 splx(s); 1369 return(0); 1370 } 1371 1372 /************************************************************************ 1373 * 1374 * MBPP Routines 1375 * 1376 * mbpp_match match one mbpp device 1377 * mbpp_attach attach mbpp devices 1378 * mbppopen open mbpp device 1379 * mbppclose close mbpp device 1380 * mbppioctl do ioctl on mbpp 1381 * mbpp_rw general rw routine 1382 * mbpp_timeout rw timeout 1383 * mbpp_start rw start after delay 1384 * mbpp_send send data 1385 * mbpp_recv recv data 1386 */ 1387 1388 int 1389 mbpp_match(device_t parent, cfdata_t cf, void *args) 1390 { 1391 struct magma_softc *sc = device_private(parent); 1392 1393 return( args == mbpp_match && sc->ms_board->mb_npar && sc->ms_mbpp == NULL ); 1394 } 1395 1396 void 1397 mbpp_attach(device_t parent, device_t dev, void *args) 1398 { 1399 struct magma_softc *sc = device_private(parent); 1400 struct mbpp_softc *ms = device_private(dev); 1401 struct mbpp_port *mp; 1402 int port; 1403 1404 sc->ms_mbpp = ms; 1405 dprintf((" addr %p", ms)); 1406 1407 for( port = 0 ; port < sc->ms_board->mb_npar ; port++ ) { 1408 mp = &ms->ms_port[port]; 1409 1410 callout_init(&mp->mp_timeout_ch, 0); 1411 callout_init(&mp->mp_start_ch, 0); 1412 1413 if( sc->ms_ncd1190 ) 1414 mp->mp_cd1190 = &sc->ms_cd1190[port]; 1415 else 1416 mp->mp_cd1400 = &sc->ms_cd1400[0]; 1417 } 1418 1419 ms->ms_nports = port; 1420 printf(": %d port%s\n", port, port == 1 ? "" : "s"); 1421 } 1422 1423 /* 1424 * open routine. returns zero if successful, else error code 1425 */ 1426 int 1427 mbppopen(dev_t dev, int flags, int mode, struct lwp *l) 1428 { 1429 int card = MAGMA_CARD(dev); 1430 int port = MAGMA_PORT(dev); 1431 struct mbpp_softc *ms; 1432 struct mbpp_port *mp; 1433 int s; 1434 1435 if ((ms = device_lookup_private(&mbpp_cd, card)) == NULL 1436 || port >= ms->ms_nports ) 1437 return(ENXIO); 1438 1439 mp = &ms->ms_port[port]; 1440 1441 s = spltty(); 1442 if( ISSET(mp->mp_flags, MBPPF_OPEN) ) { 1443 splx(s); 1444 return(EBUSY); 1445 } 1446 SET(mp->mp_flags, MBPPF_OPEN); 1447 splx(s); 1448 1449 /* set defaults */ 1450 mp->mp_burst = MBPP_BURST; 1451 mp->mp_timeout = mbpp_mstohz(MBPP_TIMEOUT); 1452 mp->mp_delay = mbpp_mstohz(MBPP_DELAY); 1453 1454 /* init chips */ 1455 if( mp->mp_cd1400 ) { /* CD1400 */ 1456 struct cd1400 *cd = mp->mp_cd1400; 1457 1458 /* set up CD1400 channel */ 1459 s = spltty(); 1460 cd1400_write_reg(cd, CD1400_CAR, 0); 1461 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET); 1462 cd1400_write_reg(cd, CD1400_LIVR, (1<<3)); 1463 splx(s); 1464 } else { /* CD1190 */ 1465 mp->mp_flags = 0; 1466 return (ENXIO); 1467 } 1468 1469 return (0); 1470 } 1471 1472 /* 1473 * close routine. returns zero if successful, else error code 1474 */ 1475 int 1476 mbppclose(dev_t dev, int flag, int mode, struct lwp *l) 1477 { 1478 struct mbpp_softc *ms = device_lookup_private(&mbpp_cd, 1479 MAGMA_CARD(dev)); 1480 struct mbpp_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1481 1482 mp->mp_flags = 0; 1483 return(0); 1484 } 1485 1486 /* 1487 * ioctl routine 1488 */ 1489 int 1490 mbppioctl(dev_t dev, u_long cmd, void *data, int flags, struct lwp *l) 1491 { 1492 struct mbpp_softc *ms = device_lookup_private(&mbpp_cd, 1493 MAGMA_CARD(dev)); 1494 struct mbpp_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1495 struct mbpp_param *bp; 1496 int error = 0; 1497 int s; 1498 1499 switch(cmd) { 1500 case MBPPIOCSPARAM: 1501 bp = (struct mbpp_param *)data; 1502 if( bp->bp_burst < MBPP_BURST_MIN || bp->bp_burst > MBPP_BURST_MAX || 1503 bp->bp_delay < MBPP_DELAY_MIN || bp->bp_delay > MBPP_DELAY_MIN ) { 1504 error = EINVAL; 1505 } else { 1506 mp->mp_burst = bp->bp_burst; 1507 mp->mp_timeout = mbpp_mstohz(bp->bp_timeout); 1508 mp->mp_delay = mbpp_mstohz(bp->bp_delay); 1509 } 1510 break; 1511 case MBPPIOCGPARAM: 1512 bp = (struct mbpp_param *)data; 1513 bp->bp_burst = mp->mp_burst; 1514 bp->bp_timeout = mbpp_hztoms(mp->mp_timeout); 1515 bp->bp_delay = mbpp_hztoms(mp->mp_delay); 1516 break; 1517 case MBPPIOCGSTAT: 1518 /* XXX make this more generic */ 1519 s = spltty(); 1520 cd1400_write_reg(mp->mp_cd1400, CD1400_CAR, 0); 1521 *(int *)data = cd1400_read_reg(mp->mp_cd1400, CD1400_PSVR); 1522 splx(s); 1523 break; 1524 default: 1525 error = ENOTTY; 1526 } 1527 1528 return(error); 1529 } 1530 1531 int 1532 mbpp_rw(dev_t dev, struct uio *uio, int flag) 1533 { 1534 int card = MAGMA_CARD(dev); 1535 int port = MAGMA_PORT(dev); 1536 struct mbpp_softc *ms = device_lookup_private(&mbpp_cd, card); 1537 struct mbpp_port *mp = &ms->ms_port[port]; 1538 char *buffer, *ptr; 1539 int buflen, cnt, len; 1540 int s, error = 0; 1541 int gotdata = 0; 1542 1543 if( uio->uio_resid == 0 ) 1544 return(0); 1545 1546 buflen = min(uio->uio_resid, mp->mp_burst); 1547 buffer = malloc(buflen, M_DEVBUF, M_WAITOK); 1548 if( buffer == NULL ) 1549 return(ENOMEM); 1550 1551 SET(mp->mp_flags, MBPPF_UIO); 1552 1553 /* 1554 * start timeout, if needed 1555 */ 1556 if( mp->mp_timeout > 0 ) { 1557 SET(mp->mp_flags, MBPPF_TIMEOUT); 1558 callout_reset(&mp->mp_timeout_ch, mp->mp_timeout, 1559 mbpp_timeout, mp); 1560 } 1561 1562 len = cnt = 0; 1563 while( uio->uio_resid > 0 ) { 1564 len = min(buflen, uio->uio_resid); 1565 ptr = buffer; 1566 1567 if( uio->uio_rw == UIO_WRITE ) { 1568 error = uiomove(ptr, len, uio); 1569 if( error ) break; 1570 } 1571 again: /* goto bad */ 1572 /* timed out? */ 1573 if( !ISSET(mp->mp_flags, MBPPF_UIO) ) 1574 break; 1575 1576 /* 1577 * perform the operation 1578 */ 1579 if( uio->uio_rw == UIO_WRITE ) { 1580 cnt = mbpp_send(mp, ptr, len); 1581 } else { 1582 cnt = mbpp_recv(mp, ptr, len); 1583 } 1584 1585 if( uio->uio_rw == UIO_READ ) { 1586 if( cnt ) { 1587 error = uiomove(ptr, cnt, uio); 1588 if( error ) break; 1589 gotdata++; 1590 } 1591 else if( gotdata ) /* consider us done */ 1592 break; 1593 } 1594 1595 /* timed out? */ 1596 if( !ISSET(mp->mp_flags, MBPPF_UIO) ) 1597 break; 1598 1599 /* 1600 * poll delay? 1601 */ 1602 if( mp->mp_delay > 0 ) { 1603 s = splsoftclock(); 1604 SET(mp->mp_flags, MBPPF_DELAY); 1605 callout_reset(&mp->mp_start_ch, mp->mp_delay, 1606 mbpp_start, mp); 1607 error = tsleep(mp, PCATCH | PZERO, "mbppdelay", 0); 1608 splx(s); 1609 if( error ) break; 1610 } 1611 1612 /* 1613 * don't call uiomove again until we used all the data we grabbed 1614 */ 1615 if( uio->uio_rw == UIO_WRITE && cnt != len ) { 1616 ptr += cnt; 1617 len -= cnt; 1618 cnt = 0; 1619 goto again; 1620 } 1621 } 1622 1623 /* 1624 * clear timeouts 1625 */ 1626 s = splsoftclock(); 1627 if( ISSET(mp->mp_flags, MBPPF_TIMEOUT) ) { 1628 callout_stop(&mp->mp_timeout_ch); 1629 CLR(mp->mp_flags, MBPPF_TIMEOUT); 1630 } 1631 if( ISSET(mp->mp_flags, MBPPF_DELAY) ) { 1632 callout_stop(&mp->mp_start_ch); 1633 CLR(mp->mp_flags, MBPPF_DELAY); 1634 } 1635 splx(s); 1636 1637 /* 1638 * adjust for those chars that we uiomoved but never actually wrote 1639 */ 1640 if( uio->uio_rw == UIO_WRITE && cnt != len ) { 1641 uio->uio_resid += (len - cnt); 1642 } 1643 1644 free(buffer, M_DEVBUF); 1645 return(error); 1646 } 1647 1648 void 1649 mbpp_timeout(void *arg) 1650 { 1651 struct mbpp_port *mp = arg; 1652 1653 CLR(mp->mp_flags, MBPPF_UIO | MBPPF_TIMEOUT); 1654 wakeup(mp); 1655 } 1656 1657 void 1658 mbpp_start(void *arg) 1659 { 1660 struct mbpp_port *mp = arg; 1661 1662 CLR(mp->mp_flags, MBPPF_DELAY); 1663 wakeup(mp); 1664 } 1665 1666 int 1667 mbpp_send(struct mbpp_port *mp, void *ptr, int len) 1668 { 1669 int s; 1670 struct cd1400 *cd = mp->mp_cd1400; 1671 1672 /* set up io information */ 1673 mp->mp_ptr = ptr; 1674 mp->mp_cnt = len; 1675 1676 /* start transmitting */ 1677 s = spltty(); 1678 if( cd ) { 1679 cd1400_write_reg(cd, CD1400_CAR, 0); 1680 1681 /* output strobe width ~1microsecond */ 1682 cd1400_write_reg(cd, CD1400_TBPR, 10); 1683 1684 /* enable channel */ 1685 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_XMTEN); 1686 cd1400_write_reg(cd, CD1400_SRER, CD1400_SRER_TXRDY); 1687 } 1688 1689 /* ZZzzz... */ 1690 tsleep(mp, PCATCH | PZERO, "mbpp_send", 0); 1691 1692 /* stop transmitting */ 1693 if( cd ) { 1694 cd1400_write_reg(cd, CD1400_CAR, 0); 1695 1696 /* disable transmitter */ 1697 cd1400_write_reg(cd, CD1400_SRER, 0); 1698 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_XMTDIS); 1699 1700 /* flush fifo */ 1701 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET | CD1400_CCR_FTF); 1702 } 1703 splx(s); 1704 1705 /* return number of chars sent */ 1706 return(len - mp->mp_cnt); 1707 } 1708 1709 int 1710 mbpp_recv(struct mbpp_port *mp, void *ptr, int len) 1711 { 1712 int s; 1713 struct cd1400 *cd = mp->mp_cd1400; 1714 1715 /* set up io information */ 1716 mp->mp_ptr = ptr; 1717 mp->mp_cnt = len; 1718 1719 /* start receiving */ 1720 s = spltty(); 1721 if( cd ) { 1722 int rcor, rbpr; 1723 1724 cd1400_write_reg(cd, CD1400_CAR, 0); 1725 1726 /* input strobe at 100kbaud (10microseconds) */ 1727 cd1400_compute_baud(100000, cd->cd_clock, &rcor, &rbpr); 1728 cd1400_write_reg(cd, CD1400_RCOR, rcor); 1729 cd1400_write_reg(cd, CD1400_RBPR, rbpr); 1730 1731 /* rx threshold */ 1732 cd1400_write_reg(cd, CD1400_COR3, MBPP_RX_FIFO_THRESHOLD); 1733 cd1400_write_ccr(cd, CD1400_CCR_CMDCORCHG | CD1400_CCR_COR3); 1734 1735 /* enable channel */ 1736 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_RCVEN); 1737 cd1400_write_reg(cd, CD1400_SRER, CD1400_SRER_RXDATA); 1738 } 1739 1740 /* ZZzzz... */ 1741 tsleep(mp, PCATCH | PZERO, "mbpp_recv", 0); 1742 1743 /* stop receiving */ 1744 if( cd ) { 1745 cd1400_write_reg(cd, CD1400_CAR, 0); 1746 1747 /* disable receiving */ 1748 cd1400_write_reg(cd, CD1400_SRER, 0); 1749 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_RCVDIS); 1750 } 1751 splx(s); 1752 1753 /* return number of chars received */ 1754 return(len - mp->mp_cnt); 1755 } 1756 1757 int 1758 mbpp_hztoms(int h) 1759 { 1760 int m = h; 1761 1762 if( m > 0 ) 1763 m = m * 1000 / hz; 1764 return(m); 1765 } 1766 1767 int 1768 mbpp_mstohz(int m) 1769 { 1770 int h = m; 1771 1772 if( h > 0 ) { 1773 h = h * hz / 1000; 1774 if( h == 0 ) 1775 h = 1000 / hz; 1776 } 1777 return(h); 1778 } 1779 1780 #endif /* NMAGMA */ 1781
Indexes created Thu Oct 02 14:10:14 GMT 2025