magma.c revision 1.56
1 /* $NetBSD: magma.c,v 1.56 2012/10/27 17:18:37 chs Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 Iain Hibbert 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 /* 29 * Driver for Magma SBus Serial/Parallel cards using the Cirrus Logic 30 * CD1400 & CD1190 chips 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: magma.c,v 1.56 2012/10/27 17:18:37 chs Exp $"); 35 36 #if 0 37 #define MAGMA_DEBUG 38 #endif 39 40 #include "magma.h" 41 #if NMAGMA > 0 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/proc.h> 46 #include <sys/device.h> 47 #include <sys/file.h> 48 #include <sys/ioctl.h> 49 #include <sys/malloc.h> 50 #include <sys/tty.h> 51 #include <sys/time.h> 52 #include <sys/kernel.h> 53 #include <sys/syslog.h> 54 #include <sys/conf.h> 55 #include <sys/errno.h> 56 #include <sys/kauth.h> 57 #include <sys/intr.h> 58 59 #include <sys/bus.h> 60 #include <machine/autoconf.h> 61 62 #include <dev/sbus/sbusvar.h> 63 64 #include <dev/ic/cd1400reg.h> 65 #include <dev/ic/cd1190reg.h> 66 67 #include <dev/sbus/mbppio.h> 68 #include <dev/sbus/magmareg.h> 69 70 #include "ioconf.h" 71 72 /* supported cards 73 * 74 * The table below lists the cards that this driver is likely to 75 * be able to support. 76 * 77 * Cards with parallel ports: except for the LC2+1Sp, they all use 78 * the CD1190 chip which I know nothing about. I've tried to leave 79 * hooks for it so it shouldn't be too hard to add support later. 80 * (I think somebody is working on this separately) 81 * 82 * Thanks to Bruce at Magma for telling me the hardware offsets. 83 */ 84 static struct magma_board_info supported_cards[] = { 85 { 86 "MAGMA_Sp", "MAGMA,4_Sp", "Magma 4 Sp", 4, 0, 87 1, 0xa000, 0xc000, 0xe000, { 0x8000, 0, 0, 0 }, 88 0, { 0, 0 } 89 }, 90 { 91 "MAGMA_Sp", "MAGMA,8_Sp", "Magma 8 Sp", 8, 0, 92 2, 0xa000, 0xc000, 0xe000, { 0x4000, 0x6000, 0, 0 }, 93 0, { 0, 0 } 94 }, 95 { 96 "MAGMA_Sp", "MAGMA,_8HS_Sp", "Magma Fast 8 Sp", 8, 0, 97 2, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0, 0 }, 98 0, { 0, 0 } 99 }, 100 { 101 "MAGMA_Sp", "MAGMA,_8SP_422", "Magma 8 Sp - 422", 8, 0, 102 2, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0, 0 }, 103 0, { 0, 0 } 104 }, 105 { 106 "MAGMA_Sp", "MAGMA,12_Sp", "Magma 12 Sp", 12, 0, 107 3, 0xa000, 0xc000, 0xe000, { 0x2000, 0x4000, 0x6000, 0 }, 108 0, { 0, 0 } 109 }, 110 { 111 "MAGMA_Sp", "MAGMA,16_Sp", "Magma 16 Sp", 16, 0, 112 4, 0xd000, 0xe000, 0xf000, { 0x8000, 0x9000, 0xa000, 0xb000 }, 113 0, { 0, 0 } 114 }, 115 { 116 "MAGMA_Sp", "MAGMA,16_Sp_2", "Magma 16 Sp", 16, 0, 117 4, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0xc000, 0xe000 }, 118 0, { 0, 0 } 119 }, 120 { 121 "MAGMA_Sp", "MAGMA,16HS_Sp", "Magma Fast 16 Sp", 16, 0, 122 4, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0xc000, 0xe000 }, 123 0, { 0, 0 } 124 }, 125 { 126 "MAGMA_Sp", "MAGMA,21_Sp", "Magma LC 2+1 Sp", 2, 1, 127 1, 0xa000, 0xc000, 0xe000, { 0x8000, 0, 0, 0 }, 128 0, { 0, 0 } 129 }, 130 { 131 "MAGMA_Sp", "MAGMA,21HS_Sp", "Magma 2+1 Sp", 2, 1, 132 1, 0xa000, 0xc000, 0xe000, { 0x4000, 0, 0, 0 }, 133 1, { 0x6000, 0 } 134 }, 135 { 136 "MAGMA_Sp", "MAGMA,41_Sp", "Magma 4+1 Sp", 4, 1, 137 1, 0xa000, 0xc000, 0xe000, { 0x4000, 0, 0, 0 }, 138 1, { 0x6000, 0 } 139 }, 140 { 141 "MAGMA_Sp", "MAGMA,82_Sp", "Magma 8+2 Sp", 8, 2, 142 2, 0xd000, 0xe000, 0xf000, { 0x8000, 0x9000, 0, 0 }, 143 2, { 0xa000, 0xb000 } 144 }, 145 { 146 "MAGMA_Sp", "MAGMA,P1_Sp", "Magma P1 Sp", 0, 1, 147 0, 0, 0, 0, { 0, 0, 0, 0 }, 148 1, { 0x8000, 0 } 149 }, 150 { 151 "MAGMA_Sp", "MAGMA,P2_Sp", "Magma P2 Sp", 0, 2, 152 0, 0, 0, 0, { 0, 0, 0, 0 }, 153 2, { 0x4000, 0x8000 } 154 }, 155 { 156 "MAGMA 2+1HS Sp", "", "Magma 2+1HS Sp", 2, 0, 157 1, 0xa000, 0xc000, 0xe000, { 0x4000, 0, 0, 0 }, 158 1, { 0x8000, 0 } 159 }, 160 { 161 NULL, NULL, NULL, 0, 0, 162 0, 0, 0, 0, { 0, 0, 0, 0 }, 163 0, { 0, 0 } 164 } 165 }; 166 167 /************************************************************************ 168 * 169 * Autoconfig Stuff 170 */ 171 172 CFATTACH_DECL_NEW(magma, sizeof(struct magma_softc), 173 magma_match, magma_attach, NULL, NULL); 174 175 CFATTACH_DECL_NEW(mtty, sizeof(struct mtty_softc), 176 mtty_match, mtty_attach, NULL, NULL); 177 178 CFATTACH_DECL_NEW(mbpp, sizeof(struct mbpp_softc), 179 mbpp_match, mbpp_attach, NULL, NULL); 180 181 dev_type_open(mttyopen); 182 dev_type_close(mttyclose); 183 dev_type_read(mttyread); 184 dev_type_write(mttywrite); 185 dev_type_ioctl(mttyioctl); 186 dev_type_stop(mttystop); 187 dev_type_tty(mttytty); 188 dev_type_poll(mttypoll); 189 190 const struct cdevsw mtty_cdevsw = { 191 mttyopen, mttyclose, mttyread, mttywrite, mttyioctl, 192 mttystop, mttytty, mttypoll, nommap, ttykqfilter, D_TTY 193 }; 194 195 dev_type_open(mbppopen); 196 dev_type_close(mbppclose); 197 dev_type_read(mbpp_rw); 198 dev_type_ioctl(mbppioctl); 199 200 const struct cdevsw mbpp_cdevsw = { 201 mbppopen, mbppclose, mbpp_rw, mbpp_rw, mbppioctl, 202 nostop, notty, nopoll, nommap, nokqfilter, D_OTHER 203 }; 204 205 /************************************************************************ 206 * 207 * CD1400 Routines 208 * 209 * cd1400_compute_baud calculate COR/BPR register values 210 * cd1400_write_ccr write a value to CD1400 ccr 211 * cd1400_read_reg read from a CD1400 register 212 * cd1400_write_reg write to a CD1400 register 213 * cd1400_enable_transmitter enable transmitting on CD1400 channel 214 */ 215 216 /* 217 * compute the bpr/cor pair for any baud rate 218 * returns 0 for success, 1 for failure 219 */ 220 int 221 cd1400_compute_baud(speed_t speed, int clock, int *cor, int *bpr) 222 { 223 int c, co, br; 224 225 if( speed < 50 || speed > 150000 ) 226 return(1); 227 228 for( c = 0, co = 8 ; co <= 2048 ; co <<= 2, c++ ) { 229 br = ((clock * 1000000) + (co * speed) / 2) / (co * speed); 230 if( br < 0x100 ) { 231 *bpr = br; 232 *cor = c; 233 return(0); 234 } 235 } 236 237 return(1); 238 } 239 240 /* 241 * Write a CD1400 channel command, should have a timeout? 242 */ 243 inline void 244 cd1400_write_ccr(struct cd1400 *cd, u_char cmd) 245 { 246 while( cd1400_read_reg(cd, CD1400_CCR) ) 247 ; 248 249 cd1400_write_reg(cd, CD1400_CCR, cmd); 250 } 251 252 /* 253 * read a value from a cd1400 register 254 */ 255 inline u_char 256 cd1400_read_reg(struct cd1400 *cd, int reg) 257 { 258 return(cd->cd_reg[reg]); 259 } 260 261 /* 262 * write a value to a cd1400 register 263 */ 264 inline void 265 cd1400_write_reg(struct cd1400 *cd, int reg, u_char value) 266 { 267 cd->cd_reg[reg] = value; 268 } 269 270 /* 271 * enable transmit service requests for cd1400 channel 272 */ 273 void 274 cd1400_enable_transmitter(struct cd1400 *cd, int channel) 275 { 276 int s, srer; 277 278 s = spltty(); 279 cd1400_write_reg(cd, CD1400_CAR, channel); 280 srer = cd1400_read_reg(cd, CD1400_SRER); 281 SET(srer, CD1400_SRER_TXRDY); 282 cd1400_write_reg(cd, CD1400_SRER, srer); 283 splx(s); 284 } 285 286 /************************************************************************ 287 * 288 * CD1190 Routines 289 */ 290 291 /* well, there are none yet */ 292 293 /************************************************************************ 294 * 295 * Magma Routines 296 * 297 * magma_match reports if we have a magma board available 298 * magma_attach attaches magma boards to the sbus 299 * magma_hard hardware level interrupt routine 300 * magma_soft software level interrupt routine 301 */ 302 303 int 304 magma_match(device_t parent, cfdata_t cf, void *aux) 305 { 306 struct sbus_attach_args *sa = aux; 307 struct magma_board_info *card; 308 309 /* See if we support this device */ 310 for (card = supported_cards; ; card++) { 311 if (card->mb_sbusname == NULL) 312 /* End of table: no match */ 313 return (0); 314 if (strcmp(sa->sa_name, card->mb_sbusname) == 0) 315 break; 316 } 317 318 dprintf(("magma: matched `%s'\n", sa->sa_name)); 319 dprintf(("magma: magma_prom `%s'\n", 320 prom_getpropstring(sa->sa_node, "magma_prom"))); 321 dprintf(("magma: intlevels `%s'\n", 322 prom_getpropstring(sa->sa_node, "intlevels"))); 323 dprintf(("magma: chiprev `%s'\n", 324 prom_getpropstring(sa->sa_node, "chiprev"))); 325 dprintf(("magma: clock `%s'\n", 326 prom_getpropstring(sa->sa_node, "clock"))); 327 328 return (1); 329 } 330 331 void 332 magma_attach(device_t parent, device_t self, void *aux) 333 { 334 struct sbus_attach_args *sa = aux; 335 struct magma_softc *sc = device_private(self); 336 struct magma_board_info *card; 337 bus_space_handle_t bh; 338 char *magma_prom, *clockstr; 339 int cd_clock; 340 int node, chip; 341 342 sc->ms_dev = self; 343 node = sa->sa_node; 344 345 /* 346 * Find the card model. 347 * Older models all have sbus node name `MAGMA_Sp' (see 348 * `supported_cards[]' above), and must be distinguished 349 * by the `magma_prom' property. 350 */ 351 magma_prom = prom_getpropstring(node, "magma_prom"); 352 353 for (card = supported_cards; card->mb_name != NULL; card++) { 354 if (strcmp(sa->sa_name, card->mb_sbusname) != 0) 355 /* Sbus node name doesn't match */ 356 continue; 357 if (strcmp(magma_prom, card->mb_name) == 0) 358 /* Model name match */ 359 break; 360 } 361 362 if( card->mb_name == NULL ) { 363 printf(": %s (unsupported)\n", magma_prom); 364 return; 365 } 366 367 dprintf((" addr %p", sc)); 368 printf(": %s\n", card->mb_realname); 369 370 sc->ms_board = card; 371 sc->ms_ncd1400 = card->mb_ncd1400; 372 sc->ms_ncd1190 = card->mb_ncd1190; 373 374 if (sbus_bus_map(sa->sa_bustag, 375 sa->sa_slot, sa->sa_offset, sa->sa_size, 376 BUS_SPACE_MAP_LINEAR, &bh) != 0) { 377 aprint_error("%s @ sbus: cannot map registers\n", 378 device_xname(self)); 379 return; 380 } 381 382 /* the SVCACK* lines are daisychained */ 383 sc->ms_svcackr = (char *)bus_space_vaddr(sa->sa_bustag, bh) 384 + card->mb_svcackr; 385 sc->ms_svcackt = (char *)bus_space_vaddr(sa->sa_bustag, bh) 386 + card->mb_svcackt; 387 sc->ms_svcackm = (char *)bus_space_vaddr(sa->sa_bustag, bh) 388 + card->mb_svcackm; 389 390 /* 391 * Find the clock speed; it's the same for all CD1400 chips 392 * on the board. 393 */ 394 clockstr = prom_getpropstring(node, "clock"); 395 if (*clockstr == '\0') 396 /* Default to 25MHz */ 397 cd_clock = 25; 398 else { 399 cd_clock = 0; 400 while (*clockstr != '\0') 401 cd_clock = (cd_clock * 10) + (*clockstr++ - '0'); 402 } 403 404 /* init the cd1400 chips */ 405 for( chip = 0 ; chip < card->mb_ncd1400 ; chip++ ) { 406 struct cd1400 *cd = &sc->ms_cd1400[chip]; 407 408 cd->cd_clock = cd_clock; 409 cd->cd_reg = (char *)bus_space_vaddr(sa->sa_bustag, bh) + 410 card->mb_cd1400[chip]; 411 412 /* prom_getpropstring(node, "chiprev"); */ 413 /* seemingly the Magma drivers just ignore the propstring */ 414 cd->cd_chiprev = cd1400_read_reg(cd, CD1400_GFRCR); 415 416 dprintf(("%s attach CD1400 %d addr %p rev %x clock %dMHz\n", 417 device_xname(sc->ms_dev), chip, 418 cd->cd_reg, cd->cd_chiprev, cd->cd_clock)); 419 420 /* clear GFRCR */ 421 cd1400_write_reg(cd, CD1400_GFRCR, 0x00); 422 423 /* reset whole chip */ 424 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET | CD1400_CCR_FULLRESET); 425 426 /* wait for revision code to be restored */ 427 while( cd1400_read_reg(cd, CD1400_GFRCR) != cd->cd_chiprev ) 428 ; 429 430 /* set the Prescaler Period Register to tick at 1ms */ 431 cd1400_write_reg(cd, CD1400_PPR, 432 ((cd->cd_clock * 1000000 / CD1400_PPR_PRESCALER + 500) / 1000)); 433 434 /* The LC2+1Sp card is the only card that doesn't have 435 * a CD1190 for the parallel port, but uses channel 0 of 436 * the CD1400, so we make a note of it for later and set up 437 * the CD1400 for parallel mode operation. 438 */ 439 if( card->mb_npar && card->mb_ncd1190 == 0 ) { 440 cd1400_write_reg(cd, CD1400_GCR, CD1400_GCR_PARALLEL); 441 cd->cd_parmode = 1; 442 } 443 } 444 445 /* init the cd1190 chips */ 446 for( chip = 0 ; chip < card->mb_ncd1190 ; chip++ ) { 447 struct cd1190 *cd = &sc->ms_cd1190[chip]; 448 449 cd->cd_reg = (char *)bus_space_vaddr(sa->sa_bustag, bh) + 450 card->mb_cd1190[chip]; 451 452 /* XXX don't know anything about these chips yet */ 453 printf("%s: CD1190 %d addr %p (unsupported)\n", 454 device_xname(self), chip, cd->cd_reg); 455 } 456 457 /* configure the children */ 458 (void)config_found(self, mtty_match, NULL); 459 (void)config_found(self, mbpp_match, NULL); 460 461 /* 462 * Establish the interrupt handlers. 463 */ 464 if (sa->sa_nintr == 0) 465 return; /* No interrupts to service!? */ 466 467 (void)bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_SERIAL, 468 magma_hard, sc); 469 sc->ms_sicookie = softint_establish(SOFTINT_SERIAL, magma_soft, sc); 470 if (sc->ms_sicookie == NULL) { 471 aprint_normal("\n"); 472 aprint_error_dev(sc->ms_dev, "cannot establish soft int handler\n"); 473 return; 474 } 475 evcnt_attach_dynamic(&sc->ms_intrcnt, EVCNT_TYPE_INTR, NULL, 476 device_xname(sc->ms_dev), "intr"); 477 } 478 479 /* 480 * hard interrupt routine 481 * 482 * returns 1 if it handled it, otherwise 0 483 * 484 * runs at IPL_SERIAL 485 */ 486 int 487 magma_hard(void *arg) 488 { 489 struct magma_softc *sc = arg; 490 struct cd1400 *cd; 491 int chip, status = 0; 492 int serviced = 0; 493 int needsoftint = 0; 494 495 /* 496 * check status of all the CD1400 chips 497 */ 498 for( chip = 0 ; chip < sc->ms_ncd1400 ; chip++ ) 499 status |= cd1400_read_reg(&sc->ms_cd1400[chip], CD1400_SVRR); 500 501 if( ISSET(status, CD1400_SVRR_RXRDY) ) { 502 u_char rivr = *sc->ms_svcackr; /* enter rx service context */ 503 int port = rivr >> 4; 504 505 if( rivr & (1<<3) ) { /* parallel port */ 506 struct mbpp_port *mbpp; 507 int n_chars; 508 509 mbpp = &sc->ms_mbpp->ms_port[port]; 510 cd = mbpp->mp_cd1400; 511 512 /* don't think we have to handle exceptions */ 513 n_chars = cd1400_read_reg(cd, CD1400_RDCR); 514 while (n_chars--) { 515 if( mbpp->mp_cnt == 0 ) { 516 SET(mbpp->mp_flags, MBPPF_WAKEUP); 517 needsoftint = 1; 518 break; 519 } 520 *mbpp->mp_ptr = cd1400_read_reg(cd,CD1400_RDSR); 521 mbpp->mp_ptr++; 522 mbpp->mp_cnt--; 523 } 524 } else { /* serial port */ 525 struct mtty_port *mtty; 526 u_char *ptr, n_chars, line_stat; 527 528 mtty = &sc->ms_mtty->ms_port[port]; 529 cd = mtty->mp_cd1400; 530 531 if( ISSET(rivr, CD1400_RIVR_EXCEPTION) ) { 532 line_stat = cd1400_read_reg(cd, CD1400_RDSR); 533 n_chars = 1; 534 } else { /* no exception, received data OK */ 535 line_stat = 0; 536 n_chars = cd1400_read_reg(cd, CD1400_RDCR); 537 } 538 539 ptr = mtty->mp_rput; 540 while( n_chars-- ) { 541 *ptr++ = line_stat; 542 *ptr++ = cd1400_read_reg(cd, CD1400_RDSR); 543 if( ptr == mtty->mp_rend ) ptr = mtty->mp_rbuf; 544 if( ptr == mtty->mp_rget ) { 545 if( ptr == mtty->mp_rbuf ) 546 ptr = mtty->mp_rend; 547 ptr -= 2; 548 SET(mtty->mp_flags, MTTYF_RING_OVERFLOW); 549 break; 550 } 551 } 552 mtty->mp_rput = ptr; 553 554 needsoftint = 1; 555 } 556 557 cd1400_write_reg(cd, CD1400_EOSRR, 0); /* end service context */ 558 serviced = 1; 559 } /* if(rx_service...) */ 560 561 if( ISSET(status, CD1400_SVRR_MDMCH) ) { 562 u_char mivr = *sc->ms_svcackm; /* enter mdm service context */ 563 int port = mivr >> 4; 564 struct mtty_port *mtty; 565 int carrier; 566 u_char msvr; 567 568 /* 569 * Handle CD (LC2+1Sp = DSR) changes. 570 */ 571 mtty = &sc->ms_mtty->ms_port[port]; 572 cd = mtty->mp_cd1400; 573 msvr = cd1400_read_reg(cd, CD1400_MSVR2); 574 carrier = ISSET(msvr, cd->cd_parmode ? CD1400_MSVR2_DSR : CD1400_MSVR2_CD); 575 576 if( mtty->mp_carrier != carrier ) { 577 SET(mtty->mp_flags, MTTYF_CARRIER_CHANGED); 578 mtty->mp_carrier = carrier; 579 needsoftint = 1; 580 } 581 582 cd1400_write_reg(cd, CD1400_EOSRR, 0); /* end service context */ 583 serviced = 1; 584 } /* if(mdm_service...) */ 585 586 if( ISSET(status, CD1400_SVRR_TXRDY) ) { 587 u_char tivr = *sc->ms_svcackt; /* enter tx service context */ 588 int port = tivr >> 4; 589 590 if( tivr & (1<<3) ) { /* parallel port */ 591 struct mbpp_port *mbpp; 592 593 mbpp = &sc->ms_mbpp->ms_port[port]; 594 cd = mbpp->mp_cd1400; 595 596 if( mbpp->mp_cnt ) { 597 int count = 0; 598 599 /* fill the fifo */ 600 while (mbpp->mp_cnt && 601 count++ < CD1400_PAR_FIFO_SIZE) { 602 cd1400_write_reg(cd, CD1400_TDR, 603 *mbpp->mp_ptr); 604 mbpp->mp_ptr++; 605 mbpp->mp_cnt--; 606 } 607 } else { 608 /* 609 * fifo is empty and we got no more data 610 * to send, so shut off interrupts and 611 * signal for a wakeup, which can't be 612 * done here in case we beat mbpp_send to 613 * the tsleep call (we are running at >spltty) 614 */ 615 cd1400_write_reg(cd, CD1400_SRER, 0); 616 SET(mbpp->mp_flags, MBPPF_WAKEUP); 617 needsoftint = 1; 618 } 619 } else { /* serial port */ 620 struct mtty_port *mtty; 621 struct tty *tp; 622 623 mtty = &sc->ms_mtty->ms_port[port]; 624 cd = mtty->mp_cd1400; 625 tp = mtty->mp_tty; 626 627 if( !ISSET(mtty->mp_flags, MTTYF_STOP) ) { 628 int count = 0; 629 630 /* check if we should start/stop a break */ 631 if( ISSET(mtty->mp_flags, MTTYF_SET_BREAK) ) { 632 cd1400_write_reg(cd, CD1400_TDR, 0); 633 cd1400_write_reg(cd, CD1400_TDR, 0x81); 634 /* should we delay too? */ 635 CLR(mtty->mp_flags, MTTYF_SET_BREAK); 636 count += 2; 637 } 638 639 if( ISSET(mtty->mp_flags, MTTYF_CLR_BREAK) ) { 640 cd1400_write_reg(cd, CD1400_TDR, 0); 641 cd1400_write_reg(cd, CD1400_TDR, 0x83); 642 CLR(mtty->mp_flags, MTTYF_CLR_BREAK); 643 count += 2; 644 } 645 646 /* I don't quite fill the fifo in case the last one is a 647 * NULL which I have to double up because its the escape 648 * code for embedded transmit characters. 649 */ 650 while( mtty->mp_txc > 0 && count < CD1400_TX_FIFO_SIZE - 1 ) { 651 u_char ch; 652 653 ch = *mtty->mp_txp; 654 655 mtty->mp_txc--; 656 mtty->mp_txp++; 657 658 if( ch == 0 ) { 659 cd1400_write_reg(cd, CD1400_TDR, ch); 660 count++; 661 } 662 663 cd1400_write_reg(cd, CD1400_TDR, ch); 664 count++; 665 } 666 } 667 668 /* if we ran out of work or are requested to STOP then 669 * shut off the txrdy interrupts and signal DONE to flush 670 * out the chars we have sent. 671 */ 672 if( mtty->mp_txc == 0 || ISSET(mtty->mp_flags, MTTYF_STOP) ) { 673 register int srer; 674 675 srer = cd1400_read_reg(cd, CD1400_SRER); 676 CLR(srer, CD1400_SRER_TXRDY); 677 cd1400_write_reg(cd, CD1400_SRER, srer); 678 CLR(mtty->mp_flags, MTTYF_STOP); 679 680 SET(mtty->mp_flags, MTTYF_DONE); 681 needsoftint = 1; 682 } 683 } 684 685 cd1400_write_reg(cd, CD1400_EOSRR, 0); /* end service context */ 686 serviced = 1; 687 } /* if(tx_service...) */ 688 689 /* XXX service CD1190 interrupts too 690 for( chip = 0 ; chip < sc->ms_ncd1190 ; chip++ ) { 691 } 692 */ 693 694 if (needsoftint) 695 /* trigger the soft interrupt */ 696 softint_schedule(sc->ms_sicookie); 697 698 return(serviced); 699 } 700 701 /* 702 * magma soft interrupt handler 703 * 704 * runs at IPL_SOFTSERIAL 705 */ 706 void 707 magma_soft(void *arg) 708 { 709 struct magma_softc *sc = arg; 710 struct mtty_softc *mtty = sc->ms_mtty; 711 struct mbpp_softc *mbpp = sc->ms_mbpp; 712 int port; 713 int s, flags; 714 715 if (mtty == NULL) 716 goto chkbpp; 717 718 /* 719 * check the tty ports to see what needs doing 720 */ 721 for( port = 0 ; port < mtty->ms_nports ; port++ ) { 722 struct mtty_port *mp = &mtty->ms_port[port]; 723 struct tty *tp = mp->mp_tty; 724 725 if( !ISSET(tp->t_state, TS_ISOPEN) ) 726 continue; 727 728 /* 729 * handle any received data 730 */ 731 while( mp->mp_rget != mp->mp_rput ) { 732 u_char stat; 733 int data; 734 735 stat = mp->mp_rget[0]; 736 data = mp->mp_rget[1]; 737 mp->mp_rget = ((mp->mp_rget + 2) == mp->mp_rend) 738 ? mp->mp_rbuf : (mp->mp_rget + 2); 739 740 if( stat & (CD1400_RDSR_BREAK | CD1400_RDSR_FE) ) 741 data |= TTY_FE; 742 if( stat & CD1400_RDSR_PE ) 743 data |= TTY_PE; 744 745 if( stat & CD1400_RDSR_OE ) 746 log(LOG_WARNING, "%s%x: fifo overflow\n", 747 device_xname(mtty->ms_dev), port); 748 749 (*tp->t_linesw->l_rint)(data, tp); 750 } 751 752 s = splserial(); /* block out hard interrupt routine */ 753 flags = mp->mp_flags; 754 CLR(mp->mp_flags, MTTYF_DONE | MTTYF_CARRIER_CHANGED | MTTYF_RING_OVERFLOW); 755 splx(s); /* ok */ 756 757 if( ISSET(flags, MTTYF_CARRIER_CHANGED) ) { 758 dprintf(("%s%x: cd %s\n", device_xname(mtty->ms_dev), 759 port, mp->mp_carrier ? "on" : "off")); 760 (*tp->t_linesw->l_modem)(tp, mp->mp_carrier); 761 } 762 763 if( ISSET(flags, MTTYF_RING_OVERFLOW) ) { 764 log(LOG_WARNING, "%s%x: ring buffer overflow\n", 765 device_xname(mtty->ms_dev), port); 766 } 767 768 if( ISSET(flags, MTTYF_DONE) ) { 769 ndflush(&tp->t_outq, mp->mp_txp - tp->t_outq.c_cf); 770 CLR(tp->t_state, TS_BUSY); 771 (*tp->t_linesw->l_start)(tp); /* might be some more */ 772 } 773 } /* for(each mtty...) */ 774 775 776 chkbpp: 777 /* 778 * Check the bpp ports (if any) to see what needs doing 779 */ 780 if (mbpp == NULL) 781 return; 782 783 for( port = 0 ; port < mbpp->ms_nports ; port++ ) { 784 struct mbpp_port *mp = &mbpp->ms_port[port]; 785 786 if( !ISSET(mp->mp_flags, MBPPF_OPEN) ) 787 continue; 788 789 s = splserial(); 790 flags = mp->mp_flags; 791 CLR(mp->mp_flags, MBPPF_WAKEUP); 792 splx(s); 793 794 if( ISSET(flags, MBPPF_WAKEUP) ) { 795 wakeup(mp); 796 } 797 798 } /* for(each mbpp...) */ 799 } 800 801 /************************************************************************ 802 * 803 * MTTY Routines 804 * 805 * mtty_match match one mtty device 806 * mtty_attach attach mtty devices 807 * mttyopen open mtty device 808 * mttyclose close mtty device 809 * mttyread read from mtty 810 * mttywrite write to mtty 811 * mttyioctl do ioctl on mtty 812 * mttytty return tty pointer for mtty 813 * mttystop stop mtty device 814 * mtty_start start mtty device 815 * mtty_param set mtty parameters 816 * mtty_modem_control set modem control lines 817 */ 818 819 int 820 mtty_match(device_t parent, cfdata_t cf, void *args) 821 { 822 struct magma_softc *sc = device_private(parent); 823 824 return( args == mtty_match && sc->ms_board->mb_nser && sc->ms_mtty == NULL ); 825 } 826 827 void 828 mtty_attach(device_t parent, device_t self, void *args) 829 { 830 struct magma_softc *sc = device_private(parent); 831 struct mtty_softc *ms = device_private(self); 832 int port, chip, chan; 833 834 sc->ms_dev = self; 835 sc->ms_mtty = ms; 836 dprintf((" addr %p", ms)); 837 838 for( port = 0, chip = 0, chan = 0 ; port < sc->ms_board->mb_nser ; port++ ) { 839 struct mtty_port *mp = &ms->ms_port[port]; 840 struct tty *tp; 841 842 mp->mp_cd1400 = &sc->ms_cd1400[chip]; 843 if (mp->mp_cd1400->cd_parmode && chan == 0) 844 chan = 1; /* skip channel 0 if parmode */ 845 mp->mp_channel = chan; 846 847 tp = tty_alloc(); 848 if (tp == NULL) { 849 break; 850 } 851 tty_attach(tp); 852 tp->t_oproc = mtty_start; 853 tp->t_param = mtty_param; 854 855 mp->mp_tty = tp; 856 857 mp->mp_rbuf = malloc(MTTY_RBUF_SIZE, M_DEVBUF, M_NOWAIT); 858 if (mp->mp_rbuf == NULL) break; 859 860 mp->mp_rend = mp->mp_rbuf + MTTY_RBUF_SIZE; 861 862 chan = (chan + 1) % CD1400_NO_OF_CHANNELS; 863 if (chan == 0) 864 chip++; 865 } 866 867 ms->ms_nports = port; 868 printf(": %d tty%s\n", port, port == 1 ? "" : "s"); 869 } 870 871 /* 872 * open routine. returns zero if successful, else error code 873 */ 874 int 875 mttyopen(dev_t dev, int flags, int mode, struct lwp *l) 876 { 877 int card = MAGMA_CARD(dev); 878 int port = MAGMA_PORT(dev); 879 struct mtty_softc *ms; 880 struct mtty_port *mp; 881 struct tty *tp; 882 struct cd1400 *cd; 883 int error, s; 884 885 if ((ms = device_lookup_private(&mtty_cd, card)) == NULL 886 || port >= ms->ms_nports ) 887 return(ENXIO); /* device not configured */ 888 889 mp = &ms->ms_port[port]; 890 tp = mp->mp_tty; 891 tp->t_dev = dev; 892 893 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 894 return (EBUSY); 895 896 s = spltty(); 897 898 if( !ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 899 900 /* set defaults */ 901 ttychars(tp); 902 tp->t_iflag = TTYDEF_IFLAG; 903 tp->t_oflag = TTYDEF_OFLAG; 904 tp->t_cflag = TTYDEF_CFLAG; 905 if( ISSET(mp->mp_openflags, TIOCFLAG_CLOCAL) ) 906 SET(tp->t_cflag, CLOCAL); 907 if( ISSET(mp->mp_openflags, TIOCFLAG_CRTSCTS) ) 908 SET(tp->t_cflag, CRTSCTS); 909 if( ISSET(mp->mp_openflags, TIOCFLAG_MDMBUF) ) 910 SET(tp->t_cflag, MDMBUF); 911 tp->t_lflag = TTYDEF_LFLAG; 912 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 913 914 /* init ring buffer */ 915 mp->mp_rput = mp->mp_rget = mp->mp_rbuf; 916 917 /* reset CD1400 channel */ 918 cd = mp->mp_cd1400; 919 cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel); 920 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET); 921 922 /* encode the port number in top half of LIVR */ 923 cd1400_write_reg(cd, CD1400_LIVR, port << 4 ); 924 925 /* sets parameters and raises DTR */ 926 (void)mtty_param(tp, &tp->t_termios); 927 928 /* set tty watermarks */ 929 ttsetwater(tp); 930 931 /* enable service requests */ 932 cd1400_write_reg(cd, CD1400_SRER, 933 CD1400_SRER_RXDATA | CD1400_SRER_MDMCH); 934 935 /* tell the tty about the carrier status */ 936 if( ISSET(mp->mp_openflags, TIOCFLAG_SOFTCAR) || 937 mp->mp_carrier ) 938 SET(tp->t_state, TS_CARR_ON); 939 else 940 CLR(tp->t_state, TS_CARR_ON); 941 } 942 splx(s); 943 944 error = ttyopen(tp, MTTY_DIALOUT(dev), ISSET(flags, O_NONBLOCK)); 945 if (error != 0) 946 goto bad; 947 948 error = (*tp->t_linesw->l_open)(dev, tp); 949 if (error != 0) 950 goto bad; 951 952 bad: 953 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 954 /* 955 * We failed to open the device, and nobody else had it opened. 956 * Clean up the state as appropriate. 957 */ 958 /* XXX - do that here */ 959 } 960 961 return (error); 962 } 963 964 /* 965 * close routine. returns zero if successful, else error code 966 */ 967 int 968 mttyclose(dev_t dev, int flag, int mode, struct lwp *l) 969 { 970 struct mtty_softc *ms = device_lookup_private(&mtty_cd, 971 MAGMA_CARD(dev)); 972 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 973 struct tty *tp = mp->mp_tty; 974 int s; 975 976 (*tp->t_linesw->l_close)(tp, flag); 977 ttyclose(tp); 978 979 s = spltty(); 980 981 /* if HUPCL is set, and the tty is no longer open 982 * shut down the port 983 */ 984 if( ISSET(tp->t_cflag, HUPCL) || !ISSET(tp->t_state, TS_ISOPEN) ) { 985 /* XXX wait until FIFO is empty before turning off the channel 986 struct cd1400 *cd = mp->mp_cd1400; 987 */ 988 989 /* drop DTR and RTS */ 990 (void)mtty_modem_control(mp, 0, DMSET); 991 992 /* turn off the channel 993 cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel); 994 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET); 995 */ 996 } 997 998 splx(s); 999 1000 return(0); 1001 } 1002 1003 /* 1004 * Read routine 1005 */ 1006 int 1007 mttyread(dev_t dev, struct uio *uio, int flags) 1008 { 1009 struct mtty_softc *ms = device_lookup_private(&mtty_cd, 1010 MAGMA_CARD(dev)); 1011 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1012 struct tty *tp = mp->mp_tty; 1013 1014 return( (*tp->t_linesw->l_read)(tp, uio, flags) ); 1015 } 1016 1017 /* 1018 * Write routine 1019 */ 1020 int 1021 mttywrite(dev_t dev, struct uio *uio, int flags) 1022 { 1023 struct mtty_softc *ms = device_lookup_private(&mtty_cd, 1024 MAGMA_CARD(dev)); 1025 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1026 struct tty *tp = mp->mp_tty; 1027 1028 return( (*tp->t_linesw->l_write)(tp, uio, flags) ); 1029 } 1030 1031 /* 1032 * Poll routine 1033 */ 1034 int 1035 mttypoll(dev_t dev, int events, struct lwp *l) 1036 { 1037 struct mtty_softc *ms = device_lookup_private(&mtty_cd, 1038 MAGMA_CARD(dev)); 1039 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1040 struct tty *tp = mp->mp_tty; 1041 1042 return ((*tp->t_linesw->l_poll)(tp, events, l)); 1043 } 1044 1045 /* 1046 * return tty pointer 1047 */ 1048 struct tty * 1049 mttytty(dev_t dev) 1050 { 1051 struct mtty_softc *ms = device_lookup_private(&mtty_cd, 1052 MAGMA_CARD(dev)); 1053 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1054 1055 return(mp->mp_tty); 1056 } 1057 1058 /* 1059 * ioctl routine 1060 */ 1061 int 1062 mttyioctl(dev_t dev, u_long cmd, void *data, int flags, struct lwp *l) 1063 { 1064 struct mtty_softc *ms = device_lookup_private(&mtty_cd, 1065 MAGMA_CARD(dev)); 1066 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1067 struct tty *tp = mp->mp_tty; 1068 int error; 1069 1070 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flags, l); 1071 if( error != EPASSTHROUGH ) return(error); 1072 1073 error = ttioctl(tp, cmd, data, flags, l); 1074 if( error != EPASSTHROUGH ) return(error); 1075 1076 error = 0; 1077 1078 switch(cmd) { 1079 case TIOCSBRK: /* set break */ 1080 SET(mp->mp_flags, MTTYF_SET_BREAK); 1081 cd1400_enable_transmitter(mp->mp_cd1400, mp->mp_channel); 1082 break; 1083 1084 case TIOCCBRK: /* clear break */ 1085 SET(mp->mp_flags, MTTYF_CLR_BREAK); 1086 cd1400_enable_transmitter(mp->mp_cd1400, mp->mp_channel); 1087 break; 1088 1089 case TIOCSDTR: /* set DTR */ 1090 mtty_modem_control(mp, TIOCM_DTR, DMBIS); 1091 break; 1092 1093 case TIOCCDTR: /* clear DTR */ 1094 mtty_modem_control(mp, TIOCM_DTR, DMBIC); 1095 break; 1096 1097 case TIOCMSET: /* set modem lines */ 1098 mtty_modem_control(mp, *((int *)data), DMSET); 1099 break; 1100 1101 case TIOCMBIS: /* bit set modem lines */ 1102 mtty_modem_control(mp, *((int *)data), DMBIS); 1103 break; 1104 1105 case TIOCMBIC: /* bit clear modem lines */ 1106 mtty_modem_control(mp, *((int *)data), DMBIC); 1107 break; 1108 1109 case TIOCMGET: /* get modem lines */ 1110 *((int *)data) = mtty_modem_control(mp, 0, DMGET); 1111 break; 1112 1113 case TIOCGFLAGS: 1114 *((int *)data) = mp->mp_openflags; 1115 break; 1116 1117 case TIOCSFLAGS: 1118 if (kauth_authorize_device_tty(l->l_cred, 1119 KAUTH_DEVICE_TTY_PRIVSET, tp)) 1120 error = EPERM; 1121 else 1122 mp->mp_openflags = *((int *)data) & 1123 (TIOCFLAG_SOFTCAR | TIOCFLAG_CLOCAL | 1124 TIOCFLAG_CRTSCTS | TIOCFLAG_MDMBUF); 1125 break; 1126 1127 default: 1128 error = EPASSTHROUGH; 1129 } 1130 1131 return(error); 1132 } 1133 1134 /* 1135 * Stop output, e.g., for ^S or output flush. 1136 */ 1137 void 1138 mttystop(struct tty *tp, int flags) 1139 { 1140 struct mtty_softc *ms = device_lookup_private(&mtty_cd, 1141 MAGMA_CARD(tp->t_dev)); 1142 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(tp->t_dev)]; 1143 int s; 1144 1145 s = spltty(); 1146 1147 if( ISSET(tp->t_state, TS_BUSY) ) { 1148 if( !ISSET(tp->t_state, TS_TTSTOP) ) 1149 SET(tp->t_state, TS_FLUSH); 1150 1151 /* 1152 * the transmit interrupt routine will disable transmit when it 1153 * notices that MTTYF_STOP has been set. 1154 */ 1155 SET(mp->mp_flags, MTTYF_STOP); 1156 } 1157 1158 splx(s); 1159 } 1160 1161 /* 1162 * Start output, after a stop. 1163 */ 1164 void 1165 mtty_start(struct tty *tp) 1166 { 1167 struct mtty_softc *ms = device_lookup_private(&mtty_cd, 1168 MAGMA_CARD(tp->t_dev)); 1169 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(tp->t_dev)]; 1170 int s; 1171 1172 s = spltty(); 1173 1174 /* we only need to do something if we are not already busy 1175 * or delaying or stopped 1176 */ 1177 if( !ISSET(tp->t_state, TS_TTSTOP | TS_TIMEOUT | TS_BUSY) ) { 1178 if (ttypull(tp)) { 1179 mp->mp_txc = ndqb(&tp->t_outq, 0); 1180 mp->mp_txp = tp->t_outq.c_cf; 1181 SET(tp->t_state, TS_BUSY); 1182 cd1400_enable_transmitter(mp->mp_cd1400, mp->mp_channel); 1183 } 1184 } 1185 1186 splx(s); 1187 } 1188 1189 /* 1190 * set/get modem line status 1191 * 1192 * bits can be: TIOCM_DTR, TIOCM_RTS, TIOCM_CTS, TIOCM_CD, TIOCM_RI, TIOCM_DSR 1193 * 1194 * note that DTR and RTS lines are exchanged, and that DSR is 1195 * not available on the LC2+1Sp card (used as CD) 1196 * 1197 * only let them fiddle with RTS if CRTSCTS is not enabled 1198 */ 1199 int 1200 mtty_modem_control(struct mtty_port *mp, int bits, int howto) 1201 { 1202 struct cd1400 *cd = mp->mp_cd1400; 1203 struct tty *tp = mp->mp_tty; 1204 int s, msvr; 1205 1206 s = spltty(); 1207 1208 cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel); 1209 1210 switch(howto) { 1211 case DMGET: /* get bits */ 1212 bits = 0; 1213 1214 bits |= TIOCM_LE; 1215 1216 msvr = cd1400_read_reg(cd, CD1400_MSVR1); 1217 if( msvr & CD1400_MSVR1_RTS ) bits |= TIOCM_DTR; 1218 1219 msvr = cd1400_read_reg(cd, CD1400_MSVR2); 1220 if( msvr & CD1400_MSVR2_DTR ) bits |= TIOCM_RTS; 1221 if( msvr & CD1400_MSVR2_CTS ) bits |= TIOCM_CTS; 1222 if( msvr & CD1400_MSVR2_RI ) bits |= TIOCM_RI; 1223 if( msvr & CD1400_MSVR2_DSR ) bits |= (cd->cd_parmode ? TIOCM_CD : TIOCM_DSR); 1224 if( msvr & CD1400_MSVR2_CD ) bits |= (cd->cd_parmode ? 0 : TIOCM_CD); 1225 1226 break; 1227 1228 case DMSET: /* reset bits */ 1229 if( !ISSET(tp->t_cflag, CRTSCTS) ) 1230 cd1400_write_reg(cd, CD1400_MSVR2, ((bits & TIOCM_RTS) ? CD1400_MSVR2_DTR : 0)); 1231 1232 cd1400_write_reg(cd, CD1400_MSVR1, ((bits & TIOCM_DTR) ? CD1400_MSVR1_RTS : 0)); 1233 1234 break; 1235 1236 case DMBIS: /* set bits */ 1237 if( (bits & TIOCM_RTS) && !ISSET(tp->t_cflag, CRTSCTS) ) 1238 cd1400_write_reg(cd, CD1400_MSVR2, CD1400_MSVR2_DTR); 1239 1240 if( bits & TIOCM_DTR ) 1241 cd1400_write_reg(cd, CD1400_MSVR1, CD1400_MSVR1_RTS); 1242 1243 break; 1244 1245 case DMBIC: /* clear bits */ 1246 if( (bits & TIOCM_RTS) && !ISSET(tp->t_cflag, CRTSCTS) ) 1247 cd1400_write_reg(cd, CD1400_MSVR2, 0); 1248 1249 if( bits & TIOCM_DTR ) 1250 cd1400_write_reg(cd, CD1400_MSVR1, 0); 1251 1252 break; 1253 } 1254 1255 splx(s); 1256 return(bits); 1257 } 1258 1259 /* 1260 * Set tty parameters, returns error or 0 on success 1261 */ 1262 int 1263 mtty_param(struct tty *tp, struct termios *t) 1264 { 1265 struct mtty_softc *ms = device_lookup_private(&mtty_cd, 1266 MAGMA_CARD(tp->t_dev)); 1267 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(tp->t_dev)]; 1268 struct cd1400 *cd = mp->mp_cd1400; 1269 int rbpr, tbpr, rcor, tcor; 1270 u_char mcor1 = 0, mcor2 = 0; 1271 int s, opt; 1272 1273 if( t->c_ospeed && cd1400_compute_baud(t->c_ospeed, cd->cd_clock, &tcor, &tbpr) ) 1274 return(EINVAL); 1275 1276 if( t->c_ispeed && cd1400_compute_baud(t->c_ispeed, cd->cd_clock, &rcor, &rbpr) ) 1277 return(EINVAL); 1278 1279 s = spltty(); 1280 1281 /* hang up the line if ospeed is zero, else raise DTR */ 1282 (void)mtty_modem_control(mp, TIOCM_DTR, (t->c_ospeed == 0 ? DMBIC : DMBIS)); 1283 1284 /* select channel, done in mtty_modem_control() */ 1285 /* cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel); */ 1286 1287 /* set transmit speed */ 1288 if( t->c_ospeed ) { 1289 cd1400_write_reg(cd, CD1400_TCOR, tcor); 1290 cd1400_write_reg(cd, CD1400_TBPR, tbpr); 1291 } 1292 1293 /* set receive speed */ 1294 if( t->c_ispeed ) { 1295 cd1400_write_reg(cd, CD1400_RCOR, rcor); 1296 cd1400_write_reg(cd, CD1400_RBPR, rbpr); 1297 } 1298 1299 /* enable transmitting and receiving on this channel */ 1300 opt = CD1400_CCR_CMDCHANCTL | CD1400_CCR_XMTEN | CD1400_CCR_RCVEN; 1301 cd1400_write_ccr(cd, opt); 1302 1303 /* set parity, data and stop bits */ 1304 opt = 0; 1305 if( ISSET(t->c_cflag, PARENB) ) 1306 opt |= (ISSET(t->c_cflag, PARODD) ? CD1400_COR1_PARODD : CD1400_COR1_PARNORMAL); 1307 1308 if( !ISSET(t->c_iflag, INPCK) ) 1309 opt |= CD1400_COR1_NOINPCK; /* no parity checking */ 1310 1311 if( ISSET(t->c_cflag, CSTOPB) ) 1312 opt |= CD1400_COR1_STOP2; 1313 1314 switch( t->c_cflag & CSIZE ) { 1315 case CS5: 1316 opt |= CD1400_COR1_CS5; 1317 break; 1318 1319 case CS6: 1320 opt |= CD1400_COR1_CS6; 1321 break; 1322 1323 case CS7: 1324 opt |= CD1400_COR1_CS7; 1325 break; 1326 1327 default: 1328 opt |= CD1400_COR1_CS8; 1329 break; 1330 } 1331 1332 cd1400_write_reg(cd, CD1400_COR1, opt); 1333 1334 /* 1335 * enable Embedded Transmit Commands (for breaks) 1336 * use the CD1400 automatic CTS flow control if CRTSCTS is set 1337 */ 1338 opt = CD1400_COR2_ETC; 1339 if( ISSET(t->c_cflag, CRTSCTS) ) opt |= CD1400_COR2_CCTS_OFLOW; 1340 cd1400_write_reg(cd, CD1400_COR2, opt); 1341 1342 cd1400_write_reg(cd, CD1400_COR3, MTTY_RX_FIFO_THRESHOLD); 1343 1344 cd1400_write_ccr(cd, CD1400_CCR_CMDCORCHG | CD1400_CCR_COR1 | CD1400_CCR_COR2 | CD1400_CCR_COR3); 1345 1346 cd1400_write_reg(cd, CD1400_COR4, CD1400_COR4_PFO_EXCEPTION); 1347 cd1400_write_reg(cd, CD1400_COR5, 0); 1348 1349 /* 1350 * if automatic RTS handshaking enabled, set DTR threshold 1351 * (RTS and DTR lines are switched, CD1400 thinks its DTR) 1352 */ 1353 if( ISSET(t->c_cflag, CRTSCTS) ) 1354 mcor1 = MTTY_RX_DTR_THRESHOLD; 1355 1356 /* set up `carrier detect' interrupts */ 1357 if( cd->cd_parmode ) { 1358 SET(mcor1, CD1400_MCOR1_DSRzd); 1359 SET(mcor2, CD1400_MCOR2_DSRod); 1360 } else { 1361 SET(mcor1, CD1400_MCOR1_CDzd); 1362 SET(mcor2, CD1400_MCOR2_CDod); 1363 } 1364 1365 cd1400_write_reg(cd, CD1400_MCOR1, mcor1); 1366 cd1400_write_reg(cd, CD1400_MCOR2, mcor2); 1367 1368 /* receive timeout 2ms */ 1369 cd1400_write_reg(cd, CD1400_RTPR, 2); 1370 1371 splx(s); 1372 return(0); 1373 } 1374 1375 /************************************************************************ 1376 * 1377 * MBPP Routines 1378 * 1379 * mbpp_match match one mbpp device 1380 * mbpp_attach attach mbpp devices 1381 * mbppopen open mbpp device 1382 * mbppclose close mbpp device 1383 * mbppioctl do ioctl on mbpp 1384 * mbpp_rw general rw routine 1385 * mbpp_timeout rw timeout 1386 * mbpp_start rw start after delay 1387 * mbpp_send send data 1388 * mbpp_recv recv data 1389 */ 1390 1391 int 1392 mbpp_match(device_t parent, cfdata_t cf, void *args) 1393 { 1394 struct magma_softc *sc = device_private(parent); 1395 1396 return( args == mbpp_match && sc->ms_board->mb_npar && sc->ms_mbpp == NULL ); 1397 } 1398 1399 void 1400 mbpp_attach(device_t parent, device_t dev, void *args) 1401 { 1402 struct magma_softc *sc = device_private(parent); 1403 struct mbpp_softc *ms = device_private(dev); 1404 struct mbpp_port *mp; 1405 int port; 1406 1407 sc->ms_mbpp = ms; 1408 dprintf((" addr %p", ms)); 1409 1410 for( port = 0 ; port < sc->ms_board->mb_npar ; port++ ) { 1411 mp = &ms->ms_port[port]; 1412 1413 callout_init(&mp->mp_timeout_ch, 0); 1414 callout_init(&mp->mp_start_ch, 0); 1415 1416 if( sc->ms_ncd1190 ) 1417 mp->mp_cd1190 = &sc->ms_cd1190[port]; 1418 else 1419 mp->mp_cd1400 = &sc->ms_cd1400[0]; 1420 } 1421 1422 ms->ms_nports = port; 1423 printf(": %d port%s\n", port, port == 1 ? "" : "s"); 1424 } 1425 1426 /* 1427 * open routine. returns zero if successful, else error code 1428 */ 1429 int 1430 mbppopen(dev_t dev, int flags, int mode, struct lwp *l) 1431 { 1432 int card = MAGMA_CARD(dev); 1433 int port = MAGMA_PORT(dev); 1434 struct mbpp_softc *ms; 1435 struct mbpp_port *mp; 1436 int s; 1437 1438 if ((ms = device_lookup_private(&mbpp_cd, card)) == NULL 1439 || port >= ms->ms_nports ) 1440 return(ENXIO); 1441 1442 mp = &ms->ms_port[port]; 1443 1444 s = spltty(); 1445 if( ISSET(mp->mp_flags, MBPPF_OPEN) ) { 1446 splx(s); 1447 return(EBUSY); 1448 } 1449 SET(mp->mp_flags, MBPPF_OPEN); 1450 splx(s); 1451 1452 /* set defaults */ 1453 mp->mp_burst = MBPP_BURST; 1454 mp->mp_timeout = mbpp_mstohz(MBPP_TIMEOUT); 1455 mp->mp_delay = mbpp_mstohz(MBPP_DELAY); 1456 1457 /* init chips */ 1458 if( mp->mp_cd1400 ) { /* CD1400 */ 1459 struct cd1400 *cd = mp->mp_cd1400; 1460 1461 /* set up CD1400 channel */ 1462 s = spltty(); 1463 cd1400_write_reg(cd, CD1400_CAR, 0); 1464 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET); 1465 cd1400_write_reg(cd, CD1400_LIVR, (1<<3)); 1466 splx(s); 1467 } else { /* CD1190 */ 1468 mp->mp_flags = 0; 1469 return (ENXIO); 1470 } 1471 1472 return (0); 1473 } 1474 1475 /* 1476 * close routine. returns zero if successful, else error code 1477 */ 1478 int 1479 mbppclose(dev_t dev, int flag, int mode, struct lwp *l) 1480 { 1481 struct mbpp_softc *ms = device_lookup_private(&mbpp_cd, 1482 MAGMA_CARD(dev)); 1483 struct mbpp_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1484 1485 mp->mp_flags = 0; 1486 return(0); 1487 } 1488 1489 /* 1490 * ioctl routine 1491 */ 1492 int 1493 mbppioctl(dev_t dev, u_long cmd, void *data, int flags, struct lwp *l) 1494 { 1495 struct mbpp_softc *ms = device_lookup_private(&mbpp_cd, 1496 MAGMA_CARD(dev)); 1497 struct mbpp_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1498 struct mbpp_param *bp; 1499 int error = 0; 1500 int s; 1501 1502 switch(cmd) { 1503 case MBPPIOCSPARAM: 1504 bp = (struct mbpp_param *)data; 1505 if( bp->bp_burst < MBPP_BURST_MIN || bp->bp_burst > MBPP_BURST_MAX || 1506 bp->bp_delay < MBPP_DELAY_MIN || bp->bp_delay > MBPP_DELAY_MIN ) { 1507 error = EINVAL; 1508 } else { 1509 mp->mp_burst = bp->bp_burst; 1510 mp->mp_timeout = mbpp_mstohz(bp->bp_timeout); 1511 mp->mp_delay = mbpp_mstohz(bp->bp_delay); 1512 } 1513 break; 1514 case MBPPIOCGPARAM: 1515 bp = (struct mbpp_param *)data; 1516 bp->bp_burst = mp->mp_burst; 1517 bp->bp_timeout = mbpp_hztoms(mp->mp_timeout); 1518 bp->bp_delay = mbpp_hztoms(mp->mp_delay); 1519 break; 1520 case MBPPIOCGSTAT: 1521 /* XXX make this more generic */ 1522 s = spltty(); 1523 cd1400_write_reg(mp->mp_cd1400, CD1400_CAR, 0); 1524 *(int *)data = cd1400_read_reg(mp->mp_cd1400, CD1400_PSVR); 1525 splx(s); 1526 break; 1527 default: 1528 error = ENOTTY; 1529 } 1530 1531 return(error); 1532 } 1533 1534 int 1535 mbpp_rw(dev_t dev, struct uio *uio, int flag) 1536 { 1537 int card = MAGMA_CARD(dev); 1538 int port = MAGMA_PORT(dev); 1539 struct mbpp_softc *ms = device_lookup_private(&mbpp_cd, card); 1540 struct mbpp_port *mp = &ms->ms_port[port]; 1541 char *buffer, *ptr; 1542 int buflen, cnt, len; 1543 int s, error = 0; 1544 int gotdata = 0; 1545 1546 if( uio->uio_resid == 0 ) 1547 return(0); 1548 1549 buflen = min(uio->uio_resid, mp->mp_burst); 1550 buffer = malloc(buflen, M_DEVBUF, M_WAITOK); 1551 if( buffer == NULL ) 1552 return(ENOMEM); 1553 1554 SET(mp->mp_flags, MBPPF_UIO); 1555 1556 /* 1557 * start timeout, if needed 1558 */ 1559 if( mp->mp_timeout > 0 ) { 1560 SET(mp->mp_flags, MBPPF_TIMEOUT); 1561 callout_reset(&mp->mp_timeout_ch, mp->mp_timeout, 1562 mbpp_timeout, mp); 1563 } 1564 1565 len = cnt = 0; 1566 while( uio->uio_resid > 0 ) { 1567 len = min(buflen, uio->uio_resid); 1568 ptr = buffer; 1569 1570 if( uio->uio_rw == UIO_WRITE ) { 1571 error = uiomove(ptr, len, uio); 1572 if( error ) break; 1573 } 1574 again: /* goto bad */ 1575 /* timed out? */ 1576 if( !ISSET(mp->mp_flags, MBPPF_UIO) ) 1577 break; 1578 1579 /* 1580 * perform the operation 1581 */ 1582 if( uio->uio_rw == UIO_WRITE ) { 1583 cnt = mbpp_send(mp, ptr, len); 1584 } else { 1585 cnt = mbpp_recv(mp, ptr, len); 1586 } 1587 1588 if( uio->uio_rw == UIO_READ ) { 1589 if( cnt ) { 1590 error = uiomove(ptr, cnt, uio); 1591 if( error ) break; 1592 gotdata++; 1593 } 1594 else if( gotdata ) /* consider us done */ 1595 break; 1596 } 1597 1598 /* timed out? */ 1599 if( !ISSET(mp->mp_flags, MBPPF_UIO) ) 1600 break; 1601 1602 /* 1603 * poll delay? 1604 */ 1605 if( mp->mp_delay > 0 ) { 1606 s = splsoftclock(); 1607 SET(mp->mp_flags, MBPPF_DELAY); 1608 callout_reset(&mp->mp_start_ch, mp->mp_delay, 1609 mbpp_start, mp); 1610 error = tsleep(mp, PCATCH | PZERO, "mbppdelay", 0); 1611 splx(s); 1612 if( error ) break; 1613 } 1614 1615 /* 1616 * don't call uiomove again until we used all the data we grabbed 1617 */ 1618 if( uio->uio_rw == UIO_WRITE && cnt != len ) { 1619 ptr += cnt; 1620 len -= cnt; 1621 cnt = 0; 1622 goto again; 1623 } 1624 } 1625 1626 /* 1627 * clear timeouts 1628 */ 1629 s = splsoftclock(); 1630 if( ISSET(mp->mp_flags, MBPPF_TIMEOUT) ) { 1631 callout_stop(&mp->mp_timeout_ch); 1632 CLR(mp->mp_flags, MBPPF_TIMEOUT); 1633 } 1634 if( ISSET(mp->mp_flags, MBPPF_DELAY) ) { 1635 callout_stop(&mp->mp_start_ch); 1636 CLR(mp->mp_flags, MBPPF_DELAY); 1637 } 1638 splx(s); 1639 1640 /* 1641 * adjust for those chars that we uiomoved but never actually wrote 1642 */ 1643 if( uio->uio_rw == UIO_WRITE && cnt != len ) { 1644 uio->uio_resid += (len - cnt); 1645 } 1646 1647 free(buffer, M_DEVBUF); 1648 return(error); 1649 } 1650 1651 void 1652 mbpp_timeout(void *arg) 1653 { 1654 struct mbpp_port *mp = arg; 1655 1656 CLR(mp->mp_flags, MBPPF_UIO | MBPPF_TIMEOUT); 1657 wakeup(mp); 1658 } 1659 1660 void 1661 mbpp_start(void *arg) 1662 { 1663 struct mbpp_port *mp = arg; 1664 1665 CLR(mp->mp_flags, MBPPF_DELAY); 1666 wakeup(mp); 1667 } 1668 1669 int 1670 mbpp_send(struct mbpp_port *mp, void *ptr, int len) 1671 { 1672 int s; 1673 struct cd1400 *cd = mp->mp_cd1400; 1674 1675 /* set up io information */ 1676 mp->mp_ptr = ptr; 1677 mp->mp_cnt = len; 1678 1679 /* start transmitting */ 1680 s = spltty(); 1681 if( cd ) { 1682 cd1400_write_reg(cd, CD1400_CAR, 0); 1683 1684 /* output strobe width ~1microsecond */ 1685 cd1400_write_reg(cd, CD1400_TBPR, 10); 1686 1687 /* enable channel */ 1688 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_XMTEN); 1689 cd1400_write_reg(cd, CD1400_SRER, CD1400_SRER_TXRDY); 1690 } 1691 1692 /* ZZzzz... */ 1693 tsleep(mp, PCATCH | PZERO, "mbpp_send", 0); 1694 1695 /* stop transmitting */ 1696 if( cd ) { 1697 cd1400_write_reg(cd, CD1400_CAR, 0); 1698 1699 /* disable transmitter */ 1700 cd1400_write_reg(cd, CD1400_SRER, 0); 1701 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_XMTDIS); 1702 1703 /* flush fifo */ 1704 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET | CD1400_CCR_FTF); 1705 } 1706 splx(s); 1707 1708 /* return number of chars sent */ 1709 return(len - mp->mp_cnt); 1710 } 1711 1712 int 1713 mbpp_recv(struct mbpp_port *mp, void *ptr, int len) 1714 { 1715 int s; 1716 struct cd1400 *cd = mp->mp_cd1400; 1717 1718 /* set up io information */ 1719 mp->mp_ptr = ptr; 1720 mp->mp_cnt = len; 1721 1722 /* start receiving */ 1723 s = spltty(); 1724 if( cd ) { 1725 int rcor, rbpr; 1726 1727 cd1400_write_reg(cd, CD1400_CAR, 0); 1728 1729 /* input strobe at 100kbaud (10microseconds) */ 1730 cd1400_compute_baud(100000, cd->cd_clock, &rcor, &rbpr); 1731 cd1400_write_reg(cd, CD1400_RCOR, rcor); 1732 cd1400_write_reg(cd, CD1400_RBPR, rbpr); 1733 1734 /* rx threshold */ 1735 cd1400_write_reg(cd, CD1400_COR3, MBPP_RX_FIFO_THRESHOLD); 1736 cd1400_write_ccr(cd, CD1400_CCR_CMDCORCHG | CD1400_CCR_COR3); 1737 1738 /* enable channel */ 1739 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_RCVEN); 1740 cd1400_write_reg(cd, CD1400_SRER, CD1400_SRER_RXDATA); 1741 } 1742 1743 /* ZZzzz... */ 1744 tsleep(mp, PCATCH | PZERO, "mbpp_recv", 0); 1745 1746 /* stop receiving */ 1747 if( cd ) { 1748 cd1400_write_reg(cd, CD1400_CAR, 0); 1749 1750 /* disable receiving */ 1751 cd1400_write_reg(cd, CD1400_SRER, 0); 1752 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_RCVDIS); 1753 } 1754 splx(s); 1755 1756 /* return number of chars received */ 1757 return(len - mp->mp_cnt); 1758 } 1759 1760 int 1761 mbpp_hztoms(int h) 1762 { 1763 int m = h; 1764 1765 if( m > 0 ) 1766 m = m * 1000 / hz; 1767 return(m); 1768 } 1769 1770 int 1771 mbpp_mstohz(int m) 1772 { 1773 int h = m; 1774 1775 if( h > 0 ) { 1776 h = h * hz / 1000; 1777 if( h == 0 ) 1778 h = 1000 / hz; 1779 } 1780 return(h); 1781 } 1782 1783 #endif /* NMAGMA */ 1784
Indexes created Mon Sep 22 05:09:51 GMT 2025