1 1.7 macallan /* $NetBSD: mgxreg.h,v 1.7 2021/11/11 19:37:30 macallan Exp $ */ 2 1.1 macallan 3 1.2 macallan /* register definitions based on OpenBSD's atxxreg.h: */ 4 1.2 macallan 5 1.2 macallan /* 6 1.2 macallan * Copyright (c) 2008 Miodrag Vallat. 7 1.3 macallan * Copyright (c) 2014 Michael Lorenz 8 1.2 macallan * 9 1.2 macallan * Permission to use, copy, modify, and distribute this software for any 10 1.2 macallan * purpose with or without fee is hereby granted, provided that the above 11 1.2 macallan * copyright notice and this permission notice appear in all copies. 12 1.2 macallan * 13 1.2 macallan * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 1.2 macallan * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 1.2 macallan * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 1.2 macallan * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 1.2 macallan * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 1.2 macallan * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 1.2 macallan * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 1.2 macallan */ 21 1.2 macallan 22 1.2 macallan /* 23 1.2 macallan * Alliance Promotion AP6422, AT24 and AT3D extended register set definitions. 24 1.2 macallan * 25 1.2 macallan * This has been reconstructed from XFree86 ``apm'' driver, whose authors 26 1.2 macallan * apparently do not believe in meaningful constants for numbers. See 27 1.2 macallan * apm_regs.h for more madness. 28 1.2 macallan */ 29 1.2 macallan 30 1.3 macallan #ifndef MGX_REG_H 31 1.3 macallan #define MGX_REG_H 32 1.3 macallan 33 1.7 macallan #define MGX_FBOFFSET 0x00000000 34 1.7 macallan #define MGX_BLTOFFSET 0x00800000 35 1.7 macallan #define MGX_FLIPOFFSET 0x01000000 36 1.6 macallan 37 1.3 macallan #define VGA_BASE 0x3c0 38 1.3 macallan #define CRTC_INDEX 0x3d4 39 1.3 macallan #define CRTC_DATA 0x3d5 40 1.3 macallan #define SEQ_INDEX 0x3c4 41 1.3 macallan #define SEQ_DATA 0x3c5 42 1.3 macallan 43 1.3 macallan /* 44 1.3 macallan * some bits from the XFree86 3.x vga256 / apm driver: 45 1.3 macallan * - sequencer registers 0x11 - 0x17 contain the chip's ID, 'Pro6424' for AT24 46 1.3 macallan */ 47 1.3 macallan 48 1.3 macallan #define SEQ_APERTURE 0x1c 49 1.3 macallan #define AP_SIZE_MASK 0x06 50 1.3 macallan #define AP_SIZE_1MB 0x00 51 1.3 macallan #define AP_SIZE_2MB 0x02 52 1.3 macallan #define AP_SIZE_4MB 0x04 53 1.3 macallan #define AP_SIZE_6MB 0x06 54 1.3 macallan #define AP_SIMULTANEOUS 0x20 /* sim. access to VRAM? */ 55 1.3 macallan 56 1.2 macallan /* 57 1.2 macallan * Clipping Control 58 1.2 macallan */ 59 1.2 macallan 60 1.2 macallan #define ATR_CLIP_CONTROL 0x0030 /* byte access */ 61 1.2 macallan #define ATR_CLIP_LEFT 0x0038 62 1.2 macallan #define ATR_CLIP_TOP 0x003a 63 1.2 macallan #define ATR_CLIP_LEFTTOP 0x0038 64 1.2 macallan #define ATR_CLIP_RIGHT 0x003c 65 1.2 macallan #define ATR_CLIP_BOTTOM 0x003e 66 1.2 macallan #define ATR_CLIP_RIGHTBOTTOM 0x003c 67 1.2 macallan 68 1.2 macallan /* 69 1.2 macallan * Drawing Engine 70 1.2 macallan */ 71 1.2 macallan 72 1.2 macallan #define ATR_DEC 0x0040 73 1.2 macallan #define ATR_ROP 0x0046 74 1.2 macallan #define ATR_BYTEMASK 0x0047 75 1.2 macallan #define ATR_PATTERN1 0x0048 76 1.2 macallan #define ATR_PATTERN2 0x004c 77 1.2 macallan #define ATR_SRC_X 0x0050 78 1.2 macallan #define ATR_SRC_Y 0x0052 79 1.5 macallan #define ATR_SRC_XY 0x0050 /* pointer in vram if DEC_SRC_LINEAR */ 80 1.2 macallan #define ATR_DST_X 0x0054 81 1.2 macallan #define ATR_DST_Y 0x0056 82 1.2 macallan #define ATR_DST_XY 0x0054 83 1.2 macallan #define ATR_W 0x0058 84 1.2 macallan #define ATR_H 0x005a 85 1.2 macallan #define ATR_WH 0x0058 86 1.2 macallan #define ATR_OFFSET 0x005c 87 1.2 macallan #define ATR_SRC_OFFSET 0x005e 88 1.2 macallan #define ATR_FG 0x0060 89 1.2 macallan #define ATR_BG 0x0064 90 1.2 macallan 91 1.2 macallan /* DEC layout */ 92 1.2 macallan #define DEC_COMMAND_MASK 0x0000003f 93 1.2 macallan #define DEC_COMMAND_SHIFT 0 94 1.2 macallan #define DEC_DIR_X_REVERSE 0x00000040 95 1.2 macallan #define DEC_DIR_Y_REVERSE 0x00000080 96 1.2 macallan #define DEC_DIR_Y_MAJOR 0x00000100 97 1.2 macallan #define DEC_SRC_LINEAR 0x00000200 98 1.2 macallan #define DEC_SRC_CONTIGUOUS 0x00000800 99 1.2 macallan #define DEC_MONOCHROME 0x00001000 100 1.2 macallan #define DEC_SRC_TRANSPARENT 0x00002000 101 1.2 macallan #define DEC_DEPTH_MASK 0x0001c000 102 1.2 macallan #define DEC_DEPTH_SHIFT 14 103 1.2 macallan #define DEC_DST_LINEAR 0x00040000 104 1.2 macallan #define DEC_DST_CONTIGUOUS 0x00080000 105 1.2 macallan #define DEC_DST_TRANSPARENT 0x00100000 106 1.2 macallan #define DEC_DST_TRANSPARENT_POLARITY 0x00200000 107 1.2 macallan #define DEC_PATTERN_MASK 0x00c00000 108 1.2 macallan #define DEC_PATTERN_SHIFT 22 109 1.2 macallan #define DEC_WIDTH_MASK 0x07000000 110 1.2 macallan #define DEC_WIDTH_SHIFT 24 111 1.2 macallan #define DEC_UPDATE_MASK 0x18000000 112 1.2 macallan #define DEC_UPDATE_SHIFT 27 113 1.2 macallan #define DEC_START_MASK 0x60000000 114 1.2 macallan #define DEC_START_SHIFT 29 115 1.2 macallan #define DEC_START 0x80000000 116 1.2 macallan 117 1.2 macallan /* DEC commands */ 118 1.2 macallan #define DEC_COMMAND_NOP 0x00 119 1.2 macallan #define DEC_COMMAND_BLT 0x01 /* screen to screen blt */ 120 1.2 macallan #define DEC_COMMAND_RECT 0x02 /* rectangle fill */ 121 1.2 macallan #define DEC_COMMAND_BLT_STRETCH 0x03 /* blt and stretch */ 122 1.2 macallan #define DEC_COMMAND_STRIP 0x04 /* strip pattern */ 123 1.2 macallan #define DEC_COMMAND_HOST_BLT 0x08 /* host to screen blt */ 124 1.2 macallan #define DEC_COMMAND_SCREEN_BLT 0x09 /* screen to host blt */ 125 1.2 macallan #define DEC_COMMAND_VECT_ENDP 0x0c /* vector with end point */ 126 1.2 macallan #define DEC_COMMAND_VECT_NO_ENDP 0x0d /* vector without end point */ 127 1.2 macallan 128 1.2 macallan /* depth */ 129 1.2 macallan #define DEC_DEPTH_8 0x01 130 1.2 macallan #define DEC_DEPTH_16 0x02 131 1.2 macallan #define DEC_DEPTH_32 0x03 132 1.2 macallan #define DEC_DEPTH_24 0x04 133 1.2 macallan 134 1.2 macallan /* width */ 135 1.2 macallan #define DEC_WIDTH_LINEAR 0x00 136 1.2 macallan #define DEC_WIDTH_640 0x01 137 1.2 macallan #define DEC_WIDTH_800 0x02 138 1.2 macallan #define DEC_WIDTH_1024 0x04 139 1.2 macallan #define DEC_WIDTH_1152 0x05 140 1.2 macallan #define DEC_WIDTH_1280 0x06 141 1.2 macallan #define DEC_WIDTH_1600 0x07 142 1.2 macallan 143 1.2 macallan /* update mode */ 144 1.2 macallan #define DEC_UPDATE_NONE 0x00 145 1.2 macallan #define DEC_UPDATE_TOP_RIGHT 0x01 146 1.2 macallan #define DEC_UPDATE_BOTTOM_LEFT 0x02 147 1.2 macallan #define DEC_UPDATE_LASTPIX 0x03 148 1.2 macallan 149 1.2 macallan /* quickstart mode - operation starts as soon as given register is written to */ 150 1.2 macallan #define DEC_START_DIMX 0x01 151 1.2 macallan #define DEC_START_SRC 0x02 152 1.2 macallan #define DEC_START_DST 0x03 153 1.2 macallan 154 1.2 macallan /* ROP */ 155 1.2 macallan #define ROP_DST 0x66 156 1.2 macallan #define ROP_SRC 0xcc 157 1.2 macallan #define ROP_INV 0x33 158 1.2 macallan #define ROP_PATTERN 0xf0 159 1.2 macallan 160 1.2 macallan /* 161 1.2 macallan * Configuration Registers 162 1.2 macallan */ 163 1.2 macallan 164 1.2 macallan #define ATR_PIXEL 0x0080 /* byte access */ 165 1.2 macallan #define PIXEL_DEPTH_MASK 0x0f 166 1.2 macallan #define PIXEL_DEPTH_SHIFT 0 167 1.2 macallan 168 1.2 macallan /* pixel depth */ 169 1.2 macallan #define PIXEL_4 0x01 170 1.2 macallan #define PIXEL_8 0x02 171 1.2 macallan #define PIXEL_15 0x0c 172 1.2 macallan #define PIXEL_16 0x0d 173 1.2 macallan #define PIXEL_24 0x0e 174 1.2 macallan #define PIXEL_32 0x0f 175 1.2 macallan 176 1.2 macallan #define ATR_APERTURE 0x00c0 /* short access */ 177 1.2 macallan 178 1.2 macallan /* 179 1.2 macallan * DPMS Control 180 1.2 macallan */ 181 1.2 macallan 182 1.2 macallan #define ATR_DPMS 0x00d0 /* byte access */ 183 1.2 macallan #define DPMS_HSYNC_DISABLE 0x01 184 1.2 macallan #define DPMS_VSYNC_DISABLE 0x02 185 1.4 macallan #define DPMS_SYNC_DISABLE_ALL 0x03 186 1.2 macallan 187 1.2 macallan /* 188 1.2 macallan * RAMDAC 189 1.2 macallan */ 190 1.2 macallan 191 1.2 macallan #define ATR_COLOR_CORRECTION 0x00e0 192 1.2 macallan #define ATR_MCLK 0x00e8 193 1.2 macallan #define ATR_PCLK 0x00ec 194 1.2 macallan 195 1.2 macallan /* 196 1.2 macallan * Hardware Cursor 197 1.2 macallan * 198 1.2 macallan * The position can not become negative; the offset register, encoded as 199 1.2 macallan * (signed y delta << 8) | signed x delta, allow the cursor image to 200 1.2 macallan * cross the upper-left corner. 201 1.2 macallan */ 202 1.2 macallan 203 1.4 macallan #define ATR_CURSOR_ENABLE 0x0140 204 1.4 macallan #define ATR_CURSOR_FG 0x0141 /* 3:3:2 */ 205 1.4 macallan #define ATR_CURSOR_BG 0x0142 /* 3:3:2 */ 206 1.4 macallan #define ATR_CURSOR_ADDRESS 0x0144 /* in KB from vram */ 207 1.4 macallan #define ATR_CURSOR_POSITION 0x0148 208 1.4 macallan #define ATR_CURSOR_HOTSPOT 0x014c /* short access */ 209 1.2 macallan 210 1.2 macallan /* 211 1.2 macallan * Identification Register 212 1.2 macallan */ 213 1.2 macallan 214 1.2 macallan #define ATR_ID 0x0182 215 1.2 macallan #define ID_AP6422 0x6422 216 1.2 macallan #define ID_AT24 0x6424 217 1.2 macallan #define ID_AT3D 0x643d 218 1.2 macallan 219 1.2 macallan /* 220 1.2 macallan * Status Registers 221 1.2 macallan */ 222 1.2 macallan 223 1.2 macallan #define ATR_FIFO_STATUS 0x01fc 224 1.2 macallan #define ATR_BLT_STATUS 0x01fd 225 1.2 macallan #define FIFO_MASK 0x0f 226 1.2 macallan #define FIFO_SHIFT 0 227 1.2 macallan #define FIFO_AP6422 4 228 1.2 macallan #define FIFO_AT24 8 229 1.2 macallan 230 1.2 macallan #define BLT_HOST_BUSY 0x01 231 1.2 macallan #define BLT_ENGINE_BUSY 0x04 232 1.2 macallan 233 1.2 macallan #define MGX_REG_ATREG_OFFSET 0x000b0000 234 1.2 macallan 235 1.2 macallan #endif /* MGX_REG_H */ 236
Indexes created Thu Sep 25 16:09:42 GMT 2025