mgxreg.h revision 1.3
1 1.3 macallan /* $NetBSD: mgxreg.h,v 1.3 2016/02/11 02:23:44 macallan Exp $ */ 2 1.1 macallan 3 1.2 macallan /* register definitions based on OpenBSD's atxxreg.h: */ 4 1.2 macallan 5 1.2 macallan /* 6 1.2 macallan * Copyright (c) 2008 Miodrag Vallat. 7 1.3 macallan * Copyright (c) 2014 Michael Lorenz 8 1.2 macallan * 9 1.2 macallan * Permission to use, copy, modify, and distribute this software for any 10 1.2 macallan * purpose with or without fee is hereby granted, provided that the above 11 1.2 macallan * copyright notice and this permission notice appear in all copies. 12 1.2 macallan * 13 1.2 macallan * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 1.2 macallan * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 1.2 macallan * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 1.2 macallan * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 1.2 macallan * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 1.2 macallan * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 1.2 macallan * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 1.2 macallan */ 21 1.2 macallan 22 1.2 macallan /* 23 1.2 macallan * Alliance Promotion AP6422, AT24 and AT3D extended register set definitions. 24 1.2 macallan * 25 1.2 macallan * This has been reconstructed from XFree86 ``apm'' driver, whose authors 26 1.2 macallan * apparently do not believe in meaningful constants for numbers. See 27 1.2 macallan * apm_regs.h for more madness. 28 1.2 macallan */ 29 1.2 macallan 30 1.3 macallan #ifndef MGX_REG_H 31 1.3 macallan #define MGX_REG_H 32 1.3 macallan 33 1.3 macallan #define VGA_BASE 0x3c0 34 1.3 macallan #define CRTC_INDEX 0x3d4 35 1.3 macallan #define CRTC_DATA 0x3d5 36 1.3 macallan #define SEQ_INDEX 0x3c4 37 1.3 macallan #define SEQ_DATA 0x3c5 38 1.3 macallan 39 1.3 macallan /* 40 1.3 macallan * some bits from the XFree86 3.x vga256 / apm driver: 41 1.3 macallan * - sequencer registers 0x11 - 0x17 contain the chip's ID, 'Pro6424' for AT24 42 1.3 macallan */ 43 1.3 macallan 44 1.3 macallan #define SEQ_APERTURE 0x1c 45 1.3 macallan #define AP_SIZE_MASK 0x06 46 1.3 macallan #define AP_SIZE_1MB 0x00 47 1.3 macallan #define AP_SIZE_2MB 0x02 48 1.3 macallan #define AP_SIZE_4MB 0x04 49 1.3 macallan #define AP_SIZE_6MB 0x06 50 1.3 macallan #define AP_SIMULTANEOUS 0x20 /* sim. access to VRAM? */ 51 1.3 macallan 52 1.2 macallan /* 53 1.2 macallan * Clipping Control 54 1.2 macallan */ 55 1.2 macallan 56 1.2 macallan #define ATR_CLIP_CONTROL 0x0030 /* byte access */ 57 1.2 macallan #define ATR_CLIP_LEFT 0x0038 58 1.2 macallan #define ATR_CLIP_TOP 0x003a 59 1.2 macallan #define ATR_CLIP_LEFTTOP 0x0038 60 1.2 macallan #define ATR_CLIP_RIGHT 0x003c 61 1.2 macallan #define ATR_CLIP_BOTTOM 0x003e 62 1.2 macallan #define ATR_CLIP_RIGHTBOTTOM 0x003c 63 1.2 macallan 64 1.2 macallan /* 65 1.2 macallan * Drawing Engine 66 1.2 macallan */ 67 1.2 macallan 68 1.2 macallan #define ATR_DEC 0x0040 69 1.2 macallan #define ATR_ROP 0x0046 70 1.2 macallan #define ATR_BYTEMASK 0x0047 71 1.2 macallan #define ATR_PATTERN1 0x0048 72 1.2 macallan #define ATR_PATTERN2 0x004c 73 1.2 macallan #define ATR_SRC_X 0x0050 74 1.2 macallan #define ATR_SRC_Y 0x0052 75 1.2 macallan #define ATR_SRC_XY 0x0050 76 1.2 macallan #define ATR_DST_X 0x0054 77 1.2 macallan #define ATR_DST_Y 0x0056 78 1.2 macallan #define ATR_DST_XY 0x0054 79 1.2 macallan #define ATR_W 0x0058 80 1.2 macallan #define ATR_H 0x005a 81 1.2 macallan #define ATR_WH 0x0058 82 1.2 macallan #define ATR_OFFSET 0x005c 83 1.2 macallan #define ATR_SRC_OFFSET 0x005e 84 1.2 macallan #define ATR_FG 0x0060 85 1.2 macallan #define ATR_BG 0x0064 86 1.2 macallan 87 1.2 macallan /* DEC layout */ 88 1.2 macallan #define DEC_COMMAND_MASK 0x0000003f 89 1.2 macallan #define DEC_COMMAND_SHIFT 0 90 1.2 macallan #define DEC_DIR_X_REVERSE 0x00000040 91 1.2 macallan #define DEC_DIR_Y_REVERSE 0x00000080 92 1.2 macallan #define DEC_DIR_Y_MAJOR 0x00000100 93 1.2 macallan #define DEC_SRC_LINEAR 0x00000200 94 1.2 macallan #define DEC_SRC_CONTIGUOUS 0x00000800 95 1.2 macallan #define DEC_MONOCHROME 0x00001000 96 1.2 macallan #define DEC_SRC_TRANSPARENT 0x00002000 97 1.2 macallan #define DEC_DEPTH_MASK 0x0001c000 98 1.2 macallan #define DEC_DEPTH_SHIFT 14 99 1.2 macallan #define DEC_DST_LINEAR 0x00040000 100 1.2 macallan #define DEC_DST_CONTIGUOUS 0x00080000 101 1.2 macallan #define DEC_DST_TRANSPARENT 0x00100000 102 1.2 macallan #define DEC_DST_TRANSPARENT_POLARITY 0x00200000 103 1.2 macallan #define DEC_PATTERN_MASK 0x00c00000 104 1.2 macallan #define DEC_PATTERN_SHIFT 22 105 1.2 macallan #define DEC_WIDTH_MASK 0x07000000 106 1.2 macallan #define DEC_WIDTH_SHIFT 24 107 1.2 macallan #define DEC_UPDATE_MASK 0x18000000 108 1.2 macallan #define DEC_UPDATE_SHIFT 27 109 1.2 macallan #define DEC_START_MASK 0x60000000 110 1.2 macallan #define DEC_START_SHIFT 29 111 1.2 macallan #define DEC_START 0x80000000 112 1.2 macallan 113 1.2 macallan /* DEC commands */ 114 1.2 macallan #define DEC_COMMAND_NOP 0x00 115 1.2 macallan #define DEC_COMMAND_BLT 0x01 /* screen to screen blt */ 116 1.2 macallan #define DEC_COMMAND_RECT 0x02 /* rectangle fill */ 117 1.2 macallan #define DEC_COMMAND_BLT_STRETCH 0x03 /* blt and stretch */ 118 1.2 macallan #define DEC_COMMAND_STRIP 0x04 /* strip pattern */ 119 1.2 macallan #define DEC_COMMAND_HOST_BLT 0x08 /* host to screen blt */ 120 1.2 macallan #define DEC_COMMAND_SCREEN_BLT 0x09 /* screen to host blt */ 121 1.2 macallan #define DEC_COMMAND_VECT_ENDP 0x0c /* vector with end point */ 122 1.2 macallan #define DEC_COMMAND_VECT_NO_ENDP 0x0d /* vector without end point */ 123 1.2 macallan 124 1.2 macallan /* depth */ 125 1.2 macallan #define DEC_DEPTH_8 0x01 126 1.2 macallan #define DEC_DEPTH_16 0x02 127 1.2 macallan #define DEC_DEPTH_32 0x03 128 1.2 macallan #define DEC_DEPTH_24 0x04 129 1.2 macallan 130 1.2 macallan /* width */ 131 1.2 macallan #define DEC_WIDTH_LINEAR 0x00 132 1.2 macallan #define DEC_WIDTH_640 0x01 133 1.2 macallan #define DEC_WIDTH_800 0x02 134 1.2 macallan #define DEC_WIDTH_1024 0x04 135 1.2 macallan #define DEC_WIDTH_1152 0x05 136 1.2 macallan #define DEC_WIDTH_1280 0x06 137 1.2 macallan #define DEC_WIDTH_1600 0x07 138 1.2 macallan 139 1.2 macallan /* update mode */ 140 1.2 macallan #define DEC_UPDATE_NONE 0x00 141 1.2 macallan #define DEC_UPDATE_TOP_RIGHT 0x01 142 1.2 macallan #define DEC_UPDATE_BOTTOM_LEFT 0x02 143 1.2 macallan #define DEC_UPDATE_LASTPIX 0x03 144 1.2 macallan 145 1.2 macallan /* quickstart mode - operation starts as soon as given register is written to */ 146 1.2 macallan #define DEC_START_DIMX 0x01 147 1.2 macallan #define DEC_START_SRC 0x02 148 1.2 macallan #define DEC_START_DST 0x03 149 1.2 macallan 150 1.2 macallan /* ROP */ 151 1.2 macallan #define ROP_DST 0x66 152 1.2 macallan #define ROP_SRC 0xcc 153 1.2 macallan #define ROP_INV 0x33 154 1.2 macallan #define ROP_PATTERN 0xf0 155 1.2 macallan 156 1.2 macallan /* 157 1.2 macallan * Configuration Registers 158 1.2 macallan */ 159 1.2 macallan 160 1.2 macallan #define ATR_PIXEL 0x0080 /* byte access */ 161 1.2 macallan #define PIXEL_DEPTH_MASK 0x0f 162 1.2 macallan #define PIXEL_DEPTH_SHIFT 0 163 1.2 macallan 164 1.2 macallan /* pixel depth */ 165 1.2 macallan #define PIXEL_4 0x01 166 1.2 macallan #define PIXEL_8 0x02 167 1.2 macallan #define PIXEL_15 0x0c 168 1.2 macallan #define PIXEL_16 0x0d 169 1.2 macallan #define PIXEL_24 0x0e 170 1.2 macallan #define PIXEL_32 0x0f 171 1.2 macallan 172 1.2 macallan #define ATR_APERTURE 0x00c0 /* short access */ 173 1.2 macallan 174 1.2 macallan /* 175 1.2 macallan * DPMS Control 176 1.2 macallan */ 177 1.2 macallan 178 1.2 macallan #define ATR_DPMS 0x00d0 /* byte access */ 179 1.2 macallan #define DPMS_HSYNC_DISABLE 0x01 180 1.2 macallan #define DPMS_VSYNC_DISABLE 0x02 181 1.2 macallan 182 1.2 macallan /* 183 1.2 macallan * RAMDAC 184 1.2 macallan */ 185 1.2 macallan 186 1.2 macallan #define ATR_COLOR_CORRECTION 0x00e0 187 1.2 macallan #define ATR_MCLK 0x00e8 188 1.2 macallan #define ATR_PCLK 0x00ec 189 1.2 macallan 190 1.2 macallan /* 191 1.2 macallan * Hardware Cursor 192 1.2 macallan * 193 1.2 macallan * The position can not become negative; the offset register, encoded as 194 1.2 macallan * (signed y delta << 8) | signed x delta, allow the cursor image to 195 1.2 macallan * cross the upper-left corner. 196 1.2 macallan */ 197 1.2 macallan 198 1.2 macallan #define ATR_CURSOR_ENABLE 0x0140 199 1.2 macallan #define ATR_CURSOR_FG 0x0141 /* 3:3:2 */ 200 1.2 macallan #define ATR_CURSOR_BG 0x0142 /* 3:3:2 */ 201 1.2 macallan #define ATR_CURSOR_ADDRESS 0x0144 /* in KB from vram */ 202 1.2 macallan #define ATR_CURSOR_POSITION 0x0148 203 1.2 macallan #define ATR_CURSOR_OFFSET 0x014c /* short access */ 204 1.2 macallan 205 1.2 macallan /* 206 1.2 macallan * Identification Register 207 1.2 macallan */ 208 1.2 macallan 209 1.2 macallan #define ATR_ID 0x0182 210 1.2 macallan #define ID_AP6422 0x6422 211 1.2 macallan #define ID_AT24 0x6424 212 1.2 macallan #define ID_AT3D 0x643d 213 1.2 macallan 214 1.2 macallan /* 215 1.2 macallan * Status Registers 216 1.2 macallan */ 217 1.2 macallan 218 1.2 macallan #define ATR_FIFO_STATUS 0x01fc 219 1.2 macallan #define ATR_BLT_STATUS 0x01fd 220 1.2 macallan #define FIFO_MASK 0x0f 221 1.2 macallan #define FIFO_SHIFT 0 222 1.2 macallan #define FIFO_AP6422 4 223 1.2 macallan #define FIFO_AT24 8 224 1.2 macallan 225 1.2 macallan #define BLT_HOST_BUSY 0x01 226 1.2 macallan #define BLT_ENGINE_BUSY 0x04 227 1.2 macallan 228 1.2 macallan #define MGX_REG_ATREG_OFFSET 0x000b0000 229 1.2 macallan 230 1.2 macallan #endif /* MGX_REG_H */ 231
Indexes created Mon Sep 29 21:09:56 GMT 2025