mgxreg.h revision 1.2
1 /* $NetBSD: mgxreg.h,v 1.2 2015/01/04 18:18:20 macallan Exp $ */ 2 3 /*- 4 * Copyright (c) 2014 Michael Lorenz 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #ifndef MGX_REG_H 30 #define MGX_REG_H 31 32 #define VGA_BASE 0x3c0 33 34 /* register definitions based on OpenBSD's atxxreg.h: */ 35 36 /* 37 * Copyright (c) 2008 Miodrag Vallat. 38 * 39 * Permission to use, copy, modify, and distribute this software for any 40 * purpose with or without fee is hereby granted, provided that the above 41 * copyright notice and this permission notice appear in all copies. 42 * 43 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 44 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 45 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 46 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 47 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 48 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 49 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 50 */ 51 52 /* 53 * Alliance Promotion AP6422, AT24 and AT3D extended register set definitions. 54 * 55 * This has been reconstructed from XFree86 ``apm'' driver, whose authors 56 * apparently do not believe in meaningful constants for numbers. See 57 * apm_regs.h for more madness. 58 */ 59 60 /* 61 * Clipping Control 62 */ 63 64 #define ATR_CLIP_CONTROL 0x0030 /* byte access */ 65 #define ATR_CLIP_LEFT 0x0038 66 #define ATR_CLIP_TOP 0x003a 67 #define ATR_CLIP_LEFTTOP 0x0038 68 #define ATR_CLIP_RIGHT 0x003c 69 #define ATR_CLIP_BOTTOM 0x003e 70 #define ATR_CLIP_RIGHTBOTTOM 0x003c 71 72 /* 73 * Drawing Engine 74 */ 75 76 #define ATR_DEC 0x0040 77 #define ATR_ROP 0x0046 78 #define ATR_BYTEMASK 0x0047 79 #define ATR_PATTERN1 0x0048 80 #define ATR_PATTERN2 0x004c 81 #define ATR_SRC_X 0x0050 82 #define ATR_SRC_Y 0x0052 83 #define ATR_SRC_XY 0x0050 84 #define ATR_DST_X 0x0054 85 #define ATR_DST_Y 0x0056 86 #define ATR_DST_XY 0x0054 87 #define ATR_W 0x0058 88 #define ATR_H 0x005a 89 #define ATR_WH 0x0058 90 #define ATR_OFFSET 0x005c 91 #define ATR_SRC_OFFSET 0x005e 92 #define ATR_FG 0x0060 93 #define ATR_BG 0x0064 94 95 /* DEC layout */ 96 #define DEC_COMMAND_MASK 0x0000003f 97 #define DEC_COMMAND_SHIFT 0 98 #define DEC_DIR_X_REVERSE 0x00000040 99 #define DEC_DIR_Y_REVERSE 0x00000080 100 #define DEC_DIR_Y_MAJOR 0x00000100 101 #define DEC_SRC_LINEAR 0x00000200 102 #define DEC_SRC_CONTIGUOUS 0x00000800 103 #define DEC_MONOCHROME 0x00001000 104 #define DEC_SRC_TRANSPARENT 0x00002000 105 #define DEC_DEPTH_MASK 0x0001c000 106 #define DEC_DEPTH_SHIFT 14 107 #define DEC_DST_LINEAR 0x00040000 108 #define DEC_DST_CONTIGUOUS 0x00080000 109 #define DEC_DST_TRANSPARENT 0x00100000 110 #define DEC_DST_TRANSPARENT_POLARITY 0x00200000 111 #define DEC_PATTERN_MASK 0x00c00000 112 #define DEC_PATTERN_SHIFT 22 113 #define DEC_WIDTH_MASK 0x07000000 114 #define DEC_WIDTH_SHIFT 24 115 #define DEC_UPDATE_MASK 0x18000000 116 #define DEC_UPDATE_SHIFT 27 117 #define DEC_START_MASK 0x60000000 118 #define DEC_START_SHIFT 29 119 #define DEC_START 0x80000000 120 121 /* DEC commands */ 122 #define DEC_COMMAND_NOP 0x00 123 #define DEC_COMMAND_BLT 0x01 /* screen to screen blt */ 124 #define DEC_COMMAND_RECT 0x02 /* rectangle fill */ 125 #define DEC_COMMAND_BLT_STRETCH 0x03 /* blt and stretch */ 126 #define DEC_COMMAND_STRIP 0x04 /* strip pattern */ 127 #define DEC_COMMAND_HOST_BLT 0x08 /* host to screen blt */ 128 #define DEC_COMMAND_SCREEN_BLT 0x09 /* screen to host blt */ 129 #define DEC_COMMAND_VECT_ENDP 0x0c /* vector with end point */ 130 #define DEC_COMMAND_VECT_NO_ENDP 0x0d /* vector without end point */ 131 132 /* depth */ 133 #define DEC_DEPTH_8 0x01 134 #define DEC_DEPTH_16 0x02 135 #define DEC_DEPTH_32 0x03 136 #define DEC_DEPTH_24 0x04 137 138 /* width */ 139 #define DEC_WIDTH_LINEAR 0x00 140 #define DEC_WIDTH_640 0x01 141 #define DEC_WIDTH_800 0x02 142 #define DEC_WIDTH_1024 0x04 143 #define DEC_WIDTH_1152 0x05 144 #define DEC_WIDTH_1280 0x06 145 #define DEC_WIDTH_1600 0x07 146 147 /* update mode */ 148 #define DEC_UPDATE_NONE 0x00 149 #define DEC_UPDATE_TOP_RIGHT 0x01 150 #define DEC_UPDATE_BOTTOM_LEFT 0x02 151 #define DEC_UPDATE_LASTPIX 0x03 152 153 /* quickstart mode - operation starts as soon as given register is written to */ 154 #define DEC_START_DIMX 0x01 155 #define DEC_START_SRC 0x02 156 #define DEC_START_DST 0x03 157 158 /* ROP */ 159 #define ROP_DST 0x66 160 #define ROP_SRC 0xcc 161 #define ROP_INV 0x33 162 #define ROP_PATTERN 0xf0 163 164 /* 165 * Configuration Registers 166 */ 167 168 #define ATR_PIXEL 0x0080 /* byte access */ 169 #define PIXEL_DEPTH_MASK 0x0f 170 #define PIXEL_DEPTH_SHIFT 0 171 172 /* pixel depth */ 173 #define PIXEL_4 0x01 174 #define PIXEL_8 0x02 175 #define PIXEL_15 0x0c 176 #define PIXEL_16 0x0d 177 #define PIXEL_24 0x0e 178 #define PIXEL_32 0x0f 179 180 #define ATR_APERTURE 0x00c0 /* short access */ 181 182 /* 183 * DPMS Control 184 */ 185 186 #define ATR_DPMS 0x00d0 /* byte access */ 187 #define DPMS_HSYNC_DISABLE 0x01 188 #define DPMS_VSYNC_DISABLE 0x02 189 190 /* 191 * RAMDAC 192 */ 193 194 #define ATR_COLOR_CORRECTION 0x00e0 195 #define ATR_MCLK 0x00e8 196 #define ATR_PCLK 0x00ec 197 198 /* 199 * Hardware Cursor 200 * 201 * The position can not become negative; the offset register, encoded as 202 * (signed y delta << 8) | signed x delta, allow the cursor image to 203 * cross the upper-left corner. 204 */ 205 206 #define ATR_CURSOR_ENABLE 0x0140 207 #define ATR_CURSOR_FG 0x0141 /* 3:3:2 */ 208 #define ATR_CURSOR_BG 0x0142 /* 3:3:2 */ 209 #define ATR_CURSOR_ADDRESS 0x0144 /* in KB from vram */ 210 #define ATR_CURSOR_POSITION 0x0148 211 #define ATR_CURSOR_OFFSET 0x014c /* short access */ 212 213 /* 214 * Identification Register 215 */ 216 217 #define ATR_ID 0x0182 218 #define ID_AP6422 0x6422 219 #define ID_AT24 0x6424 220 #define ID_AT3D 0x643d 221 222 /* 223 * Status Registers 224 */ 225 226 #define ATR_FIFO_STATUS 0x01fc 227 #define ATR_BLT_STATUS 0x01fd 228 #define FIFO_MASK 0x0f 229 #define FIFO_SHIFT 0 230 #define FIFO_AP6422 4 231 #define FIFO_AT24 8 232 233 #define BLT_HOST_BUSY 0x01 234 #define BLT_ENGINE_BUSY 0x04 235 236 #define MGX_REG_ATREG_OFFSET 0x000b0000 237 238 #endif /* MGX_REG_H */ 239
Indexes created Tue Sep 30 10:09:55 GMT 2025