mgxreg.h revision 1.3
1 /* $NetBSD: mgxreg.h,v 1.3 2016/02/11 02:23:44 macallan Exp $ */ 2 3 /* register definitions based on OpenBSD's atxxreg.h: */ 4 5 /* 6 * Copyright (c) 2008 Miodrag Vallat. 7 * Copyright (c) 2014 Michael Lorenz 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 /* 23 * Alliance Promotion AP6422, AT24 and AT3D extended register set definitions. 24 * 25 * This has been reconstructed from XFree86 ``apm'' driver, whose authors 26 * apparently do not believe in meaningful constants for numbers. See 27 * apm_regs.h for more madness. 28 */ 29 30 #ifndef MGX_REG_H 31 #define MGX_REG_H 32 33 #define VGA_BASE 0x3c0 34 #define CRTC_INDEX 0x3d4 35 #define CRTC_DATA 0x3d5 36 #define SEQ_INDEX 0x3c4 37 #define SEQ_DATA 0x3c5 38 39 /* 40 * some bits from the XFree86 3.x vga256 / apm driver: 41 * - sequencer registers 0x11 - 0x17 contain the chip's ID, 'Pro6424' for AT24 42 */ 43 44 #define SEQ_APERTURE 0x1c 45 #define AP_SIZE_MASK 0x06 46 #define AP_SIZE_1MB 0x00 47 #define AP_SIZE_2MB 0x02 48 #define AP_SIZE_4MB 0x04 49 #define AP_SIZE_6MB 0x06 50 #define AP_SIMULTANEOUS 0x20 /* sim. access to VRAM? */ 51 52 /* 53 * Clipping Control 54 */ 55 56 #define ATR_CLIP_CONTROL 0x0030 /* byte access */ 57 #define ATR_CLIP_LEFT 0x0038 58 #define ATR_CLIP_TOP 0x003a 59 #define ATR_CLIP_LEFTTOP 0x0038 60 #define ATR_CLIP_RIGHT 0x003c 61 #define ATR_CLIP_BOTTOM 0x003e 62 #define ATR_CLIP_RIGHTBOTTOM 0x003c 63 64 /* 65 * Drawing Engine 66 */ 67 68 #define ATR_DEC 0x0040 69 #define ATR_ROP 0x0046 70 #define ATR_BYTEMASK 0x0047 71 #define ATR_PATTERN1 0x0048 72 #define ATR_PATTERN2 0x004c 73 #define ATR_SRC_X 0x0050 74 #define ATR_SRC_Y 0x0052 75 #define ATR_SRC_XY 0x0050 76 #define ATR_DST_X 0x0054 77 #define ATR_DST_Y 0x0056 78 #define ATR_DST_XY 0x0054 79 #define ATR_W 0x0058 80 #define ATR_H 0x005a 81 #define ATR_WH 0x0058 82 #define ATR_OFFSET 0x005c 83 #define ATR_SRC_OFFSET 0x005e 84 #define ATR_FG 0x0060 85 #define ATR_BG 0x0064 86 87 /* DEC layout */ 88 #define DEC_COMMAND_MASK 0x0000003f 89 #define DEC_COMMAND_SHIFT 0 90 #define DEC_DIR_X_REVERSE 0x00000040 91 #define DEC_DIR_Y_REVERSE 0x00000080 92 #define DEC_DIR_Y_MAJOR 0x00000100 93 #define DEC_SRC_LINEAR 0x00000200 94 #define DEC_SRC_CONTIGUOUS 0x00000800 95 #define DEC_MONOCHROME 0x00001000 96 #define DEC_SRC_TRANSPARENT 0x00002000 97 #define DEC_DEPTH_MASK 0x0001c000 98 #define DEC_DEPTH_SHIFT 14 99 #define DEC_DST_LINEAR 0x00040000 100 #define DEC_DST_CONTIGUOUS 0x00080000 101 #define DEC_DST_TRANSPARENT 0x00100000 102 #define DEC_DST_TRANSPARENT_POLARITY 0x00200000 103 #define DEC_PATTERN_MASK 0x00c00000 104 #define DEC_PATTERN_SHIFT 22 105 #define DEC_WIDTH_MASK 0x07000000 106 #define DEC_WIDTH_SHIFT 24 107 #define DEC_UPDATE_MASK 0x18000000 108 #define DEC_UPDATE_SHIFT 27 109 #define DEC_START_MASK 0x60000000 110 #define DEC_START_SHIFT 29 111 #define DEC_START 0x80000000 112 113 /* DEC commands */ 114 #define DEC_COMMAND_NOP 0x00 115 #define DEC_COMMAND_BLT 0x01 /* screen to screen blt */ 116 #define DEC_COMMAND_RECT 0x02 /* rectangle fill */ 117 #define DEC_COMMAND_BLT_STRETCH 0x03 /* blt and stretch */ 118 #define DEC_COMMAND_STRIP 0x04 /* strip pattern */ 119 #define DEC_COMMAND_HOST_BLT 0x08 /* host to screen blt */ 120 #define DEC_COMMAND_SCREEN_BLT 0x09 /* screen to host blt */ 121 #define DEC_COMMAND_VECT_ENDP 0x0c /* vector with end point */ 122 #define DEC_COMMAND_VECT_NO_ENDP 0x0d /* vector without end point */ 123 124 /* depth */ 125 #define DEC_DEPTH_8 0x01 126 #define DEC_DEPTH_16 0x02 127 #define DEC_DEPTH_32 0x03 128 #define DEC_DEPTH_24 0x04 129 130 /* width */ 131 #define DEC_WIDTH_LINEAR 0x00 132 #define DEC_WIDTH_640 0x01 133 #define DEC_WIDTH_800 0x02 134 #define DEC_WIDTH_1024 0x04 135 #define DEC_WIDTH_1152 0x05 136 #define DEC_WIDTH_1280 0x06 137 #define DEC_WIDTH_1600 0x07 138 139 /* update mode */ 140 #define DEC_UPDATE_NONE 0x00 141 #define DEC_UPDATE_TOP_RIGHT 0x01 142 #define DEC_UPDATE_BOTTOM_LEFT 0x02 143 #define DEC_UPDATE_LASTPIX 0x03 144 145 /* quickstart mode - operation starts as soon as given register is written to */ 146 #define DEC_START_DIMX 0x01 147 #define DEC_START_SRC 0x02 148 #define DEC_START_DST 0x03 149 150 /* ROP */ 151 #define ROP_DST 0x66 152 #define ROP_SRC 0xcc 153 #define ROP_INV 0x33 154 #define ROP_PATTERN 0xf0 155 156 /* 157 * Configuration Registers 158 */ 159 160 #define ATR_PIXEL 0x0080 /* byte access */ 161 #define PIXEL_DEPTH_MASK 0x0f 162 #define PIXEL_DEPTH_SHIFT 0 163 164 /* pixel depth */ 165 #define PIXEL_4 0x01 166 #define PIXEL_8 0x02 167 #define PIXEL_15 0x0c 168 #define PIXEL_16 0x0d 169 #define PIXEL_24 0x0e 170 #define PIXEL_32 0x0f 171 172 #define ATR_APERTURE 0x00c0 /* short access */ 173 174 /* 175 * DPMS Control 176 */ 177 178 #define ATR_DPMS 0x00d0 /* byte access */ 179 #define DPMS_HSYNC_DISABLE 0x01 180 #define DPMS_VSYNC_DISABLE 0x02 181 182 /* 183 * RAMDAC 184 */ 185 186 #define ATR_COLOR_CORRECTION 0x00e0 187 #define ATR_MCLK 0x00e8 188 #define ATR_PCLK 0x00ec 189 190 /* 191 * Hardware Cursor 192 * 193 * The position can not become negative; the offset register, encoded as 194 * (signed y delta << 8) | signed x delta, allow the cursor image to 195 * cross the upper-left corner. 196 */ 197 198 #define ATR_CURSOR_ENABLE 0x0140 199 #define ATR_CURSOR_FG 0x0141 /* 3:3:2 */ 200 #define ATR_CURSOR_BG 0x0142 /* 3:3:2 */ 201 #define ATR_CURSOR_ADDRESS 0x0144 /* in KB from vram */ 202 #define ATR_CURSOR_POSITION 0x0148 203 #define ATR_CURSOR_OFFSET 0x014c /* short access */ 204 205 /* 206 * Identification Register 207 */ 208 209 #define ATR_ID 0x0182 210 #define ID_AP6422 0x6422 211 #define ID_AT24 0x6424 212 #define ID_AT3D 0x643d 213 214 /* 215 * Status Registers 216 */ 217 218 #define ATR_FIFO_STATUS 0x01fc 219 #define ATR_BLT_STATUS 0x01fd 220 #define FIFO_MASK 0x0f 221 #define FIFO_SHIFT 0 222 #define FIFO_AP6422 4 223 #define FIFO_AT24 8 224 225 #define BLT_HOST_BUSY 0x01 226 #define BLT_ENGINE_BUSY 0x04 227 228 #define MGX_REG_ATREG_OFFSET 0x000b0000 229 230 #endif /* MGX_REG_H */ 231
Indexes created Tue Sep 30 06:09:59 GMT 2025