mgxreg.h revision 1.6
1 /* $NetBSD: mgxreg.h,v 1.6 2021/10/30 05:37:39 macallan Exp $ */ 2 3 /* register definitions based on OpenBSD's atxxreg.h: */ 4 5 /* 6 * Copyright (c) 2008 Miodrag Vallat. 7 * Copyright (c) 2014 Michael Lorenz 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 /* 23 * Alliance Promotion AP6422, AT24 and AT3D extended register set definitions. 24 * 25 * This has been reconstructed from XFree86 ``apm'' driver, whose authors 26 * apparently do not believe in meaningful constants for numbers. See 27 * apm_regs.h for more madness. 28 */ 29 30 #ifndef MGX_REG_H 31 #define MGX_REG_H 32 33 #define MGX_FBOFFSET 0x00000000 34 #define MGX_BLTOFFSET 0x00800000 35 36 #define VGA_BASE 0x3c0 37 #define CRTC_INDEX 0x3d4 38 #define CRTC_DATA 0x3d5 39 #define SEQ_INDEX 0x3c4 40 #define SEQ_DATA 0x3c5 41 42 /* 43 * some bits from the XFree86 3.x vga256 / apm driver: 44 * - sequencer registers 0x11 - 0x17 contain the chip's ID, 'Pro6424' for AT24 45 */ 46 47 #define SEQ_APERTURE 0x1c 48 #define AP_SIZE_MASK 0x06 49 #define AP_SIZE_1MB 0x00 50 #define AP_SIZE_2MB 0x02 51 #define AP_SIZE_4MB 0x04 52 #define AP_SIZE_6MB 0x06 53 #define AP_SIMULTANEOUS 0x20 /* sim. access to VRAM? */ 54 55 /* 56 * Clipping Control 57 */ 58 59 #define ATR_CLIP_CONTROL 0x0030 /* byte access */ 60 #define ATR_CLIP_LEFT 0x0038 61 #define ATR_CLIP_TOP 0x003a 62 #define ATR_CLIP_LEFTTOP 0x0038 63 #define ATR_CLIP_RIGHT 0x003c 64 #define ATR_CLIP_BOTTOM 0x003e 65 #define ATR_CLIP_RIGHTBOTTOM 0x003c 66 67 /* 68 * Drawing Engine 69 */ 70 71 #define ATR_DEC 0x0040 72 #define ATR_ROP 0x0046 73 #define ATR_BYTEMASK 0x0047 74 #define ATR_PATTERN1 0x0048 75 #define ATR_PATTERN2 0x004c 76 #define ATR_SRC_X 0x0050 77 #define ATR_SRC_Y 0x0052 78 #define ATR_SRC_XY 0x0050 /* pointer in vram if DEC_SRC_LINEAR */ 79 #define ATR_DST_X 0x0054 80 #define ATR_DST_Y 0x0056 81 #define ATR_DST_XY 0x0054 82 #define ATR_W 0x0058 83 #define ATR_H 0x005a 84 #define ATR_WH 0x0058 85 #define ATR_OFFSET 0x005c 86 #define ATR_SRC_OFFSET 0x005e 87 #define ATR_FG 0x0060 88 #define ATR_BG 0x0064 89 90 /* DEC layout */ 91 #define DEC_COMMAND_MASK 0x0000003f 92 #define DEC_COMMAND_SHIFT 0 93 #define DEC_DIR_X_REVERSE 0x00000040 94 #define DEC_DIR_Y_REVERSE 0x00000080 95 #define DEC_DIR_Y_MAJOR 0x00000100 96 #define DEC_SRC_LINEAR 0x00000200 97 #define DEC_SRC_CONTIGUOUS 0x00000800 98 #define DEC_MONOCHROME 0x00001000 99 #define DEC_SRC_TRANSPARENT 0x00002000 100 #define DEC_DEPTH_MASK 0x0001c000 101 #define DEC_DEPTH_SHIFT 14 102 #define DEC_DST_LINEAR 0x00040000 103 #define DEC_DST_CONTIGUOUS 0x00080000 104 #define DEC_DST_TRANSPARENT 0x00100000 105 #define DEC_DST_TRANSPARENT_POLARITY 0x00200000 106 #define DEC_PATTERN_MASK 0x00c00000 107 #define DEC_PATTERN_SHIFT 22 108 #define DEC_WIDTH_MASK 0x07000000 109 #define DEC_WIDTH_SHIFT 24 110 #define DEC_UPDATE_MASK 0x18000000 111 #define DEC_UPDATE_SHIFT 27 112 #define DEC_START_MASK 0x60000000 113 #define DEC_START_SHIFT 29 114 #define DEC_START 0x80000000 115 116 /* DEC commands */ 117 #define DEC_COMMAND_NOP 0x00 118 #define DEC_COMMAND_BLT 0x01 /* screen to screen blt */ 119 #define DEC_COMMAND_RECT 0x02 /* rectangle fill */ 120 #define DEC_COMMAND_BLT_STRETCH 0x03 /* blt and stretch */ 121 #define DEC_COMMAND_STRIP 0x04 /* strip pattern */ 122 #define DEC_COMMAND_HOST_BLT 0x08 /* host to screen blt */ 123 #define DEC_COMMAND_SCREEN_BLT 0x09 /* screen to host blt */ 124 #define DEC_COMMAND_VECT_ENDP 0x0c /* vector with end point */ 125 #define DEC_COMMAND_VECT_NO_ENDP 0x0d /* vector without end point */ 126 127 /* depth */ 128 #define DEC_DEPTH_8 0x01 129 #define DEC_DEPTH_16 0x02 130 #define DEC_DEPTH_32 0x03 131 #define DEC_DEPTH_24 0x04 132 133 /* width */ 134 #define DEC_WIDTH_LINEAR 0x00 135 #define DEC_WIDTH_640 0x01 136 #define DEC_WIDTH_800 0x02 137 #define DEC_WIDTH_1024 0x04 138 #define DEC_WIDTH_1152 0x05 139 #define DEC_WIDTH_1280 0x06 140 #define DEC_WIDTH_1600 0x07 141 142 /* update mode */ 143 #define DEC_UPDATE_NONE 0x00 144 #define DEC_UPDATE_TOP_RIGHT 0x01 145 #define DEC_UPDATE_BOTTOM_LEFT 0x02 146 #define DEC_UPDATE_LASTPIX 0x03 147 148 /* quickstart mode - operation starts as soon as given register is written to */ 149 #define DEC_START_DIMX 0x01 150 #define DEC_START_SRC 0x02 151 #define DEC_START_DST 0x03 152 153 /* ROP */ 154 #define ROP_DST 0x66 155 #define ROP_SRC 0xcc 156 #define ROP_INV 0x33 157 #define ROP_PATTERN 0xf0 158 159 /* 160 * Configuration Registers 161 */ 162 163 #define ATR_PIXEL 0x0080 /* byte access */ 164 #define PIXEL_DEPTH_MASK 0x0f 165 #define PIXEL_DEPTH_SHIFT 0 166 167 /* pixel depth */ 168 #define PIXEL_4 0x01 169 #define PIXEL_8 0x02 170 #define PIXEL_15 0x0c 171 #define PIXEL_16 0x0d 172 #define PIXEL_24 0x0e 173 #define PIXEL_32 0x0f 174 175 #define ATR_APERTURE 0x00c0 /* short access */ 176 177 /* 178 * DPMS Control 179 */ 180 181 #define ATR_DPMS 0x00d0 /* byte access */ 182 #define DPMS_HSYNC_DISABLE 0x01 183 #define DPMS_VSYNC_DISABLE 0x02 184 #define DPMS_SYNC_DISABLE_ALL 0x03 185 186 /* 187 * RAMDAC 188 */ 189 190 #define ATR_COLOR_CORRECTION 0x00e0 191 #define ATR_MCLK 0x00e8 192 #define ATR_PCLK 0x00ec 193 194 /* 195 * Hardware Cursor 196 * 197 * The position can not become negative; the offset register, encoded as 198 * (signed y delta << 8) | signed x delta, allow the cursor image to 199 * cross the upper-left corner. 200 */ 201 202 #define ATR_CURSOR_ENABLE 0x0140 203 #define ATR_CURSOR_FG 0x0141 /* 3:3:2 */ 204 #define ATR_CURSOR_BG 0x0142 /* 3:3:2 */ 205 #define ATR_CURSOR_ADDRESS 0x0144 /* in KB from vram */ 206 #define ATR_CURSOR_POSITION 0x0148 207 #define ATR_CURSOR_HOTSPOT 0x014c /* short access */ 208 209 /* 210 * Identification Register 211 */ 212 213 #define ATR_ID 0x0182 214 #define ID_AP6422 0x6422 215 #define ID_AT24 0x6424 216 #define ID_AT3D 0x643d 217 218 /* 219 * Status Registers 220 */ 221 222 #define ATR_FIFO_STATUS 0x01fc 223 #define ATR_BLT_STATUS 0x01fd 224 #define FIFO_MASK 0x0f 225 #define FIFO_SHIFT 0 226 #define FIFO_AP6422 4 227 #define FIFO_AT24 8 228 229 #define BLT_HOST_BUSY 0x01 230 #define BLT_ENGINE_BUSY 0x04 231 232 #define MGX_REG_ATREG_OFFSET 0x000b0000 233 234 #endif /* MGX_REG_H */ 235
Indexes created Tue Sep 30 11:09:46 GMT 2025