qe.c revision 1.11
1 /* $NetBSD: qe.c,v 1.11 2000/07/09 20:57:43 pk Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1998 Jason L. Wright. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the authors may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 59 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 63 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 */ 65 66 /* 67 * Driver for the SBus qec+qe QuadEthernet board. 68 * 69 * This driver was written using the AMD MACE Am79C940 documentation, some 70 * ideas gleaned from the S/Linux driver for this card, Solaris header files, 71 * and a loan of a card from Paul Southworth of the Internet Engineering 72 * Group (www.ieng.com). 73 */ 74 75 #define QEDEBUG 76 77 #include "opt_ddb.h" 78 #include "opt_inet.h" 79 #include "opt_ccitt.h" 80 #include "opt_llc.h" 81 #include "opt_ns.h" 82 #include "bpfilter.h" 83 #include "rnd.h" 84 85 #include <sys/param.h> 86 #include <sys/systm.h> 87 #include <sys/kernel.h> 88 #include <sys/errno.h> 89 #include <sys/ioctl.h> 90 #include <sys/mbuf.h> 91 #include <sys/socket.h> 92 #include <sys/syslog.h> 93 #include <sys/device.h> 94 #include <sys/malloc.h> 95 #if NRND > 0 96 #include <sys/rnd.h> 97 #endif 98 99 #include <net/if.h> 100 #include <net/if_dl.h> 101 #include <net/if_types.h> 102 #include <net/netisr.h> 103 #include <net/if_media.h> 104 #include <net/if_ether.h> 105 106 #ifdef INET 107 #include <netinet/in.h> 108 #include <netinet/if_inarp.h> 109 #include <netinet/in_systm.h> 110 #include <netinet/in_var.h> 111 #include <netinet/ip.h> 112 #endif 113 114 #ifdef NS 115 #include <netns/ns.h> 116 #include <netns/ns_if.h> 117 #endif 118 119 #if NBPFILTER > 0 120 #include <net/bpf.h> 121 #include <net/bpfdesc.h> 122 #endif 123 124 #include <machine/bus.h> 125 #include <machine/intr.h> 126 #include <machine/autoconf.h> 127 128 #include <dev/sbus/sbusvar.h> 129 #include <dev/sbus/qecreg.h> 130 #include <dev/sbus/qecvar.h> 131 #include <dev/sbus/qereg.h> 132 133 struct qe_softc { 134 struct device sc_dev; /* base device */ 135 struct sbusdev sc_sd; /* sbus device */ 136 bus_space_tag_t sc_bustag; /* bus & dma tags */ 137 bus_dma_tag_t sc_dmatag; 138 bus_dmamap_t sc_dmamap; 139 struct ethercom sc_ethercom; 140 struct ifmedia sc_ifmedia; /* interface media */ 141 142 struct qec_softc *sc_qec; /* QEC parent */ 143 144 bus_space_handle_t sc_qr; /* QEC registers */ 145 bus_space_handle_t sc_mr; /* MACE registers */ 146 bus_space_handle_t sc_cr; /* channel registers */ 147 148 int sc_channel; /* channel number */ 149 u_int sc_rev; /* board revision */ 150 151 int sc_burst; 152 153 struct qec_ring sc_rb; /* Packet Ring Buffer */ 154 155 /* MAC address */ 156 u_int8_t sc_enaddr[6]; 157 158 #ifdef QEDEBUG 159 int sc_debug; 160 #endif 161 }; 162 163 int qematch __P((struct device *, struct cfdata *, void *)); 164 void qeattach __P((struct device *, struct device *, void *)); 165 166 void qeinit __P((struct qe_softc *)); 167 void qestart __P((struct ifnet *)); 168 void qestop __P((struct qe_softc *)); 169 void qewatchdog __P((struct ifnet *)); 170 int qeioctl __P((struct ifnet *, u_long, caddr_t)); 171 void qereset __P((struct qe_softc *)); 172 173 int qeintr __P((void *)); 174 int qe_eint __P((struct qe_softc *, u_int32_t)); 175 int qe_rint __P((struct qe_softc *)); 176 int qe_tint __P((struct qe_softc *)); 177 void qe_mcreset __P((struct qe_softc *)); 178 179 static int qe_put __P((struct qe_softc *, int, struct mbuf *)); 180 static void qe_read __P((struct qe_softc *, int, int)); 181 static struct mbuf *qe_get __P((struct qe_softc *, int, int)); 182 183 /* ifmedia callbacks */ 184 void qe_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 185 int qe_ifmedia_upd __P((struct ifnet *)); 186 187 struct cfattach qe_ca = { 188 sizeof(struct qe_softc), qematch, qeattach 189 }; 190 191 int 192 qematch(parent, cf, aux) 193 struct device *parent; 194 struct cfdata *cf; 195 void *aux; 196 { 197 struct sbus_attach_args *sa = aux; 198 199 return (strcmp(cf->cf_driver->cd_name, sa->sa_name) == 0); 200 } 201 202 void 203 qeattach(parent, self, aux) 204 struct device *parent, *self; 205 void *aux; 206 { 207 struct sbus_attach_args *sa = aux; 208 struct qec_softc *qec = (struct qec_softc *)parent; 209 struct qe_softc *sc = (struct qe_softc *)self; 210 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 211 int node = sa->sa_node; 212 bus_dma_tag_t dmatag = sa->sa_dmatag; 213 bus_dma_segment_t seg; 214 bus_size_t size; 215 int rseg, error; 216 extern void myetheraddr __P((u_char *)); 217 218 if (sa->sa_nreg < 2) { 219 printf("%s: only %d register sets\n", 220 self->dv_xname, sa->sa_nreg); 221 return; 222 } 223 224 if (bus_space_map2(sa->sa_bustag, 225 (bus_type_t)sa->sa_reg[0].sbr_slot, 226 (bus_addr_t)sa->sa_reg[0].sbr_offset, 227 (bus_size_t)sa->sa_reg[0].sbr_size, 228 BUS_SPACE_MAP_LINEAR, 0, &sc->sc_cr) != 0) { 229 printf("%s: cannot map registers\n", self->dv_xname); 230 return; 231 } 232 233 if (bus_space_map2(sa->sa_bustag, 234 (bus_type_t)sa->sa_reg[1].sbr_slot, 235 (bus_addr_t)sa->sa_reg[1].sbr_offset, 236 (bus_size_t)sa->sa_reg[1].sbr_size, 237 BUS_SPACE_MAP_LINEAR, 0, &sc->sc_mr) != 0) { 238 printf("%s: cannot map registers\n", self->dv_xname); 239 return; 240 } 241 242 sc->sc_rev = getpropint(node, "mace-version", -1); 243 printf(" rev %x", sc->sc_rev); 244 245 sc->sc_qec = qec; 246 sc->sc_qr = qec->sc_regs; 247 248 sc->sc_channel = getpropint(node, "channel#", -1); 249 sc->sc_burst = qec->sc_burst; 250 251 qestop(sc); 252 253 /* Note: no interrupt level passed */ 254 (void)bus_intr_establish(sa->sa_bustag, 0, IPL_NET, 0, qeintr, sc); 255 myetheraddr(sc->sc_enaddr); 256 257 /* 258 * Allocate descriptor ring and buffers. 259 */ 260 261 /* for now, allocate as many bufs as there are ring descriptors */ 262 sc->sc_rb.rb_ntbuf = QEC_XD_RING_MAXSIZE; 263 sc->sc_rb.rb_nrbuf = QEC_XD_RING_MAXSIZE; 264 265 size = QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 266 QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 267 sc->sc_rb.rb_ntbuf * QE_PKT_BUF_SZ + 268 sc->sc_rb.rb_nrbuf * QE_PKT_BUF_SZ; 269 270 /* Get a DMA handle */ 271 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0, 272 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 273 printf("%s: DMA map create error %d\n", self->dv_xname, error); 274 return; 275 } 276 277 /* Allocate DMA buffer */ 278 if ((error = bus_dmamem_alloc(dmatag, size, 0, 0, 279 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 280 printf("%s: DMA buffer alloc error %d\n", 281 self->dv_xname, error); 282 return; 283 } 284 285 /* Load the buffer */ 286 if ((error = bus_dmamap_load_raw(dmatag, sc->sc_dmamap, 287 &seg, rseg, size, BUS_DMA_NOWAIT)) != 0) { 288 printf("%s: DMA buffer map load error %d\n", 289 self->dv_xname, error); 290 bus_dmamem_free(dmatag, &seg, rseg); 291 return; 292 } 293 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 294 295 /* Map DMA buffer in CPU addressable space */ 296 if ((error = bus_dmamem_map(dmatag, &seg, rseg, size, 297 &sc->sc_rb.rb_membase, 298 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 299 printf("%s: DMA buffer map error %d\n", 300 self->dv_xname, error); 301 bus_dmamap_unload(dmatag, sc->sc_dmamap); 302 bus_dmamem_free(dmatag, &seg, rseg); 303 return; 304 } 305 306 /* Initialize media properties */ 307 ifmedia_init(&sc->sc_ifmedia, 0, qe_ifmedia_upd, qe_ifmedia_sts); 308 ifmedia_add(&sc->sc_ifmedia, 309 IFM_MAKEWORD(IFM_ETHER,IFM_10_T,0,0), 310 0, NULL); 311 ifmedia_add(&sc->sc_ifmedia, 312 IFM_MAKEWORD(IFM_ETHER,IFM_10_5,0,0), 313 0, NULL); 314 ifmedia_add(&sc->sc_ifmedia, 315 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,0), 316 0, NULL); 317 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO); 318 319 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 320 ifp->if_softc = sc; 321 ifp->if_start = qestart; 322 ifp->if_ioctl = qeioctl; 323 ifp->if_watchdog = qewatchdog; 324 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | 325 IFF_MULTICAST; 326 327 /* Attach the interface. */ 328 if_attach(ifp); 329 ether_ifattach(ifp, sc->sc_enaddr); 330 331 printf(" address %s\n", ether_sprintf(sc->sc_enaddr)); 332 333 #if NBPFILTER > 0 334 bpfattach(&ifp->if_bpf, ifp, DLT_EN10MB, 335 sizeof(struct ether_header)); 336 #endif 337 } 338 339 /* 340 * Pull data off an interface. 341 * Len is the length of data, with local net header stripped. 342 * We copy the data into mbufs. When full cluster sized units are present, 343 * we copy into clusters. 344 */ 345 static __inline__ struct mbuf * 346 qe_get(sc, idx, totlen) 347 struct qe_softc *sc; 348 int idx, totlen; 349 { 350 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 351 struct mbuf *m; 352 struct mbuf *top, **mp; 353 int len, pad, boff = 0; 354 caddr_t bp; 355 356 bp = sc->sc_rb.rb_rxbuf + (idx % sc->sc_rb.rb_nrbuf) * QE_PKT_BUF_SZ; 357 358 MGETHDR(m, M_DONTWAIT, MT_DATA); 359 if (m == NULL) 360 return (NULL); 361 m->m_pkthdr.rcvif = ifp; 362 m->m_pkthdr.len = totlen; 363 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 364 m->m_data += pad; 365 len = MHLEN - pad; 366 top = NULL; 367 mp = ⊤ 368 369 while (totlen > 0) { 370 if (top) { 371 MGET(m, M_DONTWAIT, MT_DATA); 372 if (m == NULL) { 373 m_freem(top); 374 return (NULL); 375 } 376 len = MLEN; 377 } 378 if (top && totlen >= MINCLSIZE) { 379 MCLGET(m, M_DONTWAIT); 380 if (m->m_flags & M_EXT) 381 len = MCLBYTES; 382 } 383 m->m_len = len = min(totlen, len); 384 bcopy(bp + boff, mtod(m, caddr_t), len); 385 boff += len; 386 totlen -= len; 387 *mp = m; 388 mp = &m->m_next; 389 } 390 391 return (top); 392 } 393 394 /* 395 * Routine to copy from mbuf chain to transmit buffer in 396 * network buffer memory. 397 */ 398 __inline__ int 399 qe_put(sc, idx, m) 400 struct qe_softc *sc; 401 int idx; 402 struct mbuf *m; 403 { 404 struct mbuf *n; 405 int len, tlen = 0, boff = 0; 406 caddr_t bp; 407 408 bp = sc->sc_rb.rb_txbuf + (idx % sc->sc_rb.rb_ntbuf) * QE_PKT_BUF_SZ; 409 410 for (; m; m = n) { 411 len = m->m_len; 412 if (len == 0) { 413 MFREE(m, n); 414 continue; 415 } 416 bcopy(mtod(m, caddr_t), bp+boff, len); 417 boff += len; 418 tlen += len; 419 MFREE(m, n); 420 } 421 return (tlen); 422 } 423 424 /* 425 * Pass a packet to the higher levels. 426 */ 427 __inline__ void 428 qe_read(sc, idx, len) 429 struct qe_softc *sc; 430 int idx, len; 431 { 432 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 433 struct mbuf *m; 434 435 if (len <= sizeof(struct ether_header) || 436 len > ETHERMTU + sizeof(struct ether_header)) { 437 438 printf("%s: invalid packet size %d; dropping\n", 439 ifp->if_xname, len); 440 441 ifp->if_ierrors++; 442 return; 443 } 444 445 /* 446 * Pull packet off interface. 447 */ 448 m = qe_get(sc, idx, len); 449 if (m == NULL) { 450 ifp->if_ierrors++; 451 return; 452 } 453 ifp->if_ipackets++; 454 455 #if NBPFILTER > 0 456 /* 457 * Check if there's a BPF listener on this interface. 458 * If so, hand off the raw packet to BPF. 459 */ 460 if (ifp->if_bpf) 461 bpf_mtap(ifp->if_bpf, m); 462 #endif 463 /* Pass the packet up. */ 464 (*ifp->if_input)(ifp, m); 465 } 466 467 /* 468 * Start output on interface. 469 * We make two assumptions here: 470 * 1) that the current priority is set to splnet _before_ this code 471 * is called *and* is returned to the appropriate priority after 472 * return 473 * 2) that the IFF_OACTIVE flag is checked before this code is called 474 * (i.e. that the output part of the interface is idle) 475 */ 476 void 477 qestart(ifp) 478 struct ifnet *ifp; 479 { 480 struct qe_softc *sc = (struct qe_softc *)ifp->if_softc; 481 struct qec_xd *txd = sc->sc_rb.rb_txd; 482 struct mbuf *m; 483 unsigned int bix, len; 484 unsigned int ntbuf = sc->sc_rb.rb_ntbuf; 485 486 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 487 return; 488 489 bix = sc->sc_rb.rb_tdhead; 490 491 for (;;) { 492 IF_DEQUEUE(&ifp->if_snd, m); 493 if (m == 0) 494 break; 495 496 #if NBPFILTER > 0 497 /* 498 * If BPF is listening on this interface, let it see the 499 * packet before we commit it to the wire. 500 */ 501 if (ifp->if_bpf) 502 bpf_mtap(ifp->if_bpf, m); 503 #endif 504 505 /* 506 * Copy the mbuf chain into the transmit buffer. 507 */ 508 len = qe_put(sc, bix, m); 509 510 /* 511 * Initialize transmit registers and start transmission 512 */ 513 txd[bix].xd_flags = QEC_XD_OWN | QEC_XD_SOP | QEC_XD_EOP | 514 (len & QEC_XD_LENGTH); 515 bus_space_write_4(sc->sc_bustag, sc->sc_cr, QE_CRI_CTRL, 516 QE_CR_CTRL_TWAKEUP); 517 518 if (++bix == QEC_XD_RING_MAXSIZE) 519 bix = 0; 520 521 if (++sc->sc_rb.rb_td_nbusy == ntbuf) { 522 ifp->if_flags |= IFF_OACTIVE; 523 break; 524 } 525 } 526 527 sc->sc_rb.rb_tdhead = bix; 528 } 529 530 void 531 qestop(sc) 532 struct qe_softc *sc; 533 { 534 bus_space_tag_t t = sc->sc_bustag; 535 bus_space_handle_t mr = sc->sc_mr; 536 bus_space_handle_t cr = sc->sc_cr; 537 int n; 538 539 #if defined(SUN4U) || defined(__GNUC__) 540 (void)&t; 541 #endif 542 /* Stop the schwurst */ 543 bus_space_write_1(t, mr, QE_MRI_BIUCC, QE_MR_BIUCC_SWRST); 544 for (n = 200; n > 0; n--) { 545 if ((bus_space_read_1(t, mr, QE_MRI_BIUCC) & 546 QE_MR_BIUCC_SWRST) == 0) 547 break; 548 DELAY(20); 549 } 550 551 /* then reset */ 552 bus_space_write_4(t, cr, QE_CRI_CTRL, QE_CR_CTRL_RESET); 553 for (n = 200; n > 0; n--) { 554 if ((bus_space_read_4(t, cr, QE_CRI_CTRL) & 555 QE_CR_CTRL_RESET) == 0) 556 break; 557 DELAY(20); 558 } 559 } 560 561 /* 562 * Reset interface. 563 */ 564 void 565 qereset(sc) 566 struct qe_softc *sc; 567 { 568 int s; 569 570 s = splnet(); 571 qestop(sc); 572 qeinit(sc); 573 splx(s); 574 } 575 576 void 577 qewatchdog(ifp) 578 struct ifnet *ifp; 579 { 580 struct qe_softc *sc = ifp->if_softc; 581 582 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 583 ifp->if_oerrors++; 584 585 qereset(sc); 586 } 587 588 /* 589 * Interrupt dispatch. 590 */ 591 int 592 qeintr(arg) 593 void *arg; 594 { 595 struct qe_softc *sc = (struct qe_softc *)arg; 596 bus_space_tag_t t = sc->sc_bustag; 597 u_int32_t qecstat, qestat; 598 int r = 0; 599 600 #if defined(SUN4U) || defined(__GNUC__) 601 (void)&t; 602 #endif 603 /* Read QEC status and channel status */ 604 qecstat = bus_space_read_4(t, sc->sc_qr, QEC_QRI_STAT); 605 #ifdef QEDEBUG 606 if (sc->sc_debug) { 607 printf("qe%d: intr: qecstat=%x\n", sc->sc_channel, qecstat); 608 } 609 #endif 610 611 /* Filter out status for this channel */ 612 qecstat = qecstat >> (4 * sc->sc_channel); 613 if ((qecstat & 0xf) == 0) 614 return (r); 615 616 qestat = bus_space_read_4(t, sc->sc_cr, QE_CRI_STAT); 617 618 #ifdef QEDEBUG 619 if (sc->sc_debug) { 620 char bits[64]; int i; 621 bus_space_tag_t t = sc->sc_bustag; 622 bus_space_handle_t mr = sc->sc_mr; 623 624 printf("qe%d: intr: qestat=%s\n", sc->sc_channel, 625 bitmask_snprintf(qestat, QE_CR_STAT_BITS, bits, sizeof(bits))); 626 627 printf("MACE registers:\n"); 628 for (i = 0 ; i < 32; i++) { 629 printf(" m[%d]=%x,", i, bus_space_read_1(t, mr, i)); 630 if (((i+1) & 7) == 0) 631 printf("\n"); 632 } 633 } 634 #endif 635 636 if (qestat & QE_CR_STAT_ALLERRORS) { 637 #ifdef QEDEBUG 638 char bits[64]; 639 printf("qe%d: eint: qestat=%s\n", sc->sc_channel, 640 bitmask_snprintf(qestat, QE_CR_STAT_BITS, bits, sizeof(bits))); 641 #endif 642 r |= qe_eint(sc, qestat); 643 if (r == -1) 644 return (1); 645 } 646 647 if (qestat & QE_CR_STAT_TXIRQ) 648 r |= qe_tint(sc); 649 650 if (qestat & QE_CR_STAT_RXIRQ) 651 r |= qe_rint(sc); 652 653 return (r); 654 } 655 656 /* 657 * Transmit interrupt. 658 */ 659 int 660 qe_tint(sc) 661 struct qe_softc *sc; 662 { 663 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 664 unsigned int bix, txflags; 665 666 bix = sc->sc_rb.rb_tdtail; 667 668 for (;;) { 669 if (sc->sc_rb.rb_td_nbusy <= 0) 670 break; 671 672 txflags = sc->sc_rb.rb_txd[bix].xd_flags; 673 674 if (txflags & QEC_XD_OWN) 675 break; 676 677 ifp->if_flags &= ~IFF_OACTIVE; 678 ifp->if_opackets++; 679 680 if (++bix == QEC_XD_RING_MAXSIZE) 681 bix = 0; 682 683 --sc->sc_rb.rb_td_nbusy; 684 } 685 686 sc->sc_rb.rb_tdtail = bix; 687 688 qestart(ifp); 689 690 if (sc->sc_rb.rb_td_nbusy == 0) 691 ifp->if_timer = 0; 692 693 return (1); 694 } 695 696 /* 697 * Receive interrupt. 698 */ 699 int 700 qe_rint(sc) 701 struct qe_softc *sc; 702 { 703 struct qec_xd *xd = sc->sc_rb.rb_rxd; 704 unsigned int bix, len; 705 unsigned int nrbuf = sc->sc_rb.rb_nrbuf; 706 #ifdef QEDEBUG 707 int npackets = 0; 708 #endif 709 710 bix = sc->sc_rb.rb_rdtail; 711 712 /* 713 * Process all buffers with valid data. 714 */ 715 for (;;) { 716 len = xd[bix].xd_flags; 717 if (len & QEC_XD_OWN) 718 break; 719 720 #ifdef QEDEBUG 721 npackets++; 722 #endif 723 724 len &= QEC_XD_LENGTH; 725 len -= 4; 726 qe_read(sc, bix, len); 727 728 /* ... */ 729 xd[(bix+nrbuf) % QEC_XD_RING_MAXSIZE].xd_flags = 730 QEC_XD_OWN | (QE_PKT_BUF_SZ & QEC_XD_LENGTH); 731 732 if (++bix == QEC_XD_RING_MAXSIZE) 733 bix = 0; 734 } 735 #ifdef QEDEBUG 736 if (npackets == 0) 737 printf("%s: rint: no packets; rb index %d; status 0x%x\n", 738 sc->sc_dev.dv_xname, bix, len); 739 #endif 740 741 sc->sc_rb.rb_rdtail = bix; 742 743 return (1); 744 } 745 746 /* 747 * Error interrupt. 748 */ 749 int 750 qe_eint(sc, why) 751 struct qe_softc *sc; 752 u_int32_t why; 753 { 754 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 755 int r = 0, rst = 0; 756 757 if (why & QE_CR_STAT_EDEFER) { 758 printf("%s: excessive tx defers.\n", sc->sc_dev.dv_xname); 759 r |= 1; 760 ifp->if_oerrors++; 761 } 762 763 if (why & QE_CR_STAT_CLOSS) { 764 printf("%s: no carrier, link down?\n", sc->sc_dev.dv_xname); 765 ifp->if_oerrors++; 766 r |= 1; 767 } 768 769 if (why & QE_CR_STAT_ERETRIES) { 770 printf("%s: excessive tx retries\n", sc->sc_dev.dv_xname); 771 ifp->if_oerrors++; 772 r |= 1; 773 rst = 1; 774 } 775 776 777 if (why & QE_CR_STAT_LCOLL) { 778 printf("%s: late tx transmission\n", sc->sc_dev.dv_xname); 779 ifp->if_oerrors++; 780 r |= 1; 781 rst = 1; 782 } 783 784 if (why & QE_CR_STAT_FUFLOW) { 785 printf("%s: tx fifo underflow\n", sc->sc_dev.dv_xname); 786 ifp->if_oerrors++; 787 r |= 1; 788 rst = 1; 789 } 790 791 if (why & QE_CR_STAT_JERROR) { 792 printf("%s: jabber seen\n", sc->sc_dev.dv_xname); 793 r |= 1; 794 } 795 796 if (why & QE_CR_STAT_BERROR) { 797 printf("%s: babble seen\n", sc->sc_dev.dv_xname); 798 r |= 1; 799 } 800 801 if (why & QE_CR_STAT_TCCOFLOW) { 802 ifp->if_collisions += 256; 803 ifp->if_oerrors += 256; 804 r |= 1; 805 } 806 807 if (why & QE_CR_STAT_TXDERROR) { 808 printf("%s: tx descriptor is bad\n", sc->sc_dev.dv_xname); 809 rst = 1; 810 r |= 1; 811 } 812 813 if (why & QE_CR_STAT_TXLERR) { 814 printf("%s: tx late error\n", sc->sc_dev.dv_xname); 815 ifp->if_oerrors++; 816 rst = 1; 817 r |= 1; 818 } 819 820 if (why & QE_CR_STAT_TXPERR) { 821 printf("%s: tx dma parity error\n", sc->sc_dev.dv_xname); 822 ifp->if_oerrors++; 823 rst = 1; 824 r |= 1; 825 } 826 827 if (why & QE_CR_STAT_TXSERR) { 828 printf("%s: tx dma sbus error ack\n", sc->sc_dev.dv_xname); 829 ifp->if_oerrors++; 830 rst = 1; 831 r |= 1; 832 } 833 834 if (why & QE_CR_STAT_RCCOFLOW) { 835 ifp->if_collisions += 256; 836 ifp->if_ierrors += 256; 837 r |= 1; 838 } 839 840 if (why & QE_CR_STAT_RUOFLOW) { 841 ifp->if_ierrors += 256; 842 r |= 1; 843 } 844 845 if (why & QE_CR_STAT_MCOFLOW) { 846 ifp->if_ierrors += 256; 847 r |= 1; 848 } 849 850 if (why & QE_CR_STAT_RXFOFLOW) { 851 printf("%s: rx fifo overflow\n", sc->sc_dev.dv_xname); 852 ifp->if_ierrors++; 853 r |= 1; 854 } 855 856 if (why & QE_CR_STAT_RLCOLL) { 857 printf("%s: rx late collision\n", sc->sc_dev.dv_xname); 858 ifp->if_ierrors++; 859 ifp->if_collisions++; 860 r |= 1; 861 } 862 863 if (why & QE_CR_STAT_FCOFLOW) { 864 ifp->if_ierrors += 256; 865 r |= 1; 866 } 867 868 if (why & QE_CR_STAT_CECOFLOW) { 869 ifp->if_ierrors += 256; 870 r |= 1; 871 } 872 873 if (why & QE_CR_STAT_RXDROP) { 874 printf("%s: rx packet dropped\n", sc->sc_dev.dv_xname); 875 ifp->if_ierrors++; 876 r |= 1; 877 } 878 879 if (why & QE_CR_STAT_RXSMALL) { 880 printf("%s: rx buffer too small\n", sc->sc_dev.dv_xname); 881 ifp->if_ierrors++; 882 r |= 1; 883 rst = 1; 884 } 885 886 if (why & QE_CR_STAT_RXLERR) { 887 printf("%s: rx late error\n", sc->sc_dev.dv_xname); 888 ifp->if_ierrors++; 889 r |= 1; 890 rst = 1; 891 } 892 893 if (why & QE_CR_STAT_RXPERR) { 894 printf("%s: rx dma parity error\n", sc->sc_dev.dv_xname); 895 ifp->if_ierrors++; 896 r |= 1; 897 rst = 1; 898 } 899 900 if (why & QE_CR_STAT_RXSERR) { 901 printf("%s: rx dma sbus error ack\n", sc->sc_dev.dv_xname); 902 ifp->if_ierrors++; 903 r |= 1; 904 rst = 1; 905 } 906 907 if (r == 0) 908 printf("%s: unexpected interrupt error: %08x\n", 909 sc->sc_dev.dv_xname, why); 910 911 if (rst) { 912 printf("%s: resetting...\n", sc->sc_dev.dv_xname); 913 qereset(sc); 914 return (-1); 915 } 916 917 return (r); 918 } 919 920 int 921 qeioctl(ifp, cmd, data) 922 struct ifnet *ifp; 923 u_long cmd; 924 caddr_t data; 925 { 926 struct qe_softc *sc = ifp->if_softc; 927 struct ifaddr *ifa = (struct ifaddr *)data; 928 struct ifreq *ifr = (struct ifreq *)data; 929 int s, error = 0; 930 931 s = splnet(); 932 933 switch (cmd) { 934 case SIOCSIFADDR: 935 ifp->if_flags |= IFF_UP; 936 switch (ifa->ifa_addr->sa_family) { 937 #ifdef INET 938 case AF_INET: 939 qeinit(sc); 940 arp_ifinit(ifp, ifa); 941 break; 942 #endif /* INET */ 943 #ifdef NS 944 case AF_NS: 945 { 946 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 947 948 if (ns_nullhost(*ina)) 949 ina->x_host = 950 *(union ns_host *)LLADDR(ifp->if_sadl); 951 else 952 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 953 sizeof(sc->sc_enaddr)); 954 /* Set new address. */ 955 qeinit(sc); 956 break; 957 } 958 #endif /* NS */ 959 default: 960 qeinit(sc); 961 break; 962 } 963 break; 964 965 case SIOCSIFFLAGS: 966 if ((ifp->if_flags & IFF_UP) == 0 && 967 (ifp->if_flags & IFF_RUNNING) != 0) { 968 /* 969 * If interface is marked down and it is running, then 970 * stop it. 971 */ 972 qestop(sc); 973 ifp->if_flags &= ~IFF_RUNNING; 974 975 } else if ((ifp->if_flags & IFF_UP) != 0 && 976 (ifp->if_flags & IFF_RUNNING) == 0) { 977 /* 978 * If interface is marked up and it is stopped, then 979 * start it. 980 */ 981 qeinit(sc); 982 983 } else { 984 /* 985 * Reset the interface to pick up changes in any other 986 * flags that affect hardware registers. 987 */ 988 qestop(sc); 989 qeinit(sc); 990 } 991 #ifdef QEDEBUG 992 sc->sc_debug = (ifp->if_flags & IFF_DEBUG) != 0 ? 1 : 0; 993 #endif 994 break; 995 996 case SIOCADDMULTI: 997 case SIOCDELMULTI: 998 error = (cmd == SIOCADDMULTI) ? 999 ether_addmulti(ifr, &sc->sc_ethercom): 1000 ether_delmulti(ifr, &sc->sc_ethercom); 1001 1002 if (error == ENETRESET) { 1003 /* 1004 * Multicast list has changed; set the hardware filter 1005 * accordingly. 1006 */ 1007 qe_mcreset(sc); 1008 error = 0; 1009 } 1010 break; 1011 1012 case SIOCGIFMEDIA: 1013 case SIOCSIFMEDIA: 1014 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, cmd); 1015 break; 1016 1017 default: 1018 error = EINVAL; 1019 break; 1020 } 1021 1022 splx(s); 1023 return (error); 1024 } 1025 1026 1027 void 1028 qeinit(sc) 1029 struct qe_softc *sc; 1030 { 1031 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1032 bus_space_tag_t t = sc->sc_bustag; 1033 bus_space_handle_t cr = sc->sc_cr; 1034 bus_space_handle_t mr = sc->sc_mr; 1035 struct qec_softc *qec = sc->sc_qec; 1036 u_int32_t qecaddr; 1037 u_int8_t *ea; 1038 int s; 1039 1040 #if defined(SUN4U) || defined(__GNUC__) 1041 (void)&t; 1042 #endif 1043 s = splimp(); 1044 1045 qestop(sc); 1046 1047 /* 1048 * Allocate descriptor ring and buffers 1049 */ 1050 qec_meminit(&sc->sc_rb, QE_PKT_BUF_SZ); 1051 1052 /* Channel registers: */ 1053 bus_space_write_4(t, cr, QE_CRI_RXDS, (u_int32_t)sc->sc_rb.rb_rxddma); 1054 bus_space_write_4(t, cr, QE_CRI_TXDS, (u_int32_t)sc->sc_rb.rb_txddma); 1055 1056 bus_space_write_4(t, cr, QE_CRI_RIMASK, 0); 1057 bus_space_write_4(t, cr, QE_CRI_TIMASK, 0); 1058 bus_space_write_4(t, cr, QE_CRI_QMASK, 0); 1059 bus_space_write_4(t, cr, QE_CRI_MMASK, QE_CR_MMASK_RXCOLL); 1060 bus_space_write_4(t, cr, QE_CRI_CCNT, 0); 1061 bus_space_write_4(t, cr, QE_CRI_PIPG, 0); 1062 1063 qecaddr = sc->sc_channel * qec->sc_msize; 1064 bus_space_write_4(t, cr, QE_CRI_RXWBUF, qecaddr); 1065 bus_space_write_4(t, cr, QE_CRI_RXRBUF, qecaddr); 1066 bus_space_write_4(t, cr, QE_CRI_TXWBUF, qecaddr + qec->sc_rsize); 1067 bus_space_write_4(t, cr, QE_CRI_TXRBUF, qecaddr + qec->sc_rsize); 1068 1069 /* MACE registers: */ 1070 bus_space_write_1(t, mr, QE_MRI_PHYCC, QE_MR_PHYCC_ASEL); 1071 bus_space_write_1(t, mr, QE_MRI_XMTFC, QE_MR_XMTFC_APADXMT); 1072 bus_space_write_1(t, mr, QE_MRI_RCVFC, 0); 1073 1074 /* 1075 * Mask MACE's receive interrupt, since we're being notified 1076 * by the QEC after DMA completes. 1077 */ 1078 bus_space_write_1(t, mr, QE_MRI_IMR, 1079 QE_MR_IMR_CERRM | QE_MR_IMR_RCVINTM); 1080 1081 bus_space_write_1(t, mr, QE_MRI_BIUCC, 1082 QE_MR_BIUCC_BSWAP | QE_MR_BIUCC_64TS); 1083 1084 bus_space_write_1(t, mr, QE_MRI_FIFOFC, 1085 QE_MR_FIFOCC_TXF16 | QE_MR_FIFOCC_RXF32 | 1086 QE_MR_FIFOCC_RFWU | QE_MR_FIFOCC_TFWU); 1087 1088 bus_space_write_1(t, mr, QE_MRI_PLSCC, QE_MR_PLSCC_TP); 1089 1090 /* 1091 * Station address 1092 */ 1093 ea = sc->sc_enaddr; 1094 bus_space_write_1(t, mr, QE_MRI_IAC, 1095 QE_MR_IAC_ADDRCHG | QE_MR_IAC_PHYADDR); 1096 bus_space_write_multi_1(t, mr, QE_MRI_PADR, ea, 6); 1097 1098 /* Apply media settings */ 1099 qe_ifmedia_upd(ifp); 1100 1101 /* 1102 * Clear Logical address filter 1103 */ 1104 bus_space_write_1(t, mr, QE_MRI_IAC, 1105 QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR); 1106 bus_space_set_multi_1(t, mr, QE_MRI_LADRF, 0, 8); 1107 bus_space_write_1(t, mr, QE_MRI_IAC, 0); 1108 1109 /* Clear missed packet count (register cleared on read) */ 1110 (void)bus_space_read_1(t, mr, QE_MRI_MPC); 1111 1112 #if 0 1113 /* test register: */ 1114 bus_space_write_1(t, mr, QE_MRI_UTR, 0); 1115 #endif 1116 1117 /* Reset multicast filter */ 1118 qe_mcreset(sc); 1119 1120 ifp->if_flags |= IFF_RUNNING; 1121 ifp->if_flags &= ~IFF_OACTIVE; 1122 splx(s); 1123 } 1124 1125 /* 1126 * Reset multicast filter. 1127 */ 1128 void 1129 qe_mcreset(sc) 1130 struct qe_softc *sc; 1131 { 1132 struct ethercom *ec = &sc->sc_ethercom; 1133 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1134 bus_space_tag_t t = sc->sc_bustag; 1135 bus_space_handle_t mr = sc->sc_mr; 1136 struct ether_multi *enm; 1137 struct ether_multistep step; 1138 u_int32_t crc; 1139 u_int16_t hash[4]; 1140 u_int8_t octet, maccc, *ladrp = (u_int8_t *)&hash[0]; 1141 int i, j; 1142 1143 #if defined(SUN4U) || defined(__GNUC__) 1144 (void)&t; 1145 #endif 1146 1147 /* We also enable transmitter & receiver here */ 1148 maccc = QE_MR_MACCC_ENXMT | QE_MR_MACCC_ENRCV; 1149 1150 if (ifp->if_flags & IFF_PROMISC) { 1151 maccc |= QE_MR_MACCC_PROM; 1152 bus_space_write_1(t, mr, QE_MRI_MACCC, maccc); 1153 return; 1154 } 1155 1156 if (ifp->if_flags & IFF_ALLMULTI) { 1157 bus_space_write_1(t, mr, QE_MRI_IAC, 1158 QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR); 1159 bus_space_set_multi_1(t, mr, QE_MRI_LADRF, 0xff, 8); 1160 bus_space_write_1(t, mr, QE_MRI_IAC, 0); 1161 bus_space_write_1(t, mr, QE_MRI_MACCC, maccc); 1162 return; 1163 } 1164 1165 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1166 1167 ETHER_FIRST_MULTI(step, ec, enm); 1168 while (enm != NULL) { 1169 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 1170 ETHER_ADDR_LEN) != 0) { 1171 /* 1172 * We must listen to a range of multicast 1173 * addresses. For now, just accept all 1174 * multicasts, rather than trying to set only 1175 * those filter bits needed to match the range. 1176 * (At this time, the only use of address 1177 * ranges is for IP multicast routing, for 1178 * which the range is big enough to require 1179 * all bits set.) 1180 */ 1181 bus_space_write_1(t, mr, QE_MRI_IAC, 1182 QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR); 1183 bus_space_set_multi_1(t, mr, QE_MRI_LADRF, 0xff, 8); 1184 bus_space_write_1(t, mr, QE_MRI_IAC, 0); 1185 ifp->if_flags |= IFF_ALLMULTI; 1186 break; 1187 } 1188 1189 crc = 0xffffffff; 1190 1191 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1192 octet = enm->enm_addrlo[i]; 1193 1194 for (j = 0; j < 8; j++) { 1195 if ((crc & 1) ^ (octet & 1)) { 1196 crc >>= 1; 1197 crc ^= MC_POLY_LE; 1198 } 1199 else 1200 crc >>= 1; 1201 octet >>= 1; 1202 } 1203 } 1204 1205 crc >>= 26; 1206 hash[crc >> 4] |= 1 << (crc & 0xf); 1207 ETHER_NEXT_MULTI(step, enm); 1208 } 1209 1210 bus_space_write_1(t, mr, QE_MRI_IAC, 1211 QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR); 1212 bus_space_write_multi_1(t, mr, QE_MRI_LADRF, ladrp, 8); 1213 bus_space_write_1(t, mr, QE_MRI_IAC, 0); 1214 bus_space_write_1(t, mr, QE_MRI_MACCC, maccc); 1215 } 1216 1217 /* 1218 * Get current media settings. 1219 */ 1220 void 1221 qe_ifmedia_sts(ifp, ifmr) 1222 struct ifnet *ifp; 1223 struct ifmediareq *ifmr; 1224 { 1225 struct qe_softc *sc = ifp->if_softc; 1226 bus_space_tag_t t = sc->sc_bustag; 1227 bus_space_handle_t mr = sc->sc_mr; 1228 u_int8_t v; 1229 1230 #if defined(SUN4U) || defined(__GNUC__) 1231 (void)&t; 1232 #endif 1233 v = bus_space_read_1(t, mr, QE_MRI_PLSCC); 1234 1235 switch (bus_space_read_1(t, mr, QE_MRI_PLSCC) & QE_MR_PLSCC_PORTMASK) { 1236 case QE_MR_PLSCC_TP: 1237 ifmr->ifm_active = IFM_ETHER | IFM_10_T; 1238 break; 1239 case QE_MR_PLSCC_AUI: 1240 ifmr->ifm_active = IFM_ETHER | IFM_10_5; 1241 break; 1242 case QE_MR_PLSCC_GPSI: 1243 case QE_MR_PLSCC_DAI: 1244 /* ... */ 1245 break; 1246 } 1247 1248 v = bus_space_read_1(t, mr, QE_MRI_PHYCC); 1249 ifmr->ifm_status |= IFM_AVALID; 1250 if ((v & QE_MR_PHYCC_LNKFL) != 0) 1251 ifmr->ifm_status &= ~IFM_ACTIVE; 1252 else 1253 ifmr->ifm_status |= IFM_ACTIVE; 1254 1255 } 1256 1257 /* 1258 * Set media options. 1259 */ 1260 int 1261 qe_ifmedia_upd(ifp) 1262 struct ifnet *ifp; 1263 { 1264 struct qe_softc *sc = ifp->if_softc; 1265 struct ifmedia *ifm = &sc->sc_ifmedia; 1266 bus_space_tag_t t = sc->sc_bustag; 1267 bus_space_handle_t mr = sc->sc_mr; 1268 int newmedia = ifm->ifm_media; 1269 u_int8_t plscc, phycc; 1270 1271 #if defined(SUN4U) || defined(__GNUC__) 1272 (void)&t; 1273 #endif 1274 if (IFM_TYPE(newmedia) != IFM_ETHER) 1275 return (EINVAL); 1276 1277 plscc = bus_space_read_1(t, mr, QE_MRI_PLSCC) & ~QE_MR_PLSCC_PORTMASK; 1278 phycc = bus_space_read_1(t, mr, QE_MRI_PHYCC) & ~QE_MR_PHYCC_ASEL; 1279 1280 if (IFM_SUBTYPE(newmedia) == IFM_AUTO) 1281 phycc |= QE_MR_PHYCC_ASEL; 1282 else if (IFM_SUBTYPE(newmedia) == IFM_10_T) 1283 plscc |= QE_MR_PLSCC_TP; 1284 else if (IFM_SUBTYPE(newmedia) == IFM_10_5) 1285 plscc |= QE_MR_PLSCC_AUI; 1286 1287 bus_space_write_1(t, mr, QE_MRI_PLSCC, plscc); 1288 bus_space_write_1(t, mr, QE_MRI_PHYCC, phycc); 1289 1290 return (0); 1291 } 1292
Indexes created Tue Sep 30 20:09:53 GMT 2025