qe.c revision 1.14
1 /* $NetBSD: qe.c,v 1.14 2001/01/14 17:38:52 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1998 Jason L. Wright. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the authors may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 59 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 63 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 */ 65 66 /* 67 * Driver for the SBus qec+qe QuadEthernet board. 68 * 69 * This driver was written using the AMD MACE Am79C940 documentation, some 70 * ideas gleaned from the S/Linux driver for this card, Solaris header files, 71 * and a loan of a card from Paul Southworth of the Internet Engineering 72 * Group (www.ieng.com). 73 */ 74 75 #define QEDEBUG 76 77 #include "opt_ddb.h" 78 #include "opt_inet.h" 79 #include "opt_ccitt.h" 80 #include "opt_llc.h" 81 #include "opt_ns.h" 82 #include "bpfilter.h" 83 #include "rnd.h" 84 85 #include <sys/param.h> 86 #include <sys/systm.h> 87 #include <sys/kernel.h> 88 #include <sys/errno.h> 89 #include <sys/ioctl.h> 90 #include <sys/mbuf.h> 91 #include <sys/socket.h> 92 #include <sys/syslog.h> 93 #include <sys/device.h> 94 #include <sys/malloc.h> 95 #if NRND > 0 96 #include <sys/rnd.h> 97 #endif 98 99 #include <net/if.h> 100 #include <net/if_dl.h> 101 #include <net/if_types.h> 102 #include <net/netisr.h> 103 #include <net/if_media.h> 104 #include <net/if_ether.h> 105 106 #ifdef INET 107 #include <netinet/in.h> 108 #include <netinet/if_inarp.h> 109 #include <netinet/in_systm.h> 110 #include <netinet/in_var.h> 111 #include <netinet/ip.h> 112 #endif 113 114 #ifdef NS 115 #include <netns/ns.h> 116 #include <netns/ns_if.h> 117 #endif 118 119 #if NBPFILTER > 0 120 #include <net/bpf.h> 121 #include <net/bpfdesc.h> 122 #endif 123 124 #include <machine/bus.h> 125 #include <machine/intr.h> 126 #include <machine/autoconf.h> 127 128 #include <dev/sbus/sbusvar.h> 129 #include <dev/sbus/qecreg.h> 130 #include <dev/sbus/qecvar.h> 131 #include <dev/sbus/qereg.h> 132 133 struct qe_softc { 134 struct device sc_dev; /* base device */ 135 struct sbusdev sc_sd; /* sbus device */ 136 bus_space_tag_t sc_bustag; /* bus & dma tags */ 137 bus_dma_tag_t sc_dmatag; 138 bus_dmamap_t sc_dmamap; 139 struct ethercom sc_ethercom; 140 struct ifmedia sc_ifmedia; /* interface media */ 141 142 struct qec_softc *sc_qec; /* QEC parent */ 143 144 bus_space_handle_t sc_qr; /* QEC registers */ 145 bus_space_handle_t sc_mr; /* MACE registers */ 146 bus_space_handle_t sc_cr; /* channel registers */ 147 148 int sc_channel; /* channel number */ 149 u_int sc_rev; /* board revision */ 150 151 int sc_burst; 152 153 struct qec_ring sc_rb; /* Packet Ring Buffer */ 154 155 /* MAC address */ 156 u_int8_t sc_enaddr[6]; 157 158 #ifdef QEDEBUG 159 int sc_debug; 160 #endif 161 }; 162 163 int qematch __P((struct device *, struct cfdata *, void *)); 164 void qeattach __P((struct device *, struct device *, void *)); 165 166 void qeinit __P((struct qe_softc *)); 167 void qestart __P((struct ifnet *)); 168 void qestop __P((struct qe_softc *)); 169 void qewatchdog __P((struct ifnet *)); 170 int qeioctl __P((struct ifnet *, u_long, caddr_t)); 171 void qereset __P((struct qe_softc *)); 172 173 int qeintr __P((void *)); 174 int qe_eint __P((struct qe_softc *, u_int32_t)); 175 int qe_rint __P((struct qe_softc *)); 176 int qe_tint __P((struct qe_softc *)); 177 void qe_mcreset __P((struct qe_softc *)); 178 179 static int qe_put __P((struct qe_softc *, int, struct mbuf *)); 180 static void qe_read __P((struct qe_softc *, int, int)); 181 static struct mbuf *qe_get __P((struct qe_softc *, int, int)); 182 183 /* ifmedia callbacks */ 184 void qe_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 185 int qe_ifmedia_upd __P((struct ifnet *)); 186 187 struct cfattach qe_ca = { 188 sizeof(struct qe_softc), qematch, qeattach 189 }; 190 191 int 192 qematch(parent, cf, aux) 193 struct device *parent; 194 struct cfdata *cf; 195 void *aux; 196 { 197 struct sbus_attach_args *sa = aux; 198 199 return (strcmp(cf->cf_driver->cd_name, sa->sa_name) == 0); 200 } 201 202 void 203 qeattach(parent, self, aux) 204 struct device *parent, *self; 205 void *aux; 206 { 207 struct sbus_attach_args *sa = aux; 208 struct qec_softc *qec = (struct qec_softc *)parent; 209 struct qe_softc *sc = (struct qe_softc *)self; 210 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 211 int node = sa->sa_node; 212 bus_dma_tag_t dmatag = sa->sa_dmatag; 213 bus_dma_segment_t seg; 214 bus_size_t size; 215 int rseg, error; 216 extern void myetheraddr __P((u_char *)); 217 218 if (sa->sa_nreg < 2) { 219 printf("%s: only %d register sets\n", 220 self->dv_xname, sa->sa_nreg); 221 return; 222 } 223 224 if (bus_space_map2(sa->sa_bustag, 225 (bus_type_t)sa->sa_reg[0].sbr_slot, 226 (bus_addr_t)sa->sa_reg[0].sbr_offset, 227 (bus_size_t)sa->sa_reg[0].sbr_size, 228 BUS_SPACE_MAP_LINEAR, 0, &sc->sc_cr) != 0) { 229 printf("%s: cannot map registers\n", self->dv_xname); 230 return; 231 } 232 233 if (bus_space_map2(sa->sa_bustag, 234 (bus_type_t)sa->sa_reg[1].sbr_slot, 235 (bus_addr_t)sa->sa_reg[1].sbr_offset, 236 (bus_size_t)sa->sa_reg[1].sbr_size, 237 BUS_SPACE_MAP_LINEAR, 0, &sc->sc_mr) != 0) { 238 printf("%s: cannot map registers\n", self->dv_xname); 239 return; 240 } 241 242 sc->sc_rev = getpropint(node, "mace-version", -1); 243 printf(" rev %x", sc->sc_rev); 244 245 sc->sc_qec = qec; 246 sc->sc_qr = qec->sc_regs; 247 248 sc->sc_channel = getpropint(node, "channel#", -1); 249 sc->sc_burst = qec->sc_burst; 250 251 qestop(sc); 252 253 /* Note: no interrupt level passed */ 254 (void)bus_intr_establish(sa->sa_bustag, 0, IPL_NET, 0, qeintr, sc); 255 myetheraddr(sc->sc_enaddr); 256 257 /* 258 * Allocate descriptor ring and buffers. 259 */ 260 261 /* for now, allocate as many bufs as there are ring descriptors */ 262 sc->sc_rb.rb_ntbuf = QEC_XD_RING_MAXSIZE; 263 sc->sc_rb.rb_nrbuf = QEC_XD_RING_MAXSIZE; 264 265 size = QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 266 QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 267 sc->sc_rb.rb_ntbuf * QE_PKT_BUF_SZ + 268 sc->sc_rb.rb_nrbuf * QE_PKT_BUF_SZ; 269 270 /* Get a DMA handle */ 271 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0, 272 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 273 printf("%s: DMA map create error %d\n", self->dv_xname, error); 274 return; 275 } 276 277 /* Allocate DMA buffer */ 278 if ((error = bus_dmamem_alloc(dmatag, size, 0, 0, 279 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 280 printf("%s: DMA buffer alloc error %d\n", 281 self->dv_xname, error); 282 return; 283 } 284 285 /* Load the buffer */ 286 if ((error = bus_dmamap_load_raw(dmatag, sc->sc_dmamap, 287 &seg, rseg, size, BUS_DMA_NOWAIT)) != 0) { 288 printf("%s: DMA buffer map load error %d\n", 289 self->dv_xname, error); 290 bus_dmamem_free(dmatag, &seg, rseg); 291 return; 292 } 293 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 294 295 /* Map DMA buffer in CPU addressable space */ 296 if ((error = bus_dmamem_map(dmatag, &seg, rseg, size, 297 &sc->sc_rb.rb_membase, 298 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 299 printf("%s: DMA buffer map error %d\n", 300 self->dv_xname, error); 301 bus_dmamap_unload(dmatag, sc->sc_dmamap); 302 bus_dmamem_free(dmatag, &seg, rseg); 303 return; 304 } 305 306 /* Initialize media properties */ 307 ifmedia_init(&sc->sc_ifmedia, 0, qe_ifmedia_upd, qe_ifmedia_sts); 308 ifmedia_add(&sc->sc_ifmedia, 309 IFM_MAKEWORD(IFM_ETHER,IFM_10_T,0,0), 310 0, NULL); 311 ifmedia_add(&sc->sc_ifmedia, 312 IFM_MAKEWORD(IFM_ETHER,IFM_10_5,0,0), 313 0, NULL); 314 ifmedia_add(&sc->sc_ifmedia, 315 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,0), 316 0, NULL); 317 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO); 318 319 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 320 ifp->if_softc = sc; 321 ifp->if_start = qestart; 322 ifp->if_ioctl = qeioctl; 323 ifp->if_watchdog = qewatchdog; 324 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | 325 IFF_MULTICAST; 326 IFQ_SET_READY(&ifp->if_snd); 327 328 /* Attach the interface. */ 329 if_attach(ifp); 330 ether_ifattach(ifp, sc->sc_enaddr); 331 332 printf(" address %s\n", ether_sprintf(sc->sc_enaddr)); 333 } 334 335 /* 336 * Pull data off an interface. 337 * Len is the length of data, with local net header stripped. 338 * We copy the data into mbufs. When full cluster sized units are present, 339 * we copy into clusters. 340 */ 341 static __inline__ struct mbuf * 342 qe_get(sc, idx, totlen) 343 struct qe_softc *sc; 344 int idx, totlen; 345 { 346 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 347 struct mbuf *m; 348 struct mbuf *top, **mp; 349 int len, pad, boff = 0; 350 caddr_t bp; 351 352 bp = sc->sc_rb.rb_rxbuf + (idx % sc->sc_rb.rb_nrbuf) * QE_PKT_BUF_SZ; 353 354 MGETHDR(m, M_DONTWAIT, MT_DATA); 355 if (m == NULL) 356 return (NULL); 357 m->m_pkthdr.rcvif = ifp; 358 m->m_pkthdr.len = totlen; 359 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 360 m->m_data += pad; 361 len = MHLEN - pad; 362 top = NULL; 363 mp = ⊤ 364 365 while (totlen > 0) { 366 if (top) { 367 MGET(m, M_DONTWAIT, MT_DATA); 368 if (m == NULL) { 369 m_freem(top); 370 return (NULL); 371 } 372 len = MLEN; 373 } 374 if (top && totlen >= MINCLSIZE) { 375 MCLGET(m, M_DONTWAIT); 376 if (m->m_flags & M_EXT) 377 len = MCLBYTES; 378 } 379 m->m_len = len = min(totlen, len); 380 bcopy(bp + boff, mtod(m, caddr_t), len); 381 boff += len; 382 totlen -= len; 383 *mp = m; 384 mp = &m->m_next; 385 } 386 387 return (top); 388 } 389 390 /* 391 * Routine to copy from mbuf chain to transmit buffer in 392 * network buffer memory. 393 */ 394 __inline__ int 395 qe_put(sc, idx, m) 396 struct qe_softc *sc; 397 int idx; 398 struct mbuf *m; 399 { 400 struct mbuf *n; 401 int len, tlen = 0, boff = 0; 402 caddr_t bp; 403 404 bp = sc->sc_rb.rb_txbuf + (idx % sc->sc_rb.rb_ntbuf) * QE_PKT_BUF_SZ; 405 406 for (; m; m = n) { 407 len = m->m_len; 408 if (len == 0) { 409 MFREE(m, n); 410 continue; 411 } 412 bcopy(mtod(m, caddr_t), bp+boff, len); 413 boff += len; 414 tlen += len; 415 MFREE(m, n); 416 } 417 return (tlen); 418 } 419 420 /* 421 * Pass a packet to the higher levels. 422 */ 423 __inline__ void 424 qe_read(sc, idx, len) 425 struct qe_softc *sc; 426 int idx, len; 427 { 428 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 429 struct mbuf *m; 430 431 if (len <= sizeof(struct ether_header) || 432 len > ETHERMTU + sizeof(struct ether_header)) { 433 434 printf("%s: invalid packet size %d; dropping\n", 435 ifp->if_xname, len); 436 437 ifp->if_ierrors++; 438 return; 439 } 440 441 /* 442 * Pull packet off interface. 443 */ 444 m = qe_get(sc, idx, len); 445 if (m == NULL) { 446 ifp->if_ierrors++; 447 return; 448 } 449 ifp->if_ipackets++; 450 451 #if NBPFILTER > 0 452 /* 453 * Check if there's a BPF listener on this interface. 454 * If so, hand off the raw packet to BPF. 455 */ 456 if (ifp->if_bpf) 457 bpf_mtap(ifp->if_bpf, m); 458 #endif 459 /* Pass the packet up. */ 460 (*ifp->if_input)(ifp, m); 461 } 462 463 /* 464 * Start output on interface. 465 * We make two assumptions here: 466 * 1) that the current priority is set to splnet _before_ this code 467 * is called *and* is returned to the appropriate priority after 468 * return 469 * 2) that the IFF_OACTIVE flag is checked before this code is called 470 * (i.e. that the output part of the interface is idle) 471 */ 472 void 473 qestart(ifp) 474 struct ifnet *ifp; 475 { 476 struct qe_softc *sc = (struct qe_softc *)ifp->if_softc; 477 struct qec_xd *txd = sc->sc_rb.rb_txd; 478 struct mbuf *m; 479 unsigned int bix, len; 480 unsigned int ntbuf = sc->sc_rb.rb_ntbuf; 481 482 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 483 return; 484 485 bix = sc->sc_rb.rb_tdhead; 486 487 for (;;) { 488 IFQ_DEQUEUE(&ifp->if_snd, m); 489 if (m == 0) 490 break; 491 492 #if NBPFILTER > 0 493 /* 494 * If BPF is listening on this interface, let it see the 495 * packet before we commit it to the wire. 496 */ 497 if (ifp->if_bpf) 498 bpf_mtap(ifp->if_bpf, m); 499 #endif 500 501 /* 502 * Copy the mbuf chain into the transmit buffer. 503 */ 504 len = qe_put(sc, bix, m); 505 506 /* 507 * Initialize transmit registers and start transmission 508 */ 509 txd[bix].xd_flags = QEC_XD_OWN | QEC_XD_SOP | QEC_XD_EOP | 510 (len & QEC_XD_LENGTH); 511 bus_space_write_4(sc->sc_bustag, sc->sc_cr, QE_CRI_CTRL, 512 QE_CR_CTRL_TWAKEUP); 513 514 if (++bix == QEC_XD_RING_MAXSIZE) 515 bix = 0; 516 517 if (++sc->sc_rb.rb_td_nbusy == ntbuf) { 518 ifp->if_flags |= IFF_OACTIVE; 519 break; 520 } 521 } 522 523 sc->sc_rb.rb_tdhead = bix; 524 } 525 526 void 527 qestop(sc) 528 struct qe_softc *sc; 529 { 530 bus_space_tag_t t = sc->sc_bustag; 531 bus_space_handle_t mr = sc->sc_mr; 532 bus_space_handle_t cr = sc->sc_cr; 533 int n; 534 535 #if defined(SUN4U) || defined(__GNUC__) 536 (void)&t; 537 #endif 538 /* Stop the schwurst */ 539 bus_space_write_1(t, mr, QE_MRI_BIUCC, QE_MR_BIUCC_SWRST); 540 for (n = 200; n > 0; n--) { 541 if ((bus_space_read_1(t, mr, QE_MRI_BIUCC) & 542 QE_MR_BIUCC_SWRST) == 0) 543 break; 544 DELAY(20); 545 } 546 547 /* then reset */ 548 bus_space_write_4(t, cr, QE_CRI_CTRL, QE_CR_CTRL_RESET); 549 for (n = 200; n > 0; n--) { 550 if ((bus_space_read_4(t, cr, QE_CRI_CTRL) & 551 QE_CR_CTRL_RESET) == 0) 552 break; 553 DELAY(20); 554 } 555 } 556 557 /* 558 * Reset interface. 559 */ 560 void 561 qereset(sc) 562 struct qe_softc *sc; 563 { 564 int s; 565 566 s = splnet(); 567 qestop(sc); 568 qeinit(sc); 569 splx(s); 570 } 571 572 void 573 qewatchdog(ifp) 574 struct ifnet *ifp; 575 { 576 struct qe_softc *sc = ifp->if_softc; 577 578 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 579 ifp->if_oerrors++; 580 581 qereset(sc); 582 } 583 584 /* 585 * Interrupt dispatch. 586 */ 587 int 588 qeintr(arg) 589 void *arg; 590 { 591 struct qe_softc *sc = (struct qe_softc *)arg; 592 bus_space_tag_t t = sc->sc_bustag; 593 u_int32_t qecstat, qestat; 594 int r = 0; 595 596 #if defined(SUN4U) || defined(__GNUC__) 597 (void)&t; 598 #endif 599 /* Read QEC status and channel status */ 600 qecstat = bus_space_read_4(t, sc->sc_qr, QEC_QRI_STAT); 601 #ifdef QEDEBUG 602 if (sc->sc_debug) { 603 printf("qe%d: intr: qecstat=%x\n", sc->sc_channel, qecstat); 604 } 605 #endif 606 607 /* Filter out status for this channel */ 608 qecstat = qecstat >> (4 * sc->sc_channel); 609 if ((qecstat & 0xf) == 0) 610 return (r); 611 612 qestat = bus_space_read_4(t, sc->sc_cr, QE_CRI_STAT); 613 614 #ifdef QEDEBUG 615 if (sc->sc_debug) { 616 char bits[64]; int i; 617 bus_space_tag_t t = sc->sc_bustag; 618 bus_space_handle_t mr = sc->sc_mr; 619 620 printf("qe%d: intr: qestat=%s\n", sc->sc_channel, 621 bitmask_snprintf(qestat, QE_CR_STAT_BITS, bits, sizeof(bits))); 622 623 printf("MACE registers:\n"); 624 for (i = 0 ; i < 32; i++) { 625 printf(" m[%d]=%x,", i, bus_space_read_1(t, mr, i)); 626 if (((i+1) & 7) == 0) 627 printf("\n"); 628 } 629 } 630 #endif 631 632 if (qestat & QE_CR_STAT_ALLERRORS) { 633 #ifdef QEDEBUG 634 char bits[64]; 635 printf("qe%d: eint: qestat=%s\n", sc->sc_channel, 636 bitmask_snprintf(qestat, QE_CR_STAT_BITS, bits, sizeof(bits))); 637 #endif 638 r |= qe_eint(sc, qestat); 639 if (r == -1) 640 return (1); 641 } 642 643 if (qestat & QE_CR_STAT_TXIRQ) 644 r |= qe_tint(sc); 645 646 if (qestat & QE_CR_STAT_RXIRQ) 647 r |= qe_rint(sc); 648 649 return (r); 650 } 651 652 /* 653 * Transmit interrupt. 654 */ 655 int 656 qe_tint(sc) 657 struct qe_softc *sc; 658 { 659 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 660 unsigned int bix, txflags; 661 662 bix = sc->sc_rb.rb_tdtail; 663 664 for (;;) { 665 if (sc->sc_rb.rb_td_nbusy <= 0) 666 break; 667 668 txflags = sc->sc_rb.rb_txd[bix].xd_flags; 669 670 if (txflags & QEC_XD_OWN) 671 break; 672 673 ifp->if_flags &= ~IFF_OACTIVE; 674 ifp->if_opackets++; 675 676 if (++bix == QEC_XD_RING_MAXSIZE) 677 bix = 0; 678 679 --sc->sc_rb.rb_td_nbusy; 680 } 681 682 sc->sc_rb.rb_tdtail = bix; 683 684 qestart(ifp); 685 686 if (sc->sc_rb.rb_td_nbusy == 0) 687 ifp->if_timer = 0; 688 689 return (1); 690 } 691 692 /* 693 * Receive interrupt. 694 */ 695 int 696 qe_rint(sc) 697 struct qe_softc *sc; 698 { 699 struct qec_xd *xd = sc->sc_rb.rb_rxd; 700 unsigned int bix, len; 701 unsigned int nrbuf = sc->sc_rb.rb_nrbuf; 702 #ifdef QEDEBUG 703 int npackets = 0; 704 #endif 705 706 bix = sc->sc_rb.rb_rdtail; 707 708 /* 709 * Process all buffers with valid data. 710 */ 711 for (;;) { 712 len = xd[bix].xd_flags; 713 if (len & QEC_XD_OWN) 714 break; 715 716 #ifdef QEDEBUG 717 npackets++; 718 #endif 719 720 len &= QEC_XD_LENGTH; 721 len -= 4; 722 qe_read(sc, bix, len); 723 724 /* ... */ 725 xd[(bix+nrbuf) % QEC_XD_RING_MAXSIZE].xd_flags = 726 QEC_XD_OWN | (QE_PKT_BUF_SZ & QEC_XD_LENGTH); 727 728 if (++bix == QEC_XD_RING_MAXSIZE) 729 bix = 0; 730 } 731 #ifdef QEDEBUG 732 if (npackets == 0) 733 printf("%s: rint: no packets; rb index %d; status 0x%x\n", 734 sc->sc_dev.dv_xname, bix, len); 735 #endif 736 737 sc->sc_rb.rb_rdtail = bix; 738 739 return (1); 740 } 741 742 /* 743 * Error interrupt. 744 */ 745 int 746 qe_eint(sc, why) 747 struct qe_softc *sc; 748 u_int32_t why; 749 { 750 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 751 int r = 0, rst = 0; 752 753 if (why & QE_CR_STAT_EDEFER) { 754 printf("%s: excessive tx defers.\n", sc->sc_dev.dv_xname); 755 r |= 1; 756 ifp->if_oerrors++; 757 } 758 759 if (why & QE_CR_STAT_CLOSS) { 760 printf("%s: no carrier, link down?\n", sc->sc_dev.dv_xname); 761 ifp->if_oerrors++; 762 r |= 1; 763 } 764 765 if (why & QE_CR_STAT_ERETRIES) { 766 printf("%s: excessive tx retries\n", sc->sc_dev.dv_xname); 767 ifp->if_oerrors++; 768 r |= 1; 769 rst = 1; 770 } 771 772 773 if (why & QE_CR_STAT_LCOLL) { 774 printf("%s: late tx transmission\n", sc->sc_dev.dv_xname); 775 ifp->if_oerrors++; 776 r |= 1; 777 rst = 1; 778 } 779 780 if (why & QE_CR_STAT_FUFLOW) { 781 printf("%s: tx fifo underflow\n", sc->sc_dev.dv_xname); 782 ifp->if_oerrors++; 783 r |= 1; 784 rst = 1; 785 } 786 787 if (why & QE_CR_STAT_JERROR) { 788 printf("%s: jabber seen\n", sc->sc_dev.dv_xname); 789 r |= 1; 790 } 791 792 if (why & QE_CR_STAT_BERROR) { 793 printf("%s: babble seen\n", sc->sc_dev.dv_xname); 794 r |= 1; 795 } 796 797 if (why & QE_CR_STAT_TCCOFLOW) { 798 ifp->if_collisions += 256; 799 ifp->if_oerrors += 256; 800 r |= 1; 801 } 802 803 if (why & QE_CR_STAT_TXDERROR) { 804 printf("%s: tx descriptor is bad\n", sc->sc_dev.dv_xname); 805 rst = 1; 806 r |= 1; 807 } 808 809 if (why & QE_CR_STAT_TXLERR) { 810 printf("%s: tx late error\n", sc->sc_dev.dv_xname); 811 ifp->if_oerrors++; 812 rst = 1; 813 r |= 1; 814 } 815 816 if (why & QE_CR_STAT_TXPERR) { 817 printf("%s: tx dma parity error\n", sc->sc_dev.dv_xname); 818 ifp->if_oerrors++; 819 rst = 1; 820 r |= 1; 821 } 822 823 if (why & QE_CR_STAT_TXSERR) { 824 printf("%s: tx dma sbus error ack\n", sc->sc_dev.dv_xname); 825 ifp->if_oerrors++; 826 rst = 1; 827 r |= 1; 828 } 829 830 if (why & QE_CR_STAT_RCCOFLOW) { 831 ifp->if_collisions += 256; 832 ifp->if_ierrors += 256; 833 r |= 1; 834 } 835 836 if (why & QE_CR_STAT_RUOFLOW) { 837 ifp->if_ierrors += 256; 838 r |= 1; 839 } 840 841 if (why & QE_CR_STAT_MCOFLOW) { 842 ifp->if_ierrors += 256; 843 r |= 1; 844 } 845 846 if (why & QE_CR_STAT_RXFOFLOW) { 847 printf("%s: rx fifo overflow\n", sc->sc_dev.dv_xname); 848 ifp->if_ierrors++; 849 r |= 1; 850 } 851 852 if (why & QE_CR_STAT_RLCOLL) { 853 printf("%s: rx late collision\n", sc->sc_dev.dv_xname); 854 ifp->if_ierrors++; 855 ifp->if_collisions++; 856 r |= 1; 857 } 858 859 if (why & QE_CR_STAT_FCOFLOW) { 860 ifp->if_ierrors += 256; 861 r |= 1; 862 } 863 864 if (why & QE_CR_STAT_CECOFLOW) { 865 ifp->if_ierrors += 256; 866 r |= 1; 867 } 868 869 if (why & QE_CR_STAT_RXDROP) { 870 printf("%s: rx packet dropped\n", sc->sc_dev.dv_xname); 871 ifp->if_ierrors++; 872 r |= 1; 873 } 874 875 if (why & QE_CR_STAT_RXSMALL) { 876 printf("%s: rx buffer too small\n", sc->sc_dev.dv_xname); 877 ifp->if_ierrors++; 878 r |= 1; 879 rst = 1; 880 } 881 882 if (why & QE_CR_STAT_RXLERR) { 883 printf("%s: rx late error\n", sc->sc_dev.dv_xname); 884 ifp->if_ierrors++; 885 r |= 1; 886 rst = 1; 887 } 888 889 if (why & QE_CR_STAT_RXPERR) { 890 printf("%s: rx dma parity error\n", sc->sc_dev.dv_xname); 891 ifp->if_ierrors++; 892 r |= 1; 893 rst = 1; 894 } 895 896 if (why & QE_CR_STAT_RXSERR) { 897 printf("%s: rx dma sbus error ack\n", sc->sc_dev.dv_xname); 898 ifp->if_ierrors++; 899 r |= 1; 900 rst = 1; 901 } 902 903 if (r == 0) 904 printf("%s: unexpected interrupt error: %08x\n", 905 sc->sc_dev.dv_xname, why); 906 907 if (rst) { 908 printf("%s: resetting...\n", sc->sc_dev.dv_xname); 909 qereset(sc); 910 return (-1); 911 } 912 913 return (r); 914 } 915 916 int 917 qeioctl(ifp, cmd, data) 918 struct ifnet *ifp; 919 u_long cmd; 920 caddr_t data; 921 { 922 struct qe_softc *sc = ifp->if_softc; 923 struct ifaddr *ifa = (struct ifaddr *)data; 924 struct ifreq *ifr = (struct ifreq *)data; 925 int s, error = 0; 926 927 s = splnet(); 928 929 switch (cmd) { 930 case SIOCSIFADDR: 931 ifp->if_flags |= IFF_UP; 932 switch (ifa->ifa_addr->sa_family) { 933 #ifdef INET 934 case AF_INET: 935 qeinit(sc); 936 arp_ifinit(ifp, ifa); 937 break; 938 #endif /* INET */ 939 #ifdef NS 940 case AF_NS: 941 { 942 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 943 944 if (ns_nullhost(*ina)) 945 ina->x_host = 946 *(union ns_host *)LLADDR(ifp->if_sadl); 947 else 948 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 949 sizeof(sc->sc_enaddr)); 950 /* Set new address. */ 951 qeinit(sc); 952 break; 953 } 954 #endif /* NS */ 955 default: 956 qeinit(sc); 957 break; 958 } 959 break; 960 961 case SIOCSIFFLAGS: 962 if ((ifp->if_flags & IFF_UP) == 0 && 963 (ifp->if_flags & IFF_RUNNING) != 0) { 964 /* 965 * If interface is marked down and it is running, then 966 * stop it. 967 */ 968 qestop(sc); 969 ifp->if_flags &= ~IFF_RUNNING; 970 971 } else if ((ifp->if_flags & IFF_UP) != 0 && 972 (ifp->if_flags & IFF_RUNNING) == 0) { 973 /* 974 * If interface is marked up and it is stopped, then 975 * start it. 976 */ 977 qeinit(sc); 978 979 } else { 980 /* 981 * Reset the interface to pick up changes in any other 982 * flags that affect hardware registers. 983 */ 984 qestop(sc); 985 qeinit(sc); 986 } 987 #ifdef QEDEBUG 988 sc->sc_debug = (ifp->if_flags & IFF_DEBUG) != 0 ? 1 : 0; 989 #endif 990 break; 991 992 case SIOCADDMULTI: 993 case SIOCDELMULTI: 994 error = (cmd == SIOCADDMULTI) ? 995 ether_addmulti(ifr, &sc->sc_ethercom): 996 ether_delmulti(ifr, &sc->sc_ethercom); 997 998 if (error == ENETRESET) { 999 /* 1000 * Multicast list has changed; set the hardware filter 1001 * accordingly. 1002 */ 1003 qe_mcreset(sc); 1004 error = 0; 1005 } 1006 break; 1007 1008 case SIOCGIFMEDIA: 1009 case SIOCSIFMEDIA: 1010 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, cmd); 1011 break; 1012 1013 default: 1014 error = EINVAL; 1015 break; 1016 } 1017 1018 splx(s); 1019 return (error); 1020 } 1021 1022 1023 void 1024 qeinit(sc) 1025 struct qe_softc *sc; 1026 { 1027 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1028 bus_space_tag_t t = sc->sc_bustag; 1029 bus_space_handle_t cr = sc->sc_cr; 1030 bus_space_handle_t mr = sc->sc_mr; 1031 struct qec_softc *qec = sc->sc_qec; 1032 u_int32_t qecaddr; 1033 u_int8_t *ea; 1034 int s; 1035 1036 #if defined(SUN4U) || defined(__GNUC__) 1037 (void)&t; 1038 #endif 1039 s = splnet(); 1040 1041 qestop(sc); 1042 1043 /* 1044 * Allocate descriptor ring and buffers 1045 */ 1046 qec_meminit(&sc->sc_rb, QE_PKT_BUF_SZ); 1047 1048 /* Channel registers: */ 1049 bus_space_write_4(t, cr, QE_CRI_RXDS, (u_int32_t)sc->sc_rb.rb_rxddma); 1050 bus_space_write_4(t, cr, QE_CRI_TXDS, (u_int32_t)sc->sc_rb.rb_txddma); 1051 1052 bus_space_write_4(t, cr, QE_CRI_RIMASK, 0); 1053 bus_space_write_4(t, cr, QE_CRI_TIMASK, 0); 1054 bus_space_write_4(t, cr, QE_CRI_QMASK, 0); 1055 bus_space_write_4(t, cr, QE_CRI_MMASK, QE_CR_MMASK_RXCOLL); 1056 bus_space_write_4(t, cr, QE_CRI_CCNT, 0); 1057 bus_space_write_4(t, cr, QE_CRI_PIPG, 0); 1058 1059 qecaddr = sc->sc_channel * qec->sc_msize; 1060 bus_space_write_4(t, cr, QE_CRI_RXWBUF, qecaddr); 1061 bus_space_write_4(t, cr, QE_CRI_RXRBUF, qecaddr); 1062 bus_space_write_4(t, cr, QE_CRI_TXWBUF, qecaddr + qec->sc_rsize); 1063 bus_space_write_4(t, cr, QE_CRI_TXRBUF, qecaddr + qec->sc_rsize); 1064 1065 /* MACE registers: */ 1066 bus_space_write_1(t, mr, QE_MRI_PHYCC, QE_MR_PHYCC_ASEL); 1067 bus_space_write_1(t, mr, QE_MRI_XMTFC, QE_MR_XMTFC_APADXMT); 1068 bus_space_write_1(t, mr, QE_MRI_RCVFC, 0); 1069 1070 /* 1071 * Mask MACE's receive interrupt, since we're being notified 1072 * by the QEC after DMA completes. 1073 */ 1074 bus_space_write_1(t, mr, QE_MRI_IMR, 1075 QE_MR_IMR_CERRM | QE_MR_IMR_RCVINTM); 1076 1077 bus_space_write_1(t, mr, QE_MRI_BIUCC, 1078 QE_MR_BIUCC_BSWAP | QE_MR_BIUCC_64TS); 1079 1080 bus_space_write_1(t, mr, QE_MRI_FIFOFC, 1081 QE_MR_FIFOCC_TXF16 | QE_MR_FIFOCC_RXF32 | 1082 QE_MR_FIFOCC_RFWU | QE_MR_FIFOCC_TFWU); 1083 1084 bus_space_write_1(t, mr, QE_MRI_PLSCC, QE_MR_PLSCC_TP); 1085 1086 /* 1087 * Station address 1088 */ 1089 ea = sc->sc_enaddr; 1090 bus_space_write_1(t, mr, QE_MRI_IAC, 1091 QE_MR_IAC_ADDRCHG | QE_MR_IAC_PHYADDR); 1092 bus_space_write_multi_1(t, mr, QE_MRI_PADR, ea, 6); 1093 1094 /* Apply media settings */ 1095 qe_ifmedia_upd(ifp); 1096 1097 /* 1098 * Clear Logical address filter 1099 */ 1100 bus_space_write_1(t, mr, QE_MRI_IAC, 1101 QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR); 1102 bus_space_set_multi_1(t, mr, QE_MRI_LADRF, 0, 8); 1103 bus_space_write_1(t, mr, QE_MRI_IAC, 0); 1104 1105 /* Clear missed packet count (register cleared on read) */ 1106 (void)bus_space_read_1(t, mr, QE_MRI_MPC); 1107 1108 #if 0 1109 /* test register: */ 1110 bus_space_write_1(t, mr, QE_MRI_UTR, 0); 1111 #endif 1112 1113 /* Reset multicast filter */ 1114 qe_mcreset(sc); 1115 1116 ifp->if_flags |= IFF_RUNNING; 1117 ifp->if_flags &= ~IFF_OACTIVE; 1118 splx(s); 1119 } 1120 1121 /* 1122 * Reset multicast filter. 1123 */ 1124 void 1125 qe_mcreset(sc) 1126 struct qe_softc *sc; 1127 { 1128 struct ethercom *ec = &sc->sc_ethercom; 1129 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1130 bus_space_tag_t t = sc->sc_bustag; 1131 bus_space_handle_t mr = sc->sc_mr; 1132 struct ether_multi *enm; 1133 struct ether_multistep step; 1134 u_int32_t crc; 1135 u_int16_t hash[4]; 1136 u_int8_t octet, maccc, *ladrp = (u_int8_t *)&hash[0]; 1137 int i, j; 1138 1139 #if defined(SUN4U) || defined(__GNUC__) 1140 (void)&t; 1141 #endif 1142 1143 /* We also enable transmitter & receiver here */ 1144 maccc = QE_MR_MACCC_ENXMT | QE_MR_MACCC_ENRCV; 1145 1146 if (ifp->if_flags & IFF_PROMISC) { 1147 maccc |= QE_MR_MACCC_PROM; 1148 bus_space_write_1(t, mr, QE_MRI_MACCC, maccc); 1149 return; 1150 } 1151 1152 if (ifp->if_flags & IFF_ALLMULTI) { 1153 bus_space_write_1(t, mr, QE_MRI_IAC, 1154 QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR); 1155 bus_space_set_multi_1(t, mr, QE_MRI_LADRF, 0xff, 8); 1156 bus_space_write_1(t, mr, QE_MRI_IAC, 0); 1157 bus_space_write_1(t, mr, QE_MRI_MACCC, maccc); 1158 return; 1159 } 1160 1161 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1162 1163 ETHER_FIRST_MULTI(step, ec, enm); 1164 while (enm != NULL) { 1165 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 1166 ETHER_ADDR_LEN) != 0) { 1167 /* 1168 * We must listen to a range of multicast 1169 * addresses. For now, just accept all 1170 * multicasts, rather than trying to set only 1171 * those filter bits needed to match the range. 1172 * (At this time, the only use of address 1173 * ranges is for IP multicast routing, for 1174 * which the range is big enough to require 1175 * all bits set.) 1176 */ 1177 bus_space_write_1(t, mr, QE_MRI_IAC, 1178 QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR); 1179 bus_space_set_multi_1(t, mr, QE_MRI_LADRF, 0xff, 8); 1180 bus_space_write_1(t, mr, QE_MRI_IAC, 0); 1181 ifp->if_flags |= IFF_ALLMULTI; 1182 break; 1183 } 1184 1185 crc = 0xffffffff; 1186 1187 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1188 octet = enm->enm_addrlo[i]; 1189 1190 for (j = 0; j < 8; j++) { 1191 if ((crc & 1) ^ (octet & 1)) { 1192 crc >>= 1; 1193 crc ^= MC_POLY_LE; 1194 } 1195 else 1196 crc >>= 1; 1197 octet >>= 1; 1198 } 1199 } 1200 1201 crc >>= 26; 1202 hash[crc >> 4] |= 1 << (crc & 0xf); 1203 ETHER_NEXT_MULTI(step, enm); 1204 } 1205 1206 bus_space_write_1(t, mr, QE_MRI_IAC, 1207 QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR); 1208 bus_space_write_multi_1(t, mr, QE_MRI_LADRF, ladrp, 8); 1209 bus_space_write_1(t, mr, QE_MRI_IAC, 0); 1210 bus_space_write_1(t, mr, QE_MRI_MACCC, maccc); 1211 } 1212 1213 /* 1214 * Get current media settings. 1215 */ 1216 void 1217 qe_ifmedia_sts(ifp, ifmr) 1218 struct ifnet *ifp; 1219 struct ifmediareq *ifmr; 1220 { 1221 struct qe_softc *sc = ifp->if_softc; 1222 bus_space_tag_t t = sc->sc_bustag; 1223 bus_space_handle_t mr = sc->sc_mr; 1224 u_int8_t v; 1225 1226 #if defined(SUN4U) || defined(__GNUC__) 1227 (void)&t; 1228 #endif 1229 v = bus_space_read_1(t, mr, QE_MRI_PLSCC); 1230 1231 switch (bus_space_read_1(t, mr, QE_MRI_PLSCC) & QE_MR_PLSCC_PORTMASK) { 1232 case QE_MR_PLSCC_TP: 1233 ifmr->ifm_active = IFM_ETHER | IFM_10_T; 1234 break; 1235 case QE_MR_PLSCC_AUI: 1236 ifmr->ifm_active = IFM_ETHER | IFM_10_5; 1237 break; 1238 case QE_MR_PLSCC_GPSI: 1239 case QE_MR_PLSCC_DAI: 1240 /* ... */ 1241 break; 1242 } 1243 1244 v = bus_space_read_1(t, mr, QE_MRI_PHYCC); 1245 ifmr->ifm_status |= IFM_AVALID; 1246 if ((v & QE_MR_PHYCC_LNKFL) != 0) 1247 ifmr->ifm_status &= ~IFM_ACTIVE; 1248 else 1249 ifmr->ifm_status |= IFM_ACTIVE; 1250 1251 } 1252 1253 /* 1254 * Set media options. 1255 */ 1256 int 1257 qe_ifmedia_upd(ifp) 1258 struct ifnet *ifp; 1259 { 1260 struct qe_softc *sc = ifp->if_softc; 1261 struct ifmedia *ifm = &sc->sc_ifmedia; 1262 bus_space_tag_t t = sc->sc_bustag; 1263 bus_space_handle_t mr = sc->sc_mr; 1264 int newmedia = ifm->ifm_media; 1265 u_int8_t plscc, phycc; 1266 1267 #if defined(SUN4U) || defined(__GNUC__) 1268 (void)&t; 1269 #endif 1270 if (IFM_TYPE(newmedia) != IFM_ETHER) 1271 return (EINVAL); 1272 1273 plscc = bus_space_read_1(t, mr, QE_MRI_PLSCC) & ~QE_MR_PLSCC_PORTMASK; 1274 phycc = bus_space_read_1(t, mr, QE_MRI_PHYCC) & ~QE_MR_PHYCC_ASEL; 1275 1276 if (IFM_SUBTYPE(newmedia) == IFM_AUTO) 1277 phycc |= QE_MR_PHYCC_ASEL; 1278 else if (IFM_SUBTYPE(newmedia) == IFM_10_T) 1279 plscc |= QE_MR_PLSCC_TP; 1280 else if (IFM_SUBTYPE(newmedia) == IFM_10_5) 1281 plscc |= QE_MR_PLSCC_AUI; 1282 1283 bus_space_write_1(t, mr, QE_MRI_PLSCC, plscc); 1284 bus_space_write_1(t, mr, QE_MRI_PHYCC, phycc); 1285 1286 return (0); 1287 } 1288
Indexes created Tue Sep 30 20:09:53 GMT 2025