qe.c revision 1.15
1 /* $NetBSD: qe.c,v 1.15 2001/03/08 02:20:40 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1998 Jason L. Wright. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the authors may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 59 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 63 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 */ 65 66 /* 67 * Driver for the SBus qec+qe QuadEthernet board. 68 * 69 * This driver was written using the AMD MACE Am79C940 documentation, some 70 * ideas gleaned from the S/Linux driver for this card, Solaris header files, 71 * and a loan of a card from Paul Southworth of the Internet Engineering 72 * Group (www.ieng.com). 73 */ 74 75 #define QEDEBUG 76 77 #include "opt_ddb.h" 78 #include "opt_inet.h" 79 #include "opt_ccitt.h" 80 #include "opt_llc.h" 81 #include "opt_ns.h" 82 #include "bpfilter.h" 83 #include "rnd.h" 84 85 #include <sys/param.h> 86 #include <sys/systm.h> 87 #include <sys/kernel.h> 88 #include <sys/errno.h> 89 #include <sys/ioctl.h> 90 #include <sys/mbuf.h> 91 #include <sys/socket.h> 92 #include <sys/syslog.h> 93 #include <sys/device.h> 94 #include <sys/malloc.h> 95 #if NRND > 0 96 #include <sys/rnd.h> 97 #endif 98 99 #include <net/if.h> 100 #include <net/if_dl.h> 101 #include <net/if_types.h> 102 #include <net/netisr.h> 103 #include <net/if_media.h> 104 #include <net/if_ether.h> 105 106 #ifdef INET 107 #include <netinet/in.h> 108 #include <netinet/if_inarp.h> 109 #include <netinet/in_systm.h> 110 #include <netinet/in_var.h> 111 #include <netinet/ip.h> 112 #endif 113 114 #ifdef NS 115 #include <netns/ns.h> 116 #include <netns/ns_if.h> 117 #endif 118 119 #if NBPFILTER > 0 120 #include <net/bpf.h> 121 #include <net/bpfdesc.h> 122 #endif 123 124 #include <machine/bus.h> 125 #include <machine/intr.h> 126 #include <machine/autoconf.h> 127 128 #include <dev/sbus/sbusvar.h> 129 #include <dev/sbus/qecreg.h> 130 #include <dev/sbus/qecvar.h> 131 #include <dev/sbus/qereg.h> 132 133 struct qe_softc { 134 struct device sc_dev; /* base device */ 135 struct sbusdev sc_sd; /* sbus device */ 136 bus_space_tag_t sc_bustag; /* bus & dma tags */ 137 bus_dma_tag_t sc_dmatag; 138 bus_dmamap_t sc_dmamap; 139 struct ethercom sc_ethercom; 140 struct ifmedia sc_ifmedia; /* interface media */ 141 142 struct qec_softc *sc_qec; /* QEC parent */ 143 144 bus_space_handle_t sc_qr; /* QEC registers */ 145 bus_space_handle_t sc_mr; /* MACE registers */ 146 bus_space_handle_t sc_cr; /* channel registers */ 147 148 int sc_channel; /* channel number */ 149 u_int sc_rev; /* board revision */ 150 151 int sc_burst; 152 153 struct qec_ring sc_rb; /* Packet Ring Buffer */ 154 155 /* MAC address */ 156 u_int8_t sc_enaddr[6]; 157 158 #ifdef QEDEBUG 159 int sc_debug; 160 #endif 161 }; 162 163 int qematch __P((struct device *, struct cfdata *, void *)); 164 void qeattach __P((struct device *, struct device *, void *)); 165 166 void qeinit __P((struct qe_softc *)); 167 void qestart __P((struct ifnet *)); 168 void qestop __P((struct qe_softc *)); 169 void qewatchdog __P((struct ifnet *)); 170 int qeioctl __P((struct ifnet *, u_long, caddr_t)); 171 void qereset __P((struct qe_softc *)); 172 173 int qeintr __P((void *)); 174 int qe_eint __P((struct qe_softc *, u_int32_t)); 175 int qe_rint __P((struct qe_softc *)); 176 int qe_tint __P((struct qe_softc *)); 177 void qe_mcreset __P((struct qe_softc *)); 178 179 static int qe_put __P((struct qe_softc *, int, struct mbuf *)); 180 static void qe_read __P((struct qe_softc *, int, int)); 181 static struct mbuf *qe_get __P((struct qe_softc *, int, int)); 182 183 /* ifmedia callbacks */ 184 void qe_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 185 int qe_ifmedia_upd __P((struct ifnet *)); 186 187 struct cfattach qe_ca = { 188 sizeof(struct qe_softc), qematch, qeattach 189 }; 190 191 int 192 qematch(parent, cf, aux) 193 struct device *parent; 194 struct cfdata *cf; 195 void *aux; 196 { 197 struct sbus_attach_args *sa = aux; 198 199 return (strcmp(cf->cf_driver->cd_name, sa->sa_name) == 0); 200 } 201 202 void 203 qeattach(parent, self, aux) 204 struct device *parent, *self; 205 void *aux; 206 { 207 struct sbus_attach_args *sa = aux; 208 struct qec_softc *qec = (struct qec_softc *)parent; 209 struct qe_softc *sc = (struct qe_softc *)self; 210 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 211 int node = sa->sa_node; 212 bus_dma_tag_t dmatag = sa->sa_dmatag; 213 bus_dma_segment_t seg; 214 bus_size_t size; 215 int rseg, error; 216 extern void myetheraddr __P((u_char *)); 217 218 if (sa->sa_nreg < 2) { 219 printf("%s: only %d register sets\n", 220 self->dv_xname, sa->sa_nreg); 221 return; 222 } 223 224 if (bus_space_map2(sa->sa_bustag, 225 (bus_type_t)sa->sa_reg[0].sbr_slot, 226 (bus_addr_t)sa->sa_reg[0].sbr_offset, 227 (bus_size_t)sa->sa_reg[0].sbr_size, 228 BUS_SPACE_MAP_LINEAR, 0, &sc->sc_cr) != 0) { 229 printf("%s: cannot map registers\n", self->dv_xname); 230 return; 231 } 232 233 if (bus_space_map2(sa->sa_bustag, 234 (bus_type_t)sa->sa_reg[1].sbr_slot, 235 (bus_addr_t)sa->sa_reg[1].sbr_offset, 236 (bus_size_t)sa->sa_reg[1].sbr_size, 237 BUS_SPACE_MAP_LINEAR, 0, &sc->sc_mr) != 0) { 238 printf("%s: cannot map registers\n", self->dv_xname); 239 return; 240 } 241 242 sc->sc_rev = getpropint(node, "mace-version", -1); 243 printf(" rev %x", sc->sc_rev); 244 245 sc->sc_qec = qec; 246 sc->sc_qr = qec->sc_regs; 247 248 sc->sc_channel = getpropint(node, "channel#", -1); 249 sc->sc_burst = qec->sc_burst; 250 251 qestop(sc); 252 253 /* Note: no interrupt level passed */ 254 (void)bus_intr_establish(sa->sa_bustag, 0, IPL_NET, 0, qeintr, sc); 255 myetheraddr(sc->sc_enaddr); 256 257 /* 258 * Allocate descriptor ring and buffers. 259 */ 260 261 /* for now, allocate as many bufs as there are ring descriptors */ 262 sc->sc_rb.rb_ntbuf = QEC_XD_RING_MAXSIZE; 263 sc->sc_rb.rb_nrbuf = QEC_XD_RING_MAXSIZE; 264 265 size = QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 266 QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 267 sc->sc_rb.rb_ntbuf * QE_PKT_BUF_SZ + 268 sc->sc_rb.rb_nrbuf * QE_PKT_BUF_SZ; 269 270 /* Get a DMA handle */ 271 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0, 272 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 273 printf("%s: DMA map create error %d\n", self->dv_xname, error); 274 return; 275 } 276 277 /* Allocate DMA buffer */ 278 if ((error = bus_dmamem_alloc(dmatag, size, 0, 0, 279 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 280 printf("%s: DMA buffer alloc error %d\n", 281 self->dv_xname, error); 282 return; 283 } 284 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 285 286 /* Map DMA buffer in CPU addressable space */ 287 if ((error = bus_dmamem_map(dmatag, &seg, rseg, size, 288 &sc->sc_rb.rb_membase, 289 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 290 printf("%s: DMA buffer map error %d\n", 291 self->dv_xname, error); 292 bus_dmamem_free(dmatag, &seg, rseg); 293 return; 294 } 295 296 /* Load the buffer */ 297 if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap, 298 sc->sc_rb.rb_membase, size, NULL, 299 BUS_DMA_NOWAIT)) != 0) { 300 printf("%s: DMA buffer map load error %d\n", 301 self->dv_xname, error); 302 bus_dmamem_unmap(dmatag, sc->sc_rb.rb_membase, size); 303 bus_dmamem_free(dmatag, &seg, rseg); 304 return; 305 } 306 307 /* Initialize media properties */ 308 ifmedia_init(&sc->sc_ifmedia, 0, qe_ifmedia_upd, qe_ifmedia_sts); 309 ifmedia_add(&sc->sc_ifmedia, 310 IFM_MAKEWORD(IFM_ETHER,IFM_10_T,0,0), 311 0, NULL); 312 ifmedia_add(&sc->sc_ifmedia, 313 IFM_MAKEWORD(IFM_ETHER,IFM_10_5,0,0), 314 0, NULL); 315 ifmedia_add(&sc->sc_ifmedia, 316 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,0), 317 0, NULL); 318 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO); 319 320 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 321 ifp->if_softc = sc; 322 ifp->if_start = qestart; 323 ifp->if_ioctl = qeioctl; 324 ifp->if_watchdog = qewatchdog; 325 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | 326 IFF_MULTICAST; 327 IFQ_SET_READY(&ifp->if_snd); 328 329 /* Attach the interface. */ 330 if_attach(ifp); 331 ether_ifattach(ifp, sc->sc_enaddr); 332 333 printf(" address %s\n", ether_sprintf(sc->sc_enaddr)); 334 } 335 336 /* 337 * Pull data off an interface. 338 * Len is the length of data, with local net header stripped. 339 * We copy the data into mbufs. When full cluster sized units are present, 340 * we copy into clusters. 341 */ 342 static __inline__ struct mbuf * 343 qe_get(sc, idx, totlen) 344 struct qe_softc *sc; 345 int idx, totlen; 346 { 347 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 348 struct mbuf *m; 349 struct mbuf *top, **mp; 350 int len, pad, boff = 0; 351 caddr_t bp; 352 353 bp = sc->sc_rb.rb_rxbuf + (idx % sc->sc_rb.rb_nrbuf) * QE_PKT_BUF_SZ; 354 355 MGETHDR(m, M_DONTWAIT, MT_DATA); 356 if (m == NULL) 357 return (NULL); 358 m->m_pkthdr.rcvif = ifp; 359 m->m_pkthdr.len = totlen; 360 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 361 m->m_data += pad; 362 len = MHLEN - pad; 363 top = NULL; 364 mp = ⊤ 365 366 while (totlen > 0) { 367 if (top) { 368 MGET(m, M_DONTWAIT, MT_DATA); 369 if (m == NULL) { 370 m_freem(top); 371 return (NULL); 372 } 373 len = MLEN; 374 } 375 if (top && totlen >= MINCLSIZE) { 376 MCLGET(m, M_DONTWAIT); 377 if (m->m_flags & M_EXT) 378 len = MCLBYTES; 379 } 380 m->m_len = len = min(totlen, len); 381 bcopy(bp + boff, mtod(m, caddr_t), len); 382 boff += len; 383 totlen -= len; 384 *mp = m; 385 mp = &m->m_next; 386 } 387 388 return (top); 389 } 390 391 /* 392 * Routine to copy from mbuf chain to transmit buffer in 393 * network buffer memory. 394 */ 395 __inline__ int 396 qe_put(sc, idx, m) 397 struct qe_softc *sc; 398 int idx; 399 struct mbuf *m; 400 { 401 struct mbuf *n; 402 int len, tlen = 0, boff = 0; 403 caddr_t bp; 404 405 bp = sc->sc_rb.rb_txbuf + (idx % sc->sc_rb.rb_ntbuf) * QE_PKT_BUF_SZ; 406 407 for (; m; m = n) { 408 len = m->m_len; 409 if (len == 0) { 410 MFREE(m, n); 411 continue; 412 } 413 bcopy(mtod(m, caddr_t), bp+boff, len); 414 boff += len; 415 tlen += len; 416 MFREE(m, n); 417 } 418 return (tlen); 419 } 420 421 /* 422 * Pass a packet to the higher levels. 423 */ 424 __inline__ void 425 qe_read(sc, idx, len) 426 struct qe_softc *sc; 427 int idx, len; 428 { 429 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 430 struct mbuf *m; 431 432 if (len <= sizeof(struct ether_header) || 433 len > ETHERMTU + sizeof(struct ether_header)) { 434 435 printf("%s: invalid packet size %d; dropping\n", 436 ifp->if_xname, len); 437 438 ifp->if_ierrors++; 439 return; 440 } 441 442 /* 443 * Pull packet off interface. 444 */ 445 m = qe_get(sc, idx, len); 446 if (m == NULL) { 447 ifp->if_ierrors++; 448 return; 449 } 450 ifp->if_ipackets++; 451 452 #if NBPFILTER > 0 453 /* 454 * Check if there's a BPF listener on this interface. 455 * If so, hand off the raw packet to BPF. 456 */ 457 if (ifp->if_bpf) 458 bpf_mtap(ifp->if_bpf, m); 459 #endif 460 /* Pass the packet up. */ 461 (*ifp->if_input)(ifp, m); 462 } 463 464 /* 465 * Start output on interface. 466 * We make two assumptions here: 467 * 1) that the current priority is set to splnet _before_ this code 468 * is called *and* is returned to the appropriate priority after 469 * return 470 * 2) that the IFF_OACTIVE flag is checked before this code is called 471 * (i.e. that the output part of the interface is idle) 472 */ 473 void 474 qestart(ifp) 475 struct ifnet *ifp; 476 { 477 struct qe_softc *sc = (struct qe_softc *)ifp->if_softc; 478 struct qec_xd *txd = sc->sc_rb.rb_txd; 479 struct mbuf *m; 480 unsigned int bix, len; 481 unsigned int ntbuf = sc->sc_rb.rb_ntbuf; 482 483 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 484 return; 485 486 bix = sc->sc_rb.rb_tdhead; 487 488 for (;;) { 489 IFQ_DEQUEUE(&ifp->if_snd, m); 490 if (m == 0) 491 break; 492 493 #if NBPFILTER > 0 494 /* 495 * If BPF is listening on this interface, let it see the 496 * packet before we commit it to the wire. 497 */ 498 if (ifp->if_bpf) 499 bpf_mtap(ifp->if_bpf, m); 500 #endif 501 502 /* 503 * Copy the mbuf chain into the transmit buffer. 504 */ 505 len = qe_put(sc, bix, m); 506 507 /* 508 * Initialize transmit registers and start transmission 509 */ 510 txd[bix].xd_flags = QEC_XD_OWN | QEC_XD_SOP | QEC_XD_EOP | 511 (len & QEC_XD_LENGTH); 512 bus_space_write_4(sc->sc_bustag, sc->sc_cr, QE_CRI_CTRL, 513 QE_CR_CTRL_TWAKEUP); 514 515 if (++bix == QEC_XD_RING_MAXSIZE) 516 bix = 0; 517 518 if (++sc->sc_rb.rb_td_nbusy == ntbuf) { 519 ifp->if_flags |= IFF_OACTIVE; 520 break; 521 } 522 } 523 524 sc->sc_rb.rb_tdhead = bix; 525 } 526 527 void 528 qestop(sc) 529 struct qe_softc *sc; 530 { 531 bus_space_tag_t t = sc->sc_bustag; 532 bus_space_handle_t mr = sc->sc_mr; 533 bus_space_handle_t cr = sc->sc_cr; 534 int n; 535 536 #if defined(SUN4U) || defined(__GNUC__) 537 (void)&t; 538 #endif 539 /* Stop the schwurst */ 540 bus_space_write_1(t, mr, QE_MRI_BIUCC, QE_MR_BIUCC_SWRST); 541 for (n = 200; n > 0; n--) { 542 if ((bus_space_read_1(t, mr, QE_MRI_BIUCC) & 543 QE_MR_BIUCC_SWRST) == 0) 544 break; 545 DELAY(20); 546 } 547 548 /* then reset */ 549 bus_space_write_4(t, cr, QE_CRI_CTRL, QE_CR_CTRL_RESET); 550 for (n = 200; n > 0; n--) { 551 if ((bus_space_read_4(t, cr, QE_CRI_CTRL) & 552 QE_CR_CTRL_RESET) == 0) 553 break; 554 DELAY(20); 555 } 556 } 557 558 /* 559 * Reset interface. 560 */ 561 void 562 qereset(sc) 563 struct qe_softc *sc; 564 { 565 int s; 566 567 s = splnet(); 568 qestop(sc); 569 qeinit(sc); 570 splx(s); 571 } 572 573 void 574 qewatchdog(ifp) 575 struct ifnet *ifp; 576 { 577 struct qe_softc *sc = ifp->if_softc; 578 579 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 580 ifp->if_oerrors++; 581 582 qereset(sc); 583 } 584 585 /* 586 * Interrupt dispatch. 587 */ 588 int 589 qeintr(arg) 590 void *arg; 591 { 592 struct qe_softc *sc = (struct qe_softc *)arg; 593 bus_space_tag_t t = sc->sc_bustag; 594 u_int32_t qecstat, qestat; 595 int r = 0; 596 597 #if defined(SUN4U) || defined(__GNUC__) 598 (void)&t; 599 #endif 600 /* Read QEC status and channel status */ 601 qecstat = bus_space_read_4(t, sc->sc_qr, QEC_QRI_STAT); 602 #ifdef QEDEBUG 603 if (sc->sc_debug) { 604 printf("qe%d: intr: qecstat=%x\n", sc->sc_channel, qecstat); 605 } 606 #endif 607 608 /* Filter out status for this channel */ 609 qecstat = qecstat >> (4 * sc->sc_channel); 610 if ((qecstat & 0xf) == 0) 611 return (r); 612 613 qestat = bus_space_read_4(t, sc->sc_cr, QE_CRI_STAT); 614 615 #ifdef QEDEBUG 616 if (sc->sc_debug) { 617 char bits[64]; int i; 618 bus_space_tag_t t = sc->sc_bustag; 619 bus_space_handle_t mr = sc->sc_mr; 620 621 printf("qe%d: intr: qestat=%s\n", sc->sc_channel, 622 bitmask_snprintf(qestat, QE_CR_STAT_BITS, bits, sizeof(bits))); 623 624 printf("MACE registers:\n"); 625 for (i = 0 ; i < 32; i++) { 626 printf(" m[%d]=%x,", i, bus_space_read_1(t, mr, i)); 627 if (((i+1) & 7) == 0) 628 printf("\n"); 629 } 630 } 631 #endif 632 633 if (qestat & QE_CR_STAT_ALLERRORS) { 634 #ifdef QEDEBUG 635 char bits[64]; 636 printf("qe%d: eint: qestat=%s\n", sc->sc_channel, 637 bitmask_snprintf(qestat, QE_CR_STAT_BITS, bits, sizeof(bits))); 638 #endif 639 r |= qe_eint(sc, qestat); 640 if (r == -1) 641 return (1); 642 } 643 644 if (qestat & QE_CR_STAT_TXIRQ) 645 r |= qe_tint(sc); 646 647 if (qestat & QE_CR_STAT_RXIRQ) 648 r |= qe_rint(sc); 649 650 return (r); 651 } 652 653 /* 654 * Transmit interrupt. 655 */ 656 int 657 qe_tint(sc) 658 struct qe_softc *sc; 659 { 660 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 661 unsigned int bix, txflags; 662 663 bix = sc->sc_rb.rb_tdtail; 664 665 for (;;) { 666 if (sc->sc_rb.rb_td_nbusy <= 0) 667 break; 668 669 txflags = sc->sc_rb.rb_txd[bix].xd_flags; 670 671 if (txflags & QEC_XD_OWN) 672 break; 673 674 ifp->if_flags &= ~IFF_OACTIVE; 675 ifp->if_opackets++; 676 677 if (++bix == QEC_XD_RING_MAXSIZE) 678 bix = 0; 679 680 --sc->sc_rb.rb_td_nbusy; 681 } 682 683 sc->sc_rb.rb_tdtail = bix; 684 685 qestart(ifp); 686 687 if (sc->sc_rb.rb_td_nbusy == 0) 688 ifp->if_timer = 0; 689 690 return (1); 691 } 692 693 /* 694 * Receive interrupt. 695 */ 696 int 697 qe_rint(sc) 698 struct qe_softc *sc; 699 { 700 struct qec_xd *xd = sc->sc_rb.rb_rxd; 701 unsigned int bix, len; 702 unsigned int nrbuf = sc->sc_rb.rb_nrbuf; 703 #ifdef QEDEBUG 704 int npackets = 0; 705 #endif 706 707 bix = sc->sc_rb.rb_rdtail; 708 709 /* 710 * Process all buffers with valid data. 711 */ 712 for (;;) { 713 len = xd[bix].xd_flags; 714 if (len & QEC_XD_OWN) 715 break; 716 717 #ifdef QEDEBUG 718 npackets++; 719 #endif 720 721 len &= QEC_XD_LENGTH; 722 len -= 4; 723 qe_read(sc, bix, len); 724 725 /* ... */ 726 xd[(bix+nrbuf) % QEC_XD_RING_MAXSIZE].xd_flags = 727 QEC_XD_OWN | (QE_PKT_BUF_SZ & QEC_XD_LENGTH); 728 729 if (++bix == QEC_XD_RING_MAXSIZE) 730 bix = 0; 731 } 732 #ifdef QEDEBUG 733 if (npackets == 0) 734 printf("%s: rint: no packets; rb index %d; status 0x%x\n", 735 sc->sc_dev.dv_xname, bix, len); 736 #endif 737 738 sc->sc_rb.rb_rdtail = bix; 739 740 return (1); 741 } 742 743 /* 744 * Error interrupt. 745 */ 746 int 747 qe_eint(sc, why) 748 struct qe_softc *sc; 749 u_int32_t why; 750 { 751 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 752 int r = 0, rst = 0; 753 754 if (why & QE_CR_STAT_EDEFER) { 755 printf("%s: excessive tx defers.\n", sc->sc_dev.dv_xname); 756 r |= 1; 757 ifp->if_oerrors++; 758 } 759 760 if (why & QE_CR_STAT_CLOSS) { 761 printf("%s: no carrier, link down?\n", sc->sc_dev.dv_xname); 762 ifp->if_oerrors++; 763 r |= 1; 764 } 765 766 if (why & QE_CR_STAT_ERETRIES) { 767 printf("%s: excessive tx retries\n", sc->sc_dev.dv_xname); 768 ifp->if_oerrors++; 769 r |= 1; 770 rst = 1; 771 } 772 773 774 if (why & QE_CR_STAT_LCOLL) { 775 printf("%s: late tx transmission\n", sc->sc_dev.dv_xname); 776 ifp->if_oerrors++; 777 r |= 1; 778 rst = 1; 779 } 780 781 if (why & QE_CR_STAT_FUFLOW) { 782 printf("%s: tx fifo underflow\n", sc->sc_dev.dv_xname); 783 ifp->if_oerrors++; 784 r |= 1; 785 rst = 1; 786 } 787 788 if (why & QE_CR_STAT_JERROR) { 789 printf("%s: jabber seen\n", sc->sc_dev.dv_xname); 790 r |= 1; 791 } 792 793 if (why & QE_CR_STAT_BERROR) { 794 printf("%s: babble seen\n", sc->sc_dev.dv_xname); 795 r |= 1; 796 } 797 798 if (why & QE_CR_STAT_TCCOFLOW) { 799 ifp->if_collisions += 256; 800 ifp->if_oerrors += 256; 801 r |= 1; 802 } 803 804 if (why & QE_CR_STAT_TXDERROR) { 805 printf("%s: tx descriptor is bad\n", sc->sc_dev.dv_xname); 806 rst = 1; 807 r |= 1; 808 } 809 810 if (why & QE_CR_STAT_TXLERR) { 811 printf("%s: tx late error\n", sc->sc_dev.dv_xname); 812 ifp->if_oerrors++; 813 rst = 1; 814 r |= 1; 815 } 816 817 if (why & QE_CR_STAT_TXPERR) { 818 printf("%s: tx dma parity error\n", sc->sc_dev.dv_xname); 819 ifp->if_oerrors++; 820 rst = 1; 821 r |= 1; 822 } 823 824 if (why & QE_CR_STAT_TXSERR) { 825 printf("%s: tx dma sbus error ack\n", sc->sc_dev.dv_xname); 826 ifp->if_oerrors++; 827 rst = 1; 828 r |= 1; 829 } 830 831 if (why & QE_CR_STAT_RCCOFLOW) { 832 ifp->if_collisions += 256; 833 ifp->if_ierrors += 256; 834 r |= 1; 835 } 836 837 if (why & QE_CR_STAT_RUOFLOW) { 838 ifp->if_ierrors += 256; 839 r |= 1; 840 } 841 842 if (why & QE_CR_STAT_MCOFLOW) { 843 ifp->if_ierrors += 256; 844 r |= 1; 845 } 846 847 if (why & QE_CR_STAT_RXFOFLOW) { 848 printf("%s: rx fifo overflow\n", sc->sc_dev.dv_xname); 849 ifp->if_ierrors++; 850 r |= 1; 851 } 852 853 if (why & QE_CR_STAT_RLCOLL) { 854 printf("%s: rx late collision\n", sc->sc_dev.dv_xname); 855 ifp->if_ierrors++; 856 ifp->if_collisions++; 857 r |= 1; 858 } 859 860 if (why & QE_CR_STAT_FCOFLOW) { 861 ifp->if_ierrors += 256; 862 r |= 1; 863 } 864 865 if (why & QE_CR_STAT_CECOFLOW) { 866 ifp->if_ierrors += 256; 867 r |= 1; 868 } 869 870 if (why & QE_CR_STAT_RXDROP) { 871 printf("%s: rx packet dropped\n", sc->sc_dev.dv_xname); 872 ifp->if_ierrors++; 873 r |= 1; 874 } 875 876 if (why & QE_CR_STAT_RXSMALL) { 877 printf("%s: rx buffer too small\n", sc->sc_dev.dv_xname); 878 ifp->if_ierrors++; 879 r |= 1; 880 rst = 1; 881 } 882 883 if (why & QE_CR_STAT_RXLERR) { 884 printf("%s: rx late error\n", sc->sc_dev.dv_xname); 885 ifp->if_ierrors++; 886 r |= 1; 887 rst = 1; 888 } 889 890 if (why & QE_CR_STAT_RXPERR) { 891 printf("%s: rx dma parity error\n", sc->sc_dev.dv_xname); 892 ifp->if_ierrors++; 893 r |= 1; 894 rst = 1; 895 } 896 897 if (why & QE_CR_STAT_RXSERR) { 898 printf("%s: rx dma sbus error ack\n", sc->sc_dev.dv_xname); 899 ifp->if_ierrors++; 900 r |= 1; 901 rst = 1; 902 } 903 904 if (r == 0) 905 printf("%s: unexpected interrupt error: %08x\n", 906 sc->sc_dev.dv_xname, why); 907 908 if (rst) { 909 printf("%s: resetting...\n", sc->sc_dev.dv_xname); 910 qereset(sc); 911 return (-1); 912 } 913 914 return (r); 915 } 916 917 int 918 qeioctl(ifp, cmd, data) 919 struct ifnet *ifp; 920 u_long cmd; 921 caddr_t data; 922 { 923 struct qe_softc *sc = ifp->if_softc; 924 struct ifaddr *ifa = (struct ifaddr *)data; 925 struct ifreq *ifr = (struct ifreq *)data; 926 int s, error = 0; 927 928 s = splnet(); 929 930 switch (cmd) { 931 case SIOCSIFADDR: 932 ifp->if_flags |= IFF_UP; 933 switch (ifa->ifa_addr->sa_family) { 934 #ifdef INET 935 case AF_INET: 936 qeinit(sc); 937 arp_ifinit(ifp, ifa); 938 break; 939 #endif /* INET */ 940 #ifdef NS 941 case AF_NS: 942 { 943 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 944 945 if (ns_nullhost(*ina)) 946 ina->x_host = 947 *(union ns_host *)LLADDR(ifp->if_sadl); 948 else 949 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 950 sizeof(sc->sc_enaddr)); 951 /* Set new address. */ 952 qeinit(sc); 953 break; 954 } 955 #endif /* NS */ 956 default: 957 qeinit(sc); 958 break; 959 } 960 break; 961 962 case SIOCSIFFLAGS: 963 if ((ifp->if_flags & IFF_UP) == 0 && 964 (ifp->if_flags & IFF_RUNNING) != 0) { 965 /* 966 * If interface is marked down and it is running, then 967 * stop it. 968 */ 969 qestop(sc); 970 ifp->if_flags &= ~IFF_RUNNING; 971 972 } else if ((ifp->if_flags & IFF_UP) != 0 && 973 (ifp->if_flags & IFF_RUNNING) == 0) { 974 /* 975 * If interface is marked up and it is stopped, then 976 * start it. 977 */ 978 qeinit(sc); 979 980 } else { 981 /* 982 * Reset the interface to pick up changes in any other 983 * flags that affect hardware registers. 984 */ 985 qestop(sc); 986 qeinit(sc); 987 } 988 #ifdef QEDEBUG 989 sc->sc_debug = (ifp->if_flags & IFF_DEBUG) != 0 ? 1 : 0; 990 #endif 991 break; 992 993 case SIOCADDMULTI: 994 case SIOCDELMULTI: 995 error = (cmd == SIOCADDMULTI) ? 996 ether_addmulti(ifr, &sc->sc_ethercom): 997 ether_delmulti(ifr, &sc->sc_ethercom); 998 999 if (error == ENETRESET) { 1000 /* 1001 * Multicast list has changed; set the hardware filter 1002 * accordingly. 1003 */ 1004 qe_mcreset(sc); 1005 error = 0; 1006 } 1007 break; 1008 1009 case SIOCGIFMEDIA: 1010 case SIOCSIFMEDIA: 1011 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, cmd); 1012 break; 1013 1014 default: 1015 error = EINVAL; 1016 break; 1017 } 1018 1019 splx(s); 1020 return (error); 1021 } 1022 1023 1024 void 1025 qeinit(sc) 1026 struct qe_softc *sc; 1027 { 1028 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1029 bus_space_tag_t t = sc->sc_bustag; 1030 bus_space_handle_t cr = sc->sc_cr; 1031 bus_space_handle_t mr = sc->sc_mr; 1032 struct qec_softc *qec = sc->sc_qec; 1033 u_int32_t qecaddr; 1034 u_int8_t *ea; 1035 int s; 1036 1037 #if defined(SUN4U) || defined(__GNUC__) 1038 (void)&t; 1039 #endif 1040 s = splnet(); 1041 1042 qestop(sc); 1043 1044 /* 1045 * Allocate descriptor ring and buffers 1046 */ 1047 qec_meminit(&sc->sc_rb, QE_PKT_BUF_SZ); 1048 1049 /* Channel registers: */ 1050 bus_space_write_4(t, cr, QE_CRI_RXDS, (u_int32_t)sc->sc_rb.rb_rxddma); 1051 bus_space_write_4(t, cr, QE_CRI_TXDS, (u_int32_t)sc->sc_rb.rb_txddma); 1052 1053 bus_space_write_4(t, cr, QE_CRI_RIMASK, 0); 1054 bus_space_write_4(t, cr, QE_CRI_TIMASK, 0); 1055 bus_space_write_4(t, cr, QE_CRI_QMASK, 0); 1056 bus_space_write_4(t, cr, QE_CRI_MMASK, QE_CR_MMASK_RXCOLL); 1057 bus_space_write_4(t, cr, QE_CRI_CCNT, 0); 1058 bus_space_write_4(t, cr, QE_CRI_PIPG, 0); 1059 1060 qecaddr = sc->sc_channel * qec->sc_msize; 1061 bus_space_write_4(t, cr, QE_CRI_RXWBUF, qecaddr); 1062 bus_space_write_4(t, cr, QE_CRI_RXRBUF, qecaddr); 1063 bus_space_write_4(t, cr, QE_CRI_TXWBUF, qecaddr + qec->sc_rsize); 1064 bus_space_write_4(t, cr, QE_CRI_TXRBUF, qecaddr + qec->sc_rsize); 1065 1066 /* MACE registers: */ 1067 bus_space_write_1(t, mr, QE_MRI_PHYCC, QE_MR_PHYCC_ASEL); 1068 bus_space_write_1(t, mr, QE_MRI_XMTFC, QE_MR_XMTFC_APADXMT); 1069 bus_space_write_1(t, mr, QE_MRI_RCVFC, 0); 1070 1071 /* 1072 * Mask MACE's receive interrupt, since we're being notified 1073 * by the QEC after DMA completes. 1074 */ 1075 bus_space_write_1(t, mr, QE_MRI_IMR, 1076 QE_MR_IMR_CERRM | QE_MR_IMR_RCVINTM); 1077 1078 bus_space_write_1(t, mr, QE_MRI_BIUCC, 1079 QE_MR_BIUCC_BSWAP | QE_MR_BIUCC_64TS); 1080 1081 bus_space_write_1(t, mr, QE_MRI_FIFOFC, 1082 QE_MR_FIFOCC_TXF16 | QE_MR_FIFOCC_RXF32 | 1083 QE_MR_FIFOCC_RFWU | QE_MR_FIFOCC_TFWU); 1084 1085 bus_space_write_1(t, mr, QE_MRI_PLSCC, QE_MR_PLSCC_TP); 1086 1087 /* 1088 * Station address 1089 */ 1090 ea = sc->sc_enaddr; 1091 bus_space_write_1(t, mr, QE_MRI_IAC, 1092 QE_MR_IAC_ADDRCHG | QE_MR_IAC_PHYADDR); 1093 bus_space_write_multi_1(t, mr, QE_MRI_PADR, ea, 6); 1094 1095 /* Apply media settings */ 1096 qe_ifmedia_upd(ifp); 1097 1098 /* 1099 * Clear Logical address filter 1100 */ 1101 bus_space_write_1(t, mr, QE_MRI_IAC, 1102 QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR); 1103 bus_space_set_multi_1(t, mr, QE_MRI_LADRF, 0, 8); 1104 bus_space_write_1(t, mr, QE_MRI_IAC, 0); 1105 1106 /* Clear missed packet count (register cleared on read) */ 1107 (void)bus_space_read_1(t, mr, QE_MRI_MPC); 1108 1109 #if 0 1110 /* test register: */ 1111 bus_space_write_1(t, mr, QE_MRI_UTR, 0); 1112 #endif 1113 1114 /* Reset multicast filter */ 1115 qe_mcreset(sc); 1116 1117 ifp->if_flags |= IFF_RUNNING; 1118 ifp->if_flags &= ~IFF_OACTIVE; 1119 splx(s); 1120 } 1121 1122 /* 1123 * Reset multicast filter. 1124 */ 1125 void 1126 qe_mcreset(sc) 1127 struct qe_softc *sc; 1128 { 1129 struct ethercom *ec = &sc->sc_ethercom; 1130 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1131 bus_space_tag_t t = sc->sc_bustag; 1132 bus_space_handle_t mr = sc->sc_mr; 1133 struct ether_multi *enm; 1134 struct ether_multistep step; 1135 u_int32_t crc; 1136 u_int16_t hash[4]; 1137 u_int8_t octet, maccc, *ladrp = (u_int8_t *)&hash[0]; 1138 int i, j; 1139 1140 #if defined(SUN4U) || defined(__GNUC__) 1141 (void)&t; 1142 #endif 1143 1144 /* We also enable transmitter & receiver here */ 1145 maccc = QE_MR_MACCC_ENXMT | QE_MR_MACCC_ENRCV; 1146 1147 if (ifp->if_flags & IFF_PROMISC) { 1148 maccc |= QE_MR_MACCC_PROM; 1149 bus_space_write_1(t, mr, QE_MRI_MACCC, maccc); 1150 return; 1151 } 1152 1153 if (ifp->if_flags & IFF_ALLMULTI) { 1154 bus_space_write_1(t, mr, QE_MRI_IAC, 1155 QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR); 1156 bus_space_set_multi_1(t, mr, QE_MRI_LADRF, 0xff, 8); 1157 bus_space_write_1(t, mr, QE_MRI_IAC, 0); 1158 bus_space_write_1(t, mr, QE_MRI_MACCC, maccc); 1159 return; 1160 } 1161 1162 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1163 1164 ETHER_FIRST_MULTI(step, ec, enm); 1165 while (enm != NULL) { 1166 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 1167 ETHER_ADDR_LEN) != 0) { 1168 /* 1169 * We must listen to a range of multicast 1170 * addresses. For now, just accept all 1171 * multicasts, rather than trying to set only 1172 * those filter bits needed to match the range. 1173 * (At this time, the only use of address 1174 * ranges is for IP multicast routing, for 1175 * which the range is big enough to require 1176 * all bits set.) 1177 */ 1178 bus_space_write_1(t, mr, QE_MRI_IAC, 1179 QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR); 1180 bus_space_set_multi_1(t, mr, QE_MRI_LADRF, 0xff, 8); 1181 bus_space_write_1(t, mr, QE_MRI_IAC, 0); 1182 ifp->if_flags |= IFF_ALLMULTI; 1183 break; 1184 } 1185 1186 crc = 0xffffffff; 1187 1188 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1189 octet = enm->enm_addrlo[i]; 1190 1191 for (j = 0; j < 8; j++) { 1192 if ((crc & 1) ^ (octet & 1)) { 1193 crc >>= 1; 1194 crc ^= MC_POLY_LE; 1195 } 1196 else 1197 crc >>= 1; 1198 octet >>= 1; 1199 } 1200 } 1201 1202 crc >>= 26; 1203 hash[crc >> 4] |= 1 << (crc & 0xf); 1204 ETHER_NEXT_MULTI(step, enm); 1205 } 1206 1207 bus_space_write_1(t, mr, QE_MRI_IAC, 1208 QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR); 1209 bus_space_write_multi_1(t, mr, QE_MRI_LADRF, ladrp, 8); 1210 bus_space_write_1(t, mr, QE_MRI_IAC, 0); 1211 bus_space_write_1(t, mr, QE_MRI_MACCC, maccc); 1212 } 1213 1214 /* 1215 * Get current media settings. 1216 */ 1217 void 1218 qe_ifmedia_sts(ifp, ifmr) 1219 struct ifnet *ifp; 1220 struct ifmediareq *ifmr; 1221 { 1222 struct qe_softc *sc = ifp->if_softc; 1223 bus_space_tag_t t = sc->sc_bustag; 1224 bus_space_handle_t mr = sc->sc_mr; 1225 u_int8_t v; 1226 1227 #if defined(SUN4U) || defined(__GNUC__) 1228 (void)&t; 1229 #endif 1230 v = bus_space_read_1(t, mr, QE_MRI_PLSCC); 1231 1232 switch (bus_space_read_1(t, mr, QE_MRI_PLSCC) & QE_MR_PLSCC_PORTMASK) { 1233 case QE_MR_PLSCC_TP: 1234 ifmr->ifm_active = IFM_ETHER | IFM_10_T; 1235 break; 1236 case QE_MR_PLSCC_AUI: 1237 ifmr->ifm_active = IFM_ETHER | IFM_10_5; 1238 break; 1239 case QE_MR_PLSCC_GPSI: 1240 case QE_MR_PLSCC_DAI: 1241 /* ... */ 1242 break; 1243 } 1244 1245 v = bus_space_read_1(t, mr, QE_MRI_PHYCC); 1246 ifmr->ifm_status |= IFM_AVALID; 1247 if ((v & QE_MR_PHYCC_LNKFL) != 0) 1248 ifmr->ifm_status &= ~IFM_ACTIVE; 1249 else 1250 ifmr->ifm_status |= IFM_ACTIVE; 1251 1252 } 1253 1254 /* 1255 * Set media options. 1256 */ 1257 int 1258 qe_ifmedia_upd(ifp) 1259 struct ifnet *ifp; 1260 { 1261 struct qe_softc *sc = ifp->if_softc; 1262 struct ifmedia *ifm = &sc->sc_ifmedia; 1263 bus_space_tag_t t = sc->sc_bustag; 1264 bus_space_handle_t mr = sc->sc_mr; 1265 int newmedia = ifm->ifm_media; 1266 u_int8_t plscc, phycc; 1267 1268 #if defined(SUN4U) || defined(__GNUC__) 1269 (void)&t; 1270 #endif 1271 if (IFM_TYPE(newmedia) != IFM_ETHER) 1272 return (EINVAL); 1273 1274 plscc = bus_space_read_1(t, mr, QE_MRI_PLSCC) & ~QE_MR_PLSCC_PORTMASK; 1275 phycc = bus_space_read_1(t, mr, QE_MRI_PHYCC) & ~QE_MR_PHYCC_ASEL; 1276 1277 if (IFM_SUBTYPE(newmedia) == IFM_AUTO) 1278 phycc |= QE_MR_PHYCC_ASEL; 1279 else if (IFM_SUBTYPE(newmedia) == IFM_10_T) 1280 plscc |= QE_MR_PLSCC_TP; 1281 else if (IFM_SUBTYPE(newmedia) == IFM_10_5) 1282 plscc |= QE_MR_PLSCC_AUI; 1283 1284 bus_space_write_1(t, mr, QE_MRI_PLSCC, plscc); 1285 bus_space_write_1(t, mr, QE_MRI_PHYCC, phycc); 1286 1287 return (0); 1288 } 1289
Indexes created Tue Sep 30 20:09:53 GMT 2025