qe.c revision 1.18
1 /* $NetBSD: qe.c,v 1.18 2001/09/26 20:53:15 eeh Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1998 Jason L. Wright. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the authors may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 59 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 63 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 */ 65 66 /* 67 * Driver for the SBus qec+qe QuadEthernet board. 68 * 69 * This driver was written using the AMD MACE Am79C940 documentation, some 70 * ideas gleaned from the S/Linux driver for this card, Solaris header files, 71 * and a loan of a card from Paul Southworth of the Internet Engineering 72 * Group (www.ieng.com). 73 */ 74 75 #define QEDEBUG 76 77 #include "opt_ddb.h" 78 #include "opt_inet.h" 79 #include "opt_ccitt.h" 80 #include "opt_llc.h" 81 #include "opt_ns.h" 82 #include "bpfilter.h" 83 #include "rnd.h" 84 85 #include <sys/param.h> 86 #include <sys/systm.h> 87 #include <sys/kernel.h> 88 #include <sys/errno.h> 89 #include <sys/ioctl.h> 90 #include <sys/mbuf.h> 91 #include <sys/socket.h> 92 #include <sys/syslog.h> 93 #include <sys/device.h> 94 #include <sys/malloc.h> 95 #if NRND > 0 96 #include <sys/rnd.h> 97 #endif 98 99 #include <net/if.h> 100 #include <net/if_dl.h> 101 #include <net/if_types.h> 102 #include <net/netisr.h> 103 #include <net/if_media.h> 104 #include <net/if_ether.h> 105 106 #ifdef INET 107 #include <netinet/in.h> 108 #include <netinet/if_inarp.h> 109 #include <netinet/in_systm.h> 110 #include <netinet/in_var.h> 111 #include <netinet/ip.h> 112 #endif 113 114 #ifdef NS 115 #include <netns/ns.h> 116 #include <netns/ns_if.h> 117 #endif 118 119 #if NBPFILTER > 0 120 #include <net/bpf.h> 121 #include <net/bpfdesc.h> 122 #endif 123 124 #include <machine/bus.h> 125 #include <machine/intr.h> 126 #include <machine/autoconf.h> 127 128 #include <dev/sbus/sbusvar.h> 129 #include <dev/sbus/qecreg.h> 130 #include <dev/sbus/qecvar.h> 131 #include <dev/sbus/qereg.h> 132 133 struct qe_softc { 134 struct device sc_dev; /* base device */ 135 struct sbusdev sc_sd; /* sbus device */ 136 bus_space_tag_t sc_bustag; /* bus & dma tags */ 137 bus_dma_tag_t sc_dmatag; 138 bus_dmamap_t sc_dmamap; 139 struct ethercom sc_ethercom; 140 struct ifmedia sc_ifmedia; /* interface media */ 141 142 struct qec_softc *sc_qec; /* QEC parent */ 143 144 bus_space_handle_t sc_qr; /* QEC registers */ 145 bus_space_handle_t sc_mr; /* MACE registers */ 146 bus_space_handle_t sc_cr; /* channel registers */ 147 148 int sc_channel; /* channel number */ 149 u_int sc_rev; /* board revision */ 150 151 int sc_burst; 152 153 struct qec_ring sc_rb; /* Packet Ring Buffer */ 154 155 /* MAC address */ 156 u_int8_t sc_enaddr[6]; 157 158 #ifdef QEDEBUG 159 int sc_debug; 160 #endif 161 }; 162 163 int qematch __P((struct device *, struct cfdata *, void *)); 164 void qeattach __P((struct device *, struct device *, void *)); 165 166 void qeinit __P((struct qe_softc *)); 167 void qestart __P((struct ifnet *)); 168 void qestop __P((struct qe_softc *)); 169 void qewatchdog __P((struct ifnet *)); 170 int qeioctl __P((struct ifnet *, u_long, caddr_t)); 171 void qereset __P((struct qe_softc *)); 172 173 int qeintr __P((void *)); 174 int qe_eint __P((struct qe_softc *, u_int32_t)); 175 int qe_rint __P((struct qe_softc *)); 176 int qe_tint __P((struct qe_softc *)); 177 void qe_mcreset __P((struct qe_softc *)); 178 179 static int qe_put __P((struct qe_softc *, int, struct mbuf *)); 180 static void qe_read __P((struct qe_softc *, int, int)); 181 static struct mbuf *qe_get __P((struct qe_softc *, int, int)); 182 183 /* ifmedia callbacks */ 184 void qe_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 185 int qe_ifmedia_upd __P((struct ifnet *)); 186 187 struct cfattach qe_ca = { 188 sizeof(struct qe_softc), qematch, qeattach 189 }; 190 191 int 192 qematch(parent, cf, aux) 193 struct device *parent; 194 struct cfdata *cf; 195 void *aux; 196 { 197 struct sbus_attach_args *sa = aux; 198 199 return (strcmp(cf->cf_driver->cd_name, sa->sa_name) == 0); 200 } 201 202 void 203 qeattach(parent, self, aux) 204 struct device *parent, *self; 205 void *aux; 206 { 207 struct sbus_attach_args *sa = aux; 208 struct qec_softc *qec = (struct qec_softc *)parent; 209 struct qe_softc *sc = (struct qe_softc *)self; 210 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 211 int node = sa->sa_node; 212 bus_dma_tag_t dmatag = sa->sa_dmatag; 213 bus_dma_segment_t seg; 214 bus_size_t size; 215 int rseg, error; 216 extern void myetheraddr __P((u_char *)); 217 218 if (sa->sa_nreg < 2) { 219 printf("%s: only %d register sets\n", 220 self->dv_xname, sa->sa_nreg); 221 return; 222 } 223 224 if (bus_space_map2(sa->sa_bustag, 225 (bus_type_t)sa->sa_reg[0].sbr_slot, 226 (bus_addr_t)sa->sa_reg[0].sbr_offset, 227 (bus_size_t)sa->sa_reg[0].sbr_size, 228 BUS_SPACE_MAP_LINEAR, 0, &sc->sc_cr) != 0) { 229 printf("%s: cannot map registers\n", self->dv_xname); 230 return; 231 } 232 233 if (bus_space_map2(sa->sa_bustag, 234 (bus_type_t)sa->sa_reg[1].sbr_slot, 235 (bus_addr_t)sa->sa_reg[1].sbr_offset, 236 (bus_size_t)sa->sa_reg[1].sbr_size, 237 BUS_SPACE_MAP_LINEAR, 0, &sc->sc_mr) != 0) { 238 printf("%s: cannot map registers\n", self->dv_xname); 239 return; 240 } 241 242 sc->sc_rev = PROM_getpropint(node, "mace-version", -1); 243 printf(" rev %x", sc->sc_rev); 244 245 sc->sc_bustag = sa->sa_bustag; 246 sc->sc_dmatag = sa->sa_dmatag; 247 sc->sc_qec = qec; 248 sc->sc_qr = qec->sc_regs; 249 250 sc->sc_channel = PROM_getpropint(node, "channel#", -1); 251 sc->sc_burst = qec->sc_burst; 252 253 qestop(sc); 254 255 /* Note: no interrupt level passed */ 256 (void)bus_intr_establish(sa->sa_bustag, 0, IPL_NET, 0, qeintr, sc); 257 myetheraddr(sc->sc_enaddr); 258 259 /* 260 * Allocate descriptor ring and buffers. 261 */ 262 263 /* for now, allocate as many bufs as there are ring descriptors */ 264 sc->sc_rb.rb_ntbuf = QEC_XD_RING_MAXSIZE; 265 sc->sc_rb.rb_nrbuf = QEC_XD_RING_MAXSIZE; 266 267 size = QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 268 QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 269 sc->sc_rb.rb_ntbuf * QE_PKT_BUF_SZ + 270 sc->sc_rb.rb_nrbuf * QE_PKT_BUF_SZ; 271 272 /* Get a DMA handle */ 273 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0, 274 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 275 printf("%s: DMA map create error %d\n", self->dv_xname, error); 276 return; 277 } 278 279 /* Allocate DMA buffer */ 280 if ((error = bus_dmamem_alloc(dmatag, size, 0, 0, 281 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 282 printf("%s: DMA buffer alloc error %d\n", 283 self->dv_xname, error); 284 return; 285 } 286 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 287 288 /* Map DMA buffer in CPU addressable space */ 289 if ((error = bus_dmamem_map(dmatag, &seg, rseg, size, 290 &sc->sc_rb.rb_membase, 291 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 292 printf("%s: DMA buffer map error %d\n", 293 self->dv_xname, error); 294 bus_dmamem_free(dmatag, &seg, rseg); 295 return; 296 } 297 298 /* Load the buffer */ 299 if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap, 300 sc->sc_rb.rb_membase, size, NULL, 301 BUS_DMA_NOWAIT)) != 0) { 302 printf("%s: DMA buffer map load error %d\n", 303 self->dv_xname, error); 304 bus_dmamem_unmap(dmatag, sc->sc_rb.rb_membase, size); 305 bus_dmamem_free(dmatag, &seg, rseg); 306 return; 307 } 308 309 /* Initialize media properties */ 310 ifmedia_init(&sc->sc_ifmedia, 0, qe_ifmedia_upd, qe_ifmedia_sts); 311 ifmedia_add(&sc->sc_ifmedia, 312 IFM_MAKEWORD(IFM_ETHER,IFM_10_T,0,0), 313 0, NULL); 314 ifmedia_add(&sc->sc_ifmedia, 315 IFM_MAKEWORD(IFM_ETHER,IFM_10_5,0,0), 316 0, NULL); 317 ifmedia_add(&sc->sc_ifmedia, 318 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,0), 319 0, NULL); 320 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO); 321 322 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 323 ifp->if_softc = sc; 324 ifp->if_start = qestart; 325 ifp->if_ioctl = qeioctl; 326 ifp->if_watchdog = qewatchdog; 327 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | 328 IFF_MULTICAST; 329 IFQ_SET_READY(&ifp->if_snd); 330 331 /* Attach the interface. */ 332 if_attach(ifp); 333 ether_ifattach(ifp, sc->sc_enaddr); 334 335 printf(" address %s\n", ether_sprintf(sc->sc_enaddr)); 336 } 337 338 /* 339 * Pull data off an interface. 340 * Len is the length of data, with local net header stripped. 341 * We copy the data into mbufs. When full cluster sized units are present, 342 * we copy into clusters. 343 */ 344 static __inline__ struct mbuf * 345 qe_get(sc, idx, totlen) 346 struct qe_softc *sc; 347 int idx, totlen; 348 { 349 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 350 struct mbuf *m; 351 struct mbuf *top, **mp; 352 int len, pad, boff = 0; 353 caddr_t bp; 354 355 bp = sc->sc_rb.rb_rxbuf + (idx % sc->sc_rb.rb_nrbuf) * QE_PKT_BUF_SZ; 356 357 MGETHDR(m, M_DONTWAIT, MT_DATA); 358 if (m == NULL) 359 return (NULL); 360 m->m_pkthdr.rcvif = ifp; 361 m->m_pkthdr.len = totlen; 362 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 363 m->m_data += pad; 364 len = MHLEN - pad; 365 top = NULL; 366 mp = ⊤ 367 368 while (totlen > 0) { 369 if (top) { 370 MGET(m, M_DONTWAIT, MT_DATA); 371 if (m == NULL) { 372 m_freem(top); 373 return (NULL); 374 } 375 len = MLEN; 376 } 377 if (top && totlen >= MINCLSIZE) { 378 MCLGET(m, M_DONTWAIT); 379 if (m->m_flags & M_EXT) 380 len = MCLBYTES; 381 } 382 m->m_len = len = min(totlen, len); 383 bcopy(bp + boff, mtod(m, caddr_t), len); 384 boff += len; 385 totlen -= len; 386 *mp = m; 387 mp = &m->m_next; 388 } 389 390 return (top); 391 } 392 393 /* 394 * Routine to copy from mbuf chain to transmit buffer in 395 * network buffer memory. 396 */ 397 __inline__ int 398 qe_put(sc, idx, m) 399 struct qe_softc *sc; 400 int idx; 401 struct mbuf *m; 402 { 403 struct mbuf *n; 404 int len, tlen = 0, boff = 0; 405 caddr_t bp; 406 407 bp = sc->sc_rb.rb_txbuf + (idx % sc->sc_rb.rb_ntbuf) * QE_PKT_BUF_SZ; 408 409 for (; m; m = n) { 410 len = m->m_len; 411 if (len == 0) { 412 MFREE(m, n); 413 continue; 414 } 415 bcopy(mtod(m, caddr_t), bp+boff, len); 416 boff += len; 417 tlen += len; 418 MFREE(m, n); 419 } 420 return (tlen); 421 } 422 423 /* 424 * Pass a packet to the higher levels. 425 */ 426 __inline__ void 427 qe_read(sc, idx, len) 428 struct qe_softc *sc; 429 int idx, len; 430 { 431 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 432 struct mbuf *m; 433 434 if (len <= sizeof(struct ether_header) || 435 len > ETHERMTU + sizeof(struct ether_header)) { 436 437 printf("%s: invalid packet size %d; dropping\n", 438 ifp->if_xname, len); 439 440 ifp->if_ierrors++; 441 return; 442 } 443 444 /* 445 * Pull packet off interface. 446 */ 447 m = qe_get(sc, idx, len); 448 if (m == NULL) { 449 ifp->if_ierrors++; 450 return; 451 } 452 ifp->if_ipackets++; 453 454 #if NBPFILTER > 0 455 /* 456 * Check if there's a BPF listener on this interface. 457 * If so, hand off the raw packet to BPF. 458 */ 459 if (ifp->if_bpf) 460 bpf_mtap(ifp->if_bpf, m); 461 #endif 462 /* Pass the packet up. */ 463 (*ifp->if_input)(ifp, m); 464 } 465 466 /* 467 * Start output on interface. 468 * We make two assumptions here: 469 * 1) that the current priority is set to splnet _before_ this code 470 * is called *and* is returned to the appropriate priority after 471 * return 472 * 2) that the IFF_OACTIVE flag is checked before this code is called 473 * (i.e. that the output part of the interface is idle) 474 */ 475 void 476 qestart(ifp) 477 struct ifnet *ifp; 478 { 479 struct qe_softc *sc = (struct qe_softc *)ifp->if_softc; 480 struct qec_xd *txd = sc->sc_rb.rb_txd; 481 struct mbuf *m; 482 unsigned int bix, len; 483 unsigned int ntbuf = sc->sc_rb.rb_ntbuf; 484 485 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 486 return; 487 488 bix = sc->sc_rb.rb_tdhead; 489 490 for (;;) { 491 IFQ_DEQUEUE(&ifp->if_snd, m); 492 if (m == 0) 493 break; 494 495 #if NBPFILTER > 0 496 /* 497 * If BPF is listening on this interface, let it see the 498 * packet before we commit it to the wire. 499 */ 500 if (ifp->if_bpf) 501 bpf_mtap(ifp->if_bpf, m); 502 #endif 503 504 /* 505 * Copy the mbuf chain into the transmit buffer. 506 */ 507 len = qe_put(sc, bix, m); 508 509 /* 510 * Initialize transmit registers and start transmission 511 */ 512 txd[bix].xd_flags = QEC_XD_OWN | QEC_XD_SOP | QEC_XD_EOP | 513 (len & QEC_XD_LENGTH); 514 bus_space_write_4(sc->sc_bustag, sc->sc_cr, QE_CRI_CTRL, 515 QE_CR_CTRL_TWAKEUP); 516 517 if (++bix == QEC_XD_RING_MAXSIZE) 518 bix = 0; 519 520 if (++sc->sc_rb.rb_td_nbusy == ntbuf) { 521 ifp->if_flags |= IFF_OACTIVE; 522 break; 523 } 524 } 525 526 sc->sc_rb.rb_tdhead = bix; 527 } 528 529 void 530 qestop(sc) 531 struct qe_softc *sc; 532 { 533 bus_space_tag_t t = sc->sc_bustag; 534 bus_space_handle_t mr = sc->sc_mr; 535 bus_space_handle_t cr = sc->sc_cr; 536 int n; 537 538 #if defined(SUN4U) || defined(__GNUC__) 539 (void)&t; 540 #endif 541 /* Stop the schwurst */ 542 bus_space_write_1(t, mr, QE_MRI_BIUCC, QE_MR_BIUCC_SWRST); 543 for (n = 200; n > 0; n--) { 544 if ((bus_space_read_1(t, mr, QE_MRI_BIUCC) & 545 QE_MR_BIUCC_SWRST) == 0) 546 break; 547 DELAY(20); 548 } 549 550 /* then reset */ 551 bus_space_write_4(t, cr, QE_CRI_CTRL, QE_CR_CTRL_RESET); 552 for (n = 200; n > 0; n--) { 553 if ((bus_space_read_4(t, cr, QE_CRI_CTRL) & 554 QE_CR_CTRL_RESET) == 0) 555 break; 556 DELAY(20); 557 } 558 } 559 560 /* 561 * Reset interface. 562 */ 563 void 564 qereset(sc) 565 struct qe_softc *sc; 566 { 567 int s; 568 569 s = splnet(); 570 qestop(sc); 571 qeinit(sc); 572 splx(s); 573 } 574 575 void 576 qewatchdog(ifp) 577 struct ifnet *ifp; 578 { 579 struct qe_softc *sc = ifp->if_softc; 580 581 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 582 ifp->if_oerrors++; 583 584 qereset(sc); 585 } 586 587 /* 588 * Interrupt dispatch. 589 */ 590 int 591 qeintr(arg) 592 void *arg; 593 { 594 struct qe_softc *sc = (struct qe_softc *)arg; 595 bus_space_tag_t t = sc->sc_bustag; 596 u_int32_t qecstat, qestat; 597 int r = 0; 598 599 #if defined(SUN4U) || defined(__GNUC__) 600 (void)&t; 601 #endif 602 /* Read QEC status and channel status */ 603 qecstat = bus_space_read_4(t, sc->sc_qr, QEC_QRI_STAT); 604 #ifdef QEDEBUG 605 if (sc->sc_debug) { 606 printf("qe%d: intr: qecstat=%x\n", sc->sc_channel, qecstat); 607 } 608 #endif 609 610 /* Filter out status for this channel */ 611 qecstat = qecstat >> (4 * sc->sc_channel); 612 if ((qecstat & 0xf) == 0) 613 return (r); 614 615 qestat = bus_space_read_4(t, sc->sc_cr, QE_CRI_STAT); 616 617 #ifdef QEDEBUG 618 if (sc->sc_debug) { 619 char bits[64]; int i; 620 bus_space_tag_t t = sc->sc_bustag; 621 bus_space_handle_t mr = sc->sc_mr; 622 623 printf("qe%d: intr: qestat=%s\n", sc->sc_channel, 624 bitmask_snprintf(qestat, QE_CR_STAT_BITS, bits, sizeof(bits))); 625 626 printf("MACE registers:\n"); 627 for (i = 0 ; i < 32; i++) { 628 printf(" m[%d]=%x,", i, bus_space_read_1(t, mr, i)); 629 if (((i+1) & 7) == 0) 630 printf("\n"); 631 } 632 } 633 #endif 634 635 if (qestat & QE_CR_STAT_ALLERRORS) { 636 #ifdef QEDEBUG 637 if (sc->sc_debug) { 638 char bits[64]; 639 printf("qe%d: eint: qestat=%s\n", sc->sc_channel, 640 bitmask_snprintf(qestat, QE_CR_STAT_BITS, bits, 641 sizeof(bits))); 642 } 643 #endif 644 r |= qe_eint(sc, qestat); 645 if (r == -1) 646 return (1); 647 } 648 649 if (qestat & QE_CR_STAT_TXIRQ) 650 r |= qe_tint(sc); 651 652 if (qestat & QE_CR_STAT_RXIRQ) 653 r |= qe_rint(sc); 654 655 return (r); 656 } 657 658 /* 659 * Transmit interrupt. 660 */ 661 int 662 qe_tint(sc) 663 struct qe_softc *sc; 664 { 665 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 666 unsigned int bix, txflags; 667 668 bix = sc->sc_rb.rb_tdtail; 669 670 for (;;) { 671 if (sc->sc_rb.rb_td_nbusy <= 0) 672 break; 673 674 txflags = sc->sc_rb.rb_txd[bix].xd_flags; 675 676 if (txflags & QEC_XD_OWN) 677 break; 678 679 ifp->if_flags &= ~IFF_OACTIVE; 680 ifp->if_opackets++; 681 682 if (++bix == QEC_XD_RING_MAXSIZE) 683 bix = 0; 684 685 --sc->sc_rb.rb_td_nbusy; 686 } 687 688 sc->sc_rb.rb_tdtail = bix; 689 690 qestart(ifp); 691 692 if (sc->sc_rb.rb_td_nbusy == 0) 693 ifp->if_timer = 0; 694 695 return (1); 696 } 697 698 /* 699 * Receive interrupt. 700 */ 701 int 702 qe_rint(sc) 703 struct qe_softc *sc; 704 { 705 struct qec_xd *xd = sc->sc_rb.rb_rxd; 706 unsigned int bix, len; 707 unsigned int nrbuf = sc->sc_rb.rb_nrbuf; 708 #ifdef QEDEBUG 709 int npackets = 0; 710 #endif 711 712 bix = sc->sc_rb.rb_rdtail; 713 714 /* 715 * Process all buffers with valid data. 716 */ 717 for (;;) { 718 len = xd[bix].xd_flags; 719 if (len & QEC_XD_OWN) 720 break; 721 722 #ifdef QEDEBUG 723 npackets++; 724 #endif 725 726 len &= QEC_XD_LENGTH; 727 len -= 4; 728 qe_read(sc, bix, len); 729 730 /* ... */ 731 xd[(bix+nrbuf) % QEC_XD_RING_MAXSIZE].xd_flags = 732 QEC_XD_OWN | (QE_PKT_BUF_SZ & QEC_XD_LENGTH); 733 734 if (++bix == QEC_XD_RING_MAXSIZE) 735 bix = 0; 736 } 737 #ifdef QEDEBUG 738 if (npackets == 0 && sc->sc_debug) 739 printf("%s: rint: no packets; rb index %d; status 0x%x\n", 740 sc->sc_dev.dv_xname, bix, len); 741 #endif 742 743 sc->sc_rb.rb_rdtail = bix; 744 745 return (1); 746 } 747 748 /* 749 * Error interrupt. 750 */ 751 int 752 qe_eint(sc, why) 753 struct qe_softc *sc; 754 u_int32_t why; 755 { 756 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 757 int r = 0, rst = 0; 758 759 if (why & QE_CR_STAT_EDEFER) { 760 printf("%s: excessive tx defers.\n", sc->sc_dev.dv_xname); 761 r |= 1; 762 ifp->if_oerrors++; 763 } 764 765 if (why & QE_CR_STAT_CLOSS) { 766 printf("%s: no carrier, link down?\n", sc->sc_dev.dv_xname); 767 ifp->if_oerrors++; 768 r |= 1; 769 } 770 771 if (why & QE_CR_STAT_ERETRIES) { 772 printf("%s: excessive tx retries\n", sc->sc_dev.dv_xname); 773 ifp->if_oerrors++; 774 r |= 1; 775 rst = 1; 776 } 777 778 779 if (why & QE_CR_STAT_LCOLL) { 780 printf("%s: late tx transmission\n", sc->sc_dev.dv_xname); 781 ifp->if_oerrors++; 782 r |= 1; 783 rst = 1; 784 } 785 786 if (why & QE_CR_STAT_FUFLOW) { 787 printf("%s: tx fifo underflow\n", sc->sc_dev.dv_xname); 788 ifp->if_oerrors++; 789 r |= 1; 790 rst = 1; 791 } 792 793 if (why & QE_CR_STAT_JERROR) { 794 printf("%s: jabber seen\n", sc->sc_dev.dv_xname); 795 r |= 1; 796 } 797 798 if (why & QE_CR_STAT_BERROR) { 799 printf("%s: babble seen\n", sc->sc_dev.dv_xname); 800 r |= 1; 801 } 802 803 if (why & QE_CR_STAT_TCCOFLOW) { 804 ifp->if_collisions += 256; 805 ifp->if_oerrors += 256; 806 r |= 1; 807 } 808 809 if (why & QE_CR_STAT_TXDERROR) { 810 printf("%s: tx descriptor is bad\n", sc->sc_dev.dv_xname); 811 rst = 1; 812 r |= 1; 813 } 814 815 if (why & QE_CR_STAT_TXLERR) { 816 printf("%s: tx late error\n", sc->sc_dev.dv_xname); 817 ifp->if_oerrors++; 818 rst = 1; 819 r |= 1; 820 } 821 822 if (why & QE_CR_STAT_TXPERR) { 823 printf("%s: tx dma parity error\n", sc->sc_dev.dv_xname); 824 ifp->if_oerrors++; 825 rst = 1; 826 r |= 1; 827 } 828 829 if (why & QE_CR_STAT_TXSERR) { 830 printf("%s: tx dma sbus error ack\n", sc->sc_dev.dv_xname); 831 ifp->if_oerrors++; 832 rst = 1; 833 r |= 1; 834 } 835 836 if (why & QE_CR_STAT_RCCOFLOW) { 837 ifp->if_collisions += 256; 838 ifp->if_ierrors += 256; 839 r |= 1; 840 } 841 842 if (why & QE_CR_STAT_RUOFLOW) { 843 ifp->if_ierrors += 256; 844 r |= 1; 845 } 846 847 if (why & QE_CR_STAT_MCOFLOW) { 848 ifp->if_ierrors += 256; 849 r |= 1; 850 } 851 852 if (why & QE_CR_STAT_RXFOFLOW) { 853 printf("%s: rx fifo overflow\n", sc->sc_dev.dv_xname); 854 ifp->if_ierrors++; 855 r |= 1; 856 } 857 858 if (why & QE_CR_STAT_RLCOLL) { 859 printf("%s: rx late collision\n", sc->sc_dev.dv_xname); 860 ifp->if_ierrors++; 861 ifp->if_collisions++; 862 r |= 1; 863 } 864 865 if (why & QE_CR_STAT_FCOFLOW) { 866 ifp->if_ierrors += 256; 867 r |= 1; 868 } 869 870 if (why & QE_CR_STAT_CECOFLOW) { 871 ifp->if_ierrors += 256; 872 r |= 1; 873 } 874 875 if (why & QE_CR_STAT_RXDROP) { 876 printf("%s: rx packet dropped\n", sc->sc_dev.dv_xname); 877 ifp->if_ierrors++; 878 r |= 1; 879 } 880 881 if (why & QE_CR_STAT_RXSMALL) { 882 printf("%s: rx buffer too small\n", sc->sc_dev.dv_xname); 883 ifp->if_ierrors++; 884 r |= 1; 885 rst = 1; 886 } 887 888 if (why & QE_CR_STAT_RXLERR) { 889 printf("%s: rx late error\n", sc->sc_dev.dv_xname); 890 ifp->if_ierrors++; 891 r |= 1; 892 rst = 1; 893 } 894 895 if (why & QE_CR_STAT_RXPERR) { 896 printf("%s: rx dma parity error\n", sc->sc_dev.dv_xname); 897 ifp->if_ierrors++; 898 r |= 1; 899 rst = 1; 900 } 901 902 if (why & QE_CR_STAT_RXSERR) { 903 printf("%s: rx dma sbus error ack\n", sc->sc_dev.dv_xname); 904 ifp->if_ierrors++; 905 r |= 1; 906 rst = 1; 907 } 908 909 if (r == 0) 910 printf("%s: unexpected interrupt error: %08x\n", 911 sc->sc_dev.dv_xname, why); 912 913 if (rst) { 914 printf("%s: resetting...\n", sc->sc_dev.dv_xname); 915 qereset(sc); 916 return (-1); 917 } 918 919 return (r); 920 } 921 922 int 923 qeioctl(ifp, cmd, data) 924 struct ifnet *ifp; 925 u_long cmd; 926 caddr_t data; 927 { 928 struct qe_softc *sc = ifp->if_softc; 929 struct ifaddr *ifa = (struct ifaddr *)data; 930 struct ifreq *ifr = (struct ifreq *)data; 931 int s, error = 0; 932 933 s = splnet(); 934 935 switch (cmd) { 936 case SIOCSIFADDR: 937 ifp->if_flags |= IFF_UP; 938 switch (ifa->ifa_addr->sa_family) { 939 #ifdef INET 940 case AF_INET: 941 qeinit(sc); 942 arp_ifinit(ifp, ifa); 943 break; 944 #endif /* INET */ 945 #ifdef NS 946 case AF_NS: 947 { 948 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 949 950 if (ns_nullhost(*ina)) 951 ina->x_host = 952 *(union ns_host *)LLADDR(ifp->if_sadl); 953 else 954 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 955 sizeof(sc->sc_enaddr)); 956 /* Set new address. */ 957 qeinit(sc); 958 break; 959 } 960 #endif /* NS */ 961 default: 962 qeinit(sc); 963 break; 964 } 965 break; 966 967 case SIOCSIFFLAGS: 968 if ((ifp->if_flags & IFF_UP) == 0 && 969 (ifp->if_flags & IFF_RUNNING) != 0) { 970 /* 971 * If interface is marked down and it is running, then 972 * stop it. 973 */ 974 qestop(sc); 975 ifp->if_flags &= ~IFF_RUNNING; 976 977 } else if ((ifp->if_flags & IFF_UP) != 0 && 978 (ifp->if_flags & IFF_RUNNING) == 0) { 979 /* 980 * If interface is marked up and it is stopped, then 981 * start it. 982 */ 983 qeinit(sc); 984 985 } else { 986 /* 987 * Reset the interface to pick up changes in any other 988 * flags that affect hardware registers. 989 */ 990 qestop(sc); 991 qeinit(sc); 992 } 993 #ifdef QEDEBUG 994 sc->sc_debug = (ifp->if_flags & IFF_DEBUG) != 0 ? 1 : 0; 995 #endif 996 break; 997 998 case SIOCADDMULTI: 999 case SIOCDELMULTI: 1000 error = (cmd == SIOCADDMULTI) ? 1001 ether_addmulti(ifr, &sc->sc_ethercom): 1002 ether_delmulti(ifr, &sc->sc_ethercom); 1003 1004 if (error == ENETRESET) { 1005 /* 1006 * Multicast list has changed; set the hardware filter 1007 * accordingly. 1008 */ 1009 qe_mcreset(sc); 1010 error = 0; 1011 } 1012 break; 1013 1014 case SIOCGIFMEDIA: 1015 case SIOCSIFMEDIA: 1016 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, cmd); 1017 break; 1018 1019 default: 1020 error = EINVAL; 1021 break; 1022 } 1023 1024 splx(s); 1025 return (error); 1026 } 1027 1028 1029 void 1030 qeinit(sc) 1031 struct qe_softc *sc; 1032 { 1033 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1034 bus_space_tag_t t = sc->sc_bustag; 1035 bus_space_handle_t cr = sc->sc_cr; 1036 bus_space_handle_t mr = sc->sc_mr; 1037 struct qec_softc *qec = sc->sc_qec; 1038 u_int32_t qecaddr; 1039 u_int8_t *ea; 1040 int s; 1041 1042 #if defined(SUN4U) || defined(__GNUC__) 1043 (void)&t; 1044 #endif 1045 s = splnet(); 1046 1047 qestop(sc); 1048 1049 /* 1050 * Allocate descriptor ring and buffers 1051 */ 1052 qec_meminit(&sc->sc_rb, QE_PKT_BUF_SZ); 1053 1054 /* Channel registers: */ 1055 bus_space_write_4(t, cr, QE_CRI_RXDS, (u_int32_t)sc->sc_rb.rb_rxddma); 1056 bus_space_write_4(t, cr, QE_CRI_TXDS, (u_int32_t)sc->sc_rb.rb_txddma); 1057 1058 bus_space_write_4(t, cr, QE_CRI_RIMASK, 0); 1059 bus_space_write_4(t, cr, QE_CRI_TIMASK, 0); 1060 bus_space_write_4(t, cr, QE_CRI_QMASK, 0); 1061 bus_space_write_4(t, cr, QE_CRI_MMASK, QE_CR_MMASK_RXCOLL); 1062 bus_space_write_4(t, cr, QE_CRI_CCNT, 0); 1063 bus_space_write_4(t, cr, QE_CRI_PIPG, 0); 1064 1065 qecaddr = sc->sc_channel * qec->sc_msize; 1066 bus_space_write_4(t, cr, QE_CRI_RXWBUF, qecaddr); 1067 bus_space_write_4(t, cr, QE_CRI_RXRBUF, qecaddr); 1068 bus_space_write_4(t, cr, QE_CRI_TXWBUF, qecaddr + qec->sc_rsize); 1069 bus_space_write_4(t, cr, QE_CRI_TXRBUF, qecaddr + qec->sc_rsize); 1070 1071 /* MACE registers: */ 1072 bus_space_write_1(t, mr, QE_MRI_PHYCC, QE_MR_PHYCC_ASEL); 1073 bus_space_write_1(t, mr, QE_MRI_XMTFC, QE_MR_XMTFC_APADXMT); 1074 bus_space_write_1(t, mr, QE_MRI_RCVFC, 0); 1075 1076 /* 1077 * Mask MACE's receive interrupt, since we're being notified 1078 * by the QEC after DMA completes. 1079 */ 1080 bus_space_write_1(t, mr, QE_MRI_IMR, 1081 QE_MR_IMR_CERRM | QE_MR_IMR_RCVINTM); 1082 1083 bus_space_write_1(t, mr, QE_MRI_BIUCC, 1084 QE_MR_BIUCC_BSWAP | QE_MR_BIUCC_64TS); 1085 1086 bus_space_write_1(t, mr, QE_MRI_FIFOFC, 1087 QE_MR_FIFOCC_TXF16 | QE_MR_FIFOCC_RXF32 | 1088 QE_MR_FIFOCC_RFWU | QE_MR_FIFOCC_TFWU); 1089 1090 bus_space_write_1(t, mr, QE_MRI_PLSCC, QE_MR_PLSCC_TP); 1091 1092 /* 1093 * Station address 1094 */ 1095 ea = sc->sc_enaddr; 1096 bus_space_write_1(t, mr, QE_MRI_IAC, 1097 QE_MR_IAC_ADDRCHG | QE_MR_IAC_PHYADDR); 1098 bus_space_write_multi_1(t, mr, QE_MRI_PADR, ea, 6); 1099 1100 /* Apply media settings */ 1101 qe_ifmedia_upd(ifp); 1102 1103 /* 1104 * Clear Logical address filter 1105 */ 1106 bus_space_write_1(t, mr, QE_MRI_IAC, 1107 QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR); 1108 bus_space_set_multi_1(t, mr, QE_MRI_LADRF, 0, 8); 1109 bus_space_write_1(t, mr, QE_MRI_IAC, 0); 1110 1111 /* Clear missed packet count (register cleared on read) */ 1112 (void)bus_space_read_1(t, mr, QE_MRI_MPC); 1113 1114 #if 0 1115 /* test register: */ 1116 bus_space_write_1(t, mr, QE_MRI_UTR, 0); 1117 #endif 1118 1119 /* Reset multicast filter */ 1120 qe_mcreset(sc); 1121 1122 ifp->if_flags |= IFF_RUNNING; 1123 ifp->if_flags &= ~IFF_OACTIVE; 1124 splx(s); 1125 } 1126 1127 /* 1128 * Reset multicast filter. 1129 */ 1130 void 1131 qe_mcreset(sc) 1132 struct qe_softc *sc; 1133 { 1134 struct ethercom *ec = &sc->sc_ethercom; 1135 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1136 bus_space_tag_t t = sc->sc_bustag; 1137 bus_space_handle_t mr = sc->sc_mr; 1138 struct ether_multi *enm; 1139 struct ether_multistep step; 1140 u_int32_t crc; 1141 u_int16_t hash[4]; 1142 u_int8_t octet, maccc, *ladrp = (u_int8_t *)&hash[0]; 1143 int i, j; 1144 1145 #if defined(SUN4U) || defined(__GNUC__) 1146 (void)&t; 1147 #endif 1148 1149 /* We also enable transmitter & receiver here */ 1150 maccc = QE_MR_MACCC_ENXMT | QE_MR_MACCC_ENRCV; 1151 1152 if (ifp->if_flags & IFF_PROMISC) { 1153 maccc |= QE_MR_MACCC_PROM; 1154 bus_space_write_1(t, mr, QE_MRI_MACCC, maccc); 1155 return; 1156 } 1157 1158 if (ifp->if_flags & IFF_ALLMULTI) { 1159 bus_space_write_1(t, mr, QE_MRI_IAC, 1160 QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR); 1161 bus_space_set_multi_1(t, mr, QE_MRI_LADRF, 0xff, 8); 1162 bus_space_write_1(t, mr, QE_MRI_IAC, 0); 1163 bus_space_write_1(t, mr, QE_MRI_MACCC, maccc); 1164 return; 1165 } 1166 1167 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1168 1169 ETHER_FIRST_MULTI(step, ec, enm); 1170 while (enm != NULL) { 1171 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 1172 ETHER_ADDR_LEN) != 0) { 1173 /* 1174 * We must listen to a range of multicast 1175 * addresses. For now, just accept all 1176 * multicasts, rather than trying to set only 1177 * those filter bits needed to match the range. 1178 * (At this time, the only use of address 1179 * ranges is for IP multicast routing, for 1180 * which the range is big enough to require 1181 * all bits set.) 1182 */ 1183 bus_space_write_1(t, mr, QE_MRI_IAC, 1184 QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR); 1185 bus_space_set_multi_1(t, mr, QE_MRI_LADRF, 0xff, 8); 1186 bus_space_write_1(t, mr, QE_MRI_IAC, 0); 1187 ifp->if_flags |= IFF_ALLMULTI; 1188 break; 1189 } 1190 1191 crc = 0xffffffff; 1192 1193 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1194 octet = enm->enm_addrlo[i]; 1195 1196 for (j = 0; j < 8; j++) { 1197 if ((crc & 1) ^ (octet & 1)) { 1198 crc >>= 1; 1199 crc ^= MC_POLY_LE; 1200 } 1201 else 1202 crc >>= 1; 1203 octet >>= 1; 1204 } 1205 } 1206 1207 crc >>= 26; 1208 hash[crc >> 4] |= 1 << (crc & 0xf); 1209 ETHER_NEXT_MULTI(step, enm); 1210 } 1211 1212 bus_space_write_1(t, mr, QE_MRI_IAC, 1213 QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR); 1214 bus_space_write_multi_1(t, mr, QE_MRI_LADRF, ladrp, 8); 1215 bus_space_write_1(t, mr, QE_MRI_IAC, 0); 1216 bus_space_write_1(t, mr, QE_MRI_MACCC, maccc); 1217 } 1218 1219 /* 1220 * Get current media settings. 1221 */ 1222 void 1223 qe_ifmedia_sts(ifp, ifmr) 1224 struct ifnet *ifp; 1225 struct ifmediareq *ifmr; 1226 { 1227 struct qe_softc *sc = ifp->if_softc; 1228 bus_space_tag_t t = sc->sc_bustag; 1229 bus_space_handle_t mr = sc->sc_mr; 1230 u_int8_t v; 1231 1232 #if defined(SUN4U) || defined(__GNUC__) 1233 (void)&t; 1234 #endif 1235 v = bus_space_read_1(t, mr, QE_MRI_PLSCC); 1236 1237 switch (bus_space_read_1(t, mr, QE_MRI_PLSCC) & QE_MR_PLSCC_PORTMASK) { 1238 case QE_MR_PLSCC_TP: 1239 ifmr->ifm_active = IFM_ETHER | IFM_10_T; 1240 break; 1241 case QE_MR_PLSCC_AUI: 1242 ifmr->ifm_active = IFM_ETHER | IFM_10_5; 1243 break; 1244 case QE_MR_PLSCC_GPSI: 1245 case QE_MR_PLSCC_DAI: 1246 /* ... */ 1247 break; 1248 } 1249 1250 v = bus_space_read_1(t, mr, QE_MRI_PHYCC); 1251 ifmr->ifm_status |= IFM_AVALID; 1252 if ((v & QE_MR_PHYCC_LNKFL) != 0) 1253 ifmr->ifm_status &= ~IFM_ACTIVE; 1254 else 1255 ifmr->ifm_status |= IFM_ACTIVE; 1256 1257 } 1258 1259 /* 1260 * Set media options. 1261 */ 1262 int 1263 qe_ifmedia_upd(ifp) 1264 struct ifnet *ifp; 1265 { 1266 struct qe_softc *sc = ifp->if_softc; 1267 struct ifmedia *ifm = &sc->sc_ifmedia; 1268 bus_space_tag_t t = sc->sc_bustag; 1269 bus_space_handle_t mr = sc->sc_mr; 1270 int newmedia = ifm->ifm_media; 1271 u_int8_t plscc, phycc; 1272 1273 #if defined(SUN4U) || defined(__GNUC__) 1274 (void)&t; 1275 #endif 1276 if (IFM_TYPE(newmedia) != IFM_ETHER) 1277 return (EINVAL); 1278 1279 plscc = bus_space_read_1(t, mr, QE_MRI_PLSCC) & ~QE_MR_PLSCC_PORTMASK; 1280 phycc = bus_space_read_1(t, mr, QE_MRI_PHYCC) & ~QE_MR_PHYCC_ASEL; 1281 1282 if (IFM_SUBTYPE(newmedia) == IFM_AUTO) 1283 phycc |= QE_MR_PHYCC_ASEL; 1284 else if (IFM_SUBTYPE(newmedia) == IFM_10_T) 1285 plscc |= QE_MR_PLSCC_TP; 1286 else if (IFM_SUBTYPE(newmedia) == IFM_10_5) 1287 plscc |= QE_MR_PLSCC_AUI; 1288 1289 bus_space_write_1(t, mr, QE_MRI_PLSCC, plscc); 1290 bus_space_write_1(t, mr, QE_MRI_PHYCC, phycc); 1291 1292 return (0); 1293 } 1294
Indexes created Tue Sep 30 20:09:53 GMT 2025