qe.c revision 1.7
1 /* $NetBSD: qe.c,v 1.7 1999/06/24 19:59:14 pk Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1998 Jason L. Wright. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the authors may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 59 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 63 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 */ 65 66 /* 67 * Driver for the SBus qec+qe QuadEthernet board. 68 * 69 * This driver was written using the AMD MACE Am79C940 documentation, some 70 * ideas gleaned from the S/Linux driver for this card, Solaris header files, 71 * and a loan of a card from Paul Southworth of the Internet Engineering 72 * Group (www.ieng.com). 73 */ 74 75 #define QEDEBUG 76 77 #include "opt_ddb.h" 78 #include "opt_inet.h" 79 #include "opt_ccitt.h" 80 #include "opt_llc.h" 81 #include "opt_ns.h" 82 #include "bpfilter.h" 83 #include "rnd.h" 84 85 #include <sys/param.h> 86 #include <sys/systm.h> 87 #include <sys/kernel.h> 88 #include <sys/errno.h> 89 #include <sys/ioctl.h> 90 #include <sys/mbuf.h> 91 #include <sys/socket.h> 92 #include <sys/syslog.h> 93 #include <sys/device.h> 94 #include <sys/malloc.h> 95 #if NRND > 0 96 #include <sys/rnd.h> 97 #endif 98 99 #include <net/if.h> 100 #include <net/if_dl.h> 101 #include <net/if_types.h> 102 #include <net/netisr.h> 103 #include <net/if_media.h> 104 #include <net/if_ether.h> 105 106 #ifdef INET 107 #include <netinet/in.h> 108 #include <netinet/if_inarp.h> 109 #include <netinet/in_systm.h> 110 #include <netinet/in_var.h> 111 #include <netinet/ip.h> 112 #endif 113 114 #ifdef NS 115 #include <netns/ns.h> 116 #include <netns/ns_if.h> 117 #endif 118 119 #if NBPFILTER > 0 120 #include <net/bpf.h> 121 #include <net/bpfdesc.h> 122 #endif 123 124 #include <machine/autoconf.h> 125 #include <machine/bus.h> 126 #include <machine/cpu.h> 127 128 #include <dev/sbus/sbusvar.h> 129 #include <dev/sbus/qecreg.h> 130 #include <dev/sbus/qecvar.h> 131 #include <dev/sbus/qereg.h> 132 133 struct qe_softc { 134 struct device sc_dev; /* base device */ 135 struct sbusdev sc_sd; /* sbus device */ 136 bus_space_tag_t sc_bustag; /* bus & dma tags */ 137 bus_dma_tag_t sc_dmatag; 138 struct ethercom sc_ethercom; 139 struct ifmedia sc_ifmedia; /* interface media */ 140 141 struct qec_softc *sc_qec; /* QEC parent */ 142 143 bus_space_handle_t sc_qr; /* QEC registers */ 144 bus_space_handle_t sc_mr; /* MACE registers */ 145 bus_space_handle_t sc_cr; /* channel registers */ 146 147 int sc_channel; /* channel number */ 148 u_int sc_rev; /* board revision */ 149 150 int sc_burst; 151 152 struct qec_ring sc_rb; /* Packet Ring Buffer */ 153 154 /* MAC address */ 155 u_int8_t sc_enaddr[6]; 156 157 #ifdef QEDEBUG 158 int sc_debug; 159 #endif 160 }; 161 162 int qematch __P((struct device *, struct cfdata *, void *)); 163 void qeattach __P((struct device *, struct device *, void *)); 164 165 void qeinit __P((struct qe_softc *)); 166 void qestart __P((struct ifnet *)); 167 void qestop __P((struct qe_softc *)); 168 void qewatchdog __P((struct ifnet *)); 169 int qeioctl __P((struct ifnet *, u_long, caddr_t)); 170 void qereset __P((struct qe_softc *)); 171 172 int qeintr __P((void *)); 173 int qe_eint __P((struct qe_softc *, u_int32_t)); 174 int qe_rint __P((struct qe_softc *)); 175 int qe_tint __P((struct qe_softc *)); 176 void qe_mcreset __P((struct qe_softc *)); 177 178 static int qe_put __P((struct qe_softc *, int, struct mbuf *)); 179 static void qe_read __P((struct qe_softc *, int, int)); 180 static struct mbuf *qe_get __P((struct qe_softc *, int, int)); 181 182 /* ifmedia callbacks */ 183 void qe_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 184 int qe_ifmedia_upd __P((struct ifnet *)); 185 186 struct cfattach qe_ca = { 187 sizeof(struct qe_softc), qematch, qeattach 188 }; 189 190 int 191 qematch(parent, cf, aux) 192 struct device *parent; 193 struct cfdata *cf; 194 void *aux; 195 { 196 struct sbus_attach_args *sa = aux; 197 198 return (strcmp(cf->cf_driver->cd_name, sa->sa_name) == 0); 199 } 200 201 void 202 qeattach(parent, self, aux) 203 struct device *parent, *self; 204 void *aux; 205 { 206 struct sbus_attach_args *sa = aux; 207 struct qec_softc *qec = (struct qec_softc *)parent; 208 struct qe_softc *sc = (struct qe_softc *)self; 209 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 210 int node = sa->sa_node; 211 bus_dma_segment_t seg; 212 bus_size_t size; 213 int rseg, error; 214 extern void myetheraddr __P((u_char *)); 215 216 if (sa->sa_nreg < 2) { 217 printf("%s: only %d register sets\n", 218 self->dv_xname, sa->sa_nreg); 219 return; 220 } 221 222 if (bus_space_map2(sa->sa_bustag, 223 (bus_type_t)sa->sa_reg[0].sbr_slot, 224 (bus_addr_t)sa->sa_reg[0].sbr_offset, 225 (bus_size_t)sa->sa_reg[0].sbr_size, 226 BUS_SPACE_MAP_LINEAR, 0, &sc->sc_cr) != 0) { 227 printf("%s: cannot map registers\n", self->dv_xname); 228 return; 229 } 230 231 if (bus_space_map2(sa->sa_bustag, 232 (bus_type_t)sa->sa_reg[1].sbr_slot, 233 (bus_addr_t)sa->sa_reg[1].sbr_offset, 234 (bus_size_t)sa->sa_reg[1].sbr_size, 235 BUS_SPACE_MAP_LINEAR, 0, &sc->sc_mr) != 0) { 236 printf("%s: cannot map registers\n", self->dv_xname); 237 return; 238 } 239 240 sc->sc_rev = getpropint(node, "mace-version", -1); 241 printf(" rev %x", sc->sc_rev); 242 243 sc->sc_qec = qec; 244 sc->sc_qr = qec->sc_regs; 245 246 sc->sc_channel = getpropint(node, "channel#", -1); 247 sc->sc_burst = qec->sc_burst; 248 249 qestop(sc); 250 251 /* Note: no interrupt level passed */ 252 (void)bus_intr_establish(sa->sa_bustag, 0, 0, qeintr, sc); 253 myetheraddr(sc->sc_enaddr); 254 255 /* 256 * Allocate descriptor ring and buffers. 257 */ 258 259 /* for now, allocate as many bufs as there are ring descriptors */ 260 sc->sc_rb.rb_ntbuf = QEC_XD_RING_MAXSIZE; 261 sc->sc_rb.rb_nrbuf = QEC_XD_RING_MAXSIZE; 262 263 size = QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 264 QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 265 sc->sc_rb.rb_ntbuf * QE_PKT_BUF_SZ + 266 sc->sc_rb.rb_nrbuf * QE_PKT_BUF_SZ; 267 if ((error = bus_dmamem_alloc(sa->sa_dmatag, size, 268 NBPG, 0, 269 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 270 printf("%s: DMA buffer alloc error %d\n", 271 self->dv_xname, error); 272 return; 273 } 274 sc->sc_rb.rb_dmabase = seg.ds_addr; 275 276 if ((error = bus_dmamem_map(sa->sa_dmatag, &seg, rseg, size, 277 &sc->sc_rb.rb_membase, 278 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 279 printf("%s: DMA buffer map error %d\n", 280 self->dv_xname, error); 281 bus_dmamem_free(sa->sa_dmatag, &seg, rseg); 282 return; 283 } 284 285 /* Initialize media properties */ 286 ifmedia_init(&sc->sc_ifmedia, 0, qe_ifmedia_upd, qe_ifmedia_sts); 287 ifmedia_add(&sc->sc_ifmedia, 288 IFM_MAKEWORD(IFM_ETHER,IFM_10_T,0,0), 289 0, NULL); 290 ifmedia_add(&sc->sc_ifmedia, 291 IFM_MAKEWORD(IFM_ETHER,IFM_10_5,0,0), 292 0, NULL); 293 ifmedia_add(&sc->sc_ifmedia, 294 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,0), 295 0, NULL); 296 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO); 297 298 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 299 ifp->if_softc = sc; 300 ifp->if_start = qestart; 301 ifp->if_ioctl = qeioctl; 302 ifp->if_watchdog = qewatchdog; 303 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | 304 IFF_MULTICAST; 305 306 /* Attach the interface. */ 307 if_attach(ifp); 308 ether_ifattach(ifp, sc->sc_enaddr); 309 310 printf(" address %s\n", ether_sprintf(sc->sc_enaddr)); 311 312 #if NBPFILTER > 0 313 bpfattach(&ifp->if_bpf, ifp, DLT_EN10MB, 314 sizeof(struct ether_header)); 315 #endif 316 } 317 318 /* 319 * Pull data off an interface. 320 * Len is the length of data, with local net header stripped. 321 * We copy the data into mbufs. When full cluster sized units are present, 322 * we copy into clusters. 323 */ 324 static __inline__ struct mbuf * 325 qe_get(sc, idx, totlen) 326 struct qe_softc *sc; 327 int idx, totlen; 328 { 329 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 330 struct mbuf *m; 331 struct mbuf *top, **mp; 332 int len, pad, boff = 0; 333 caddr_t bp; 334 335 bp = sc->sc_rb.rb_rxbuf + (idx % sc->sc_rb.rb_nrbuf) * QE_PKT_BUF_SZ; 336 337 MGETHDR(m, M_DONTWAIT, MT_DATA); 338 if (m == NULL) 339 return (NULL); 340 m->m_pkthdr.rcvif = ifp; 341 m->m_pkthdr.len = totlen; 342 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 343 m->m_data += pad; 344 len = MHLEN - pad; 345 top = NULL; 346 mp = ⊤ 347 348 while (totlen > 0) { 349 if (top) { 350 MGET(m, M_DONTWAIT, MT_DATA); 351 if (m == NULL) { 352 m_freem(top); 353 return (NULL); 354 } 355 len = MLEN; 356 } 357 if (top && totlen >= MINCLSIZE) { 358 MCLGET(m, M_DONTWAIT); 359 if (m->m_flags & M_EXT) 360 len = MCLBYTES; 361 } 362 m->m_len = len = min(totlen, len); 363 bcopy(bp + boff, mtod(m, caddr_t), len); 364 boff += len; 365 totlen -= len; 366 *mp = m; 367 mp = &m->m_next; 368 } 369 370 return (top); 371 } 372 373 /* 374 * Routine to copy from mbuf chain to transmit buffer in 375 * network buffer memory. 376 */ 377 __inline__ int 378 qe_put(sc, idx, m) 379 struct qe_softc *sc; 380 int idx; 381 struct mbuf *m; 382 { 383 struct mbuf *n; 384 int len, tlen = 0, boff = 0; 385 caddr_t bp; 386 387 bp = sc->sc_rb.rb_txbuf + (idx % sc->sc_rb.rb_ntbuf) * QE_PKT_BUF_SZ; 388 389 for (; m; m = n) { 390 len = m->m_len; 391 if (len == 0) { 392 MFREE(m, n); 393 continue; 394 } 395 bcopy(mtod(m, caddr_t), bp+boff, len); 396 boff += len; 397 tlen += len; 398 MFREE(m, n); 399 } 400 return (tlen); 401 } 402 403 /* 404 * Pass a packet to the higher levels. 405 */ 406 __inline__ void 407 qe_read(sc, idx, len) 408 struct qe_softc *sc; 409 int idx, len; 410 { 411 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 412 struct mbuf *m; 413 414 if (len <= sizeof(struct ether_header) || 415 len > ETHERMTU + sizeof(struct ether_header)) { 416 417 printf("%s: invalid packet size %d; dropping\n", 418 ifp->if_xname, len); 419 420 ifp->if_ierrors++; 421 return; 422 } 423 424 /* 425 * Pull packet off interface. 426 */ 427 m = qe_get(sc, idx, len); 428 if (m == NULL) { 429 ifp->if_ierrors++; 430 return; 431 } 432 ifp->if_ipackets++; 433 434 #if NBPFILTER > 0 435 /* 436 * Check if there's a BPF listener on this interface. 437 * If so, hand off the raw packet to BPF. 438 */ 439 if (ifp->if_bpf) 440 bpf_mtap(ifp->if_bpf, m); 441 #endif 442 /* Pass the packet up. */ 443 (*ifp->if_input)(ifp, m); 444 } 445 446 /* 447 * Start output on interface. 448 * We make two assumptions here: 449 * 1) that the current priority is set to splnet _before_ this code 450 * is called *and* is returned to the appropriate priority after 451 * return 452 * 2) that the IFF_OACTIVE flag is checked before this code is called 453 * (i.e. that the output part of the interface is idle) 454 */ 455 void 456 qestart(ifp) 457 struct ifnet *ifp; 458 { 459 struct qe_softc *sc = (struct qe_softc *)ifp->if_softc; 460 struct qec_xd *txd = sc->sc_rb.rb_txd; 461 struct mbuf *m; 462 unsigned int bix, len; 463 unsigned int ntbuf = sc->sc_rb.rb_ntbuf; 464 465 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 466 return; 467 468 bix = sc->sc_rb.rb_tdhead; 469 470 for (;;) { 471 IF_DEQUEUE(&ifp->if_snd, m); 472 if (m == 0) 473 break; 474 475 #if NBPFILTER > 0 476 /* 477 * If BPF is listening on this interface, let it see the 478 * packet before we commit it to the wire. 479 */ 480 if (ifp->if_bpf) 481 bpf_mtap(ifp->if_bpf, m); 482 #endif 483 484 /* 485 * Copy the mbuf chain into the transmit buffer. 486 */ 487 len = qe_put(sc, bix, m); 488 489 /* 490 * Initialize transmit registers and start transmission 491 */ 492 txd[bix].xd_flags = QEC_XD_OWN | QEC_XD_SOP | QEC_XD_EOP | 493 (len & QEC_XD_LENGTH); 494 bus_space_write_4(sc->sc_bustag, sc->sc_cr, QE_CRI_CTRL, 495 QE_CR_CTRL_TWAKEUP); 496 497 if (++bix == QEC_XD_RING_MAXSIZE) 498 bix = 0; 499 500 if (++sc->sc_rb.rb_td_nbusy == ntbuf) { 501 ifp->if_flags |= IFF_OACTIVE; 502 break; 503 } 504 } 505 506 sc->sc_rb.rb_tdhead = bix; 507 } 508 509 void 510 qestop(sc) 511 struct qe_softc *sc; 512 { 513 bus_space_tag_t t = sc->sc_bustag; 514 bus_space_handle_t mr = sc->sc_mr; 515 bus_space_handle_t cr = sc->sc_cr; 516 int n; 517 518 #if defined(SUN4U) || defined(__GNUC__) 519 (void)&t; 520 #endif 521 /* Stop the schwurst */ 522 bus_space_write_1(t, mr, QE_MRI_BIUCC, QE_MR_BIUCC_SWRST); 523 for (n = 200; n > 0; n--) { 524 if ((bus_space_read_1(t, mr, QE_MRI_BIUCC) & 525 QE_MR_BIUCC_SWRST) == 0) 526 break; 527 DELAY(20); 528 } 529 530 /* then reset */ 531 bus_space_write_4(t, cr, QE_CRI_CTRL, QE_CR_CTRL_RESET); 532 for (n = 200; n > 0; n--) { 533 if ((bus_space_read_4(t, cr, QE_CRI_CTRL) & 534 QE_CR_CTRL_RESET) == 0) 535 break; 536 DELAY(20); 537 } 538 } 539 540 /* 541 * Reset interface. 542 */ 543 void 544 qereset(sc) 545 struct qe_softc *sc; 546 { 547 int s; 548 549 s = splnet(); 550 qestop(sc); 551 qeinit(sc); 552 splx(s); 553 } 554 555 void 556 qewatchdog(ifp) 557 struct ifnet *ifp; 558 { 559 struct qe_softc *sc = ifp->if_softc; 560 561 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 562 ifp->if_oerrors++; 563 564 qereset(sc); 565 } 566 567 /* 568 * Interrupt dispatch. 569 */ 570 int 571 qeintr(arg) 572 void *arg; 573 { 574 struct qe_softc *sc = (struct qe_softc *)arg; 575 bus_space_tag_t t = sc->sc_bustag; 576 u_int32_t qecstat, qestat; 577 int r = 0; 578 579 #if defined(SUN4U) || defined(__GNUC__) 580 (void)&t; 581 #endif 582 /* Read QEC status and channel status */ 583 qecstat = bus_space_read_4(t, sc->sc_qr, QEC_QRI_STAT); 584 #ifdef QEDEBUG 585 if (sc->sc_debug) { 586 printf("qe%d: intr: qecstat=%x\n", sc->sc_channel, qecstat); 587 } 588 #endif 589 590 /* Filter out status for this channel */ 591 qecstat = qecstat >> (4 * sc->sc_channel); 592 if ((qecstat & 0xf) == 0) 593 return (r); 594 595 qestat = bus_space_read_4(t, sc->sc_cr, QE_CRI_STAT); 596 597 #ifdef QEDEBUG 598 if (sc->sc_debug) { 599 char bits[64]; int i; 600 bus_space_tag_t t = sc->sc_bustag; 601 bus_space_handle_t mr = sc->sc_mr; 602 603 printf("qe%d: intr: qestat=%s\n", sc->sc_channel, 604 bitmask_snprintf(qestat, QE_CR_STAT_BITS, bits, sizeof(bits))); 605 606 printf("MACE registers:\n"); 607 for (i = 0 ; i < 32; i++) { 608 printf(" m[%d]=%x,", i, bus_space_read_1(t, mr, i)); 609 if (((i+1) & 7) == 0) 610 printf("\n"); 611 } 612 } 613 #endif 614 615 if (qestat & QE_CR_STAT_ALLERRORS) { 616 #ifdef QEDEBUG 617 char bits[64]; 618 printf("qe%d: eint: qestat=%s\n", sc->sc_channel, 619 bitmask_snprintf(qestat, QE_CR_STAT_BITS, bits, sizeof(bits))); 620 #endif 621 r |= qe_eint(sc, qestat); 622 if (r == -1) 623 return (1); 624 } 625 626 if (qestat & QE_CR_STAT_TXIRQ) 627 r |= qe_tint(sc); 628 629 if (qestat & QE_CR_STAT_RXIRQ) 630 r |= qe_rint(sc); 631 632 return (r); 633 } 634 635 /* 636 * Transmit interrupt. 637 */ 638 int 639 qe_tint(sc) 640 struct qe_softc *sc; 641 { 642 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 643 unsigned int bix, txflags; 644 645 bix = sc->sc_rb.rb_tdtail; 646 647 for (;;) { 648 if (sc->sc_rb.rb_td_nbusy <= 0) 649 break; 650 651 txflags = sc->sc_rb.rb_txd[bix].xd_flags; 652 653 if (txflags & QEC_XD_OWN) 654 break; 655 656 ifp->if_flags &= ~IFF_OACTIVE; 657 ifp->if_opackets++; 658 659 if (++bix == QEC_XD_RING_MAXSIZE) 660 bix = 0; 661 662 --sc->sc_rb.rb_td_nbusy; 663 } 664 665 sc->sc_rb.rb_tdtail = bix; 666 667 qestart(ifp); 668 669 if (sc->sc_rb.rb_td_nbusy == 0) 670 ifp->if_timer = 0; 671 672 return (1); 673 } 674 675 /* 676 * Receive interrupt. 677 */ 678 int 679 qe_rint(sc) 680 struct qe_softc *sc; 681 { 682 struct qec_xd *xd = sc->sc_rb.rb_rxd; 683 unsigned int bix, len; 684 unsigned int nrbuf = sc->sc_rb.rb_nrbuf; 685 #ifdef QEDEBUG 686 int npackets = 0; 687 #endif 688 689 bix = sc->sc_rb.rb_rdtail; 690 691 /* 692 * Process all buffers with valid data. 693 */ 694 for (;;) { 695 len = xd[bix].xd_flags; 696 if (len & QEC_XD_OWN) 697 break; 698 699 #ifdef QEDEBUG 700 npackets++; 701 #endif 702 703 len &= QEC_XD_LENGTH; 704 len -= 4; 705 qe_read(sc, bix, len); 706 707 /* ... */ 708 xd[(bix+nrbuf) % QEC_XD_RING_MAXSIZE].xd_flags = 709 QEC_XD_OWN | (QE_PKT_BUF_SZ & QEC_XD_LENGTH); 710 711 if (++bix == QEC_XD_RING_MAXSIZE) 712 bix = 0; 713 } 714 #ifdef QEDEBUG 715 if (npackets == 0) 716 printf("%s: rint: no packets; rb index %d; status 0x%x\n", 717 sc->sc_dev.dv_xname, bix, len); 718 #endif 719 720 sc->sc_rb.rb_rdtail = bix; 721 722 return (1); 723 } 724 725 /* 726 * Error interrupt. 727 */ 728 int 729 qe_eint(sc, why) 730 struct qe_softc *sc; 731 u_int32_t why; 732 { 733 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 734 int r = 0, rst = 0; 735 736 if (why & QE_CR_STAT_EDEFER) { 737 printf("%s: excessive tx defers.\n", sc->sc_dev.dv_xname); 738 r |= 1; 739 ifp->if_oerrors++; 740 } 741 742 if (why & QE_CR_STAT_CLOSS) { 743 printf("%s: no carrier, link down?\n", sc->sc_dev.dv_xname); 744 ifp->if_oerrors++; 745 r |= 1; 746 } 747 748 if (why & QE_CR_STAT_ERETRIES) { 749 printf("%s: excessive tx retries\n", sc->sc_dev.dv_xname); 750 ifp->if_oerrors++; 751 r |= 1; 752 rst = 1; 753 } 754 755 756 if (why & QE_CR_STAT_LCOLL) { 757 printf("%s: late tx transmission\n", sc->sc_dev.dv_xname); 758 ifp->if_oerrors++; 759 r |= 1; 760 rst = 1; 761 } 762 763 if (why & QE_CR_STAT_FUFLOW) { 764 printf("%s: tx fifo underflow\n", sc->sc_dev.dv_xname); 765 ifp->if_oerrors++; 766 r |= 1; 767 rst = 1; 768 } 769 770 if (why & QE_CR_STAT_JERROR) { 771 printf("%s: jabber seen\n", sc->sc_dev.dv_xname); 772 r |= 1; 773 } 774 775 if (why & QE_CR_STAT_BERROR) { 776 printf("%s: babble seen\n", sc->sc_dev.dv_xname); 777 r |= 1; 778 } 779 780 if (why & QE_CR_STAT_TCCOFLOW) { 781 ifp->if_collisions += 256; 782 ifp->if_oerrors += 256; 783 r |= 1; 784 } 785 786 if (why & QE_CR_STAT_TXDERROR) { 787 printf("%s: tx descriptor is bad\n", sc->sc_dev.dv_xname); 788 rst = 1; 789 r |= 1; 790 } 791 792 if (why & QE_CR_STAT_TXLERR) { 793 printf("%s: tx late error\n", sc->sc_dev.dv_xname); 794 ifp->if_oerrors++; 795 rst = 1; 796 r |= 1; 797 } 798 799 if (why & QE_CR_STAT_TXPERR) { 800 printf("%s: tx dma parity error\n", sc->sc_dev.dv_xname); 801 ifp->if_oerrors++; 802 rst = 1; 803 r |= 1; 804 } 805 806 if (why & QE_CR_STAT_TXSERR) { 807 printf("%s: tx dma sbus error ack\n", sc->sc_dev.dv_xname); 808 ifp->if_oerrors++; 809 rst = 1; 810 r |= 1; 811 } 812 813 if (why & QE_CR_STAT_RCCOFLOW) { 814 ifp->if_collisions += 256; 815 ifp->if_ierrors += 256; 816 r |= 1; 817 } 818 819 if (why & QE_CR_STAT_RUOFLOW) { 820 ifp->if_ierrors += 256; 821 r |= 1; 822 } 823 824 if (why & QE_CR_STAT_MCOFLOW) { 825 ifp->if_ierrors += 256; 826 r |= 1; 827 } 828 829 if (why & QE_CR_STAT_RXFOFLOW) { 830 printf("%s: rx fifo overflow\n", sc->sc_dev.dv_xname); 831 ifp->if_ierrors++; 832 r |= 1; 833 } 834 835 if (why & QE_CR_STAT_RLCOLL) { 836 printf("%s: rx late collision\n", sc->sc_dev.dv_xname); 837 ifp->if_ierrors++; 838 ifp->if_collisions++; 839 r |= 1; 840 } 841 842 if (why & QE_CR_STAT_FCOFLOW) { 843 ifp->if_ierrors += 256; 844 r |= 1; 845 } 846 847 if (why & QE_CR_STAT_CECOFLOW) { 848 ifp->if_ierrors += 256; 849 r |= 1; 850 } 851 852 if (why & QE_CR_STAT_RXDROP) { 853 printf("%s: rx packet dropped\n", sc->sc_dev.dv_xname); 854 ifp->if_ierrors++; 855 r |= 1; 856 } 857 858 if (why & QE_CR_STAT_RXSMALL) { 859 printf("%s: rx buffer too small\n", sc->sc_dev.dv_xname); 860 ifp->if_ierrors++; 861 r |= 1; 862 rst = 1; 863 } 864 865 if (why & QE_CR_STAT_RXLERR) { 866 printf("%s: rx late error\n", sc->sc_dev.dv_xname); 867 ifp->if_ierrors++; 868 r |= 1; 869 rst = 1; 870 } 871 872 if (why & QE_CR_STAT_RXPERR) { 873 printf("%s: rx dma parity error\n", sc->sc_dev.dv_xname); 874 ifp->if_ierrors++; 875 r |= 1; 876 rst = 1; 877 } 878 879 if (why & QE_CR_STAT_RXSERR) { 880 printf("%s: rx dma sbus error ack\n", sc->sc_dev.dv_xname); 881 ifp->if_ierrors++; 882 r |= 1; 883 rst = 1; 884 } 885 886 if (r == 0) 887 printf("%s: unexpected interrupt error: %08x\n", 888 sc->sc_dev.dv_xname, why); 889 890 if (rst) { 891 printf("%s: resetting...\n", sc->sc_dev.dv_xname); 892 qereset(sc); 893 return (-1); 894 } 895 896 return (r); 897 } 898 899 int 900 qeioctl(ifp, cmd, data) 901 struct ifnet *ifp; 902 u_long cmd; 903 caddr_t data; 904 { 905 struct qe_softc *sc = ifp->if_softc; 906 struct ifaddr *ifa = (struct ifaddr *)data; 907 struct ifreq *ifr = (struct ifreq *)data; 908 int s, error = 0; 909 910 s = splnet(); 911 912 switch (cmd) { 913 case SIOCSIFADDR: 914 ifp->if_flags |= IFF_UP; 915 switch (ifa->ifa_addr->sa_family) { 916 #ifdef INET 917 case AF_INET: 918 qeinit(sc); 919 arp_ifinit(ifp, ifa); 920 break; 921 #endif /* INET */ 922 #ifdef NS 923 case AF_NS: 924 { 925 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 926 927 if (ns_nullhost(*ina)) 928 ina->x_host = 929 *(union ns_host *)LLADDR(ifp->if_sadl); 930 else 931 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 932 sizeof(sc->sc_enaddr)); 933 /* Set new address. */ 934 qeinit(sc); 935 break; 936 } 937 #endif /* NS */ 938 default: 939 qeinit(sc); 940 break; 941 } 942 break; 943 944 case SIOCSIFFLAGS: 945 if ((ifp->if_flags & IFF_UP) == 0 && 946 (ifp->if_flags & IFF_RUNNING) != 0) { 947 /* 948 * If interface is marked down and it is running, then 949 * stop it. 950 */ 951 qestop(sc); 952 ifp->if_flags &= ~IFF_RUNNING; 953 954 } else if ((ifp->if_flags & IFF_UP) != 0 && 955 (ifp->if_flags & IFF_RUNNING) == 0) { 956 /* 957 * If interface is marked up and it is stopped, then 958 * start it. 959 */ 960 qeinit(sc); 961 962 } else { 963 /* 964 * Reset the interface to pick up changes in any other 965 * flags that affect hardware registers. 966 */ 967 qestop(sc); 968 qeinit(sc); 969 } 970 #ifdef QEDEBUG 971 sc->sc_debug = (ifp->if_flags & IFF_DEBUG) != 0 ? 1 : 0; 972 #endif 973 break; 974 975 case SIOCADDMULTI: 976 case SIOCDELMULTI: 977 error = (cmd == SIOCADDMULTI) ? 978 ether_addmulti(ifr, &sc->sc_ethercom): 979 ether_delmulti(ifr, &sc->sc_ethercom); 980 981 if (error == ENETRESET) { 982 /* 983 * Multicast list has changed; set the hardware filter 984 * accordingly. 985 */ 986 qe_mcreset(sc); 987 error = 0; 988 } 989 break; 990 991 case SIOCGIFMEDIA: 992 case SIOCSIFMEDIA: 993 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, cmd); 994 break; 995 996 default: 997 error = EINVAL; 998 break; 999 } 1000 1001 splx(s); 1002 return (error); 1003 } 1004 1005 1006 void 1007 qeinit(sc) 1008 struct qe_softc *sc; 1009 { 1010 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1011 bus_space_tag_t t = sc->sc_bustag; 1012 bus_space_handle_t cr = sc->sc_cr; 1013 bus_space_handle_t mr = sc->sc_mr; 1014 struct qec_softc *qec = sc->sc_qec; 1015 u_int32_t qecaddr; 1016 u_int8_t *ea; 1017 int s; 1018 1019 #if defined(SUN4U) || defined(__GNUC__) 1020 (void)&t; 1021 #endif 1022 s = splimp(); 1023 1024 qestop(sc); 1025 1026 /* 1027 * Allocate descriptor ring and buffers 1028 */ 1029 qec_meminit(&sc->sc_rb, QE_PKT_BUF_SZ); 1030 1031 /* Channel registers: */ 1032 bus_space_write_4(t, cr, QE_CRI_RXDS, (u_int32_t)sc->sc_rb.rb_rxddma); 1033 bus_space_write_4(t, cr, QE_CRI_TXDS, (u_int32_t)sc->sc_rb.rb_txddma); 1034 1035 bus_space_write_4(t, cr, QE_CRI_RIMASK, 0); 1036 bus_space_write_4(t, cr, QE_CRI_TIMASK, 0); 1037 bus_space_write_4(t, cr, QE_CRI_QMASK, 0); 1038 bus_space_write_4(t, cr, QE_CRI_MMASK, QE_CR_MMASK_RXCOLL); 1039 bus_space_write_4(t, cr, QE_CRI_CCNT, 0); 1040 bus_space_write_4(t, cr, QE_CRI_PIPG, 0); 1041 1042 qecaddr = sc->sc_channel * qec->sc_msize; 1043 bus_space_write_4(t, cr, QE_CRI_RXWBUF, qecaddr); 1044 bus_space_write_4(t, cr, QE_CRI_RXRBUF, qecaddr); 1045 bus_space_write_4(t, cr, QE_CRI_TXWBUF, qecaddr + qec->sc_rsize); 1046 bus_space_write_4(t, cr, QE_CRI_TXRBUF, qecaddr + qec->sc_rsize); 1047 1048 /* MACE registers: */ 1049 bus_space_write_1(t, mr, QE_MRI_PHYCC, QE_MR_PHYCC_ASEL); 1050 bus_space_write_1(t, mr, QE_MRI_XMTFC, QE_MR_XMTFC_APADXMT); 1051 bus_space_write_1(t, mr, QE_MRI_RCVFC, 0); 1052 1053 /* 1054 * Mask MACE's receive interrupt, since we're being notified 1055 * by the QEC after DMA completes. 1056 */ 1057 bus_space_write_1(t, mr, QE_MRI_IMR, 1058 QE_MR_IMR_CERRM | QE_MR_IMR_RCVINTM); 1059 1060 bus_space_write_1(t, mr, QE_MRI_BIUCC, 1061 QE_MR_BIUCC_BSWAP | QE_MR_BIUCC_64TS); 1062 1063 bus_space_write_1(t, mr, QE_MRI_FIFOFC, 1064 QE_MR_FIFOCC_TXF16 | QE_MR_FIFOCC_RXF32 | 1065 QE_MR_FIFOCC_RFWU | QE_MR_FIFOCC_TFWU); 1066 1067 bus_space_write_1(t, mr, QE_MRI_PLSCC, QE_MR_PLSCC_TP); 1068 1069 /* 1070 * Station address 1071 */ 1072 ea = sc->sc_enaddr; 1073 bus_space_write_1(t, mr, QE_MRI_IAC, 1074 QE_MR_IAC_ADDRCHG | QE_MR_IAC_PHYADDR); 1075 bus_space_write_multi_1(t, mr, QE_MRI_PADR, ea, 6); 1076 1077 /* Apply media settings */ 1078 qe_ifmedia_upd(ifp); 1079 1080 /* 1081 * Clear Logical address filter 1082 */ 1083 bus_space_write_1(t, mr, QE_MRI_IAC, 1084 QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR); 1085 bus_space_set_multi_1(t, mr, QE_MRI_LADRF, 0, 8); 1086 bus_space_write_1(t, mr, QE_MRI_IAC, 0); 1087 1088 /* Clear missed packet count (register cleared on read) */ 1089 (void)bus_space_read_1(t, mr, QE_MRI_MPC); 1090 1091 #if 0 1092 /* test register: */ 1093 bus_space_write_1(t, mr, QE_MRI_UTR, 0); 1094 #endif 1095 1096 /* Reset multicast filter */ 1097 qe_mcreset(sc); 1098 1099 ifp->if_flags |= IFF_RUNNING; 1100 ifp->if_flags &= ~IFF_OACTIVE; 1101 splx(s); 1102 } 1103 1104 /* 1105 * Reset multicast filter. 1106 */ 1107 void 1108 qe_mcreset(sc) 1109 struct qe_softc *sc; 1110 { 1111 struct ethercom *ec = &sc->sc_ethercom; 1112 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1113 bus_space_tag_t t = sc->sc_bustag; 1114 bus_space_handle_t mr = sc->sc_mr; 1115 struct ether_multi *enm; 1116 struct ether_multistep step; 1117 u_int32_t crc; 1118 u_int16_t hash[4]; 1119 u_int8_t octet, maccc, *ladrp = (u_int8_t *)&hash[0]; 1120 int i, j; 1121 1122 #if defined(SUN4U) || defined(__GNUC__) 1123 (void)&t; 1124 #endif 1125 1126 /* We also enable transmitter & receiver here */ 1127 maccc = QE_MR_MACCC_ENXMT | QE_MR_MACCC_ENRCV; 1128 1129 if (ifp->if_flags & IFF_PROMISC) { 1130 maccc |= QE_MR_MACCC_PROM; 1131 bus_space_write_1(t, mr, QE_MRI_MACCC, maccc); 1132 return; 1133 } 1134 1135 if (ifp->if_flags & IFF_ALLMULTI) { 1136 bus_space_write_1(t, mr, QE_MRI_IAC, 1137 QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR); 1138 bus_space_set_multi_1(t, mr, QE_MRI_LADRF, 0xff, 8); 1139 bus_space_write_1(t, mr, QE_MRI_IAC, 0); 1140 bus_space_write_1(t, mr, QE_MRI_MACCC, maccc); 1141 return; 1142 } 1143 1144 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1145 1146 ETHER_FIRST_MULTI(step, ec, enm); 1147 while (enm != NULL) { 1148 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 1149 ETHER_ADDR_LEN) != 0) { 1150 /* 1151 * We must listen to a range of multicast 1152 * addresses. For now, just accept all 1153 * multicasts, rather than trying to set only 1154 * those filter bits needed to match the range. 1155 * (At this time, the only use of address 1156 * ranges is for IP multicast routing, for 1157 * which the range is big enough to require 1158 * all bits set.) 1159 */ 1160 bus_space_write_1(t, mr, QE_MRI_IAC, 1161 QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR); 1162 bus_space_set_multi_1(t, mr, QE_MRI_LADRF, 0xff, 8); 1163 bus_space_write_1(t, mr, QE_MRI_IAC, 0); 1164 ifp->if_flags |= IFF_ALLMULTI; 1165 break; 1166 } 1167 1168 crc = 0xffffffff; 1169 1170 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1171 octet = enm->enm_addrlo[i]; 1172 1173 for (j = 0; j < 8; j++) { 1174 if ((crc & 1) ^ (octet & 1)) { 1175 crc >>= 1; 1176 crc ^= MC_POLY_LE; 1177 } 1178 else 1179 crc >>= 1; 1180 octet >>= 1; 1181 } 1182 } 1183 1184 crc >>= 26; 1185 hash[crc >> 4] |= 1 << (crc & 0xf); 1186 ETHER_NEXT_MULTI(step, enm); 1187 } 1188 1189 bus_space_write_1(t, mr, QE_MRI_IAC, 1190 QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR); 1191 bus_space_write_multi_1(t, mr, QE_MRI_LADRF, ladrp, 8); 1192 bus_space_write_1(t, mr, QE_MRI_IAC, 0); 1193 bus_space_write_1(t, mr, QE_MRI_MACCC, maccc); 1194 } 1195 1196 /* 1197 * Get current media settings. 1198 */ 1199 void 1200 qe_ifmedia_sts(ifp, ifmr) 1201 struct ifnet *ifp; 1202 struct ifmediareq *ifmr; 1203 { 1204 struct qe_softc *sc = ifp->if_softc; 1205 bus_space_tag_t t = sc->sc_bustag; 1206 bus_space_handle_t mr = sc->sc_mr; 1207 u_int8_t v; 1208 1209 #if defined(SUN4U) || defined(__GNUC__) 1210 (void)&t; 1211 #endif 1212 v = bus_space_read_1(t, mr, QE_MRI_PLSCC); 1213 1214 switch (bus_space_read_1(t, mr, QE_MRI_PLSCC) & QE_MR_PLSCC_PORTMASK) { 1215 case QE_MR_PLSCC_TP: 1216 ifmr->ifm_active = IFM_ETHER | IFM_10_T; 1217 break; 1218 case QE_MR_PLSCC_AUI: 1219 ifmr->ifm_active = IFM_ETHER | IFM_10_5; 1220 break; 1221 case QE_MR_PLSCC_GPSI: 1222 case QE_MR_PLSCC_DAI: 1223 /* ... */ 1224 break; 1225 } 1226 1227 v = bus_space_read_1(t, mr, QE_MRI_PHYCC); 1228 ifmr->ifm_status |= IFM_AVALID; 1229 if ((v & QE_MR_PHYCC_LNKFL) != 0) 1230 ifmr->ifm_status &= ~IFM_ACTIVE; 1231 else 1232 ifmr->ifm_status |= IFM_ACTIVE; 1233 1234 } 1235 1236 /* 1237 * Set media options. 1238 */ 1239 int 1240 qe_ifmedia_upd(ifp) 1241 struct ifnet *ifp; 1242 { 1243 struct qe_softc *sc = ifp->if_softc; 1244 struct ifmedia *ifm = &sc->sc_ifmedia; 1245 bus_space_tag_t t = sc->sc_bustag; 1246 bus_space_handle_t mr = sc->sc_mr; 1247 int newmedia = ifm->ifm_media; 1248 u_int8_t plscc, phycc; 1249 1250 #if defined(SUN4U) || defined(__GNUC__) 1251 (void)&t; 1252 #endif 1253 if (IFM_TYPE(newmedia) != IFM_ETHER) 1254 return (EINVAL); 1255 1256 plscc = bus_space_read_1(t, mr, QE_MRI_PLSCC) & ~QE_MR_PLSCC_PORTMASK; 1257 phycc = bus_space_read_1(t, mr, QE_MRI_PHYCC) & ~QE_MR_PHYCC_ASEL; 1258 1259 if (IFM_SUBTYPE(newmedia) == IFM_AUTO) 1260 phycc |= QE_MR_PHYCC_ASEL; 1261 else if (IFM_SUBTYPE(newmedia) == IFM_10_T) 1262 plscc |= QE_MR_PLSCC_TP; 1263 else if (IFM_SUBTYPE(newmedia) == IFM_10_5) 1264 plscc |= QE_MR_PLSCC_AUI; 1265 1266 bus_space_write_1(t, mr, QE_MRI_PLSCC, plscc); 1267 bus_space_write_1(t, mr, QE_MRI_PHYCC, phycc); 1268 1269 return (0); 1270 } 1271
Indexes created Tue Sep 30 20:09:53 GMT 2025