qe.c revision 1.9
1 /* $NetBSD: qe.c,v 1.9 2000/05/10 14:16:11 pk Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1998 Jason L. Wright. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the authors may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 59 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 63 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 */ 65 66 /* 67 * Driver for the SBus qec+qe QuadEthernet board. 68 * 69 * This driver was written using the AMD MACE Am79C940 documentation, some 70 * ideas gleaned from the S/Linux driver for this card, Solaris header files, 71 * and a loan of a card from Paul Southworth of the Internet Engineering 72 * Group (www.ieng.com). 73 */ 74 75 #define QEDEBUG 76 77 #include "opt_ddb.h" 78 #include "opt_inet.h" 79 #include "opt_ccitt.h" 80 #include "opt_llc.h" 81 #include "opt_ns.h" 82 #include "bpfilter.h" 83 #include "rnd.h" 84 85 #include <sys/param.h> 86 #include <sys/systm.h> 87 #include <sys/kernel.h> 88 #include <sys/errno.h> 89 #include <sys/ioctl.h> 90 #include <sys/mbuf.h> 91 #include <sys/socket.h> 92 #include <sys/syslog.h> 93 #include <sys/device.h> 94 #include <sys/malloc.h> 95 #if NRND > 0 96 #include <sys/rnd.h> 97 #endif 98 99 #include <net/if.h> 100 #include <net/if_dl.h> 101 #include <net/if_types.h> 102 #include <net/netisr.h> 103 #include <net/if_media.h> 104 #include <net/if_ether.h> 105 106 #ifdef INET 107 #include <netinet/in.h> 108 #include <netinet/if_inarp.h> 109 #include <netinet/in_systm.h> 110 #include <netinet/in_var.h> 111 #include <netinet/ip.h> 112 #endif 113 114 #ifdef NS 115 #include <netns/ns.h> 116 #include <netns/ns_if.h> 117 #endif 118 119 #if NBPFILTER > 0 120 #include <net/bpf.h> 121 #include <net/bpfdesc.h> 122 #endif 123 124 #include <machine/autoconf.h> 125 #include <machine/bus.h> 126 #include <machine/cpu.h> 127 128 #include <dev/sbus/sbusvar.h> 129 #include <dev/sbus/qecreg.h> 130 #include <dev/sbus/qecvar.h> 131 #include <dev/sbus/qereg.h> 132 133 struct qe_softc { 134 struct device sc_dev; /* base device */ 135 struct sbusdev sc_sd; /* sbus device */ 136 bus_space_tag_t sc_bustag; /* bus & dma tags */ 137 bus_dma_tag_t sc_dmatag; 138 bus_dmamap_t sc_dmamap; 139 struct ethercom sc_ethercom; 140 struct ifmedia sc_ifmedia; /* interface media */ 141 142 struct qec_softc *sc_qec; /* QEC parent */ 143 144 bus_space_handle_t sc_qr; /* QEC registers */ 145 bus_space_handle_t sc_mr; /* MACE registers */ 146 bus_space_handle_t sc_cr; /* channel registers */ 147 148 int sc_channel; /* channel number */ 149 u_int sc_rev; /* board revision */ 150 151 int sc_burst; 152 153 struct qec_ring sc_rb; /* Packet Ring Buffer */ 154 155 /* MAC address */ 156 u_int8_t sc_enaddr[6]; 157 158 #ifdef QEDEBUG 159 int sc_debug; 160 #endif 161 }; 162 163 int qematch __P((struct device *, struct cfdata *, void *)); 164 void qeattach __P((struct device *, struct device *, void *)); 165 166 void qeinit __P((struct qe_softc *)); 167 void qestart __P((struct ifnet *)); 168 void qestop __P((struct qe_softc *)); 169 void qewatchdog __P((struct ifnet *)); 170 int qeioctl __P((struct ifnet *, u_long, caddr_t)); 171 void qereset __P((struct qe_softc *)); 172 173 int qeintr __P((void *)); 174 int qe_eint __P((struct qe_softc *, u_int32_t)); 175 int qe_rint __P((struct qe_softc *)); 176 int qe_tint __P((struct qe_softc *)); 177 void qe_mcreset __P((struct qe_softc *)); 178 179 static int qe_put __P((struct qe_softc *, int, struct mbuf *)); 180 static void qe_read __P((struct qe_softc *, int, int)); 181 static struct mbuf *qe_get __P((struct qe_softc *, int, int)); 182 183 /* ifmedia callbacks */ 184 void qe_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 185 int qe_ifmedia_upd __P((struct ifnet *)); 186 187 struct cfattach qe_ca = { 188 sizeof(struct qe_softc), qematch, qeattach 189 }; 190 191 int 192 qematch(parent, cf, aux) 193 struct device *parent; 194 struct cfdata *cf; 195 void *aux; 196 { 197 struct sbus_attach_args *sa = aux; 198 199 return (strcmp(cf->cf_driver->cd_name, sa->sa_name) == 0); 200 } 201 202 void 203 qeattach(parent, self, aux) 204 struct device *parent, *self; 205 void *aux; 206 { 207 struct sbus_attach_args *sa = aux; 208 struct qec_softc *qec = (struct qec_softc *)parent; 209 struct qe_softc *sc = (struct qe_softc *)self; 210 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 211 int node = sa->sa_node; 212 bus_dma_tag_t dmatag = sa->sa_dmatag; 213 bus_dma_segment_t seg; 214 bus_size_t size; 215 int rseg, error; 216 extern void myetheraddr __P((u_char *)); 217 218 if (sa->sa_nreg < 2) { 219 printf("%s: only %d register sets\n", 220 self->dv_xname, sa->sa_nreg); 221 return; 222 } 223 224 if (bus_space_map2(sa->sa_bustag, 225 (bus_type_t)sa->sa_reg[0].sbr_slot, 226 (bus_addr_t)sa->sa_reg[0].sbr_offset, 227 (bus_size_t)sa->sa_reg[0].sbr_size, 228 BUS_SPACE_MAP_LINEAR, 0, &sc->sc_cr) != 0) { 229 printf("%s: cannot map registers\n", self->dv_xname); 230 return; 231 } 232 233 if (bus_space_map2(sa->sa_bustag, 234 (bus_type_t)sa->sa_reg[1].sbr_slot, 235 (bus_addr_t)sa->sa_reg[1].sbr_offset, 236 (bus_size_t)sa->sa_reg[1].sbr_size, 237 BUS_SPACE_MAP_LINEAR, 0, &sc->sc_mr) != 0) { 238 printf("%s: cannot map registers\n", self->dv_xname); 239 return; 240 } 241 242 sc->sc_rev = getpropint(node, "mace-version", -1); 243 printf(" rev %x", sc->sc_rev); 244 245 sc->sc_qec = qec; 246 sc->sc_qr = qec->sc_regs; 247 248 sc->sc_channel = getpropint(node, "channel#", -1); 249 sc->sc_burst = qec->sc_burst; 250 251 qestop(sc); 252 253 /* Note: no interrupt level passed */ 254 (void)bus_intr_establish(sa->sa_bustag, 0, 0, qeintr, sc); 255 myetheraddr(sc->sc_enaddr); 256 257 /* 258 * Allocate descriptor ring and buffers. 259 */ 260 261 /* for now, allocate as many bufs as there are ring descriptors */ 262 sc->sc_rb.rb_ntbuf = QEC_XD_RING_MAXSIZE; 263 sc->sc_rb.rb_nrbuf = QEC_XD_RING_MAXSIZE; 264 265 size = QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 266 QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 267 sc->sc_rb.rb_ntbuf * QE_PKT_BUF_SZ + 268 sc->sc_rb.rb_nrbuf * QE_PKT_BUF_SZ; 269 270 /* Get a DMA handle */ 271 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0, 272 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 273 printf("%s: DMA map create error %d\n", self->dv_xname, error); 274 return; 275 } 276 277 /* Allocate DMA buffer */ 278 if ((error = bus_dmamem_alloc(dmatag, size, 279 NBPG, 0, 280 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 281 printf("%s: DMA buffer alloc error %d\n", 282 self->dv_xname, error); 283 return; 284 } 285 286 /* Load the buffer */ 287 if ((error = bus_dmamap_load_raw(dmatag, sc->sc_dmamap, 288 &seg, rseg, size, BUS_DMA_NOWAIT)) != 0) { 289 printf("%s: DMA buffer map load error %d\n", 290 self->dv_xname, error); 291 bus_dmamem_free(dmatag, &seg, rseg); 292 return; 293 } 294 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 295 296 /* Map DMA buffer in CPU addressable space */ 297 if ((error = bus_dmamem_map(dmatag, &seg, rseg, size, 298 &sc->sc_rb.rb_membase, 299 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 300 printf("%s: DMA buffer map error %d\n", 301 self->dv_xname, error); 302 bus_dmamap_unload(dmatag, sc->sc_dmamap); 303 bus_dmamem_free(dmatag, &seg, rseg); 304 return; 305 } 306 307 /* Initialize media properties */ 308 ifmedia_init(&sc->sc_ifmedia, 0, qe_ifmedia_upd, qe_ifmedia_sts); 309 ifmedia_add(&sc->sc_ifmedia, 310 IFM_MAKEWORD(IFM_ETHER,IFM_10_T,0,0), 311 0, NULL); 312 ifmedia_add(&sc->sc_ifmedia, 313 IFM_MAKEWORD(IFM_ETHER,IFM_10_5,0,0), 314 0, NULL); 315 ifmedia_add(&sc->sc_ifmedia, 316 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,0), 317 0, NULL); 318 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO); 319 320 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 321 ifp->if_softc = sc; 322 ifp->if_start = qestart; 323 ifp->if_ioctl = qeioctl; 324 ifp->if_watchdog = qewatchdog; 325 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | 326 IFF_MULTICAST; 327 328 /* Attach the interface. */ 329 if_attach(ifp); 330 ether_ifattach(ifp, sc->sc_enaddr); 331 332 printf(" address %s\n", ether_sprintf(sc->sc_enaddr)); 333 334 #if NBPFILTER > 0 335 bpfattach(&ifp->if_bpf, ifp, DLT_EN10MB, 336 sizeof(struct ether_header)); 337 #endif 338 } 339 340 /* 341 * Pull data off an interface. 342 * Len is the length of data, with local net header stripped. 343 * We copy the data into mbufs. When full cluster sized units are present, 344 * we copy into clusters. 345 */ 346 static __inline__ struct mbuf * 347 qe_get(sc, idx, totlen) 348 struct qe_softc *sc; 349 int idx, totlen; 350 { 351 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 352 struct mbuf *m; 353 struct mbuf *top, **mp; 354 int len, pad, boff = 0; 355 caddr_t bp; 356 357 bp = sc->sc_rb.rb_rxbuf + (idx % sc->sc_rb.rb_nrbuf) * QE_PKT_BUF_SZ; 358 359 MGETHDR(m, M_DONTWAIT, MT_DATA); 360 if (m == NULL) 361 return (NULL); 362 m->m_pkthdr.rcvif = ifp; 363 m->m_pkthdr.len = totlen; 364 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 365 m->m_data += pad; 366 len = MHLEN - pad; 367 top = NULL; 368 mp = ⊤ 369 370 while (totlen > 0) { 371 if (top) { 372 MGET(m, M_DONTWAIT, MT_DATA); 373 if (m == NULL) { 374 m_freem(top); 375 return (NULL); 376 } 377 len = MLEN; 378 } 379 if (top && totlen >= MINCLSIZE) { 380 MCLGET(m, M_DONTWAIT); 381 if (m->m_flags & M_EXT) 382 len = MCLBYTES; 383 } 384 m->m_len = len = min(totlen, len); 385 bcopy(bp + boff, mtod(m, caddr_t), len); 386 boff += len; 387 totlen -= len; 388 *mp = m; 389 mp = &m->m_next; 390 } 391 392 return (top); 393 } 394 395 /* 396 * Routine to copy from mbuf chain to transmit buffer in 397 * network buffer memory. 398 */ 399 __inline__ int 400 qe_put(sc, idx, m) 401 struct qe_softc *sc; 402 int idx; 403 struct mbuf *m; 404 { 405 struct mbuf *n; 406 int len, tlen = 0, boff = 0; 407 caddr_t bp; 408 409 bp = sc->sc_rb.rb_txbuf + (idx % sc->sc_rb.rb_ntbuf) * QE_PKT_BUF_SZ; 410 411 for (; m; m = n) { 412 len = m->m_len; 413 if (len == 0) { 414 MFREE(m, n); 415 continue; 416 } 417 bcopy(mtod(m, caddr_t), bp+boff, len); 418 boff += len; 419 tlen += len; 420 MFREE(m, n); 421 } 422 return (tlen); 423 } 424 425 /* 426 * Pass a packet to the higher levels. 427 */ 428 __inline__ void 429 qe_read(sc, idx, len) 430 struct qe_softc *sc; 431 int idx, len; 432 { 433 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 434 struct mbuf *m; 435 436 if (len <= sizeof(struct ether_header) || 437 len > ETHERMTU + sizeof(struct ether_header)) { 438 439 printf("%s: invalid packet size %d; dropping\n", 440 ifp->if_xname, len); 441 442 ifp->if_ierrors++; 443 return; 444 } 445 446 /* 447 * Pull packet off interface. 448 */ 449 m = qe_get(sc, idx, len); 450 if (m == NULL) { 451 ifp->if_ierrors++; 452 return; 453 } 454 ifp->if_ipackets++; 455 456 #if NBPFILTER > 0 457 /* 458 * Check if there's a BPF listener on this interface. 459 * If so, hand off the raw packet to BPF. 460 */ 461 if (ifp->if_bpf) 462 bpf_mtap(ifp->if_bpf, m); 463 #endif 464 /* Pass the packet up. */ 465 (*ifp->if_input)(ifp, m); 466 } 467 468 /* 469 * Start output on interface. 470 * We make two assumptions here: 471 * 1) that the current priority is set to splnet _before_ this code 472 * is called *and* is returned to the appropriate priority after 473 * return 474 * 2) that the IFF_OACTIVE flag is checked before this code is called 475 * (i.e. that the output part of the interface is idle) 476 */ 477 void 478 qestart(ifp) 479 struct ifnet *ifp; 480 { 481 struct qe_softc *sc = (struct qe_softc *)ifp->if_softc; 482 struct qec_xd *txd = sc->sc_rb.rb_txd; 483 struct mbuf *m; 484 unsigned int bix, len; 485 unsigned int ntbuf = sc->sc_rb.rb_ntbuf; 486 487 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 488 return; 489 490 bix = sc->sc_rb.rb_tdhead; 491 492 for (;;) { 493 IF_DEQUEUE(&ifp->if_snd, m); 494 if (m == 0) 495 break; 496 497 #if NBPFILTER > 0 498 /* 499 * If BPF is listening on this interface, let it see the 500 * packet before we commit it to the wire. 501 */ 502 if (ifp->if_bpf) 503 bpf_mtap(ifp->if_bpf, m); 504 #endif 505 506 /* 507 * Copy the mbuf chain into the transmit buffer. 508 */ 509 len = qe_put(sc, bix, m); 510 511 /* 512 * Initialize transmit registers and start transmission 513 */ 514 txd[bix].xd_flags = QEC_XD_OWN | QEC_XD_SOP | QEC_XD_EOP | 515 (len & QEC_XD_LENGTH); 516 bus_space_write_4(sc->sc_bustag, sc->sc_cr, QE_CRI_CTRL, 517 QE_CR_CTRL_TWAKEUP); 518 519 if (++bix == QEC_XD_RING_MAXSIZE) 520 bix = 0; 521 522 if (++sc->sc_rb.rb_td_nbusy == ntbuf) { 523 ifp->if_flags |= IFF_OACTIVE; 524 break; 525 } 526 } 527 528 sc->sc_rb.rb_tdhead = bix; 529 } 530 531 void 532 qestop(sc) 533 struct qe_softc *sc; 534 { 535 bus_space_tag_t t = sc->sc_bustag; 536 bus_space_handle_t mr = sc->sc_mr; 537 bus_space_handle_t cr = sc->sc_cr; 538 int n; 539 540 #if defined(SUN4U) || defined(__GNUC__) 541 (void)&t; 542 #endif 543 /* Stop the schwurst */ 544 bus_space_write_1(t, mr, QE_MRI_BIUCC, QE_MR_BIUCC_SWRST); 545 for (n = 200; n > 0; n--) { 546 if ((bus_space_read_1(t, mr, QE_MRI_BIUCC) & 547 QE_MR_BIUCC_SWRST) == 0) 548 break; 549 DELAY(20); 550 } 551 552 /* then reset */ 553 bus_space_write_4(t, cr, QE_CRI_CTRL, QE_CR_CTRL_RESET); 554 for (n = 200; n > 0; n--) { 555 if ((bus_space_read_4(t, cr, QE_CRI_CTRL) & 556 QE_CR_CTRL_RESET) == 0) 557 break; 558 DELAY(20); 559 } 560 } 561 562 /* 563 * Reset interface. 564 */ 565 void 566 qereset(sc) 567 struct qe_softc *sc; 568 { 569 int s; 570 571 s = splnet(); 572 qestop(sc); 573 qeinit(sc); 574 splx(s); 575 } 576 577 void 578 qewatchdog(ifp) 579 struct ifnet *ifp; 580 { 581 struct qe_softc *sc = ifp->if_softc; 582 583 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 584 ifp->if_oerrors++; 585 586 qereset(sc); 587 } 588 589 /* 590 * Interrupt dispatch. 591 */ 592 int 593 qeintr(arg) 594 void *arg; 595 { 596 struct qe_softc *sc = (struct qe_softc *)arg; 597 bus_space_tag_t t = sc->sc_bustag; 598 u_int32_t qecstat, qestat; 599 int r = 0; 600 601 #if defined(SUN4U) || defined(__GNUC__) 602 (void)&t; 603 #endif 604 /* Read QEC status and channel status */ 605 qecstat = bus_space_read_4(t, sc->sc_qr, QEC_QRI_STAT); 606 #ifdef QEDEBUG 607 if (sc->sc_debug) { 608 printf("qe%d: intr: qecstat=%x\n", sc->sc_channel, qecstat); 609 } 610 #endif 611 612 /* Filter out status for this channel */ 613 qecstat = qecstat >> (4 * sc->sc_channel); 614 if ((qecstat & 0xf) == 0) 615 return (r); 616 617 qestat = bus_space_read_4(t, sc->sc_cr, QE_CRI_STAT); 618 619 #ifdef QEDEBUG 620 if (sc->sc_debug) { 621 char bits[64]; int i; 622 bus_space_tag_t t = sc->sc_bustag; 623 bus_space_handle_t mr = sc->sc_mr; 624 625 printf("qe%d: intr: qestat=%s\n", sc->sc_channel, 626 bitmask_snprintf(qestat, QE_CR_STAT_BITS, bits, sizeof(bits))); 627 628 printf("MACE registers:\n"); 629 for (i = 0 ; i < 32; i++) { 630 printf(" m[%d]=%x,", i, bus_space_read_1(t, mr, i)); 631 if (((i+1) & 7) == 0) 632 printf("\n"); 633 } 634 } 635 #endif 636 637 if (qestat & QE_CR_STAT_ALLERRORS) { 638 #ifdef QEDEBUG 639 char bits[64]; 640 printf("qe%d: eint: qestat=%s\n", sc->sc_channel, 641 bitmask_snprintf(qestat, QE_CR_STAT_BITS, bits, sizeof(bits))); 642 #endif 643 r |= qe_eint(sc, qestat); 644 if (r == -1) 645 return (1); 646 } 647 648 if (qestat & QE_CR_STAT_TXIRQ) 649 r |= qe_tint(sc); 650 651 if (qestat & QE_CR_STAT_RXIRQ) 652 r |= qe_rint(sc); 653 654 return (r); 655 } 656 657 /* 658 * Transmit interrupt. 659 */ 660 int 661 qe_tint(sc) 662 struct qe_softc *sc; 663 { 664 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 665 unsigned int bix, txflags; 666 667 bix = sc->sc_rb.rb_tdtail; 668 669 for (;;) { 670 if (sc->sc_rb.rb_td_nbusy <= 0) 671 break; 672 673 txflags = sc->sc_rb.rb_txd[bix].xd_flags; 674 675 if (txflags & QEC_XD_OWN) 676 break; 677 678 ifp->if_flags &= ~IFF_OACTIVE; 679 ifp->if_opackets++; 680 681 if (++bix == QEC_XD_RING_MAXSIZE) 682 bix = 0; 683 684 --sc->sc_rb.rb_td_nbusy; 685 } 686 687 sc->sc_rb.rb_tdtail = bix; 688 689 qestart(ifp); 690 691 if (sc->sc_rb.rb_td_nbusy == 0) 692 ifp->if_timer = 0; 693 694 return (1); 695 } 696 697 /* 698 * Receive interrupt. 699 */ 700 int 701 qe_rint(sc) 702 struct qe_softc *sc; 703 { 704 struct qec_xd *xd = sc->sc_rb.rb_rxd; 705 unsigned int bix, len; 706 unsigned int nrbuf = sc->sc_rb.rb_nrbuf; 707 #ifdef QEDEBUG 708 int npackets = 0; 709 #endif 710 711 bix = sc->sc_rb.rb_rdtail; 712 713 /* 714 * Process all buffers with valid data. 715 */ 716 for (;;) { 717 len = xd[bix].xd_flags; 718 if (len & QEC_XD_OWN) 719 break; 720 721 #ifdef QEDEBUG 722 npackets++; 723 #endif 724 725 len &= QEC_XD_LENGTH; 726 len -= 4; 727 qe_read(sc, bix, len); 728 729 /* ... */ 730 xd[(bix+nrbuf) % QEC_XD_RING_MAXSIZE].xd_flags = 731 QEC_XD_OWN | (QE_PKT_BUF_SZ & QEC_XD_LENGTH); 732 733 if (++bix == QEC_XD_RING_MAXSIZE) 734 bix = 0; 735 } 736 #ifdef QEDEBUG 737 if (npackets == 0) 738 printf("%s: rint: no packets; rb index %d; status 0x%x\n", 739 sc->sc_dev.dv_xname, bix, len); 740 #endif 741 742 sc->sc_rb.rb_rdtail = bix; 743 744 return (1); 745 } 746 747 /* 748 * Error interrupt. 749 */ 750 int 751 qe_eint(sc, why) 752 struct qe_softc *sc; 753 u_int32_t why; 754 { 755 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 756 int r = 0, rst = 0; 757 758 if (why & QE_CR_STAT_EDEFER) { 759 printf("%s: excessive tx defers.\n", sc->sc_dev.dv_xname); 760 r |= 1; 761 ifp->if_oerrors++; 762 } 763 764 if (why & QE_CR_STAT_CLOSS) { 765 printf("%s: no carrier, link down?\n", sc->sc_dev.dv_xname); 766 ifp->if_oerrors++; 767 r |= 1; 768 } 769 770 if (why & QE_CR_STAT_ERETRIES) { 771 printf("%s: excessive tx retries\n", sc->sc_dev.dv_xname); 772 ifp->if_oerrors++; 773 r |= 1; 774 rst = 1; 775 } 776 777 778 if (why & QE_CR_STAT_LCOLL) { 779 printf("%s: late tx transmission\n", sc->sc_dev.dv_xname); 780 ifp->if_oerrors++; 781 r |= 1; 782 rst = 1; 783 } 784 785 if (why & QE_CR_STAT_FUFLOW) { 786 printf("%s: tx fifo underflow\n", sc->sc_dev.dv_xname); 787 ifp->if_oerrors++; 788 r |= 1; 789 rst = 1; 790 } 791 792 if (why & QE_CR_STAT_JERROR) { 793 printf("%s: jabber seen\n", sc->sc_dev.dv_xname); 794 r |= 1; 795 } 796 797 if (why & QE_CR_STAT_BERROR) { 798 printf("%s: babble seen\n", sc->sc_dev.dv_xname); 799 r |= 1; 800 } 801 802 if (why & QE_CR_STAT_TCCOFLOW) { 803 ifp->if_collisions += 256; 804 ifp->if_oerrors += 256; 805 r |= 1; 806 } 807 808 if (why & QE_CR_STAT_TXDERROR) { 809 printf("%s: tx descriptor is bad\n", sc->sc_dev.dv_xname); 810 rst = 1; 811 r |= 1; 812 } 813 814 if (why & QE_CR_STAT_TXLERR) { 815 printf("%s: tx late error\n", sc->sc_dev.dv_xname); 816 ifp->if_oerrors++; 817 rst = 1; 818 r |= 1; 819 } 820 821 if (why & QE_CR_STAT_TXPERR) { 822 printf("%s: tx dma parity error\n", sc->sc_dev.dv_xname); 823 ifp->if_oerrors++; 824 rst = 1; 825 r |= 1; 826 } 827 828 if (why & QE_CR_STAT_TXSERR) { 829 printf("%s: tx dma sbus error ack\n", sc->sc_dev.dv_xname); 830 ifp->if_oerrors++; 831 rst = 1; 832 r |= 1; 833 } 834 835 if (why & QE_CR_STAT_RCCOFLOW) { 836 ifp->if_collisions += 256; 837 ifp->if_ierrors += 256; 838 r |= 1; 839 } 840 841 if (why & QE_CR_STAT_RUOFLOW) { 842 ifp->if_ierrors += 256; 843 r |= 1; 844 } 845 846 if (why & QE_CR_STAT_MCOFLOW) { 847 ifp->if_ierrors += 256; 848 r |= 1; 849 } 850 851 if (why & QE_CR_STAT_RXFOFLOW) { 852 printf("%s: rx fifo overflow\n", sc->sc_dev.dv_xname); 853 ifp->if_ierrors++; 854 r |= 1; 855 } 856 857 if (why & QE_CR_STAT_RLCOLL) { 858 printf("%s: rx late collision\n", sc->sc_dev.dv_xname); 859 ifp->if_ierrors++; 860 ifp->if_collisions++; 861 r |= 1; 862 } 863 864 if (why & QE_CR_STAT_FCOFLOW) { 865 ifp->if_ierrors += 256; 866 r |= 1; 867 } 868 869 if (why & QE_CR_STAT_CECOFLOW) { 870 ifp->if_ierrors += 256; 871 r |= 1; 872 } 873 874 if (why & QE_CR_STAT_RXDROP) { 875 printf("%s: rx packet dropped\n", sc->sc_dev.dv_xname); 876 ifp->if_ierrors++; 877 r |= 1; 878 } 879 880 if (why & QE_CR_STAT_RXSMALL) { 881 printf("%s: rx buffer too small\n", sc->sc_dev.dv_xname); 882 ifp->if_ierrors++; 883 r |= 1; 884 rst = 1; 885 } 886 887 if (why & QE_CR_STAT_RXLERR) { 888 printf("%s: rx late error\n", sc->sc_dev.dv_xname); 889 ifp->if_ierrors++; 890 r |= 1; 891 rst = 1; 892 } 893 894 if (why & QE_CR_STAT_RXPERR) { 895 printf("%s: rx dma parity error\n", sc->sc_dev.dv_xname); 896 ifp->if_ierrors++; 897 r |= 1; 898 rst = 1; 899 } 900 901 if (why & QE_CR_STAT_RXSERR) { 902 printf("%s: rx dma sbus error ack\n", sc->sc_dev.dv_xname); 903 ifp->if_ierrors++; 904 r |= 1; 905 rst = 1; 906 } 907 908 if (r == 0) 909 printf("%s: unexpected interrupt error: %08x\n", 910 sc->sc_dev.dv_xname, why); 911 912 if (rst) { 913 printf("%s: resetting...\n", sc->sc_dev.dv_xname); 914 qereset(sc); 915 return (-1); 916 } 917 918 return (r); 919 } 920 921 int 922 qeioctl(ifp, cmd, data) 923 struct ifnet *ifp; 924 u_long cmd; 925 caddr_t data; 926 { 927 struct qe_softc *sc = ifp->if_softc; 928 struct ifaddr *ifa = (struct ifaddr *)data; 929 struct ifreq *ifr = (struct ifreq *)data; 930 int s, error = 0; 931 932 s = splnet(); 933 934 switch (cmd) { 935 case SIOCSIFADDR: 936 ifp->if_flags |= IFF_UP; 937 switch (ifa->ifa_addr->sa_family) { 938 #ifdef INET 939 case AF_INET: 940 qeinit(sc); 941 arp_ifinit(ifp, ifa); 942 break; 943 #endif /* INET */ 944 #ifdef NS 945 case AF_NS: 946 { 947 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 948 949 if (ns_nullhost(*ina)) 950 ina->x_host = 951 *(union ns_host *)LLADDR(ifp->if_sadl); 952 else 953 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 954 sizeof(sc->sc_enaddr)); 955 /* Set new address. */ 956 qeinit(sc); 957 break; 958 } 959 #endif /* NS */ 960 default: 961 qeinit(sc); 962 break; 963 } 964 break; 965 966 case SIOCSIFFLAGS: 967 if ((ifp->if_flags & IFF_UP) == 0 && 968 (ifp->if_flags & IFF_RUNNING) != 0) { 969 /* 970 * If interface is marked down and it is running, then 971 * stop it. 972 */ 973 qestop(sc); 974 ifp->if_flags &= ~IFF_RUNNING; 975 976 } else if ((ifp->if_flags & IFF_UP) != 0 && 977 (ifp->if_flags & IFF_RUNNING) == 0) { 978 /* 979 * If interface is marked up and it is stopped, then 980 * start it. 981 */ 982 qeinit(sc); 983 984 } else { 985 /* 986 * Reset the interface to pick up changes in any other 987 * flags that affect hardware registers. 988 */ 989 qestop(sc); 990 qeinit(sc); 991 } 992 #ifdef QEDEBUG 993 sc->sc_debug = (ifp->if_flags & IFF_DEBUG) != 0 ? 1 : 0; 994 #endif 995 break; 996 997 case SIOCADDMULTI: 998 case SIOCDELMULTI: 999 error = (cmd == SIOCADDMULTI) ? 1000 ether_addmulti(ifr, &sc->sc_ethercom): 1001 ether_delmulti(ifr, &sc->sc_ethercom); 1002 1003 if (error == ENETRESET) { 1004 /* 1005 * Multicast list has changed; set the hardware filter 1006 * accordingly. 1007 */ 1008 qe_mcreset(sc); 1009 error = 0; 1010 } 1011 break; 1012 1013 case SIOCGIFMEDIA: 1014 case SIOCSIFMEDIA: 1015 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, cmd); 1016 break; 1017 1018 default: 1019 error = EINVAL; 1020 break; 1021 } 1022 1023 splx(s); 1024 return (error); 1025 } 1026 1027 1028 void 1029 qeinit(sc) 1030 struct qe_softc *sc; 1031 { 1032 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1033 bus_space_tag_t t = sc->sc_bustag; 1034 bus_space_handle_t cr = sc->sc_cr; 1035 bus_space_handle_t mr = sc->sc_mr; 1036 struct qec_softc *qec = sc->sc_qec; 1037 u_int32_t qecaddr; 1038 u_int8_t *ea; 1039 int s; 1040 1041 #if defined(SUN4U) || defined(__GNUC__) 1042 (void)&t; 1043 #endif 1044 s = splimp(); 1045 1046 qestop(sc); 1047 1048 /* 1049 * Allocate descriptor ring and buffers 1050 */ 1051 qec_meminit(&sc->sc_rb, QE_PKT_BUF_SZ); 1052 1053 /* Channel registers: */ 1054 bus_space_write_4(t, cr, QE_CRI_RXDS, (u_int32_t)sc->sc_rb.rb_rxddma); 1055 bus_space_write_4(t, cr, QE_CRI_TXDS, (u_int32_t)sc->sc_rb.rb_txddma); 1056 1057 bus_space_write_4(t, cr, QE_CRI_RIMASK, 0); 1058 bus_space_write_4(t, cr, QE_CRI_TIMASK, 0); 1059 bus_space_write_4(t, cr, QE_CRI_QMASK, 0); 1060 bus_space_write_4(t, cr, QE_CRI_MMASK, QE_CR_MMASK_RXCOLL); 1061 bus_space_write_4(t, cr, QE_CRI_CCNT, 0); 1062 bus_space_write_4(t, cr, QE_CRI_PIPG, 0); 1063 1064 qecaddr = sc->sc_channel * qec->sc_msize; 1065 bus_space_write_4(t, cr, QE_CRI_RXWBUF, qecaddr); 1066 bus_space_write_4(t, cr, QE_CRI_RXRBUF, qecaddr); 1067 bus_space_write_4(t, cr, QE_CRI_TXWBUF, qecaddr + qec->sc_rsize); 1068 bus_space_write_4(t, cr, QE_CRI_TXRBUF, qecaddr + qec->sc_rsize); 1069 1070 /* MACE registers: */ 1071 bus_space_write_1(t, mr, QE_MRI_PHYCC, QE_MR_PHYCC_ASEL); 1072 bus_space_write_1(t, mr, QE_MRI_XMTFC, QE_MR_XMTFC_APADXMT); 1073 bus_space_write_1(t, mr, QE_MRI_RCVFC, 0); 1074 1075 /* 1076 * Mask MACE's receive interrupt, since we're being notified 1077 * by the QEC after DMA completes. 1078 */ 1079 bus_space_write_1(t, mr, QE_MRI_IMR, 1080 QE_MR_IMR_CERRM | QE_MR_IMR_RCVINTM); 1081 1082 bus_space_write_1(t, mr, QE_MRI_BIUCC, 1083 QE_MR_BIUCC_BSWAP | QE_MR_BIUCC_64TS); 1084 1085 bus_space_write_1(t, mr, QE_MRI_FIFOFC, 1086 QE_MR_FIFOCC_TXF16 | QE_MR_FIFOCC_RXF32 | 1087 QE_MR_FIFOCC_RFWU | QE_MR_FIFOCC_TFWU); 1088 1089 bus_space_write_1(t, mr, QE_MRI_PLSCC, QE_MR_PLSCC_TP); 1090 1091 /* 1092 * Station address 1093 */ 1094 ea = sc->sc_enaddr; 1095 bus_space_write_1(t, mr, QE_MRI_IAC, 1096 QE_MR_IAC_ADDRCHG | QE_MR_IAC_PHYADDR); 1097 bus_space_write_multi_1(t, mr, QE_MRI_PADR, ea, 6); 1098 1099 /* Apply media settings */ 1100 qe_ifmedia_upd(ifp); 1101 1102 /* 1103 * Clear Logical address filter 1104 */ 1105 bus_space_write_1(t, mr, QE_MRI_IAC, 1106 QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR); 1107 bus_space_set_multi_1(t, mr, QE_MRI_LADRF, 0, 8); 1108 bus_space_write_1(t, mr, QE_MRI_IAC, 0); 1109 1110 /* Clear missed packet count (register cleared on read) */ 1111 (void)bus_space_read_1(t, mr, QE_MRI_MPC); 1112 1113 #if 0 1114 /* test register: */ 1115 bus_space_write_1(t, mr, QE_MRI_UTR, 0); 1116 #endif 1117 1118 /* Reset multicast filter */ 1119 qe_mcreset(sc); 1120 1121 ifp->if_flags |= IFF_RUNNING; 1122 ifp->if_flags &= ~IFF_OACTIVE; 1123 splx(s); 1124 } 1125 1126 /* 1127 * Reset multicast filter. 1128 */ 1129 void 1130 qe_mcreset(sc) 1131 struct qe_softc *sc; 1132 { 1133 struct ethercom *ec = &sc->sc_ethercom; 1134 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1135 bus_space_tag_t t = sc->sc_bustag; 1136 bus_space_handle_t mr = sc->sc_mr; 1137 struct ether_multi *enm; 1138 struct ether_multistep step; 1139 u_int32_t crc; 1140 u_int16_t hash[4]; 1141 u_int8_t octet, maccc, *ladrp = (u_int8_t *)&hash[0]; 1142 int i, j; 1143 1144 #if defined(SUN4U) || defined(__GNUC__) 1145 (void)&t; 1146 #endif 1147 1148 /* We also enable transmitter & receiver here */ 1149 maccc = QE_MR_MACCC_ENXMT | QE_MR_MACCC_ENRCV; 1150 1151 if (ifp->if_flags & IFF_PROMISC) { 1152 maccc |= QE_MR_MACCC_PROM; 1153 bus_space_write_1(t, mr, QE_MRI_MACCC, maccc); 1154 return; 1155 } 1156 1157 if (ifp->if_flags & IFF_ALLMULTI) { 1158 bus_space_write_1(t, mr, QE_MRI_IAC, 1159 QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR); 1160 bus_space_set_multi_1(t, mr, QE_MRI_LADRF, 0xff, 8); 1161 bus_space_write_1(t, mr, QE_MRI_IAC, 0); 1162 bus_space_write_1(t, mr, QE_MRI_MACCC, maccc); 1163 return; 1164 } 1165 1166 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1167 1168 ETHER_FIRST_MULTI(step, ec, enm); 1169 while (enm != NULL) { 1170 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 1171 ETHER_ADDR_LEN) != 0) { 1172 /* 1173 * We must listen to a range of multicast 1174 * addresses. For now, just accept all 1175 * multicasts, rather than trying to set only 1176 * those filter bits needed to match the range. 1177 * (At this time, the only use of address 1178 * ranges is for IP multicast routing, for 1179 * which the range is big enough to require 1180 * all bits set.) 1181 */ 1182 bus_space_write_1(t, mr, QE_MRI_IAC, 1183 QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR); 1184 bus_space_set_multi_1(t, mr, QE_MRI_LADRF, 0xff, 8); 1185 bus_space_write_1(t, mr, QE_MRI_IAC, 0); 1186 ifp->if_flags |= IFF_ALLMULTI; 1187 break; 1188 } 1189 1190 crc = 0xffffffff; 1191 1192 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1193 octet = enm->enm_addrlo[i]; 1194 1195 for (j = 0; j < 8; j++) { 1196 if ((crc & 1) ^ (octet & 1)) { 1197 crc >>= 1; 1198 crc ^= MC_POLY_LE; 1199 } 1200 else 1201 crc >>= 1; 1202 octet >>= 1; 1203 } 1204 } 1205 1206 crc >>= 26; 1207 hash[crc >> 4] |= 1 << (crc & 0xf); 1208 ETHER_NEXT_MULTI(step, enm); 1209 } 1210 1211 bus_space_write_1(t, mr, QE_MRI_IAC, 1212 QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR); 1213 bus_space_write_multi_1(t, mr, QE_MRI_LADRF, ladrp, 8); 1214 bus_space_write_1(t, mr, QE_MRI_IAC, 0); 1215 bus_space_write_1(t, mr, QE_MRI_MACCC, maccc); 1216 } 1217 1218 /* 1219 * Get current media settings. 1220 */ 1221 void 1222 qe_ifmedia_sts(ifp, ifmr) 1223 struct ifnet *ifp; 1224 struct ifmediareq *ifmr; 1225 { 1226 struct qe_softc *sc = ifp->if_softc; 1227 bus_space_tag_t t = sc->sc_bustag; 1228 bus_space_handle_t mr = sc->sc_mr; 1229 u_int8_t v; 1230 1231 #if defined(SUN4U) || defined(__GNUC__) 1232 (void)&t; 1233 #endif 1234 v = bus_space_read_1(t, mr, QE_MRI_PLSCC); 1235 1236 switch (bus_space_read_1(t, mr, QE_MRI_PLSCC) & QE_MR_PLSCC_PORTMASK) { 1237 case QE_MR_PLSCC_TP: 1238 ifmr->ifm_active = IFM_ETHER | IFM_10_T; 1239 break; 1240 case QE_MR_PLSCC_AUI: 1241 ifmr->ifm_active = IFM_ETHER | IFM_10_5; 1242 break; 1243 case QE_MR_PLSCC_GPSI: 1244 case QE_MR_PLSCC_DAI: 1245 /* ... */ 1246 break; 1247 } 1248 1249 v = bus_space_read_1(t, mr, QE_MRI_PHYCC); 1250 ifmr->ifm_status |= IFM_AVALID; 1251 if ((v & QE_MR_PHYCC_LNKFL) != 0) 1252 ifmr->ifm_status &= ~IFM_ACTIVE; 1253 else 1254 ifmr->ifm_status |= IFM_ACTIVE; 1255 1256 } 1257 1258 /* 1259 * Set media options. 1260 */ 1261 int 1262 qe_ifmedia_upd(ifp) 1263 struct ifnet *ifp; 1264 { 1265 struct qe_softc *sc = ifp->if_softc; 1266 struct ifmedia *ifm = &sc->sc_ifmedia; 1267 bus_space_tag_t t = sc->sc_bustag; 1268 bus_space_handle_t mr = sc->sc_mr; 1269 int newmedia = ifm->ifm_media; 1270 u_int8_t plscc, phycc; 1271 1272 #if defined(SUN4U) || defined(__GNUC__) 1273 (void)&t; 1274 #endif 1275 if (IFM_TYPE(newmedia) != IFM_ETHER) 1276 return (EINVAL); 1277 1278 plscc = bus_space_read_1(t, mr, QE_MRI_PLSCC) & ~QE_MR_PLSCC_PORTMASK; 1279 phycc = bus_space_read_1(t, mr, QE_MRI_PHYCC) & ~QE_MR_PHYCC_ASEL; 1280 1281 if (IFM_SUBTYPE(newmedia) == IFM_AUTO) 1282 phycc |= QE_MR_PHYCC_ASEL; 1283 else if (IFM_SUBTYPE(newmedia) == IFM_10_T) 1284 plscc |= QE_MR_PLSCC_TP; 1285 else if (IFM_SUBTYPE(newmedia) == IFM_10_5) 1286 plscc |= QE_MR_PLSCC_AUI; 1287 1288 bus_space_write_1(t, mr, QE_MRI_PLSCC, plscc); 1289 bus_space_write_1(t, mr, QE_MRI_PHYCC, phycc); 1290 1291 return (0); 1292 } 1293
Indexes created Tue Sep 30 20:09:53 GMT 2025