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qecreg.h revision 1.1 
      1 /*	$NetBSD: qecreg.h,v 1.1 1998/07/27 19:27:19 pk Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 1998 Theo de Raadt.  All rights reserved.
      5  *
      6  * Redistribution and use in source and binary forms, with or without
      7  * modification, are permitted provided that the following conditions
      8  * are met:
      9  * 1. Redistributions of source code must retain the above copyright
     10  *    notice, this list of conditions and the following disclaimer.
     11  * 2. Redistributions in binary form must reproduce the above copyright
     12  *    notice, this list of conditions and the following disclaimer in the
     13  *    documentation and/or other materials provided with the distribution.
     14  * 3. The name of the author may not be used to endorse or promote products
     15  *    derived from this software without specific prior written permission.
     16  *
     17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     19  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     20  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     22  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     26  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     27  */
     28 
     29 /* QEC registers */
     30 struct qecregs {
     31 	volatile u_int32_t ctrl;		/* control */
     32 	volatile u_int32_t stat;		/* status */
     33 	volatile u_int32_t psize;		/* packet size */
     34 	volatile u_int32_t msize;		/* local-mem size (64K) */
     35 	volatile u_int32_t rsize;		/* receive partition size */
     36 	volatile u_int32_t tsize;		/* transmit partition size */
     37 };
     38 
     39 #define QEC_CTRL_MMODE		0x40000000	/* MACE qec mode */
     40 #define QEC_CTRL_BMODE		0x10000000	/* BE qec mode */
     41 #define QEC_CTRL_EPAR		0x00000020	/* enable parity */
     42 #define QEC_CTRL_ACNTRL		0x00000018	/* sbus arbitration control */
     43 #define QEC_CTRL_B64		0x00000004	/* 64 byte dvma bursts */
     44 #define QEC_CTRL_B32		0x00000002	/* 32 byte dvma bursts */
     45 #define QEC_CTRL_B16		0x00000000	/* 16 byte dvma bursts */
     46 #define QEC_CTRL_RESET		0x00000001	/* reset the qec */
     47 
     48 #define QEC_STAT_TX		0x00000008	/* bigmac transmit irq */
     49 #define QEC_STAT_RX		0x00000004	/* bigmac receive irq */
     50 #define QEC_STAT_BM		0x00000002	/* bigmac qec irq */
     51 #define QEC_STAT_ER		0x00000001	/* bigmac error irq */
     52 
     53 #define QEC_PSIZE_2048		0x00		/* 2k packet size */
     54 #define QEC_PSIZE_4096		0x01		/* 4k packet size */
     55 #define QEC_PSIZE_6144		0x10		/* 6k packet size */
     56 #define QEC_PSIZE_8192		0x11		/* 8k packet size */
     57