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qecreg.h revision 1.3 
      1 /*	$NetBSD: qecreg.h,v 1.3 2008/04/28 20:23:57 martin Exp $	*/
      2 
      3 /*-
      4  * Copyright (c) 1998 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by Paul Kranenburg.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  *
     19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29  * POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 /*
     33  * Copyright (c) 1998 Theo de Raadt and Jason L. Wright.
     34  * All rights reserved.
     35  *
     36  * Redistribution and use in source and binary forms, with or without
     37  * modification, are permitted provided that the following conditions
     38  * are met:
     39  * 1. Redistributions of source code must retain the above copyright
     40  *    notice, this list of conditions and the following disclaimer.
     41  * 2. Redistributions in binary form must reproduce the above copyright
     42  *    notice, this list of conditions and the following disclaimer in the
     43  *    documentation and/or other materials provided with the distribution.
     44  * 3. The name of the authors may not be used to endorse or promote products
     45  *    derived from this software without specific prior written permission.
     46  *
     47  * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR
     48  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     49  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     50  * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
     51  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     52  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     53  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     54  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     55  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     56  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     57  */
     58 
     59 /*
     60  * QEC registers layout
     61  *-
     62 struct qecregs {
     63 	u_int32_t	qec_ctrl;	// control
     64 	u_int32_t	qec_stat;	// status
     65 	u_int32_t	qec_psize;	// packet size
     66 	u_int32_t	qec_msize;	// local-mem size (64K)
     67 	u_int32_t	qec_rsize;	// receive partition size
     68 	u_int32_t	qec_tsize;	// transmit partition size
     69 };
     70  */
     71 #define QEC_QRI_CTRL	(0*4)
     72 #define QEC_QRI_STAT	(1*4)
     73 #define QEC_QRI_PSIZE	(2*4)
     74 #define QEC_QRI_MSIZE	(3*4)
     75 #define QEC_QRI_RSIZE	(4*4)
     76 #define QEC_QRI_TSIZE	(5*4)
     77 
     78 #define QEC_CTRL_MODEMASK	0xf0000000	/* QEC mode: */
     79 #define  QEC_CTRL_MMODE		0x40000000	/*   MACE qec mode */
     80 #define  QEC_CTRL_BMODE		0x10000000	/*   BE qec mode */
     81 #define QEC_CTRL_EPAR		0x00000020	/* enable parity */
     82 #define QEC_CTRL_ACNTRL		0x00000018	/* sbus arbitration control */
     83 #define QEC_CTRL_B64		0x00000004	/* 64 byte dvma bursts */
     84 #define QEC_CTRL_B32		0x00000002	/* 32 byte dvma bursts */
     85 #define QEC_CTRL_B16		0x00000000	/* 16 byte dvma bursts */
     86 #define QEC_CTRL_RESET		0x00000001	/* reset the qec */
     87 
     88 #define QEC_STAT_TX		0x00000008	/* bigmac transmit irq */
     89 #define QEC_STAT_RX		0x00000004	/* bigmac receive irq */
     90 #define QEC_STAT_BM		0x00000002	/* bigmac qec irq */
     91 #define QEC_STAT_ER		0x00000001	/* bigmac error irq */
     92 
     93 #define QEC_PSIZE_2048		0x00		/* 2k packet size */
     94 #define QEC_PSIZE_4096		0x01		/* 4k packet size */
     95 #define QEC_PSIZE_6144		0x10		/* 6k packet size */
     96 #define QEC_PSIZE_8192		0x11		/* 8k packet size */
     97 
     98 
     99 
    100 /*
    101  * Transmit & receive buffer descriptor.
    102  */
    103 struct qec_xd {
    104 	volatile u_int32_t	xd_flags;	/* see below */
    105 	volatile u_int32_t	xd_addr;	/* Buffer address (DMA) */
    106 };
    107 #define QEC_XD_OWN	0x80000000	/* ownership: 1=hw, 0=sw */
    108 #define QEC_XD_SOP	0x40000000	/* start of packet marker (xmit) */
    109 #define QEC_XD_EOP	0x20000000	/* end of packet marker (xmit) */
    110 #define QEC_XD_UPDATE	0x10000000	/* being updated? */
    111 #define QEC_XD_LENGTH	0x00001fff	/* packet length mask */
    112 /* Descriptor ring size is fixed */
    113 #define QEC_XD_RING_MAXSIZE	256		/* maximum ring size */
    114