qereg.h revision 1.1
1 /* $NetBSD: qereg.h,v 1.1 1999/01/17 20:44:18 pk Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1998 Jason L. Wright. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the authors may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 59 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 63 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 */ 65 66 /* 67 * QE Channel registers 68 *- 69 struct qe_cregs { 70 u_int32_t ctrl; // control 71 u_int32_t stat; // status 72 u_int32_t rxds; // rx descriptor ring ptr 73 u_int32_t txds; // tx descriptor ring ptr 74 u_int32_t rimask; // rx interrupt mask 75 u_int32_t timask; // tx interrupt mask 76 u_int32_t qmask; // qec error interrupt mask 77 u_int32_t mmask; // mace error interrupt mask 78 u_int32_t rxwbufptr; // local memory rx write ptr 79 u_int32_t rxrbufptr; // local memory rx read ptr 80 u_int32_t txwbufptr; // local memory tx write ptr 81 u_int32_t txrbufptr; // local memory tx read ptr 82 u_int32_t ccnt; // collision counter 83 u_int32_t pipg; // inter-frame gap 84 }; 85 * register indices: */ 86 #define QE_CRI_CTRL (0*4) 87 #define QE_CRI_STAT (1*4) 88 #define QE_CRI_RXDS (2*4) 89 #define QE_CRI_TXDS (3*4) 90 #define QE_CRI_RIMASK (4*4) 91 #define QE_CRI_TIMASK (5*4) 92 #define QE_CRI_QMASK (6*4) 93 #define QE_CRI_MMASK (7*4) 94 #define QE_CRI_RXWBUF (8*4) 95 #define QE_CRI_RXRBUF (9*4) 96 #define QE_CRI_TXWBUF (10*4) 97 #define QE_CRI_TXRBUF (11*4) 98 #define QE_CRI_CCNT (12*4) 99 #define QE_CRI_PIPG (13*4) 100 101 /* qe_cregs.ctrl: control. */ 102 #define QE_CR_CTRL_RXOFF 0x00000004 /* disable receiver */ 103 #define QE_CR_CTRL_RESET 0x00000002 /* reset this channel */ 104 #define QE_CR_CTRL_TWAKEUP 0x00000001 /* tx dma wakeup */ 105 106 /* qe_cregs.stat: status. */ 107 #define QE_CR_STAT_EDEFER 0x10000000 /* excessive defers */ 108 #define QE_CR_STAT_CLOSS 0x08000000 /* loss of carrier */ 109 #define QE_CR_STAT_ERETRIES 0x04000000 /* >16 retries */ 110 #define QE_CR_STAT_LCOLL 0x02000000 /* late tx collision */ 111 #define QE_CR_STAT_FUFLOW 0x01000000 /* fifo underflow */ 112 #define QE_CR_STAT_JERROR 0x00800000 /* jabber error */ 113 #define QE_CR_STAT_BERROR 0x00400000 /* babble error */ 114 #define QE_CR_STAT_TXIRQ 0x00200000 /* tx interrupt */ 115 #define QE_CR_STAT_TCCOFLOW 0x00100000 /* tx collision cntr expired */ 116 #define QE_CR_STAT_TXDERROR 0x00080000 /* tx descriptor is bad */ 117 #define QE_CR_STAT_TXLERR 0x00040000 /* tx late error */ 118 #define QE_CR_STAT_TXPERR 0x00020000 /* tx parity error */ 119 #define QE_CR_STAT_TXSERR 0x00010000 /* tx sbus error ack */ 120 #define QE_CR_STAT_RCCOFLOW 0x00001000 /* rx collision cntr expired */ 121 #define QE_CR_STAT_RUOFLOW 0x00000800 /* rx runt counter expired */ 122 #define QE_CR_STAT_MCOFLOW 0x00000400 /* rx missed counter expired */ 123 #define QE_CR_STAT_RXFOFLOW 0x00000200 /* rx fifo over flow */ 124 #define QE_CR_STAT_RLCOLL 0x00000100 /* rx late collision */ 125 #define QE_CR_STAT_FCOFLOW 0x00000080 /* rx frame counter expired */ 126 #define QE_CR_STAT_CECOFLOW 0x00000040 /* rx crc error cntr expired */ 127 #define QE_CR_STAT_RXIRQ 0x00000020 /* rx interrupt */ 128 #define QE_CR_STAT_RXDROP 0x00000010 /* rx dropped packet */ 129 #define QE_CR_STAT_RXSMALL 0x00000008 /* rx buffer too small */ 130 #define QE_CR_STAT_RXLERR 0x00000004 /* rx late error */ 131 #define QE_CR_STAT_RXPERR 0x00000002 /* rx parity error */ 132 #define QE_CR_STAT_RXSERR 0x00000001 /* rx sbus error ack */ 133 #define QE_CR_STAT_BITS "\177\020" \ 134 "b\0RXSERR\0b\1RXPERR\0b\2RXLERR\0" \ 135 "b\3RXSMALL\0b\4RXDROP\0b\5RXIRQ\0" \ 136 "b\6CECOFLOW\0b\7FCOFLOW\0b\10RLCOLL\0" \ 137 "b\11RXFOFLOW\0b\12MCOFLOW\0b\13RUOFLOW\0" \ 138 "b\14RCCOFLOW\0b\15TXSERR\0b\16TXPERR\0" \ 139 "b\17TXLERR\0b\20TXDERROR\0b\21TCCOFLOW\0" \ 140 "b\22TXIRQ\0b\23BERROR\0b\24JERROR\0" \ 141 "b\25FUFLOW\0b\26LCOLL\0b\27ERETRIES\0" \ 142 "b\30CLOSS\0b\31EDEFER\0\0" 143 144 /* 145 * Errors: all status bits except for TX/RX IRQ 146 */ 147 #define QE_CR_STAT_ALLERRORS \ 148 ( QE_CR_STAT_EDEFER | QE_CR_STAT_CLOSS | QE_CR_STAT_ERETRIES \ 149 | QE_CR_STAT_LCOLL | QE_CR_STAT_FUFLOW | QE_CR_STAT_JERROR \ 150 | QE_CR_STAT_BERROR | QE_CR_STAT_TCCOFLOW | QE_CR_STAT_TXDERROR \ 151 | QE_CR_STAT_TXLERR | QE_CR_STAT_TXPERR | QE_CR_STAT_TXSERR \ 152 | QE_CR_STAT_RCCOFLOW | QE_CR_STAT_RUOFLOW | QE_CR_STAT_MCOFLOW \ 153 | QE_CR_STAT_RXFOFLOW | QE_CR_STAT_RLCOLL | QE_CR_STAT_FCOFLOW \ 154 | QE_CR_STAT_CECOFLOW | QE_CR_STAT_RXDROP | QE_CR_STAT_RXSMALL \ 155 | QE_CR_STAT_RXLERR | QE_CR_STAT_RXPERR | QE_CR_STAT_RXSERR) 156 157 /* qe_cregs.qmask: qec error interrupt mask. */ 158 #define QE_CR_QMASK_COFLOW 0x00100000 /* collision cntr overflow */ 159 #define QE_CR_QMASK_TXDERROR 0x00080000 /* tx descriptor error */ 160 #define QE_CR_QMASK_TXLERR 0x00040000 /* tx late error */ 161 #define QE_CR_QMASK_TXPERR 0x00020000 /* tx parity error */ 162 #define QE_CR_QMASK_TXSERR 0x00010000 /* tx sbus error ack */ 163 #define QE_CR_QMASK_RXDROP 0x00000010 /* rx packet dropped */ 164 #define QE_CR_QMASK_RXSMALL 0x00000008 /* rx buffer too small */ 165 #define QE_CR_QMASK_RXLERR 0x00000004 /* rx late error */ 166 #define QE_CR_QMASK_RXPERR 0x00000002 /* rx parity error */ 167 #define QE_CR_QMASK_RXSERR 0x00000001 /* rx sbus error ack */ 168 169 /* qe_cregs.mmask: MACE error interrupt mask. */ 170 #define QE_CR_MMASK_EDEFER 0x10000000 /* excess defer */ 171 #define QE_CR_MMASK_CLOSS 0x08000000 /* carrier loss */ 172 #define QE_CR_MMASK_ERETRY 0x04000000 /* excess retry */ 173 #define QE_CR_MMASK_LCOLL 0x02000000 /* late collision error */ 174 #define QE_CR_MMASK_UFLOW 0x01000000 /* underflow */ 175 #define QE_CR_MMASK_JABBER 0x00800000 /* jabber error */ 176 #define QE_CR_MMASK_BABBLE 0x00400000 /* babble error */ 177 #define QE_CR_MMASK_OFLOW 0x00000800 /* overflow */ 178 #define QE_CR_MMASK_RXCOLL 0x00000400 /* rx coll-cntr overflow */ 179 #define QE_CR_MMASK_RPKT 0x00000200 /* runt pkt overflow */ 180 #define QE_CR_MMASK_MPKT 0x00000100 /* missed pkt overflow */ 181 182 /* qe_cregs.pipg: inter-frame gap. */ 183 #define QE_CR_PIPG_TENAB 0x00000020 /* enable throttle */ 184 #define QE_CR_PIPG_MMODE 0x00000010 /* manual mode */ 185 #define QE_CR_PIPG_WMASK 0x0000000f /* sbus wait mask */ 186 187 /* 188 * MACE registers 189 *- 190 struct qe_mregs { 191 u_int8_t rcvfifo; [0] // receive fifo 192 u_int8_t xmtfifo; [1] // transmit fifo 193 u_int8_t xmtfc; [2] // transmit frame control 194 u_int8_t xmtfs; [3] // transmit frame status 195 u_int8_t xmtrc; [4] // tx retry count 196 u_int8_t rcvfc; [5] // receive frame control 197 u_int8_t rcvfs; [6] // receive frame status 198 u_int8_t fifofc; [7] // fifo frame count 199 u_int8_t ir; [8] // interrupt register 200 u_int8_t imr; [9] // interrupt mask register 201 u_int8_t pr; [10] // poll register 202 u_int8_t biucc; [11] // biu config control 203 u_int8_t fifocc; [12] // fifo config control 204 u_int8_t maccc; [13] // mac config control 205 u_int8_t plscc; [14] // pls config control 206 u_int8_t phycc; [15] // phy config control 207 u_int8_t chipid1; [16] // chipid, low byte 208 u_int8_t chipid2; [17] // chipid, high byte 209 u_int8_t iac; [18] // internal address config 210 u_int8_t _reserved0; [19] // reserved 211 u_int8_t ladrf; [20] // logical address filter 212 u_int8_t padr; [21] // physical address 213 u_int8_t _reserved1; [22] // reserved 214 u_int8_t _reserved2; [23] // reserved 215 u_int8_t mpc; [24] // missed packet count 216 u_int8_t _reserved3; [25] // reserved 217 u_int8_t rntpc; [26] // runt packet count 218 u_int8_t rcvcc; [27] // receive collision count 219 u_int8_t _reserved4; [28] // reserved 220 u_int8_t utr; [29] // user test register 221 u_int8_t rtr1; [30] // reserved test register 1 222 u_int8_t rtr2; [31] // reserved test register 2 223 }; 224 * register indices: */ 225 #define QE_MRI_RCVFIFO 0 // receive fifo 226 #define QE_MRI_XMTFIFO 1 // transmit fifo 227 #define QE_MRI_XMTFC 2 // transmit frame control 228 #define QE_MRI_XMTFS 3 // transmit frame status 229 #define QE_MRI_XMTRC 4 // tx retry count 230 #define QE_MRI_RCVFC 5 // receive frame control 231 #define QE_MRI_RCVFS 6 // receive frame status 232 #define QE_MRI_FIFOFC 7 // fifo frame count 233 #define QE_MRI_IR 8 // interrupt register 234 #define QE_MRI_IMR 9 // interrupt mask register 235 #define QE_MRI_PR 10 // poll register 236 #define QE_MRI_BIUCC 11 // biu config control 237 #define QE_MRI_FIFOCC 12 // fifo config control 238 #define QE_MRI_MACCC 13 // mac config control 239 #define QE_MRI_PLSCC 14 // pls config control 240 #define QE_MRI_PHYCC 15 // phy config control 241 #define QE_MRI_CHIPID1 16 // chipid, low byte 242 #define QE_MRI_CHIPID2 17 // chipid, high byte 243 #define QE_MRI_IAC 18 // internal address config 244 #define QE_MRI_LADRF 20 // logical address filter 245 #define QE_MRI_PADR 21 // physical address 246 #define QE_MRI_MPC 24 // missed packet count 247 #define QE_MRI_RNTPC 26 // runt packet count 248 #define QE_MRI_RCVCC 27 // receive collision count 249 #define QE_MRI_UTR 29 // user test register 250 #define QE_MRI_RTR1 30 // reserved test register 1 251 #define QE_MRI_RTR2 31 // reserved test register 2 252 253 /* qe_mregs.xmtfc: transmit frame control. */ 254 #define QE_MR_XMTFC_DRETRY 0x80 /* disable retries */ 255 #define QE_MR_XMTFC_DXMTFCS 0x08 /* disable tx fcs */ 256 #define QE_MR_XMTFC_APADXMT 0x01 /* enable auto padding */ 257 258 /* qe_mregs.xmtfs: transmit frame status. */ 259 #define QE_MR_XMTFS_XMTSV 0x80 /* tx valid */ 260 #define QE_MR_XMTFS_UFLO 0x40 /* tx underflow */ 261 #define QE_MR_XMTFS_LCOL 0x20 /* tx late collision */ 262 #define QE_MR_XMTFS_MORE 0x10 /* tx > 1 retries */ 263 #define QE_MR_XMTFS_ONE 0x08 /* tx 1 retry */ 264 #define QE_MR_XMTFS_DEFER 0x04 /* tx pkt deferred */ 265 #define QE_MR_XMTFS_LCAR 0x02 /* tx carrier lost */ 266 #define QE_MR_XMTFS_RTRY 0x01 /* tx retry error */ 267 268 /* qe_mregs.xmtrc: transmit retry count. */ 269 #define QE_MR_XMTRC_EXDEF 0x80 /* tx excess defers */ 270 #define QE_MR_XMTRC_XMTRC 0x0f /* tx retry count mask */ 271 272 /* qe_mregs.rcvfc: receive frame control. */ 273 #define QE_MR_RCVFC_LLRCV 0x08 /* rx low latency */ 274 #define QE_MR_RCVFC_MR 0x04 /* rx addr match/reject */ 275 #define QE_MR_RCVFC_ASTRPRCV 0x01 /* rx auto strip */ 276 277 /* qe_mregs.rcvfs: receive frame status. */ 278 #define QE_MR_RCVFS_OFLO 0x80 /* rx overflow */ 279 #define QE_MR_RCVFS_CLSN 0x40 /* rx late collision */ 280 #define QE_MR_RCVFS_FRAM 0x20 /* rx framing error */ 281 #define QE_MR_RCVFS_FCS 0x10 /* rx fcs error */ 282 #define QE_MR_RCVFS_RCVCNT 0x0f /* rx msg byte count mask */ 283 284 /* qe_mregs.fifofc: fifo frame count. */ 285 #define QE_MR_FIFOFC_RCVFC 0xf0 /* rx fifo frame count */ 286 #define QE_MR_FIFOFC_XMTFC 0x0f /* tx fifo frame count */ 287 288 /* qe_mregs.ir: interrupt register. */ 289 #define QE_MR_IR_JAB 0x80 /* jabber error */ 290 #define QE_MR_IR_BABL 0x40 /* babble error */ 291 #define QE_MR_IR_CERR 0x20 /* collision error */ 292 #define QE_MR_IR_RCVCCO 0x10 /* collision cnt overflow */ 293 #define QE_MR_IR_RNTPCO 0x08 /* runt pkt cnt overflow */ 294 #define QE_MR_IR_MPCO 0x04 /* miss pkt cnt overflow */ 295 #define QE_MR_IR_RCVINT 0x02 /* packet received */ 296 #define QE_MR_IR_XMTINT 0x01 /* packet transmitted */ 297 298 /* qe_mregs.imr: interrupt mask register. */ 299 #define QE_MR_IMR_JABM 0x80 /* jabber errors */ 300 #define QE_MR_IMR_BABLM 0x40 /* babble errors */ 301 #define QE_MR_IMR_CERRM 0x20 /* collision errors */ 302 #define QE_MR_IMR_RCVCCOM 0x10 /* rx collision count oflow */ 303 #define QE_MR_IMR_RNTPCOM 0x08 /* runt pkt cnt ovrflw */ 304 #define QE_MR_IMR_MPCOM 0x04 /* miss pkt cnt ovrflw */ 305 #define QE_MR_IMR_RCVINTM 0x02 /* rx interrupts */ 306 #define QE_MR_IMR_XMTINTM 0x01 /* tx interrupts */ 307 308 /* qe_mregs.pr: poll register. */ 309 #define QE_MR_PR_XMTSV 0x80 /* tx status is valid */ 310 #define QE_MR_PR_TDTREQ 0x40 /* tx data xfer request */ 311 #define QE_MR_PR_RDTREQ 0x20 /* rx data xfer request */ 312 313 /* qe_mregs.biucc: biu config control. */ 314 #define QE_MR_BIUCC_BSWAP 0x40 /* byte swap */ 315 #define QE_MR_BIUCC_4TS 0x00 /* 4byte xmit start point */ 316 #define QE_MR_BIUCC_16TS 0x10 /* 16byte xmit start point */ 317 #define QE_MR_BIUCC_64TS 0x20 /* 64byte xmit start point */ 318 #define QE_MR_BIUCC_112TS 0x30 /* 112byte xmit start point */ 319 #define QE_MR_BIUCC_SWRST 0x01 /* sw-reset mace */ 320 321 /* qe_mregs.fifocc: fifo config control. */ 322 #define QE_MR_FIFOCC_TXF8 0x00 /* tx fifo 8 write cycles */ 323 #define QE_MR_FIFOCC_TXF32 0x80 /* tx fifo 32 write cycles */ 324 #define QE_MR_FIFOCC_TXF16 0x40 /* tx fifo 16 write cycles */ 325 #define QE_MR_FIFOCC_RXF64 0x20 /* rx fifo 64 write cycles */ 326 #define QE_MR_FIFOCC_RXF32 0x10 /* rx fifo 32 write cycles */ 327 #define QE_MR_FIFOCC_RXF16 0x00 /* rx fifo 16 write cycles */ 328 #define QE_MR_FIFOCC_TFWU 0x08 /* tx fifo watermark update */ 329 #define QE_MR_FIFOCC_RFWU 0x04 /* rx fifo watermark update */ 330 #define QE_MR_FIFOCC_XMTBRST 0x02 /* tx burst enable */ 331 #define QE_MR_FIFOCC_RCVBRST 0x01 /* rx burst enable */ 332 333 /* qe_mregs.maccc: mac config control. */ 334 #define QE_MR_MACCC_PROM 0x80 /* promiscuous mode enable */ 335 #define QE_MR_MACCC_DXMT2PD 0x40 /* tx 2part deferral enable */ 336 #define QE_MR_MACCC_EMBA 0x20 /* modified backoff enable */ 337 #define QE_MR_MACCC_DRCVPA 0x08 /* rx physical addr disable */ 338 #define QE_MR_MACCC_DRCVBC 0x04 /* rx broadcast disable */ 339 #define QE_MR_MACCC_ENXMT 0x02 /* enable transmitter */ 340 #define QE_MR_MACCC_ENRCV 0x01 /* enable receiver */ 341 342 /* qe_mregs.plscc: pls config control. */ 343 #define QE_MR_PLSCC_XMTSEL 0x08 /* tx mode select */ 344 #define QE_MR_PLSCC_PORTMASK 0x06 /* port selection bits */ 345 #define QE_MR_PLSCC_GPSI 0x06 /* use gpsi connector */ 346 #define QE_MR_PLSCC_DAI 0x04 /* use dai connector */ 347 #define QE_MR_PLSCC_TP 0x02 /* use twistedpair connector */ 348 #define QE_MR_PLSCC_AUI 0x00 /* use aui connector */ 349 #define QE_MR_PLSCC_ENPLSIO 0x01 /* pls i/o enable */ 350 351 /* qe_mregs.phycc: phy config control. */ 352 #define QE_MR_PHYCC_LNKFL 0x80 /* link fail */ 353 #define QE_MR_PHYCC_DLNKTST 0x40 /* disable link test logic */ 354 #define QE_MR_PHYCC_REVPOL 0x20 /* rx polarity */ 355 #define QE_MR_PHYCC_DAPC 0x10 /* autopolaritycorrect disab */ 356 #define QE_MR_PHYCC_LRT 0x08 /* select low threshold */ 357 #define QE_MR_PHYCC_ASEL 0x04 /* connector port auto-sel */ 358 #define QE_MR_PHYCC_RWAKE 0x02 /* remote wakeup */ 359 #define QE_MR_PHYCC_AWAKE 0x01 /* auto wakeup */ 360 361 /* qe_mregs.iac: internal address config. */ 362 #define QE_MR_IAC_ADDRCHG 0x80 /* start address change */ 363 #define QE_MR_IAC_PHYADDR 0x04 /* physical address reset */ 364 #define QE_MR_IAC_LOGADDR 0x02 /* logical address reset */ 365 366 /* qe_mregs.utr: user test register. */ 367 #define QE_MR_UTR_RTRE 0x80 /* enable resv test register */ 368 #define QE_MR_UTR_RTRD 0x40 /* disab resv test register */ 369 #define QE_MR_UTR_RPA 0x20 /* accept runt packets */ 370 #define QE_MR_UTR_FCOLL 0x10 /* force collision status */ 371 #define QE_MR_UTR_RCVSFCSE 0x08 /* enable fcs on rx */ 372 #define QE_MR_UTR_INTLOOPM 0x06 /* Internal loopback w/mandec */ 373 #define QE_MR_UTR_INTLOOP 0x04 /* Internal loopback */ 374 #define QE_MR_UTR_EXTLOOP 0x02 /* external loopback */ 375 #define QE_MR_UTR_NOLOOP 0x00 /* no loopback */ 376 377 /* Buffer and Ring sizes: fixed ring size */ 378 #define QE_TX_RING_MAXSIZE 256 /* maximum tx ring size */ 379 #define QE_RX_RING_MAXSIZE 256 /* maximum rx ring size */ 380 #define QE_TX_RING_SIZE 16 381 #define QE_RX_RING_SIZE 16 382 #define QE_PKT_BUF_SZ 2048 383 384 #define MC_POLY_LE 0xedb88320 /* mcast crc, little endian */ 385
Indexes created Wed Oct 01 07:09:59 GMT 2025