spif.c revision 1.1.2.6
1 1.1.2.6 skrll /* $NetBSD: spif.c,v 1.1.2.6 2005/03/04 16:50:32 skrll Exp $ */ 2 1.1.2.2 skrll /* $OpenBSD: spif.c,v 1.12 2003/10/03 16:44:51 miod Exp $ */ 3 1.1.2.2 skrll 4 1.1.2.2 skrll /* 5 1.1.2.2 skrll * Copyright (c) 1999-2002 Jason L. Wright (jason (at) thought.net) 6 1.1.2.2 skrll * All rights reserved. 7 1.1.2.2 skrll * 8 1.1.2.2 skrll * Redistribution and use in source and binary forms, with or without 9 1.1.2.2 skrll * modification, are permitted provided that the following conditions 10 1.1.2.2 skrll * are met: 11 1.1.2.2 skrll * 1. Redistributions of source code must retain the above copyright 12 1.1.2.2 skrll * notice, this list of conditions and the following disclaimer. 13 1.1.2.2 skrll * 2. Redistributions in binary form must reproduce the above copyright 14 1.1.2.2 skrll * notice, this list of conditions and the following disclaimer in the 15 1.1.2.2 skrll * documentation and/or other materials provided with the distribution. 16 1.1.2.2 skrll * 17 1.1.2.2 skrll * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 1.1.2.2 skrll * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 19 1.1.2.2 skrll * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 20 1.1.2.2 skrll * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 21 1.1.2.2 skrll * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 22 1.1.2.2 skrll * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 23 1.1.2.2 skrll * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 1.1.2.2 skrll * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 25 1.1.2.2 skrll * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 26 1.1.2.2 skrll * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 1.1.2.2 skrll * POSSIBILITY OF SUCH DAMAGE. 28 1.1.2.2 skrll * 29 1.1.2.2 skrll * Effort sponsored in part by the Defense Advanced Research Projects 30 1.1.2.2 skrll * Agency (DARPA) and Air Force Research Laboratory, Air Force 31 1.1.2.2 skrll * Materiel Command, USAF, under agreement number F30602-01-2-0537. 32 1.1.2.2 skrll * 33 1.1.2.2 skrll */ 34 1.1.2.2 skrll 35 1.1.2.2 skrll /* 36 1.1.2.2 skrll * Driver for the SUNW,spif: 8 serial, 1 parallel sbus board 37 1.1.2.2 skrll * based heavily on Iain Hibbert's driver for the MAGMA cards 38 1.1.2.2 skrll */ 39 1.1.2.2 skrll 40 1.1.2.2 skrll /* Ported to NetBSD 2.0 by Hauke Fath */ 41 1.1.2.2 skrll 42 1.1.2.2 skrll 43 1.1.2.2 skrll #include <sys/cdefs.h> 44 1.1.2.6 skrll __KERNEL_RCSID(0, "$NetBSD: spif.c,v 1.1.2.6 2005/03/04 16:50:32 skrll Exp $"); 45 1.1.2.2 skrll 46 1.1.2.2 skrll #include "spif.h" 47 1.1.2.2 skrll #if NSPIF > 0 48 1.1.2.2 skrll 49 1.1.2.2 skrll #include <sys/param.h> 50 1.1.2.2 skrll #include <sys/systm.h> 51 1.1.2.2 skrll #include <sys/proc.h> 52 1.1.2.2 skrll #include <sys/device.h> 53 1.1.2.2 skrll #include <sys/file.h> 54 1.1.2.2 skrll #include <sys/ioctl.h> 55 1.1.2.2 skrll #include <sys/malloc.h> 56 1.1.2.2 skrll #include <sys/tty.h> 57 1.1.2.2 skrll #include <sys/time.h> 58 1.1.2.2 skrll #include <sys/kernel.h> 59 1.1.2.2 skrll #include <sys/syslog.h> 60 1.1.2.2 skrll #include <sys/conf.h> 61 1.1.2.2 skrll #include <sys/errno.h> 62 1.1.2.2 skrll 63 1.1.2.2 skrll #include <machine/bus.h> 64 1.1.2.2 skrll #include <machine/intr.h> 65 1.1.2.2 skrll #include <machine/autoconf.h> 66 1.1.2.2 skrll #include <machine/promlib.h> 67 1.1.2.2 skrll 68 1.1.2.2 skrll #include <dev/sbus/sbusvar.h> 69 1.1.2.2 skrll 70 1.1.2.2 skrll #include <dev/sbus/spifvar.h> 71 1.1.2.2 skrll #include <dev/sbus/spifreg.h> 72 1.1.2.2 skrll 73 1.1.2.2 skrll 74 1.1.2.2 skrll /* Autoconfig stuff */ 75 1.1.2.2 skrll 76 1.1.2.2 skrll CFATTACH_DECL(spif, sizeof(struct spif_softc), 77 1.1.2.2 skrll spif_match, spif_attach, NULL, NULL); 78 1.1.2.2 skrll 79 1.1.2.2 skrll CFATTACH_DECL(stty, sizeof(struct stty_softc), 80 1.1.2.2 skrll stty_match, stty_attach, NULL, NULL); 81 1.1.2.2 skrll 82 1.1.2.2 skrll CFATTACH_DECL(sbpp, sizeof(struct sbpp_softc), 83 1.1.2.2 skrll sbpp_match, sbpp_attach, NULL, NULL); 84 1.1.2.2 skrll 85 1.1.2.2 skrll extern struct cfdriver spif_cd; 86 1.1.2.2 skrll extern struct cfdriver stty_cd; 87 1.1.2.2 skrll extern struct cfdriver sbpp_cd; 88 1.1.2.2 skrll 89 1.1.2.2 skrll dev_type_open(stty_open); 90 1.1.2.2 skrll dev_type_close(stty_close); 91 1.1.2.2 skrll dev_type_read(stty_read); 92 1.1.2.2 skrll dev_type_write(stty_write); 93 1.1.2.2 skrll dev_type_ioctl(stty_ioctl); 94 1.1.2.2 skrll dev_type_stop(stty_stop); 95 1.1.2.2 skrll dev_type_tty(stty_tty); 96 1.1.2.2 skrll dev_type_poll(stty_poll); 97 1.1.2.2 skrll 98 1.1.2.2 skrll const struct cdevsw stty_cdevsw = { 99 1.1.2.2 skrll stty_open, stty_close, stty_read, stty_write, stty_ioctl, 100 1.1.2.2 skrll stty_stop, stty_tty, stty_poll, nommap, ttykqfilter, D_TTY 101 1.1.2.2 skrll }; 102 1.1.2.2 skrll 103 1.1.2.2 skrll dev_type_open(sbpp_open); 104 1.1.2.2 skrll dev_type_close(sbpp_close); 105 1.1.2.2 skrll dev_type_read(sbpp_read); 106 1.1.2.2 skrll dev_type_write(sbpp_write); 107 1.1.2.2 skrll dev_type_ioctl(sbpp_ioctl); 108 1.1.2.2 skrll dev_type_poll(sbpp_poll); 109 1.1.2.2 skrll 110 1.1.2.2 skrll const struct cdevsw sbpp_cdevsw = { 111 1.1.2.2 skrll sbpp_open, sbpp_close, sbpp_read, sbpp_write, sbpp_ioctl, 112 1.1.2.2 skrll nostop, notty, sbpp_poll, nommap, nokqfilter, 113 1.1.2.2 skrll }; 114 1.1.2.2 skrll 115 1.1.2.2 skrll 116 1.1.2.2 skrll /* normal STC access */ 117 1.1.2.2 skrll #define STC_WRITE(sc,r,v) \ 118 1.1.2.2 skrll bus_space_write_1((sc)->sc_bustag, (sc)->sc_stch, (r), (v)) 119 1.1.2.2 skrll #define STC_READ(sc,r) \ 120 1.1.2.2 skrll bus_space_read_1((sc)->sc_bustag, (sc)->sc_stch, (r)) 121 1.1.2.2 skrll 122 1.1.2.2 skrll /* IACK STC access */ 123 1.1.2.2 skrll #define ISTC_WRITE(sc,r,v) \ 124 1.1.2.2 skrll bus_space_write_1((sc)->sc_bustag, (sc)->sc_istch, (r), (v)) 125 1.1.2.2 skrll #define ISTC_READ(sc,r) \ 126 1.1.2.2 skrll bus_space_read_1((sc)->sc_bustag, (sc)->sc_istch, (r)) 127 1.1.2.2 skrll 128 1.1.2.2 skrll /* PPC access */ 129 1.1.2.2 skrll #define PPC_WRITE(sc,r,v) \ 130 1.1.2.2 skrll bus_space_write_1((sc)->sc_bustag, (sc)->sc_ppch, (r), (v)) 131 1.1.2.2 skrll #define PPC_READ(sc,r) \ 132 1.1.2.2 skrll bus_space_read_1((sc)->sc_bustag, (sc)->sc_ppch, (r)) 133 1.1.2.2 skrll 134 1.1.2.2 skrll #define DTR_WRITE(sc,port,v) \ 135 1.1.2.2 skrll do { \ 136 1.1.2.2 skrll sc->sc_ttys->sc_port[(port)].sp_dtr = v; \ 137 1.1.2.2 skrll bus_space_write_1((sc)->sc_bustag, \ 138 1.1.2.2 skrll sc->sc_dtrh, port, (v == 0) ? 1 : 0); \ 139 1.1.2.2 skrll } while (0) 140 1.1.2.2 skrll 141 1.1.2.2 skrll #define DTR_READ(sc,port) ((sc)->sc_ttys->sc_port[(port)].sp_dtr) 142 1.1.2.2 skrll 143 1.1.2.2 skrll 144 1.1.2.2 skrll int 145 1.1.2.2 skrll spif_match(parent, vcf, aux) 146 1.1.2.2 skrll struct device *parent; 147 1.1.2.2 skrll struct cfdata *vcf; 148 1.1.2.2 skrll void *aux; 149 1.1.2.2 skrll { 150 1.1.2.2 skrll struct sbus_attach_args *sa = aux; 151 1.1.2.2 skrll 152 1.1.2.2 skrll if (strcmp(vcf->cf_name, sa->sa_name) && 153 1.1.2.2 skrll strcmp("SUNW,spif", sa->sa_name)) 154 1.1.2.2 skrll return (0); 155 1.1.2.2 skrll return (1); 156 1.1.2.2 skrll } 157 1.1.2.2 skrll 158 1.1.2.6 skrll void 159 1.1.2.2 skrll spif_attach(parent, self, aux) 160 1.1.2.2 skrll struct device *parent, *self; 161 1.1.2.2 skrll void *aux; 162 1.1.2.2 skrll { 163 1.1.2.2 skrll struct spif_softc *sc = (struct spif_softc *)self; 164 1.1.2.2 skrll struct sbus_attach_args *sa = aux; 165 1.1.2.2 skrll 166 1.1.2.2 skrll if (sa->sa_nintr != 2) { 167 1.1.2.2 skrll printf(": expected %d interrupts, got %d\n", 2, sa->sa_nintr); 168 1.1.2.2 skrll return; 169 1.1.2.2 skrll } 170 1.1.2.2 skrll 171 1.1.2.2 skrll if (sa->sa_nreg != 1) { 172 1.1.2.2 skrll printf(": expected %d registers, got %d\n", 1, sa->sa_nreg); 173 1.1.2.2 skrll return; 174 1.1.2.2 skrll } 175 1.1.2.2 skrll 176 1.1.2.2 skrll sc->sc_bustag = sa->sa_bustag; 177 1.1.2.2 skrll if (sbus_bus_map(sa->sa_bustag, sa->sa_slot, 178 1.1.2.2 skrll sa->sa_offset, sa->sa_size, 179 1.1.2.2 skrll 0, &sc->sc_regh) != 0) { 180 1.1.2.2 skrll printf(": can't map registers\n"); 181 1.1.2.2 skrll return; 182 1.1.2.2 skrll } 183 1.1.2.2 skrll 184 1.1.2.2 skrll if (bus_space_subregion(sc->sc_bustag, sc->sc_regh, 185 1.1.2.2 skrll DTR_REG_OFFSET, DTR_REG_LEN, &sc->sc_dtrh) != 0) { 186 1.1.2.2 skrll printf(": can't map dtr regs\n"); 187 1.1.2.2 skrll goto fail_unmapregs; 188 1.1.2.2 skrll } 189 1.1.2.2 skrll 190 1.1.2.2 skrll if (bus_space_subregion(sc->sc_bustag, sc->sc_regh, 191 1.1.2.2 skrll STC_REG_OFFSET, STC_REG_LEN, &sc->sc_stch) != 0) { 192 1.1.2.2 skrll printf(": can't map dtr regs\n"); 193 1.1.2.2 skrll goto fail_unmapregs; 194 1.1.2.2 skrll } 195 1.1.2.2 skrll 196 1.1.2.2 skrll if (bus_space_subregion(sc->sc_bustag, sc->sc_regh, 197 1.1.2.2 skrll ISTC_REG_OFFSET, ISTC_REG_LEN, &sc->sc_istch) != 0) { 198 1.1.2.2 skrll printf(": can't map dtr regs\n"); 199 1.1.2.2 skrll goto fail_unmapregs; 200 1.1.2.2 skrll } 201 1.1.2.2 skrll 202 1.1.2.2 skrll if (bus_space_subregion(sc->sc_bustag, sc->sc_regh, 203 1.1.2.2 skrll PPC_REG_OFFSET, PPC_REG_LEN, &sc->sc_ppch) != 0) { 204 1.1.2.2 skrll printf(": can't map dtr regs\n"); 205 1.1.2.2 skrll goto fail_unmapregs; 206 1.1.2.2 skrll } 207 1.1.2.2 skrll 208 1.1.2.2 skrll sc->sc_ppcih = bus_intr_establish(sa->sa_bustag, 209 1.1.2.2 skrll sa->sa_intr[PARALLEL_INTR].oi_pri, IPL_SERIAL, spif_ppcintr, sc); 210 1.1.2.2 skrll if (sc->sc_ppcih == NULL) { 211 1.1.2.2 skrll printf(": failed to establish ppc interrupt\n"); 212 1.1.2.2 skrll goto fail_unmapregs; 213 1.1.2.2 skrll } 214 1.1.2.2 skrll 215 1.1.2.2 skrll sc->sc_stcih = bus_intr_establish(sa->sa_bustag, 216 1.1.2.2 skrll sa->sa_intr[SERIAL_INTR].oi_pri, IPL_SERIAL, spif_stcintr, sc); 217 1.1.2.2 skrll if (sc->sc_stcih == NULL) { 218 1.1.2.2 skrll printf(": failed to establish stc interrupt\n"); 219 1.1.2.2 skrll goto fail_unmapregs; 220 1.1.2.2 skrll } 221 1.1.2.2 skrll 222 1.1.2.2 skrll sc->sc_softih = softintr_establish(IPL_TTY, spif_softintr, sc); 223 1.1.2.2 skrll if (sc->sc_softih == NULL) { 224 1.1.2.2 skrll printf(": can't get soft intr\n"); 225 1.1.2.2 skrll goto fail_unmapregs; 226 1.1.2.2 skrll } 227 1.1.2.2 skrll 228 1.1.2.2 skrll sc->sc_node = sa->sa_node; 229 1.1.2.2 skrll 230 1.1.2.2 skrll sc->sc_rev = prom_getpropint(sc->sc_node, "revlev", 0); 231 1.1.2.2 skrll 232 1.1.2.2 skrll sc->sc_osc = prom_getpropint(sc->sc_node, "verosc", 0); 233 1.1.2.2 skrll switch (sc->sc_osc) { 234 1.1.2.2 skrll case SPIF_OSC10: 235 1.1.2.2 skrll sc->sc_osc = 10000000; 236 1.1.2.2 skrll break; 237 1.1.2.2 skrll case SPIF_OSC9: 238 1.1.2.2 skrll default: 239 1.1.2.2 skrll sc->sc_osc = 9830400; 240 1.1.2.2 skrll break; 241 1.1.2.2 skrll } 242 1.1.2.2 skrll 243 1.1.2.2 skrll sc->sc_nser = 8; 244 1.1.2.2 skrll sc->sc_npar = 1; 245 1.1.2.2 skrll 246 1.1.2.2 skrll sc->sc_rev2 = STC_READ(sc, STC_GFRCR); 247 1.1.2.2 skrll STC_WRITE(sc, STC_GSVR, 0); 248 1.1.2.2 skrll 249 1.1.2.2 skrll stty_write_ccr(sc, CD180_CCR_CMD_RESET | CD180_CCR_RESETALL); 250 1.1.2.2 skrll while (STC_READ(sc, STC_GSVR) != 0xff); 251 1.1.2.2 skrll while (STC_READ(sc, STC_GFRCR) != sc->sc_rev2); 252 1.1.2.2 skrll 253 1.1.2.2 skrll STC_WRITE(sc, STC_PPRH, CD180_PPRH); 254 1.1.2.2 skrll STC_WRITE(sc, STC_PPRL, CD180_PPRL); 255 1.1.2.2 skrll STC_WRITE(sc, STC_MSMR, SPIF_MSMR); 256 1.1.2.2 skrll STC_WRITE(sc, STC_TSMR, SPIF_TSMR); 257 1.1.2.2 skrll STC_WRITE(sc, STC_RSMR, SPIF_RSMR); 258 1.1.2.2 skrll STC_WRITE(sc, STC_GSVR, 0); 259 1.1.2.2 skrll STC_WRITE(sc, STC_GSCR1, 0); 260 1.1.2.2 skrll STC_WRITE(sc, STC_GSCR2, 0); 261 1.1.2.2 skrll STC_WRITE(sc, STC_GSCR3, 0); 262 1.1.2.2 skrll 263 1.1.2.2 skrll printf(": rev %x chiprev %x osc %sMHz\n", 264 1.1.2.2 skrll sc->sc_rev, sc->sc_rev2, clockfreq(sc->sc_osc)); 265 1.1.2.2 skrll 266 1.1.2.2 skrll (void)config_found(self, stty_match, NULL); 267 1.1.2.2 skrll (void)config_found(self, sbpp_match, NULL); 268 1.1.2.2 skrll 269 1.1.2.2 skrll return; 270 1.1.2.2 skrll 271 1.1.2.2 skrll fail_unmapregs: 272 1.1.2.2 skrll bus_space_unmap(sa->sa_bustag, sc->sc_regh, sa->sa_size); 273 1.1.2.2 skrll } 274 1.1.2.2 skrll 275 1.1.2.2 skrll int 276 1.1.2.2 skrll stty_match(parent, vcf, aux) 277 1.1.2.2 skrll struct device *parent; 278 1.1.2.2 skrll struct cfdata *vcf; 279 1.1.2.2 skrll void *aux; 280 1.1.2.2 skrll { 281 1.1.2.2 skrll struct spif_softc *sc = (struct spif_softc *)parent; 282 1.1.2.2 skrll 283 1.1.2.2 skrll return (aux == stty_match && sc->sc_ttys == NULL); 284 1.1.2.2 skrll } 285 1.1.2.2 skrll 286 1.1.2.2 skrll void 287 1.1.2.2 skrll stty_attach(parent, dev, aux) 288 1.1.2.2 skrll struct device *parent, *dev; 289 1.1.2.2 skrll void *aux; 290 1.1.2.2 skrll { 291 1.1.2.2 skrll struct spif_softc *sc = (struct spif_softc *)parent; 292 1.1.2.2 skrll struct stty_softc *ssc = (struct stty_softc *)dev; 293 1.1.2.2 skrll int port; 294 1.1.2.2 skrll 295 1.1.2.2 skrll sc->sc_ttys = ssc; 296 1.1.2.2 skrll 297 1.1.2.2 skrll for (port = 0; port < sc->sc_nser; port++) { 298 1.1.2.2 skrll struct stty_port *sp = &ssc->sc_port[port]; 299 1.1.2.2 skrll struct tty *tp; 300 1.1.2.2 skrll 301 1.1.2.2 skrll DTR_WRITE(sc, port, 0); 302 1.1.2.2 skrll 303 1.1.2.2 skrll tp = ttymalloc(); 304 1.1.2.2 skrll 305 1.1.2.2 skrll tp->t_oproc = stty_start; 306 1.1.2.2 skrll tp->t_param = stty_param; 307 1.1.2.2 skrll 308 1.1.2.2 skrll sp->sp_tty = tp; 309 1.1.2.2 skrll sp->sp_sc = sc; 310 1.1.2.2 skrll sp->sp_channel = port; 311 1.1.2.2 skrll 312 1.1.2.2 skrll sp->sp_rbuf = malloc(STTY_RBUF_SIZE, M_DEVBUF, M_NOWAIT); 313 1.1.2.2 skrll if(sp->sp_rbuf == NULL) 314 1.1.2.2 skrll break; 315 1.1.2.2 skrll 316 1.1.2.2 skrll sp->sp_rend = sp->sp_rbuf + STTY_RBUF_SIZE; 317 1.1.2.2 skrll } 318 1.1.2.2 skrll 319 1.1.2.2 skrll ssc->sc_nports = port; 320 1.1.2.2 skrll 321 1.1.2.2 skrll printf(": %d tty%s\n", port, port == 1 ? "" : "s"); 322 1.1.2.2 skrll } 323 1.1.2.2 skrll 324 1.1.2.2 skrll int 325 1.1.2.5 skrll stty_open(dev, flags, mode, l) 326 1.1.2.2 skrll dev_t dev; 327 1.1.2.2 skrll int flags; 328 1.1.2.2 skrll int mode; 329 1.1.2.5 skrll struct lwp *l; 330 1.1.2.2 skrll { 331 1.1.2.2 skrll struct spif_softc *csc; 332 1.1.2.2 skrll struct stty_softc *sc; 333 1.1.2.2 skrll struct stty_port *sp; 334 1.1.2.2 skrll struct tty *tp; 335 1.1.2.2 skrll int card = SPIF_CARD(dev); 336 1.1.2.2 skrll int port = SPIF_PORT(dev); 337 1.1.2.2 skrll int s; 338 1.1.2.2 skrll 339 1.1.2.2 skrll if (card >= stty_cd.cd_ndevs || card >= spif_cd.cd_ndevs) 340 1.1.2.2 skrll return (ENXIO); 341 1.1.2.2 skrll 342 1.1.2.2 skrll sc = stty_cd.cd_devs[card]; 343 1.1.2.2 skrll csc = spif_cd.cd_devs[card]; 344 1.1.2.2 skrll if (sc == NULL || csc == NULL) 345 1.1.2.2 skrll return (ENXIO); 346 1.1.2.2 skrll 347 1.1.2.2 skrll if (port >= sc->sc_nports) 348 1.1.2.2 skrll return (ENXIO); 349 1.1.2.2 skrll 350 1.1.2.2 skrll sp = &sc->sc_port[port]; 351 1.1.2.2 skrll tp = sp->sp_tty; 352 1.1.2.2 skrll tp->t_dev = dev; 353 1.1.2.2 skrll 354 1.1.2.2 skrll if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 355 1.1.2.2 skrll ttychars(tp); 356 1.1.2.2 skrll tp->t_iflag = TTYDEF_IFLAG; 357 1.1.2.2 skrll tp->t_oflag = TTYDEF_OFLAG; 358 1.1.2.2 skrll tp->t_cflag = TTYDEF_CFLAG; 359 1.1.2.2 skrll if (ISSET(sp->sp_openflags, TIOCFLAG_CLOCAL)) 360 1.1.2.2 skrll SET(tp->t_cflag, CLOCAL); 361 1.1.2.2 skrll if (ISSET(sp->sp_openflags, TIOCFLAG_CRTSCTS)) 362 1.1.2.2 skrll SET(tp->t_cflag, CRTSCTS); 363 1.1.2.2 skrll if (ISSET(sp->sp_openflags, TIOCFLAG_MDMBUF)) 364 1.1.2.2 skrll SET(tp->t_cflag, MDMBUF); 365 1.1.2.2 skrll tp->t_lflag = TTYDEF_LFLAG; 366 1.1.2.2 skrll tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 367 1.1.2.2 skrll 368 1.1.2.2 skrll sp->sp_rput = sp->sp_rget = sp->sp_rbuf; 369 1.1.2.2 skrll 370 1.1.2.2 skrll s = spltty(); 371 1.1.2.2 skrll 372 1.1.2.2 skrll STC_WRITE(csc, STC_CAR, sp->sp_channel); 373 1.1.2.2 skrll stty_write_ccr(csc, CD180_CCR_CMD_RESET|CD180_CCR_RESETCHAN); 374 1.1.2.2 skrll STC_WRITE(csc, STC_CAR, sp->sp_channel); 375 1.1.2.2 skrll 376 1.1.2.2 skrll stty_param(tp, &tp->t_termios); 377 1.1.2.2 skrll 378 1.1.2.2 skrll ttsetwater(tp); 379 1.1.2.2 skrll 380 1.1.2.2 skrll STC_WRITE(csc, STC_SRER, CD180_SRER_CD | CD180_SRER_RXD); 381 1.1.2.2 skrll 382 1.1.2.2 skrll if (ISSET(sp->sp_openflags, TIOCFLAG_SOFTCAR) || sp->sp_carrier) 383 1.1.2.2 skrll SET(tp->t_state, TS_CARR_ON); 384 1.1.2.2 skrll else 385 1.1.2.2 skrll CLR(tp->t_state, TS_CARR_ON); 386 1.1.2.2 skrll } 387 1.1.2.5 skrll else if (ISSET(tp->t_state, TS_XCLUDE) && 388 1.1.2.5 skrll l->l_proc->p_ucred->cr_uid != 0) { 389 1.1.2.2 skrll return (EBUSY); 390 1.1.2.2 skrll } else { 391 1.1.2.2 skrll s = spltty(); 392 1.1.2.2 skrll } 393 1.1.2.2 skrll 394 1.1.2.2 skrll if (!ISSET(flags, O_NONBLOCK)) { 395 1.1.2.2 skrll while (!ISSET(tp->t_cflag, CLOCAL) && 396 1.1.2.2 skrll !ISSET(tp->t_state, TS_CARR_ON)) { 397 1.1.2.2 skrll int error; 398 1.1.2.2 skrll error = ttysleep(tp, &tp->t_rawq, TTIPRI | PCATCH, 399 1.1.2.2 skrll "sttycd", 0); 400 1.1.2.2 skrll if (error != 0) { 401 1.1.2.2 skrll splx(s); 402 1.1.2.2 skrll return (error); 403 1.1.2.2 skrll } 404 1.1.2.2 skrll } 405 1.1.2.2 skrll } 406 1.1.2.2 skrll 407 1.1.2.2 skrll splx(s); 408 1.1.2.2 skrll 409 1.1.2.2 skrll return ((*tp->t_linesw->l_open)(dev, tp)); 410 1.1.2.2 skrll } 411 1.1.2.2 skrll 412 1.1.2.2 skrll int 413 1.1.2.5 skrll stty_close(dev, flags, mode, l) 414 1.1.2.2 skrll dev_t dev; 415 1.1.2.2 skrll int flags; 416 1.1.2.2 skrll int mode; 417 1.1.2.5 skrll struct lwp *l; 418 1.1.2.2 skrll { 419 1.1.2.2 skrll struct stty_softc *sc = stty_cd.cd_devs[SPIF_CARD(dev)]; 420 1.1.2.2 skrll struct stty_port *sp = &sc->sc_port[SPIF_PORT(dev)]; 421 1.1.2.2 skrll struct spif_softc *csc = sp->sp_sc; 422 1.1.2.2 skrll struct tty *tp = sp->sp_tty; 423 1.1.2.2 skrll int port = SPIF_PORT(dev); 424 1.1.2.2 skrll int s; 425 1.1.2.2 skrll 426 1.1.2.2 skrll (*tp->t_linesw->l_close)(tp, flags); 427 1.1.2.2 skrll s = spltty(); 428 1.1.2.2 skrll 429 1.1.2.2 skrll if (ISSET(tp->t_cflag, HUPCL) || !ISSET(tp->t_state, TS_ISOPEN)) { 430 1.1.2.2 skrll stty_modem_control(sp, 0, DMSET); 431 1.1.2.2 skrll STC_WRITE(csc, STC_CAR, port); 432 1.1.2.2 skrll STC_WRITE(csc, STC_CCR, 433 1.1.2.2 skrll CD180_CCR_CMD_RESET|CD180_CCR_RESETCHAN); 434 1.1.2.2 skrll } 435 1.1.2.2 skrll 436 1.1.2.2 skrll splx(s); 437 1.1.2.2 skrll ttyclose(tp); 438 1.1.2.2 skrll return (0); 439 1.1.2.2 skrll } 440 1.1.2.2 skrll 441 1.1.2.2 skrll int 442 1.1.2.5 skrll stty_ioctl(dev, cmd, data, flags, l) 443 1.1.2.2 skrll dev_t dev; 444 1.1.2.2 skrll u_long cmd; 445 1.1.2.2 skrll caddr_t data; 446 1.1.2.2 skrll int flags; 447 1.1.2.5 skrll struct lwp *l; 448 1.1.2.2 skrll { 449 1.1.2.2 skrll struct stty_softc *stc = stty_cd.cd_devs[SPIF_CARD(dev)]; 450 1.1.2.2 skrll struct stty_port *sp = &stc->sc_port[SPIF_PORT(dev)]; 451 1.1.2.2 skrll struct spif_softc *sc = sp->sp_sc; 452 1.1.2.2 skrll struct tty *tp = sp->sp_tty; 453 1.1.2.2 skrll int error; 454 1.1.2.2 skrll 455 1.1.2.5 skrll error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flags, l); 456 1.1.2.2 skrll if (error >= 0) 457 1.1.2.2 skrll return (error); 458 1.1.2.2 skrll 459 1.1.2.5 skrll error = ttioctl(tp, cmd, data, flags, l); 460 1.1.2.2 skrll if (error >= 0) 461 1.1.2.2 skrll return (error); 462 1.1.2.2 skrll 463 1.1.2.2 skrll error = 0; 464 1.1.2.2 skrll 465 1.1.2.2 skrll switch (cmd) { 466 1.1.2.2 skrll case TIOCSBRK: 467 1.1.2.2 skrll SET(sp->sp_flags, STTYF_SET_BREAK); 468 1.1.2.2 skrll STC_WRITE(sc, STC_CAR, sp->sp_channel); 469 1.1.2.2 skrll STC_WRITE(sc, STC_SRER, 470 1.1.2.2 skrll STC_READ(sc, STC_SRER) | CD180_SRER_TXD); 471 1.1.2.2 skrll break; 472 1.1.2.2 skrll case TIOCCBRK: 473 1.1.2.2 skrll SET(sp->sp_flags, STTYF_CLR_BREAK); 474 1.1.2.2 skrll STC_WRITE(sc, STC_CAR, sp->sp_channel); 475 1.1.2.2 skrll STC_WRITE(sc, STC_SRER, 476 1.1.2.2 skrll STC_READ(sc, STC_SRER) | CD180_SRER_TXD); 477 1.1.2.2 skrll break; 478 1.1.2.2 skrll case TIOCSDTR: 479 1.1.2.2 skrll stty_modem_control(sp, TIOCM_DTR, DMBIS); 480 1.1.2.2 skrll break; 481 1.1.2.2 skrll case TIOCCDTR: 482 1.1.2.2 skrll stty_modem_control(sp, TIOCM_DTR, DMBIC); 483 1.1.2.2 skrll break; 484 1.1.2.2 skrll case TIOCMBIS: 485 1.1.2.2 skrll stty_modem_control(sp, *((int *)data), DMBIS); 486 1.1.2.2 skrll break; 487 1.1.2.2 skrll case TIOCMBIC: 488 1.1.2.2 skrll stty_modem_control(sp, *((int *)data), DMBIC); 489 1.1.2.2 skrll break; 490 1.1.2.2 skrll case TIOCMGET: 491 1.1.2.2 skrll *((int *)data) = stty_modem_control(sp, 0, DMGET); 492 1.1.2.2 skrll break; 493 1.1.2.2 skrll case TIOCMSET: 494 1.1.2.2 skrll stty_modem_control(sp, *((int *)data), DMSET); 495 1.1.2.2 skrll break; 496 1.1.2.2 skrll case TIOCGFLAGS: 497 1.1.2.2 skrll *((int *)data) = sp->sp_openflags; 498 1.1.2.2 skrll break; 499 1.1.2.2 skrll case TIOCSFLAGS: 500 1.1.2.5 skrll if( suser(l->l_proc->p_ucred, &l->l_proc->p_acflag) ) 501 1.1.2.2 skrll error = EPERM; 502 1.1.2.2 skrll else 503 1.1.2.2 skrll sp->sp_openflags = *((int *)data) & 504 1.1.2.2 skrll (TIOCFLAG_SOFTCAR | TIOCFLAG_CLOCAL | 505 1.1.2.2 skrll TIOCFLAG_CRTSCTS | TIOCFLAG_MDMBUF); 506 1.1.2.2 skrll break; 507 1.1.2.2 skrll default: 508 1.1.2.2 skrll error = ENOTTY; 509 1.1.2.2 skrll } 510 1.1.2.2 skrll 511 1.1.2.2 skrll return (error); 512 1.1.2.2 skrll } 513 1.1.2.2 skrll 514 1.1.2.2 skrll int 515 1.1.2.2 skrll stty_modem_control(sp, bits, how) 516 1.1.2.2 skrll struct stty_port *sp; 517 1.1.2.2 skrll int bits, how; 518 1.1.2.2 skrll { 519 1.1.2.2 skrll struct spif_softc *csc = sp->sp_sc; 520 1.1.2.2 skrll struct tty *tp = sp->sp_tty; 521 1.1.2.2 skrll int s, msvr; 522 1.1.2.2 skrll 523 1.1.2.2 skrll s = spltty(); 524 1.1.2.2 skrll STC_WRITE(csc, STC_CAR, sp->sp_channel); 525 1.1.2.2 skrll 526 1.1.2.2 skrll switch (how) { 527 1.1.2.2 skrll case DMGET: 528 1.1.2.2 skrll bits = TIOCM_LE; 529 1.1.2.2 skrll if (DTR_READ(csc, sp->sp_channel)) 530 1.1.2.2 skrll bits |= TIOCM_DTR; 531 1.1.2.2 skrll msvr = STC_READ(csc, STC_MSVR); 532 1.1.2.2 skrll if (ISSET(msvr, CD180_MSVR_DSR)) 533 1.1.2.2 skrll bits |= TIOCM_DSR; 534 1.1.2.2 skrll if (ISSET(msvr, CD180_MSVR_CD)) 535 1.1.2.2 skrll bits |= TIOCM_CD; 536 1.1.2.2 skrll if (ISSET(msvr, CD180_MSVR_CTS)) 537 1.1.2.2 skrll bits |= TIOCM_CTS; 538 1.1.2.2 skrll if (ISSET(msvr, CD180_MSVR_RTS)) 539 1.1.2.2 skrll bits |= TIOCM_RTS; 540 1.1.2.2 skrll break; 541 1.1.2.2 skrll case DMSET: 542 1.1.2.2 skrll DTR_WRITE(csc, sp->sp_channel, ISSET(bits, TIOCM_DTR) ? 1 : 0); 543 1.1.2.2 skrll if (ISSET(bits, TIOCM_RTS)) 544 1.1.2.2 skrll STC_WRITE(csc, STC_MSVR, 545 1.1.2.2 skrll STC_READ(csc, STC_MSVR) & (~CD180_MSVR_RTS)); 546 1.1.2.2 skrll else 547 1.1.2.2 skrll STC_WRITE(csc, STC_MSVR, 548 1.1.2.2 skrll STC_READ(csc, STC_MSVR) | CD180_MSVR_RTS); 549 1.1.2.2 skrll break; 550 1.1.2.2 skrll case DMBIS: 551 1.1.2.2 skrll if (ISSET(bits, TIOCM_DTR)) 552 1.1.2.2 skrll DTR_WRITE(csc, sp->sp_channel, 1); 553 1.1.2.2 skrll if (ISSET(bits, TIOCM_RTS) && !ISSET(tp->t_cflag, CRTSCTS)) 554 1.1.2.2 skrll STC_WRITE(csc, STC_MSVR, 555 1.1.2.2 skrll STC_READ(csc, STC_MSVR) & (~CD180_MSVR_RTS)); 556 1.1.2.2 skrll break; 557 1.1.2.2 skrll case DMBIC: 558 1.1.2.2 skrll if (ISSET(bits, TIOCM_DTR)) 559 1.1.2.2 skrll DTR_WRITE(csc, sp->sp_channel, 0); 560 1.1.2.2 skrll if (ISSET(bits, TIOCM_RTS)) 561 1.1.2.2 skrll STC_WRITE(csc, STC_MSVR, 562 1.1.2.2 skrll STC_READ(csc, STC_MSVR) | CD180_MSVR_RTS); 563 1.1.2.2 skrll break; 564 1.1.2.2 skrll } 565 1.1.2.2 skrll 566 1.1.2.2 skrll splx(s); 567 1.1.2.2 skrll return (bits); 568 1.1.2.2 skrll } 569 1.1.2.2 skrll 570 1.1.2.2 skrll int 571 1.1.2.2 skrll stty_param(tp, t) 572 1.1.2.2 skrll struct tty *tp; 573 1.1.2.2 skrll struct termios *t; 574 1.1.2.2 skrll { 575 1.1.2.2 skrll struct stty_softc *st = stty_cd.cd_devs[SPIF_CARD(tp->t_dev)]; 576 1.1.2.2 skrll struct stty_port *sp = &st->sc_port[SPIF_PORT(tp->t_dev)]; 577 1.1.2.2 skrll struct spif_softc *sc = sp->sp_sc; 578 1.1.2.2 skrll u_int8_t rbprl, rbprh, tbprl, tbprh; 579 1.1.2.2 skrll int s, opt; 580 1.1.2.2 skrll 581 1.1.2.2 skrll if (t->c_ospeed && 582 1.1.2.2 skrll stty_compute_baud(t->c_ospeed, sc->sc_osc, &tbprl, &tbprh)) 583 1.1.2.2 skrll return (EINVAL); 584 1.1.2.2 skrll 585 1.1.2.2 skrll if (t->c_ispeed && 586 1.1.2.2 skrll stty_compute_baud(t->c_ispeed, sc->sc_osc, &rbprl, &rbprh)) 587 1.1.2.2 skrll return (EINVAL); 588 1.1.2.2 skrll 589 1.1.2.2 skrll s = spltty(); 590 1.1.2.2 skrll 591 1.1.2.2 skrll /* hang up line if ospeed is zero, otherwise raise DTR */ 592 1.1.2.2 skrll stty_modem_control(sp, TIOCM_DTR, 593 1.1.2.2 skrll (t->c_ospeed == 0 ? DMBIC : DMBIS)); 594 1.1.2.2 skrll 595 1.1.2.2 skrll STC_WRITE(sc, STC_CAR, sp->sp_channel); 596 1.1.2.2 skrll 597 1.1.2.2 skrll opt = 0; 598 1.1.2.2 skrll if (ISSET(t->c_cflag, PARENB)) { 599 1.1.2.2 skrll opt |= CD180_COR1_PARMODE_NORMAL; 600 1.1.2.2 skrll opt |= (ISSET(t->c_cflag, PARODD) ? 601 1.1.2.2 skrll CD180_COR1_ODDPAR : 602 1.1.2.2 skrll CD180_COR1_EVENPAR); 603 1.1.2.2 skrll } 604 1.1.2.2 skrll else 605 1.1.2.2 skrll opt |= CD180_COR1_PARMODE_NO; 606 1.1.2.2 skrll 607 1.1.2.2 skrll if (!ISSET(t->c_iflag, INPCK)) 608 1.1.2.2 skrll opt |= CD180_COR1_IGNPAR; 609 1.1.2.2 skrll 610 1.1.2.2 skrll if (ISSET(t->c_cflag, CSTOPB)) 611 1.1.2.2 skrll opt |= CD180_COR1_STOP2; 612 1.1.2.2 skrll 613 1.1.2.2 skrll switch (t->c_cflag & CSIZE) { 614 1.1.2.2 skrll case CS5: 615 1.1.2.2 skrll opt |= CD180_COR1_CS5; 616 1.1.2.2 skrll break; 617 1.1.2.2 skrll case CS6: 618 1.1.2.2 skrll opt |= CD180_COR1_CS6; 619 1.1.2.2 skrll break; 620 1.1.2.2 skrll case CS7: 621 1.1.2.2 skrll opt |= CD180_COR1_CS7; 622 1.1.2.2 skrll break; 623 1.1.2.2 skrll default: 624 1.1.2.2 skrll opt |= CD180_COR1_CS8; 625 1.1.2.2 skrll break; 626 1.1.2.2 skrll } 627 1.1.2.2 skrll STC_WRITE(sc, STC_COR1, opt); 628 1.1.2.2 skrll stty_write_ccr(sc, CD180_CCR_CMD_COR|CD180_CCR_CORCHG1); 629 1.1.2.2 skrll 630 1.1.2.2 skrll opt = CD180_COR2_ETC; 631 1.1.2.2 skrll if (ISSET(t->c_cflag, CRTSCTS)) 632 1.1.2.2 skrll opt |= CD180_COR2_CTSAE; 633 1.1.2.2 skrll STC_WRITE(sc, STC_COR2, opt); 634 1.1.2.2 skrll stty_write_ccr(sc, CD180_CCR_CMD_COR|CD180_CCR_CORCHG2); 635 1.1.2.2 skrll 636 1.1.2.2 skrll STC_WRITE(sc, STC_COR3, STTY_RX_FIFO_THRESHOLD); 637 1.1.2.2 skrll stty_write_ccr(sc, CD180_CCR_CMD_COR|CD180_CCR_CORCHG3); 638 1.1.2.2 skrll 639 1.1.2.2 skrll STC_WRITE(sc, STC_SCHR1, 0x11); 640 1.1.2.2 skrll STC_WRITE(sc, STC_SCHR2, 0x13); 641 1.1.2.2 skrll STC_WRITE(sc, STC_SCHR3, 0x11); 642 1.1.2.2 skrll STC_WRITE(sc, STC_SCHR4, 0x13); 643 1.1.2.2 skrll STC_WRITE(sc, STC_RTPR, 0x12); 644 1.1.2.2 skrll 645 1.1.2.2 skrll STC_WRITE(sc, STC_MCOR1, CD180_MCOR1_CDZD | STTY_RX_DTR_THRESHOLD); 646 1.1.2.2 skrll STC_WRITE(sc, STC_MCOR2, CD180_MCOR2_CDOD); 647 1.1.2.2 skrll STC_WRITE(sc, STC_MCR, 0); 648 1.1.2.2 skrll 649 1.1.2.2 skrll if (t->c_ospeed) { 650 1.1.2.2 skrll STC_WRITE(sc, STC_TBPRH, tbprh); 651 1.1.2.2 skrll STC_WRITE(sc, STC_TBPRL, tbprl); 652 1.1.2.2 skrll } 653 1.1.2.2 skrll 654 1.1.2.2 skrll if (t->c_ispeed) { 655 1.1.2.2 skrll STC_WRITE(sc, STC_RBPRH, rbprh); 656 1.1.2.2 skrll STC_WRITE(sc, STC_RBPRL, rbprl); 657 1.1.2.2 skrll } 658 1.1.2.2 skrll 659 1.1.2.2 skrll stty_write_ccr(sc, CD180_CCR_CMD_CHAN | 660 1.1.2.2 skrll CD180_CCR_CHAN_TXEN | CD180_CCR_CHAN_RXEN); 661 1.1.2.2 skrll 662 1.1.2.2 skrll sp->sp_carrier = STC_READ(sc, STC_MSVR) & CD180_MSVR_CD; 663 1.1.2.2 skrll 664 1.1.2.2 skrll splx(s); 665 1.1.2.2 skrll return (0); 666 1.1.2.2 skrll } 667 1.1.2.2 skrll 668 1.1.2.2 skrll int 669 1.1.2.2 skrll stty_read(dev, uio, flags) 670 1.1.2.2 skrll dev_t dev; 671 1.1.2.2 skrll struct uio *uio; 672 1.1.2.2 skrll int flags; 673 1.1.2.2 skrll { 674 1.1.2.2 skrll struct stty_softc *sc = stty_cd.cd_devs[SPIF_CARD(dev)]; 675 1.1.2.2 skrll struct stty_port *sp = &sc->sc_port[SPIF_PORT(dev)]; 676 1.1.2.2 skrll struct tty *tp = sp->sp_tty; 677 1.1.2.2 skrll 678 1.1.2.2 skrll return ((*tp->t_linesw->l_read)(tp, uio, flags)); 679 1.1.2.2 skrll } 680 1.1.2.2 skrll 681 1.1.2.2 skrll int 682 1.1.2.2 skrll stty_write(dev, uio, flags) 683 1.1.2.2 skrll dev_t dev; 684 1.1.2.2 skrll struct uio *uio; 685 1.1.2.2 skrll int flags; 686 1.1.2.2 skrll { 687 1.1.2.2 skrll struct stty_softc *sc = stty_cd.cd_devs[SPIF_CARD(dev)]; 688 1.1.2.2 skrll struct stty_port *sp = &sc->sc_port[SPIF_PORT(dev)]; 689 1.1.2.2 skrll struct tty *tp = sp->sp_tty; 690 1.1.2.2 skrll 691 1.1.2.2 skrll return ((*tp->t_linesw->l_write)(tp, uio, flags)); 692 1.1.2.2 skrll } 693 1.1.2.2 skrll 694 1.1.2.2 skrll int 695 1.1.2.5 skrll stty_poll(dev, events, l) 696 1.1.2.2 skrll dev_t dev; 697 1.1.2.2 skrll int events; 698 1.1.2.5 skrll struct lwp *l; 699 1.1.2.2 skrll { 700 1.1.2.2 skrll struct stty_softc *sc = stty_cd.cd_devs[SPIF_CARD(dev)]; 701 1.1.2.2 skrll struct stty_port *sp = &sc->sc_port[SPIF_PORT(dev)]; 702 1.1.2.2 skrll struct tty *tp = sp->sp_tty; 703 1.1.2.6 skrll 704 1.1.2.5 skrll return ((*tp->t_linesw->l_poll)(tp, events, l)); 705 1.1.2.2 skrll } 706 1.1.2.2 skrll 707 1.1.2.2 skrll struct tty * 708 1.1.2.2 skrll stty_tty(dev) 709 1.1.2.2 skrll dev_t dev; 710 1.1.2.2 skrll { 711 1.1.2.2 skrll struct stty_softc *sc = stty_cd.cd_devs[SPIF_CARD(dev)]; 712 1.1.2.2 skrll struct stty_port *sp = &sc->sc_port[SPIF_PORT(dev)]; 713 1.1.2.2 skrll 714 1.1.2.2 skrll return (sp->sp_tty); 715 1.1.2.2 skrll } 716 1.1.2.2 skrll 717 1.1.2.2 skrll void 718 1.1.2.2 skrll stty_stop(tp, flags) 719 1.1.2.2 skrll struct tty *tp; 720 1.1.2.2 skrll int flags; 721 1.1.2.2 skrll { 722 1.1.2.2 skrll struct stty_softc *sc = stty_cd.cd_devs[SPIF_CARD(tp->t_dev)]; 723 1.1.2.2 skrll struct stty_port *sp = &sc->sc_port[SPIF_PORT(tp->t_dev)]; 724 1.1.2.2 skrll int s; 725 1.1.2.2 skrll 726 1.1.2.2 skrll s = spltty(); 727 1.1.2.2 skrll if (ISSET(tp->t_state, TS_BUSY)) { 728 1.1.2.2 skrll if (!ISSET(tp->t_state, TS_TTSTOP)) 729 1.1.2.2 skrll SET(tp->t_state, TS_FLUSH); 730 1.1.2.2 skrll SET(sp->sp_flags, STTYF_STOP); 731 1.1.2.2 skrll } 732 1.1.2.2 skrll splx(s); 733 1.1.2.2 skrll } 734 1.1.2.2 skrll 735 1.1.2.2 skrll void 736 1.1.2.2 skrll stty_start(tp) 737 1.1.2.2 skrll struct tty *tp; 738 1.1.2.2 skrll { 739 1.1.2.2 skrll struct stty_softc *stc = stty_cd.cd_devs[SPIF_CARD(tp->t_dev)]; 740 1.1.2.2 skrll struct stty_port *sp = &stc->sc_port[SPIF_PORT(tp->t_dev)]; 741 1.1.2.2 skrll struct spif_softc *sc = sp->sp_sc; 742 1.1.2.2 skrll int s; 743 1.1.2.2 skrll 744 1.1.2.2 skrll s = spltty(); 745 1.1.2.2 skrll 746 1.1.2.2 skrll if (!ISSET(tp->t_state, TS_TTSTOP | TS_TIMEOUT | TS_BUSY)) { 747 1.1.2.2 skrll if (tp->t_outq.c_cc <= tp->t_lowat) { 748 1.1.2.2 skrll if (ISSET(tp->t_state, TS_ASLEEP)) { 749 1.1.2.2 skrll CLR(tp->t_state, TS_ASLEEP); 750 1.1.2.2 skrll wakeup(&tp->t_outq); 751 1.1.2.2 skrll } 752 1.1.2.2 skrll selwakeup(&tp->t_wsel); 753 1.1.2.2 skrll } 754 1.1.2.2 skrll if (tp->t_outq.c_cc) { 755 1.1.2.2 skrll sp->sp_txc = ndqb(&tp->t_outq, 0); 756 1.1.2.2 skrll sp->sp_txp = tp->t_outq.c_cf; 757 1.1.2.2 skrll SET(tp->t_state, TS_BUSY); 758 1.1.2.2 skrll STC_WRITE(sc, STC_CAR, sp->sp_channel); 759 1.1.2.2 skrll STC_WRITE(sc, STC_SRER, 760 1.1.2.2 skrll STC_READ(sc, STC_SRER) | CD180_SRER_TXD); 761 1.1.2.2 skrll } 762 1.1.2.2 skrll } 763 1.1.2.2 skrll 764 1.1.2.2 skrll splx(s); 765 1.1.2.2 skrll } 766 1.1.2.2 skrll 767 1.1.2.2 skrll int 768 1.1.2.2 skrll spif_stcintr_rxexception(sc, needsoftp) 769 1.1.2.2 skrll struct spif_softc *sc; 770 1.1.2.2 skrll int *needsoftp; 771 1.1.2.2 skrll { 772 1.1.2.2 skrll struct stty_port *sp; 773 1.1.2.2 skrll u_int8_t channel, *ptr; 774 1.1.2.2 skrll 775 1.1.2.2 skrll channel = CD180_GSCR_CHANNEL(STC_READ(sc, STC_GSCR1)); 776 1.1.2.2 skrll sp = &sc->sc_ttys->sc_port[channel]; 777 1.1.2.2 skrll ptr = sp->sp_rput; 778 1.1.2.2 skrll *ptr++ = STC_READ(sc, STC_RCSR); 779 1.1.2.2 skrll *ptr++ = STC_READ(sc, STC_RDR); 780 1.1.2.2 skrll if (ptr == sp->sp_rend) 781 1.1.2.2 skrll ptr = sp->sp_rbuf; 782 1.1.2.2 skrll if (ptr == sp->sp_rget) { 783 1.1.2.2 skrll if (ptr == sp->sp_rbuf) 784 1.1.2.2 skrll ptr = sp->sp_rend; 785 1.1.2.2 skrll ptr -= 2; 786 1.1.2.2 skrll SET(sp->sp_flags, STTYF_RING_OVERFLOW); 787 1.1.2.2 skrll } 788 1.1.2.2 skrll STC_WRITE(sc, STC_EOSRR, 0); 789 1.1.2.2 skrll *needsoftp = 1; 790 1.1.2.2 skrll sp->sp_rput = ptr; 791 1.1.2.2 skrll return (1); 792 1.1.2.2 skrll } 793 1.1.2.2 skrll 794 1.1.2.2 skrll int 795 1.1.2.2 skrll spif_stcintr_rx(sc, needsoftp) 796 1.1.2.2 skrll struct spif_softc *sc; 797 1.1.2.2 skrll int *needsoftp; 798 1.1.2.2 skrll { 799 1.1.2.2 skrll struct stty_port *sp; 800 1.1.2.2 skrll u_int8_t channel, *ptr, cnt, rcsr; 801 1.1.2.2 skrll int i; 802 1.1.2.2 skrll 803 1.1.2.2 skrll channel = CD180_GSCR_CHANNEL(STC_READ(sc, STC_GSCR1)); 804 1.1.2.2 skrll sp = &sc->sc_ttys->sc_port[channel]; 805 1.1.2.2 skrll ptr = sp->sp_rput; 806 1.1.2.2 skrll cnt = STC_READ(sc, STC_RDCR); 807 1.1.2.2 skrll for (i = 0; i < cnt; i++) { 808 1.1.2.2 skrll *ptr++ = 0; 809 1.1.2.2 skrll rcsr = STC_READ(sc, STC_RCSR); 810 1.1.2.2 skrll *ptr++ = STC_READ(sc, STC_RDR); 811 1.1.2.2 skrll if (ptr == sp->sp_rend) 812 1.1.2.2 skrll ptr = sp->sp_rbuf; 813 1.1.2.2 skrll if (ptr == sp->sp_rget) { 814 1.1.2.2 skrll if (ptr == sp->sp_rbuf) 815 1.1.2.2 skrll ptr = sp->sp_rend; 816 1.1.2.2 skrll ptr -= 2; 817 1.1.2.2 skrll SET(sp->sp_flags, STTYF_RING_OVERFLOW); 818 1.1.2.2 skrll break; 819 1.1.2.2 skrll } 820 1.1.2.2 skrll } 821 1.1.2.2 skrll STC_WRITE(sc, STC_EOSRR, 0); 822 1.1.2.2 skrll if (cnt) { 823 1.1.2.2 skrll *needsoftp = 1; 824 1.1.2.2 skrll sp->sp_rput = ptr; 825 1.1.2.2 skrll } 826 1.1.2.2 skrll return (1); 827 1.1.2.2 skrll } 828 1.1.2.2 skrll 829 1.1.2.2 skrll int 830 1.1.2.2 skrll spif_stcintr_tx(sc, needsoftp) 831 1.1.2.2 skrll struct spif_softc *sc; 832 1.1.2.2 skrll int *needsoftp; 833 1.1.2.2 skrll { 834 1.1.2.2 skrll struct stty_port *sp; 835 1.1.2.2 skrll u_int8_t channel, ch; 836 1.1.2.2 skrll int cnt = 0; 837 1.1.2.2 skrll 838 1.1.2.2 skrll channel = CD180_GSCR_CHANNEL(STC_READ(sc, STC_GSCR1)); 839 1.1.2.2 skrll sp = &sc->sc_ttys->sc_port[channel]; 840 1.1.2.2 skrll if (!ISSET(sp->sp_flags, STTYF_STOP)) { 841 1.1.2.2 skrll if (ISSET(sp->sp_flags, STTYF_SET_BREAK)) { 842 1.1.2.2 skrll STC_WRITE(sc, STC_TDR, 0); 843 1.1.2.2 skrll STC_WRITE(sc, STC_TDR, 0x81); 844 1.1.2.2 skrll CLR(sp->sp_flags, STTYF_SET_BREAK); 845 1.1.2.2 skrll cnt += 2; 846 1.1.2.2 skrll } 847 1.1.2.2 skrll if (ISSET(sp->sp_flags, STTYF_CLR_BREAK)) { 848 1.1.2.2 skrll STC_WRITE(sc, STC_TDR, 0); 849 1.1.2.2 skrll STC_WRITE(sc, STC_TDR, 0x83); 850 1.1.2.2 skrll CLR(sp->sp_flags, STTYF_CLR_BREAK); 851 1.1.2.2 skrll cnt += 2; 852 1.1.2.2 skrll } 853 1.1.2.2 skrll 854 1.1.2.2 skrll while (sp->sp_txc > 0 && cnt < (CD180_TX_FIFO_SIZE-1)) { 855 1.1.2.2 skrll ch = *sp->sp_txp; 856 1.1.2.2 skrll sp->sp_txc--; 857 1.1.2.2 skrll sp->sp_txp++; 858 1.1.2.2 skrll 859 1.1.2.2 skrll if (ch == 0) { 860 1.1.2.2 skrll STC_WRITE(sc, STC_TDR, ch); 861 1.1.2.2 skrll cnt++; 862 1.1.2.2 skrll } 863 1.1.2.2 skrll STC_WRITE(sc, STC_TDR, ch); 864 1.1.2.2 skrll cnt++; 865 1.1.2.2 skrll } 866 1.1.2.2 skrll } 867 1.1.2.2 skrll 868 1.1.2.2 skrll if (sp->sp_txc == 0 || 869 1.1.2.2 skrll ISSET(sp->sp_flags, STTYF_STOP)) { 870 1.1.2.2 skrll STC_WRITE(sc, STC_SRER, STC_READ(sc, STC_SRER) & 871 1.1.2.2 skrll (~CD180_SRER_TXD)); 872 1.1.2.2 skrll CLR(sp->sp_flags, STTYF_STOP); 873 1.1.2.2 skrll SET(sp->sp_flags, STTYF_DONE); 874 1.1.2.2 skrll *needsoftp = 1; 875 1.1.2.2 skrll } 876 1.1.2.2 skrll 877 1.1.2.2 skrll STC_WRITE(sc, STC_EOSRR, 0); 878 1.1.2.2 skrll 879 1.1.2.2 skrll return (1); 880 1.1.2.2 skrll } 881 1.1.2.2 skrll 882 1.1.2.2 skrll int 883 1.1.2.2 skrll spif_stcintr_mx(sc, needsoftp) 884 1.1.2.2 skrll struct spif_softc *sc; 885 1.1.2.2 skrll int *needsoftp; 886 1.1.2.2 skrll { 887 1.1.2.2 skrll struct stty_port *sp; 888 1.1.2.2 skrll u_int8_t channel, mcr; 889 1.1.2.2 skrll 890 1.1.2.2 skrll channel = CD180_GSCR_CHANNEL(STC_READ(sc, STC_GSCR1)); 891 1.1.2.2 skrll sp = &sc->sc_ttys->sc_port[channel]; 892 1.1.2.2 skrll mcr = STC_READ(sc, STC_MCR); 893 1.1.2.2 skrll if (mcr & CD180_MCR_CD) { 894 1.1.2.2 skrll SET(sp->sp_flags, STTYF_CDCHG); 895 1.1.2.2 skrll *needsoftp = 1; 896 1.1.2.2 skrll } 897 1.1.2.2 skrll STC_WRITE(sc, STC_MCR, 0); 898 1.1.2.2 skrll STC_WRITE(sc, STC_EOSRR, 0); 899 1.1.2.2 skrll return (1); 900 1.1.2.2 skrll } 901 1.1.2.2 skrll 902 1.1.2.2 skrll int 903 1.1.2.2 skrll spif_stcintr(vsc) 904 1.1.2.2 skrll void *vsc; 905 1.1.2.2 skrll { 906 1.1.2.2 skrll struct spif_softc *sc = (struct spif_softc *)vsc; 907 1.1.2.2 skrll int needsoft = 0, r = 0, i; 908 1.1.2.2 skrll u_int8_t ar; 909 1.1.2.2 skrll 910 1.1.2.2 skrll for (i = 0; i < 8; i++) { 911 1.1.2.2 skrll ar = ISTC_READ(sc, STC_RRAR) & CD180_GSVR_IMASK; 912 1.1.2.2 skrll if (ar == CD180_GSVR_RXGOOD) 913 1.1.2.2 skrll r |= spif_stcintr_rx(sc, &needsoft); 914 1.1.2.2 skrll else if (ar == CD180_GSVR_RXEXCEPTION) 915 1.1.2.2 skrll r |= spif_stcintr_rxexception(sc, &needsoft); 916 1.1.2.2 skrll } 917 1.1.2.2 skrll 918 1.1.2.2 skrll for (i = 0; i < 8; i++) { 919 1.1.2.2 skrll ar = ISTC_READ(sc, STC_TRAR) & CD180_GSVR_IMASK; 920 1.1.2.2 skrll if (ar == CD180_GSVR_TXDATA) 921 1.1.2.2 skrll r |= spif_stcintr_tx(sc, &needsoft); 922 1.1.2.2 skrll } 923 1.1.2.2 skrll 924 1.1.2.2 skrll for (i = 0; i < 8; i++) { 925 1.1.2.2 skrll ar = ISTC_READ(sc, STC_MRAR) & CD180_GSVR_IMASK; 926 1.1.2.2 skrll if (ar == CD180_GSVR_STATCHG) 927 1.1.2.2 skrll r |= spif_stcintr_mx(sc, &needsoft); 928 1.1.2.2 skrll } 929 1.1.2.2 skrll 930 1.1.2.2 skrll if (needsoft) 931 1.1.2.2 skrll softintr_schedule(sc->sc_softih); 932 1.1.2.2 skrll return (r); 933 1.1.2.2 skrll } 934 1.1.2.2 skrll 935 1.1.2.2 skrll void 936 1.1.2.2 skrll spif_softintr(vsc) 937 1.1.2.2 skrll void *vsc; 938 1.1.2.2 skrll { 939 1.1.2.2 skrll struct spif_softc *sc = (struct spif_softc *)vsc; 940 1.1.2.2 skrll struct stty_softc *stc = sc->sc_ttys; 941 1.1.2.2 skrll int r = 0, i, data, s, flags; 942 1.1.2.2 skrll u_int8_t stat, msvr; 943 1.1.2.2 skrll struct stty_port *sp; 944 1.1.2.2 skrll struct tty *tp; 945 1.1.2.2 skrll 946 1.1.2.2 skrll if (stc != NULL) { 947 1.1.2.2 skrll for (i = 0; i < stc->sc_nports; i++) { 948 1.1.2.2 skrll sp = &stc->sc_port[i]; 949 1.1.2.2 skrll tp = sp->sp_tty; 950 1.1.2.2 skrll 951 1.1.2.2 skrll if (!ISSET(tp->t_state, TS_ISOPEN)) 952 1.1.2.2 skrll continue; 953 1.1.2.2 skrll 954 1.1.2.2 skrll while (sp->sp_rget != sp->sp_rput) { 955 1.1.2.2 skrll stat = sp->sp_rget[0]; 956 1.1.2.2 skrll data = sp->sp_rget[1]; 957 1.1.2.2 skrll sp->sp_rget += 2; 958 1.1.2.2 skrll if (sp->sp_rget == sp->sp_rend) 959 1.1.2.2 skrll sp->sp_rget = sp->sp_rbuf; 960 1.1.2.2 skrll 961 1.1.2.2 skrll if (stat & (CD180_RCSR_BE | CD180_RCSR_FE)) 962 1.1.2.2 skrll data |= TTY_FE; 963 1.1.2.2 skrll 964 1.1.2.2 skrll if (stat & CD180_RCSR_PE) 965 1.1.2.2 skrll data |= TTY_PE; 966 1.1.2.2 skrll 967 1.1.2.2 skrll (*tp->t_linesw->l_rint)(data, tp); 968 1.1.2.2 skrll r = 1; 969 1.1.2.2 skrll } 970 1.1.2.2 skrll 971 1.1.2.2 skrll s = splhigh(); 972 1.1.2.2 skrll flags = sp->sp_flags; 973 1.1.2.2 skrll CLR(sp->sp_flags, STTYF_DONE | STTYF_CDCHG | 974 1.1.2.2 skrll STTYF_RING_OVERFLOW); 975 1.1.2.2 skrll splx(s); 976 1.1.2.2 skrll 977 1.1.2.2 skrll if (ISSET(flags, STTYF_CDCHG)) { 978 1.1.2.2 skrll s = spltty(); 979 1.1.2.2 skrll STC_WRITE(sc, STC_CAR, i); 980 1.1.2.2 skrll msvr = STC_READ(sc, STC_MSVR); 981 1.1.2.2 skrll splx(s); 982 1.1.2.2 skrll 983 1.1.2.2 skrll sp->sp_carrier = msvr & CD180_MSVR_CD; 984 1.1.2.2 skrll (*tp->t_linesw->l_modem)(tp, 985 1.1.2.2 skrll sp->sp_carrier); 986 1.1.2.2 skrll r = 1; 987 1.1.2.2 skrll } 988 1.1.2.2 skrll 989 1.1.2.2 skrll if (ISSET(flags, STTYF_RING_OVERFLOW)) { 990 1.1.2.2 skrll log(LOG_WARNING, "%s-%x: ring overflow\n", 991 1.1.2.2 skrll stc->sc_dev.dv_xname, i); 992 1.1.2.2 skrll r = 1; 993 1.1.2.2 skrll } 994 1.1.2.2 skrll 995 1.1.2.2 skrll if (ISSET(flags, STTYF_DONE)) { 996 1.1.2.2 skrll ndflush(&tp->t_outq, 997 1.1.2.2 skrll sp->sp_txp - tp->t_outq.c_cf); 998 1.1.2.2 skrll CLR(tp->t_state, TS_BUSY); 999 1.1.2.2 skrll (*tp->t_linesw->l_start)(tp); 1000 1.1.2.2 skrll r = 1; 1001 1.1.2.2 skrll } 1002 1.1.2.2 skrll } 1003 1.1.2.2 skrll } 1004 1.1.2.2 skrll } 1005 1.1.2.2 skrll 1006 1.1.2.2 skrll void 1007 1.1.2.2 skrll stty_write_ccr(sc, val) 1008 1.1.2.2 skrll struct spif_softc *sc; 1009 1.1.2.2 skrll u_int8_t val; 1010 1.1.2.2 skrll { 1011 1.1.2.2 skrll int tries = 100000; 1012 1.1.2.2 skrll 1013 1.1.2.2 skrll while (STC_READ(sc, STC_CCR) && tries--) 1014 1.1.2.2 skrll /*EMPTY*/; 1015 1.1.2.2 skrll if (tries == 0) 1016 1.1.2.2 skrll printf("%s: ccr timeout\n", sc->sc_dev.dv_xname); 1017 1.1.2.2 skrll STC_WRITE(sc, STC_CCR, val); 1018 1.1.2.2 skrll } 1019 1.1.2.2 skrll 1020 1.1.2.2 skrll int 1021 1.1.2.2 skrll stty_compute_baud(speed, clock, bprlp, bprhp) 1022 1.1.2.2 skrll speed_t speed; 1023 1.1.2.2 skrll int clock; 1024 1.1.2.2 skrll u_int8_t *bprlp, *bprhp; 1025 1.1.2.2 skrll { 1026 1.1.2.2 skrll u_int32_t rate; 1027 1.1.2.2 skrll 1028 1.1.2.2 skrll rate = (2 * clock) / (16 * speed); 1029 1.1.2.2 skrll if (rate & 1) 1030 1.1.2.2 skrll rate = (rate >> 1) + 1; 1031 1.1.2.2 skrll else 1032 1.1.2.2 skrll rate = rate >> 1; 1033 1.1.2.2 skrll 1034 1.1.2.2 skrll if (rate > 0xffff || rate == 0) 1035 1.1.2.2 skrll return (1); 1036 1.1.2.2 skrll 1037 1.1.2.2 skrll *bprlp = rate & 0xff; 1038 1.1.2.2 skrll *bprhp = (rate >> 8) & 0xff; 1039 1.1.2.2 skrll return (0); 1040 1.1.2.2 skrll } 1041 1.1.2.2 skrll 1042 1.1.2.2 skrll int 1043 1.1.2.2 skrll sbpp_match(parent, vcf, aux) 1044 1.1.2.2 skrll struct device *parent; 1045 1.1.2.2 skrll struct cfdata *vcf; 1046 1.1.2.2 skrll void *aux; 1047 1.1.2.2 skrll { 1048 1.1.2.2 skrll struct spif_softc *sc = (struct spif_softc *)parent; 1049 1.1.2.2 skrll 1050 1.1.2.2 skrll return (aux == sbpp_match && sc->sc_bpps == NULL); 1051 1.1.2.2 skrll } 1052 1.1.2.2 skrll 1053 1.1.2.2 skrll void 1054 1.1.2.2 skrll sbpp_attach(parent, dev, aux) 1055 1.1.2.2 skrll struct device *parent, *dev; 1056 1.1.2.2 skrll void *aux; 1057 1.1.2.2 skrll { 1058 1.1.2.2 skrll struct spif_softc *sc = (struct spif_softc *)parent; 1059 1.1.2.2 skrll struct sbpp_softc *psc = (struct sbpp_softc *)dev; 1060 1.1.2.2 skrll int port; 1061 1.1.2.2 skrll 1062 1.1.2.2 skrll sc->sc_bpps = psc; 1063 1.1.2.2 skrll 1064 1.1.2.2 skrll for (port = 0; port < sc->sc_npar; port++) { 1065 1.1.2.2 skrll } 1066 1.1.2.2 skrll 1067 1.1.2.2 skrll psc->sc_nports = port; 1068 1.1.2.2 skrll printf(": %d port%s\n", port, port == 1 ? "" : "s"); 1069 1.1.2.2 skrll } 1070 1.1.2.2 skrll 1071 1.1.2.2 skrll int 1072 1.1.2.5 skrll sbpp_open(dev, flags, mode, l) 1073 1.1.2.2 skrll dev_t dev; 1074 1.1.2.2 skrll int flags; 1075 1.1.2.2 skrll int mode; 1076 1.1.2.5 skrll struct lwp *l; 1077 1.1.2.2 skrll { 1078 1.1.2.2 skrll return (ENXIO); 1079 1.1.2.2 skrll } 1080 1.1.2.2 skrll 1081 1.1.2.2 skrll int 1082 1.1.2.5 skrll sbpp_close(dev, flags, mode, l) 1083 1.1.2.2 skrll dev_t dev; 1084 1.1.2.2 skrll int flags; 1085 1.1.2.2 skrll int mode; 1086 1.1.2.5 skrll struct lwp *l; 1087 1.1.2.2 skrll { 1088 1.1.2.2 skrll return (ENXIO); 1089 1.1.2.2 skrll } 1090 1.1.2.2 skrll 1091 1.1.2.2 skrll int 1092 1.1.2.2 skrll spif_ppcintr(v) 1093 1.1.2.2 skrll void *v; 1094 1.1.2.2 skrll { 1095 1.1.2.2 skrll return (0); 1096 1.1.2.2 skrll } 1097 1.1.2.2 skrll 1098 1.1.2.2 skrll int 1099 1.1.2.2 skrll sbpp_read(dev, uio, flags) 1100 1.1.2.2 skrll dev_t dev; 1101 1.1.2.2 skrll struct uio *uio; 1102 1.1.2.2 skrll int flags; 1103 1.1.2.2 skrll { 1104 1.1.2.2 skrll return (sbpp_rw(dev, uio)); 1105 1.1.2.2 skrll } 1106 1.1.2.2 skrll 1107 1.1.2.2 skrll int 1108 1.1.2.2 skrll sbpp_write(dev, uio, flags) 1109 1.1.2.2 skrll dev_t dev; 1110 1.1.2.2 skrll struct uio *uio; 1111 1.1.2.2 skrll int flags; 1112 1.1.2.2 skrll { 1113 1.1.2.2 skrll return (sbpp_rw(dev, uio)); 1114 1.1.2.2 skrll } 1115 1.1.2.2 skrll 1116 1.1.2.2 skrll int 1117 1.1.2.2 skrll sbpp_rw(dev, uio) 1118 1.1.2.2 skrll dev_t dev; 1119 1.1.2.2 skrll struct uio *uio; 1120 1.1.2.2 skrll { 1121 1.1.2.2 skrll return (ENXIO); 1122 1.1.2.2 skrll } 1123 1.1.2.2 skrll 1124 1.1.2.2 skrll int 1125 1.1.2.5 skrll sbpp_poll(dev, events, l) 1126 1.1.2.2 skrll dev_t dev; 1127 1.1.2.2 skrll int events; 1128 1.1.2.5 skrll struct lwp *l; 1129 1.1.2.2 skrll { 1130 1.1.2.5 skrll return (seltrue(dev, events, l)); 1131 1.1.2.2 skrll } 1132 1.1.2.2 skrll 1133 1.1.2.2 skrll int 1134 1.1.2.5 skrll sbpp_ioctl(dev, cmd, data, flags, l) 1135 1.1.2.2 skrll dev_t dev; 1136 1.1.2.2 skrll u_long cmd; 1137 1.1.2.2 skrll caddr_t data; 1138 1.1.2.2 skrll int flags; 1139 1.1.2.5 skrll struct lwp *l; 1140 1.1.2.2 skrll { 1141 1.1.2.2 skrll int error; 1142 1.1.2.2 skrll 1143 1.1.2.2 skrll error = ENOTTY; 1144 1.1.2.2 skrll 1145 1.1.2.2 skrll return (error); 1146 1.1.2.2 skrll } 1147 1.1.2.2 skrll 1148 1.1.2.2 skrll #endif /* NSPIF */ 1149
Indexes created Mon Oct 20 20:10:13 GMT 2025