spif.c revision 1.20
1 /* $NetBSD: spif.c,v 1.20 2009/03/14 15:36:21 dsl Exp $ */ 2 /* $OpenBSD: spif.c,v 1.12 2003/10/03 16:44:51 miod Exp $ */ 3 4 /* 5 * Copyright (c) 1999-2002 Jason L. Wright (jason (at) thought.net) 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 19 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 20 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 21 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 22 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 23 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 25 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 26 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 * 29 * Effort sponsored in part by the Defense Advanced Research Projects 30 * Agency (DARPA) and Air Force Research Laboratory, Air Force 31 * Materiel Command, USAF, under agreement number F30602-01-2-0537. 32 * 33 */ 34 35 /* 36 * Driver for the SUNW,spif: 8 serial, 1 parallel sbus board 37 * based heavily on Iain Hibbert's driver for the MAGMA cards 38 */ 39 40 /* Ported to NetBSD 2.0 by Hauke Fath */ 41 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: spif.c,v 1.20 2009/03/14 15:36:21 dsl Exp $"); 45 46 #include "spif.h" 47 #if NSPIF > 0 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/proc.h> 52 #include <sys/device.h> 53 #include <sys/file.h> 54 #include <sys/ioctl.h> 55 #include <sys/malloc.h> 56 #include <sys/tty.h> 57 #include <sys/time.h> 58 #include <sys/kernel.h> 59 #include <sys/syslog.h> 60 #include <sys/conf.h> 61 #include <sys/errno.h> 62 #include <sys/kauth.h> 63 #include <sys/intr.h> 64 65 #include <sys/bus.h> 66 #include <machine/autoconf.h> 67 #include <machine/promlib.h> 68 69 #include <dev/sbus/sbusvar.h> 70 71 #include <dev/sbus/spifvar.h> 72 #include <dev/sbus/spifreg.h> 73 74 75 /* Autoconfig stuff */ 76 77 CFATTACH_DECL(spif, sizeof(struct spif_softc), 78 spif_match, spif_attach, NULL, NULL); 79 80 CFATTACH_DECL(stty, sizeof(struct stty_softc), 81 stty_match, stty_attach, NULL, NULL); 82 83 CFATTACH_DECL(sbpp, sizeof(struct sbpp_softc), 84 sbpp_match, sbpp_attach, NULL, NULL); 85 86 extern struct cfdriver spif_cd; 87 extern struct cfdriver stty_cd; 88 extern struct cfdriver sbpp_cd; 89 90 dev_type_open(stty_open); 91 dev_type_close(stty_close); 92 dev_type_read(stty_read); 93 dev_type_write(stty_write); 94 dev_type_ioctl(stty_ioctl); 95 dev_type_stop(stty_stop); 96 dev_type_tty(stty_tty); 97 dev_type_poll(stty_poll); 98 99 const struct cdevsw stty_cdevsw = { 100 stty_open, stty_close, stty_read, stty_write, stty_ioctl, 101 stty_stop, stty_tty, stty_poll, nommap, ttykqfilter, D_TTY 102 }; 103 104 dev_type_open(sbpp_open); 105 dev_type_close(sbpp_close); 106 dev_type_read(sbpp_read); 107 dev_type_write(sbpp_write); 108 dev_type_ioctl(sbpp_ioctl); 109 dev_type_poll(sbpp_poll); 110 111 const struct cdevsw sbpp_cdevsw = { 112 sbpp_open, sbpp_close, sbpp_read, sbpp_write, sbpp_ioctl, 113 nostop, notty, sbpp_poll, nommap, nokqfilter, D_OTHER 114 }; 115 116 117 /* normal STC access */ 118 #define STC_WRITE(sc,r,v) \ 119 bus_space_write_1((sc)->sc_bustag, (sc)->sc_stch, (r), (v)) 120 #define STC_READ(sc,r) \ 121 bus_space_read_1((sc)->sc_bustag, (sc)->sc_stch, (r)) 122 123 /* IACK STC access */ 124 #define ISTC_WRITE(sc,r,v) \ 125 bus_space_write_1((sc)->sc_bustag, (sc)->sc_istch, (r), (v)) 126 #define ISTC_READ(sc,r) \ 127 bus_space_read_1((sc)->sc_bustag, (sc)->sc_istch, (r)) 128 129 /* PPC access */ 130 #define PPC_WRITE(sc,r,v) \ 131 bus_space_write_1((sc)->sc_bustag, (sc)->sc_ppch, (r), (v)) 132 #define PPC_READ(sc,r) \ 133 bus_space_read_1((sc)->sc_bustag, (sc)->sc_ppch, (r)) 134 135 #define DTR_WRITE(sc,port,v) \ 136 do { \ 137 sc->sc_ttys->sc_port[(port)].sp_dtr = v; \ 138 bus_space_write_1((sc)->sc_bustag, \ 139 sc->sc_dtrh, port, (v == 0) ? 1 : 0); \ 140 } while (0) 141 142 #define DTR_READ(sc,port) ((sc)->sc_ttys->sc_port[(port)].sp_dtr) 143 144 145 int 146 spif_match(struct device *parent, struct cfdata *vcf, void *aux) 147 { 148 struct sbus_attach_args *sa = aux; 149 150 if (strcmp(vcf->cf_name, sa->sa_name) && 151 strcmp("SUNW,spif", sa->sa_name)) 152 return (0); 153 return (1); 154 } 155 156 void 157 spif_attach(parent, self, aux) 158 struct device *parent, *self; 159 void *aux; 160 { 161 struct spif_softc *sc = device_private(self); 162 struct sbus_attach_args *sa = aux; 163 164 if (sa->sa_nintr != 2) { 165 printf(": expected %d interrupts, got %d\n", 2, sa->sa_nintr); 166 return; 167 } 168 169 if (sa->sa_nreg != 1) { 170 printf(": expected %d registers, got %d\n", 1, sa->sa_nreg); 171 return; 172 } 173 174 sc->sc_bustag = sa->sa_bustag; 175 if (sbus_bus_map(sa->sa_bustag, sa->sa_slot, 176 sa->sa_offset, sa->sa_size, 177 0, &sc->sc_regh) != 0) { 178 printf(": can't map registers\n"); 179 return; 180 } 181 182 if (bus_space_subregion(sc->sc_bustag, sc->sc_regh, 183 DTR_REG_OFFSET, DTR_REG_LEN, &sc->sc_dtrh) != 0) { 184 printf(": can't map dtr regs\n"); 185 goto fail_unmapregs; 186 } 187 188 if (bus_space_subregion(sc->sc_bustag, sc->sc_regh, 189 STC_REG_OFFSET, STC_REG_LEN, &sc->sc_stch) != 0) { 190 printf(": can't map dtr regs\n"); 191 goto fail_unmapregs; 192 } 193 194 if (bus_space_subregion(sc->sc_bustag, sc->sc_regh, 195 ISTC_REG_OFFSET, ISTC_REG_LEN, &sc->sc_istch) != 0) { 196 printf(": can't map dtr regs\n"); 197 goto fail_unmapregs; 198 } 199 200 if (bus_space_subregion(sc->sc_bustag, sc->sc_regh, 201 PPC_REG_OFFSET, PPC_REG_LEN, &sc->sc_ppch) != 0) { 202 printf(": can't map dtr regs\n"); 203 goto fail_unmapregs; 204 } 205 206 sc->sc_ppcih = bus_intr_establish(sa->sa_bustag, 207 sa->sa_intr[PARALLEL_INTR].oi_pri, IPL_SERIAL, spif_ppcintr, sc); 208 if (sc->sc_ppcih == NULL) { 209 printf(": failed to establish ppc interrupt\n"); 210 goto fail_unmapregs; 211 } 212 213 sc->sc_stcih = bus_intr_establish(sa->sa_bustag, 214 sa->sa_intr[SERIAL_INTR].oi_pri, IPL_SERIAL, spif_stcintr, sc); 215 if (sc->sc_stcih == NULL) { 216 printf(": failed to establish stc interrupt\n"); 217 goto fail_unmapregs; 218 } 219 220 sc->sc_softih = softint_establish(SOFTINT_SERIAL, spif_softintr, sc); 221 if (sc->sc_softih == NULL) { 222 printf(": can't get soft intr\n"); 223 goto fail_unmapregs; 224 } 225 226 sc->sc_node = sa->sa_node; 227 228 sc->sc_rev = prom_getpropint(sc->sc_node, "revlev", 0); 229 230 sc->sc_osc = prom_getpropint(sc->sc_node, "verosc", 0); 231 switch (sc->sc_osc) { 232 case SPIF_OSC10: 233 sc->sc_osc = 10000000; 234 break; 235 case SPIF_OSC9: 236 default: 237 sc->sc_osc = 9830400; 238 break; 239 } 240 241 sc->sc_nser = 8; 242 sc->sc_npar = 1; 243 244 sc->sc_rev2 = STC_READ(sc, STC_GFRCR); 245 STC_WRITE(sc, STC_GSVR, 0); 246 247 stty_write_ccr(sc, CD180_CCR_CMD_RESET | CD180_CCR_RESETALL); 248 while (STC_READ(sc, STC_GSVR) != 0xff); 249 while (STC_READ(sc, STC_GFRCR) != sc->sc_rev2); 250 251 STC_WRITE(sc, STC_PPRH, CD180_PPRH); 252 STC_WRITE(sc, STC_PPRL, CD180_PPRL); 253 STC_WRITE(sc, STC_MSMR, SPIF_MSMR); 254 STC_WRITE(sc, STC_TSMR, SPIF_TSMR); 255 STC_WRITE(sc, STC_RSMR, SPIF_RSMR); 256 STC_WRITE(sc, STC_GSVR, 0); 257 STC_WRITE(sc, STC_GSCR1, 0); 258 STC_WRITE(sc, STC_GSCR2, 0); 259 STC_WRITE(sc, STC_GSCR3, 0); 260 261 printf(": rev %x chiprev %x osc %sMHz\n", 262 sc->sc_rev, sc->sc_rev2, clockfreq(sc->sc_osc)); 263 264 (void)config_found(self, stty_match, NULL); 265 (void)config_found(self, sbpp_match, NULL); 266 267 return; 268 269 fail_unmapregs: 270 bus_space_unmap(sa->sa_bustag, sc->sc_regh, sa->sa_size); 271 } 272 273 int 274 stty_match(struct device *parent, struct cfdata *vcf, void *aux) 275 { 276 struct spif_softc *sc = device_private(parent); 277 278 return (aux == stty_match && sc->sc_ttys == NULL); 279 } 280 281 void 282 stty_attach(parent, dev, aux) 283 struct device *parent, *dev; 284 void *aux; 285 { 286 struct spif_softc *sc = device_private(parent); 287 struct stty_softc *ssc = device_private(dev); 288 int port; 289 290 sc->sc_ttys = ssc; 291 292 for (port = 0; port < sc->sc_nser; port++) { 293 struct stty_port *sp = &ssc->sc_port[port]; 294 struct tty *tp; 295 296 DTR_WRITE(sc, port, 0); 297 298 tp = ttymalloc(); 299 300 tp->t_oproc = stty_start; 301 tp->t_param = stty_param; 302 303 sp->sp_tty = tp; 304 sp->sp_sc = sc; 305 sp->sp_channel = port; 306 307 sp->sp_rbuf = malloc(STTY_RBUF_SIZE, M_DEVBUF, M_NOWAIT); 308 if(sp->sp_rbuf == NULL) 309 break; 310 311 sp->sp_rend = sp->sp_rbuf + STTY_RBUF_SIZE; 312 } 313 314 ssc->sc_nports = port; 315 316 printf(": %d tty%s\n", port, port == 1 ? "" : "s"); 317 } 318 319 int 320 stty_open(dev_t dev, int flags, int mode, struct lwp *l) 321 { 322 struct spif_softc *csc; 323 struct stty_softc *sc; 324 struct stty_port *sp; 325 struct tty *tp; 326 int card = SPIF_CARD(dev); 327 int port = SPIF_PORT(dev); 328 329 sc = device_lookup_private(&stty_cd, card); 330 csc = device_lookup_private(&spif_cd, card); 331 if (sc == NULL || csc == NULL) 332 return (ENXIO); 333 334 if (port >= sc->sc_nports) 335 return (ENXIO); 336 337 sp = &sc->sc_port[port]; 338 tp = sp->sp_tty; 339 tp->t_dev = dev; 340 341 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 342 return (EBUSY); 343 344 mutex_spin_enter(&tty_lock); 345 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 346 ttychars(tp); 347 tp->t_iflag = TTYDEF_IFLAG; 348 tp->t_oflag = TTYDEF_OFLAG; 349 tp->t_cflag = TTYDEF_CFLAG; 350 if (ISSET(sp->sp_openflags, TIOCFLAG_CLOCAL)) 351 SET(tp->t_cflag, CLOCAL); 352 if (ISSET(sp->sp_openflags, TIOCFLAG_CRTSCTS)) 353 SET(tp->t_cflag, CRTSCTS); 354 if (ISSET(sp->sp_openflags, TIOCFLAG_MDMBUF)) 355 SET(tp->t_cflag, MDMBUF); 356 tp->t_lflag = TTYDEF_LFLAG; 357 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 358 359 sp->sp_rput = sp->sp_rget = sp->sp_rbuf; 360 361 STC_WRITE(csc, STC_CAR, sp->sp_channel); 362 stty_write_ccr(csc, CD180_CCR_CMD_RESET|CD180_CCR_RESETCHAN); 363 STC_WRITE(csc, STC_CAR, sp->sp_channel); 364 365 stty_param(tp, &tp->t_termios); 366 367 ttsetwater(tp); 368 369 STC_WRITE(csc, STC_SRER, CD180_SRER_CD | CD180_SRER_RXD); 370 371 if (ISSET(sp->sp_openflags, TIOCFLAG_SOFTCAR) || sp->sp_carrier) 372 SET(tp->t_state, TS_CARR_ON); 373 else 374 CLR(tp->t_state, TS_CARR_ON); 375 } 376 377 if (!ISSET(flags, O_NONBLOCK)) { 378 while (!ISSET(tp->t_cflag, CLOCAL) && 379 !ISSET(tp->t_state, TS_CARR_ON)) { 380 int error; 381 error = ttysleep(tp, &tp->t_rawcv, true, 0); 382 if (error != 0) { 383 mutex_spin_exit(&tty_lock); 384 return (error); 385 } 386 } 387 } 388 mutex_spin_exit(&tty_lock); 389 390 return ((*tp->t_linesw->l_open)(dev, tp)); 391 } 392 393 int 394 stty_close(dev_t dev, int flags, int mode, struct lwp *l) 395 { 396 struct stty_softc *sc = device_lookup_private(&stty_cd, SPIF_CARD(dev)); 397 struct stty_port *sp = &sc->sc_port[SPIF_PORT(dev)]; 398 struct spif_softc *csc = sp->sp_sc; 399 struct tty *tp = sp->sp_tty; 400 int port = SPIF_PORT(dev); 401 int s; 402 403 (*tp->t_linesw->l_close)(tp, flags); 404 s = spltty(); 405 406 if (ISSET(tp->t_cflag, HUPCL) || !ISSET(tp->t_state, TS_ISOPEN)) { 407 stty_modem_control(sp, 0, DMSET); 408 STC_WRITE(csc, STC_CAR, port); 409 STC_WRITE(csc, STC_CCR, 410 CD180_CCR_CMD_RESET|CD180_CCR_RESETCHAN); 411 } 412 413 splx(s); 414 ttyclose(tp); 415 return (0); 416 } 417 418 int 419 stty_ioctl(dev_t dev, u_long cmd, void *data, int flags, struct lwp *l) 420 { 421 struct stty_softc *stc = device_lookup_private(&stty_cd, 422 SPIF_CARD(dev)); 423 struct stty_port *sp = &stc->sc_port[SPIF_PORT(dev)]; 424 struct spif_softc *sc = sp->sp_sc; 425 struct tty *tp = sp->sp_tty; 426 int error; 427 428 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flags, l); 429 if (error >= 0) 430 return (error); 431 432 error = ttioctl(tp, cmd, data, flags, l); 433 if (error >= 0) 434 return (error); 435 436 error = 0; 437 438 switch (cmd) { 439 case TIOCSBRK: 440 SET(sp->sp_flags, STTYF_SET_BREAK); 441 STC_WRITE(sc, STC_CAR, sp->sp_channel); 442 STC_WRITE(sc, STC_SRER, 443 STC_READ(sc, STC_SRER) | CD180_SRER_TXD); 444 break; 445 case TIOCCBRK: 446 SET(sp->sp_flags, STTYF_CLR_BREAK); 447 STC_WRITE(sc, STC_CAR, sp->sp_channel); 448 STC_WRITE(sc, STC_SRER, 449 STC_READ(sc, STC_SRER) | CD180_SRER_TXD); 450 break; 451 case TIOCSDTR: 452 stty_modem_control(sp, TIOCM_DTR, DMBIS); 453 break; 454 case TIOCCDTR: 455 stty_modem_control(sp, TIOCM_DTR, DMBIC); 456 break; 457 case TIOCMBIS: 458 stty_modem_control(sp, *((int *)data), DMBIS); 459 break; 460 case TIOCMBIC: 461 stty_modem_control(sp, *((int *)data), DMBIC); 462 break; 463 case TIOCMGET: 464 *((int *)data) = stty_modem_control(sp, 0, DMGET); 465 break; 466 case TIOCMSET: 467 stty_modem_control(sp, *((int *)data), DMSET); 468 break; 469 case TIOCGFLAGS: 470 *((int *)data) = sp->sp_openflags; 471 break; 472 case TIOCSFLAGS: 473 if (kauth_authorize_device_tty(l->l_cred, 474 KAUTH_DEVICE_TTY_PRIVSET, tp)) 475 error = EPERM; 476 else 477 sp->sp_openflags = *((int *)data) & 478 (TIOCFLAG_SOFTCAR | TIOCFLAG_CLOCAL | 479 TIOCFLAG_CRTSCTS | TIOCFLAG_MDMBUF); 480 break; 481 default: 482 error = ENOTTY; 483 } 484 485 return (error); 486 } 487 488 int 489 stty_modem_control(sp, bits, how) 490 struct stty_port *sp; 491 int bits, how; 492 { 493 struct spif_softc *csc = sp->sp_sc; 494 struct tty *tp = sp->sp_tty; 495 int s, msvr; 496 497 s = spltty(); 498 STC_WRITE(csc, STC_CAR, sp->sp_channel); 499 500 switch (how) { 501 case DMGET: 502 bits = TIOCM_LE; 503 if (DTR_READ(csc, sp->sp_channel)) 504 bits |= TIOCM_DTR; 505 msvr = STC_READ(csc, STC_MSVR); 506 if (ISSET(msvr, CD180_MSVR_DSR)) 507 bits |= TIOCM_DSR; 508 if (ISSET(msvr, CD180_MSVR_CD)) 509 bits |= TIOCM_CD; 510 if (ISSET(msvr, CD180_MSVR_CTS)) 511 bits |= TIOCM_CTS; 512 if (ISSET(msvr, CD180_MSVR_RTS)) 513 bits |= TIOCM_RTS; 514 break; 515 case DMSET: 516 DTR_WRITE(csc, sp->sp_channel, ISSET(bits, TIOCM_DTR) ? 1 : 0); 517 if (ISSET(bits, TIOCM_RTS)) 518 STC_WRITE(csc, STC_MSVR, 519 STC_READ(csc, STC_MSVR) & (~CD180_MSVR_RTS)); 520 else 521 STC_WRITE(csc, STC_MSVR, 522 STC_READ(csc, STC_MSVR) | CD180_MSVR_RTS); 523 break; 524 case DMBIS: 525 if (ISSET(bits, TIOCM_DTR)) 526 DTR_WRITE(csc, sp->sp_channel, 1); 527 if (ISSET(bits, TIOCM_RTS) && !ISSET(tp->t_cflag, CRTSCTS)) 528 STC_WRITE(csc, STC_MSVR, 529 STC_READ(csc, STC_MSVR) & (~CD180_MSVR_RTS)); 530 break; 531 case DMBIC: 532 if (ISSET(bits, TIOCM_DTR)) 533 DTR_WRITE(csc, sp->sp_channel, 0); 534 if (ISSET(bits, TIOCM_RTS)) 535 STC_WRITE(csc, STC_MSVR, 536 STC_READ(csc, STC_MSVR) | CD180_MSVR_RTS); 537 break; 538 } 539 540 splx(s); 541 return (bits); 542 } 543 544 int 545 stty_param(struct tty *tp, struct termios *t) 546 { 547 struct stty_softc *st = device_lookup_private(&stty_cd, 548 SPIF_CARD(tp->t_dev)); 549 struct stty_port *sp = &st->sc_port[SPIF_PORT(tp->t_dev)]; 550 struct spif_softc *sc = sp->sp_sc; 551 u_int8_t rbprl, rbprh, tbprl, tbprh; 552 int s, opt; 553 554 if (t->c_ospeed && 555 stty_compute_baud(t->c_ospeed, sc->sc_osc, &tbprl, &tbprh)) 556 return (EINVAL); 557 558 if (t->c_ispeed && 559 stty_compute_baud(t->c_ispeed, sc->sc_osc, &rbprl, &rbprh)) 560 return (EINVAL); 561 562 s = spltty(); 563 564 /* hang up line if ospeed is zero, otherwise raise DTR */ 565 stty_modem_control(sp, TIOCM_DTR, 566 (t->c_ospeed == 0 ? DMBIC : DMBIS)); 567 568 STC_WRITE(sc, STC_CAR, sp->sp_channel); 569 570 opt = 0; 571 if (ISSET(t->c_cflag, PARENB)) { 572 opt |= CD180_COR1_PARMODE_NORMAL; 573 opt |= (ISSET(t->c_cflag, PARODD) ? 574 CD180_COR1_ODDPAR : 575 CD180_COR1_EVENPAR); 576 } 577 else 578 opt |= CD180_COR1_PARMODE_NO; 579 580 if (!ISSET(t->c_iflag, INPCK)) 581 opt |= CD180_COR1_IGNPAR; 582 583 if (ISSET(t->c_cflag, CSTOPB)) 584 opt |= CD180_COR1_STOP2; 585 586 switch (t->c_cflag & CSIZE) { 587 case CS5: 588 opt |= CD180_COR1_CS5; 589 break; 590 case CS6: 591 opt |= CD180_COR1_CS6; 592 break; 593 case CS7: 594 opt |= CD180_COR1_CS7; 595 break; 596 default: 597 opt |= CD180_COR1_CS8; 598 break; 599 } 600 STC_WRITE(sc, STC_COR1, opt); 601 stty_write_ccr(sc, CD180_CCR_CMD_COR|CD180_CCR_CORCHG1); 602 603 opt = CD180_COR2_ETC; 604 if (ISSET(t->c_cflag, CRTSCTS)) 605 opt |= CD180_COR2_CTSAE; 606 STC_WRITE(sc, STC_COR2, opt); 607 stty_write_ccr(sc, CD180_CCR_CMD_COR|CD180_CCR_CORCHG2); 608 609 STC_WRITE(sc, STC_COR3, STTY_RX_FIFO_THRESHOLD); 610 stty_write_ccr(sc, CD180_CCR_CMD_COR|CD180_CCR_CORCHG3); 611 612 STC_WRITE(sc, STC_SCHR1, 0x11); 613 STC_WRITE(sc, STC_SCHR2, 0x13); 614 STC_WRITE(sc, STC_SCHR3, 0x11); 615 STC_WRITE(sc, STC_SCHR4, 0x13); 616 STC_WRITE(sc, STC_RTPR, 0x12); 617 618 STC_WRITE(sc, STC_MCOR1, CD180_MCOR1_CDZD | STTY_RX_DTR_THRESHOLD); 619 STC_WRITE(sc, STC_MCOR2, CD180_MCOR2_CDOD); 620 STC_WRITE(sc, STC_MCR, 0); 621 622 if (t->c_ospeed) { 623 STC_WRITE(sc, STC_TBPRH, tbprh); 624 STC_WRITE(sc, STC_TBPRL, tbprl); 625 } 626 627 if (t->c_ispeed) { 628 STC_WRITE(sc, STC_RBPRH, rbprh); 629 STC_WRITE(sc, STC_RBPRL, rbprl); 630 } 631 632 stty_write_ccr(sc, CD180_CCR_CMD_CHAN | 633 CD180_CCR_CHAN_TXEN | CD180_CCR_CHAN_RXEN); 634 635 sp->sp_carrier = STC_READ(sc, STC_MSVR) & CD180_MSVR_CD; 636 637 splx(s); 638 return (0); 639 } 640 641 int 642 stty_read(dev_t dev, struct uio *uio, int flags) 643 { 644 struct stty_softc *sc = device_lookup_private(&stty_cd, SPIF_CARD(dev)); 645 struct stty_port *sp = &sc->sc_port[SPIF_PORT(dev)]; 646 struct tty *tp = sp->sp_tty; 647 648 return ((*tp->t_linesw->l_read)(tp, uio, flags)); 649 } 650 651 int 652 stty_write(dev_t dev, struct uio *uio, int flags) 653 { 654 struct stty_softc *sc = device_lookup_private(&stty_cd, SPIF_CARD(dev)); 655 struct stty_port *sp = &sc->sc_port[SPIF_PORT(dev)]; 656 struct tty *tp = sp->sp_tty; 657 658 return ((*tp->t_linesw->l_write)(tp, uio, flags)); 659 } 660 661 int 662 stty_poll(dev_t dev, int events, struct lwp *l) 663 { 664 struct stty_softc *sc = device_lookup_private(&stty_cd, SPIF_CARD(dev)); 665 struct stty_port *sp = &sc->sc_port[SPIF_PORT(dev)]; 666 struct tty *tp = sp->sp_tty; 667 668 return ((*tp->t_linesw->l_poll)(tp, events, l)); 669 } 670 671 struct tty * 672 stty_tty(dev_t dev) 673 { 674 struct stty_softc *sc = device_lookup_private(&stty_cd, SPIF_CARD(dev)); 675 struct stty_port *sp = &sc->sc_port[SPIF_PORT(dev)]; 676 677 return (sp->sp_tty); 678 } 679 680 void 681 stty_stop(struct tty *tp, int flags) 682 { 683 struct stty_softc *sc = device_lookup_private(&stty_cd, 684 SPIF_CARD(tp->t_dev)); 685 struct stty_port *sp = &sc->sc_port[SPIF_PORT(tp->t_dev)]; 686 int s; 687 688 s = spltty(); 689 if (ISSET(tp->t_state, TS_BUSY)) { 690 if (!ISSET(tp->t_state, TS_TTSTOP)) 691 SET(tp->t_state, TS_FLUSH); 692 SET(sp->sp_flags, STTYF_STOP); 693 } 694 splx(s); 695 } 696 697 void 698 stty_start(struct tty *tp) 699 { 700 struct stty_softc *stc = device_lookup_private(&stty_cd, 701 SPIF_CARD(tp->t_dev)); 702 struct stty_port *sp = &stc->sc_port[SPIF_PORT(tp->t_dev)]; 703 struct spif_softc *sc = sp->sp_sc; 704 int s; 705 706 s = spltty(); 707 708 if (!ISSET(tp->t_state, TS_TTSTOP | TS_TIMEOUT | TS_BUSY)) { 709 if (ttypull(tp)) { 710 sp->sp_txc = ndqb(&tp->t_outq, 0); 711 sp->sp_txp = tp->t_outq.c_cf; 712 SET(tp->t_state, TS_BUSY); 713 STC_WRITE(sc, STC_CAR, sp->sp_channel); 714 STC_WRITE(sc, STC_SRER, 715 STC_READ(sc, STC_SRER) | CD180_SRER_TXD); 716 } 717 } 718 719 splx(s); 720 } 721 722 int 723 spif_stcintr_rxexception(struct spif_softc *sc, int *needsoftp) 724 { 725 struct stty_port *sp; 726 u_int8_t channel, *ptr; 727 728 channel = CD180_GSCR_CHANNEL(STC_READ(sc, STC_GSCR1)); 729 sp = &sc->sc_ttys->sc_port[channel]; 730 ptr = sp->sp_rput; 731 *ptr++ = STC_READ(sc, STC_RCSR); 732 *ptr++ = STC_READ(sc, STC_RDR); 733 if (ptr == sp->sp_rend) 734 ptr = sp->sp_rbuf; 735 if (ptr == sp->sp_rget) { 736 if (ptr == sp->sp_rbuf) 737 ptr = sp->sp_rend; 738 ptr -= 2; 739 SET(sp->sp_flags, STTYF_RING_OVERFLOW); 740 } 741 STC_WRITE(sc, STC_EOSRR, 0); 742 *needsoftp = 1; 743 sp->sp_rput = ptr; 744 return (1); 745 } 746 747 int 748 spif_stcintr_rx(struct spif_softc *sc, int *needsoftp) 749 { 750 struct stty_port *sp; 751 u_int8_t channel, *ptr, cnt, rcsr; 752 int i; 753 754 channel = CD180_GSCR_CHANNEL(STC_READ(sc, STC_GSCR1)); 755 sp = &sc->sc_ttys->sc_port[channel]; 756 ptr = sp->sp_rput; 757 cnt = STC_READ(sc, STC_RDCR); 758 for (i = 0; i < cnt; i++) { 759 *ptr++ = 0; 760 rcsr = STC_READ(sc, STC_RCSR); 761 *ptr++ = STC_READ(sc, STC_RDR); 762 if (ptr == sp->sp_rend) 763 ptr = sp->sp_rbuf; 764 if (ptr == sp->sp_rget) { 765 if (ptr == sp->sp_rbuf) 766 ptr = sp->sp_rend; 767 ptr -= 2; 768 SET(sp->sp_flags, STTYF_RING_OVERFLOW); 769 break; 770 } 771 } 772 STC_WRITE(sc, STC_EOSRR, 0); 773 if (cnt) { 774 *needsoftp = 1; 775 sp->sp_rput = ptr; 776 } 777 return (1); 778 } 779 780 int 781 spif_stcintr_tx(struct spif_softc *sc, int *needsoftp) 782 { 783 struct stty_port *sp; 784 u_int8_t channel, ch; 785 int cnt = 0; 786 787 channel = CD180_GSCR_CHANNEL(STC_READ(sc, STC_GSCR1)); 788 sp = &sc->sc_ttys->sc_port[channel]; 789 if (!ISSET(sp->sp_flags, STTYF_STOP)) { 790 if (ISSET(sp->sp_flags, STTYF_SET_BREAK)) { 791 STC_WRITE(sc, STC_TDR, 0); 792 STC_WRITE(sc, STC_TDR, 0x81); 793 CLR(sp->sp_flags, STTYF_SET_BREAK); 794 cnt += 2; 795 } 796 if (ISSET(sp->sp_flags, STTYF_CLR_BREAK)) { 797 STC_WRITE(sc, STC_TDR, 0); 798 STC_WRITE(sc, STC_TDR, 0x83); 799 CLR(sp->sp_flags, STTYF_CLR_BREAK); 800 cnt += 2; 801 } 802 803 while (sp->sp_txc > 0 && cnt < (CD180_TX_FIFO_SIZE-1)) { 804 ch = *sp->sp_txp; 805 sp->sp_txc--; 806 sp->sp_txp++; 807 808 if (ch == 0) { 809 STC_WRITE(sc, STC_TDR, ch); 810 cnt++; 811 } 812 STC_WRITE(sc, STC_TDR, ch); 813 cnt++; 814 } 815 } 816 817 if (sp->sp_txc == 0 || 818 ISSET(sp->sp_flags, STTYF_STOP)) { 819 STC_WRITE(sc, STC_SRER, STC_READ(sc, STC_SRER) & 820 (~CD180_SRER_TXD)); 821 CLR(sp->sp_flags, STTYF_STOP); 822 SET(sp->sp_flags, STTYF_DONE); 823 *needsoftp = 1; 824 } 825 826 STC_WRITE(sc, STC_EOSRR, 0); 827 828 return (1); 829 } 830 831 int 832 spif_stcintr_mx(struct spif_softc *sc, int *needsoftp) 833 { 834 struct stty_port *sp; 835 u_int8_t channel, mcr; 836 837 channel = CD180_GSCR_CHANNEL(STC_READ(sc, STC_GSCR1)); 838 sp = &sc->sc_ttys->sc_port[channel]; 839 mcr = STC_READ(sc, STC_MCR); 840 if (mcr & CD180_MCR_CD) { 841 SET(sp->sp_flags, STTYF_CDCHG); 842 *needsoftp = 1; 843 } 844 STC_WRITE(sc, STC_MCR, 0); 845 STC_WRITE(sc, STC_EOSRR, 0); 846 return (1); 847 } 848 849 int 850 spif_stcintr(void *vsc) 851 { 852 struct spif_softc *sc = (struct spif_softc *)vsc; 853 int needsoft = 0, r = 0, i; 854 u_int8_t ar; 855 856 for (i = 0; i < 8; i++) { 857 ar = ISTC_READ(sc, STC_RRAR) & CD180_GSVR_IMASK; 858 if (ar == CD180_GSVR_RXGOOD) 859 r |= spif_stcintr_rx(sc, &needsoft); 860 else if (ar == CD180_GSVR_RXEXCEPTION) 861 r |= spif_stcintr_rxexception(sc, &needsoft); 862 } 863 864 for (i = 0; i < 8; i++) { 865 ar = ISTC_READ(sc, STC_TRAR) & CD180_GSVR_IMASK; 866 if (ar == CD180_GSVR_TXDATA) 867 r |= spif_stcintr_tx(sc, &needsoft); 868 } 869 870 for (i = 0; i < 8; i++) { 871 ar = ISTC_READ(sc, STC_MRAR) & CD180_GSVR_IMASK; 872 if (ar == CD180_GSVR_STATCHG) 873 r |= spif_stcintr_mx(sc, &needsoft); 874 } 875 876 if (needsoft) 877 softint_schedule(sc->sc_softih); 878 return (r); 879 } 880 881 void 882 spif_softintr(void *vsc) 883 { 884 struct spif_softc *sc = (struct spif_softc *)vsc; 885 struct stty_softc *stc = sc->sc_ttys; 886 int r = 0, i, data, s, flags; 887 u_int8_t stat, msvr; 888 struct stty_port *sp; 889 struct tty *tp; 890 891 if (stc != NULL) { 892 for (i = 0; i < stc->sc_nports; i++) { 893 sp = &stc->sc_port[i]; 894 tp = sp->sp_tty; 895 896 if (!ISSET(tp->t_state, TS_ISOPEN)) 897 continue; 898 899 while (sp->sp_rget != sp->sp_rput) { 900 stat = sp->sp_rget[0]; 901 data = sp->sp_rget[1]; 902 sp->sp_rget += 2; 903 if (sp->sp_rget == sp->sp_rend) 904 sp->sp_rget = sp->sp_rbuf; 905 906 if (stat & (CD180_RCSR_BE | CD180_RCSR_FE)) 907 data |= TTY_FE; 908 909 if (stat & CD180_RCSR_PE) 910 data |= TTY_PE; 911 912 (*tp->t_linesw->l_rint)(data, tp); 913 r = 1; 914 } 915 916 s = splhigh(); 917 flags = sp->sp_flags; 918 CLR(sp->sp_flags, STTYF_DONE | STTYF_CDCHG | 919 STTYF_RING_OVERFLOW); 920 splx(s); 921 922 if (ISSET(flags, STTYF_CDCHG)) { 923 s = spltty(); 924 STC_WRITE(sc, STC_CAR, i); 925 msvr = STC_READ(sc, STC_MSVR); 926 splx(s); 927 928 sp->sp_carrier = msvr & CD180_MSVR_CD; 929 (*tp->t_linesw->l_modem)(tp, 930 sp->sp_carrier); 931 r = 1; 932 } 933 934 if (ISSET(flags, STTYF_RING_OVERFLOW)) { 935 log(LOG_WARNING, "%s-%x: ring overflow\n", 936 device_xname(&stc->sc_dev), i); 937 r = 1; 938 } 939 940 if (ISSET(flags, STTYF_DONE)) { 941 ndflush(&tp->t_outq, 942 sp->sp_txp - tp->t_outq.c_cf); 943 CLR(tp->t_state, TS_BUSY); 944 (*tp->t_linesw->l_start)(tp); 945 r = 1; 946 } 947 } 948 } 949 } 950 951 void 952 stty_write_ccr(struct spif_softc *sc, u_int8_t val) 953 { 954 int tries = 100000; 955 956 while (STC_READ(sc, STC_CCR) && tries--) 957 /*EMPTY*/; 958 if (tries == 0) 959 aprint_error_dev(&sc->sc_dev, "ccr timeout\n"); 960 STC_WRITE(sc, STC_CCR, val); 961 } 962 963 int 964 stty_compute_baud(speed, clock, bprlp, bprhp) 965 speed_t speed; 966 int clock; 967 u_int8_t *bprlp, *bprhp; 968 { 969 u_int32_t rate; 970 971 rate = (2 * clock) / (16 * speed); 972 if (rate & 1) 973 rate = (rate >> 1) + 1; 974 else 975 rate = rate >> 1; 976 977 if (rate > 0xffff || rate == 0) 978 return (1); 979 980 *bprlp = rate & 0xff; 981 *bprhp = (rate >> 8) & 0xff; 982 return (0); 983 } 984 985 int 986 sbpp_match(struct device *parent, struct cfdata *vcf, void *aux) 987 { 988 struct spif_softc *sc = device_private(parent); 989 990 return (aux == sbpp_match && sc->sc_bpps == NULL); 991 } 992 993 void 994 sbpp_attach(parent, dev, aux) 995 struct device *parent, *dev; 996 void *aux; 997 { 998 struct spif_softc *sc = device_private(parent); 999 struct sbpp_softc *psc = device_private(dev); 1000 int port; 1001 1002 sc->sc_bpps = psc; 1003 1004 for (port = 0; port < sc->sc_npar; port++) { 1005 } 1006 1007 psc->sc_nports = port; 1008 printf(": %d port%s\n", port, port == 1 ? "" : "s"); 1009 } 1010 1011 int 1012 sbpp_open(dev_t dev, int flags, int mode, struct lwp *l) 1013 { 1014 return (ENXIO); 1015 } 1016 1017 int 1018 sbpp_close(dev_t dev, int flags, int mode, struct lwp *l) 1019 { 1020 return (ENXIO); 1021 } 1022 1023 int 1024 spif_ppcintr(void *v) 1025 { 1026 return (0); 1027 } 1028 1029 int 1030 sbpp_read(dev_t dev, struct uio *uio, int flags) 1031 { 1032 return (sbpp_rw(dev, uio)); 1033 } 1034 1035 int 1036 sbpp_write(dev_t dev, struct uio *uio, int flags) 1037 { 1038 return (sbpp_rw(dev, uio)); 1039 } 1040 1041 int 1042 sbpp_rw(dev_t dev, struct uio *uio) 1043 { 1044 return (ENXIO); 1045 } 1046 1047 int 1048 sbpp_poll(dev_t dev, int events, struct lwp *l) 1049 { 1050 return (seltrue(dev, events, l)); 1051 } 1052 1053 int 1054 sbpp_ioctl(dev_t dev, u_long cmd, void *data, int flags, struct lwp *l) 1055 { 1056 int error; 1057 1058 error = ENOTTY; 1059 1060 return (error); 1061 } 1062 1063 #endif /* NSPIF */ 1064
Indexes created Wed Sep 24 05:09:52 GMT 2025