1 1.5 andvar /* $NetBSD: spifvar.h,v 1.5 2022/10/31 20:30:23 andvar Exp $ */ 2 1.1 mrg /* $OpenBSD: spifvar.h,v 1.3 2003/06/02 18:32:41 jason Exp $ */ 3 1.1 mrg 4 1.1 mrg /* 5 1.1 mrg * Copyright (c) 1999-2002 Jason L. Wright (jason (at) thought.net) 6 1.1 mrg * All rights reserved. 7 1.1 mrg * 8 1.1 mrg * Redistribution and use in source and binary forms, with or without 9 1.1 mrg * modification, are permitted provided that the following conditions 10 1.1 mrg * are met: 11 1.1 mrg * 1. Redistributions of source code must retain the above copyright 12 1.1 mrg * notice, this list of conditions and the following disclaimer. 13 1.1 mrg * 2. Redistributions in binary form must reproduce the above copyright 14 1.1 mrg * notice, this list of conditions and the following disclaimer in the 15 1.1 mrg * documentation and/or other materials provided with the distribution. 16 1.1 mrg * 17 1.1 mrg * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 1.1 mrg * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 19 1.1 mrg * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 20 1.1 mrg * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 21 1.1 mrg * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 22 1.1 mrg * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 23 1.1 mrg * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 1.1 mrg * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 25 1.1 mrg * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 26 1.1 mrg * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 1.1 mrg * POSSIBILITY OF SUCH DAMAGE. 28 1.1 mrg * 29 1.1 mrg * Effort sponsored in part by the Defense Advanced Research Projects 30 1.1 mrg * Agency (DARPA) and Air Force Research Laboratory, Air Force 31 1.1 mrg * Materiel Command, USAF, under agreement number F30602-01-2-0537. 32 1.1 mrg * 33 1.1 mrg */ 34 1.1 mrg 35 1.1 mrg #define SPIF_MAX_SERIAL 8 36 1.1 mrg #define SPIF_MAX_PARALLEL 1 37 1.1 mrg 38 1.1 mrg struct stty_port { 39 1.1 mrg struct tty *sp_tty; /* tty device */ 40 1.1 mrg struct spif_softc *sp_sc; /* pointer back to registers */ 41 1.1 mrg int sp_channel; /* channel number */ 42 1.1 mrg u_char *sp_rbuf; /* ring buffer start */ 43 1.1 mrg u_char *sp_rend; /* ring buffer end */ 44 1.1 mrg u_char *sp_rget; /* ring buffer read pointer */ 45 1.1 mrg u_char *sp_rput; /* ring buffer write pointer */ 46 1.1 mrg u_char *sp_txp; /* transmit character pointer */ 47 1.1 mrg int sp_txc; /* transmit character counter */ 48 1.1 mrg 49 1.1 mrg int sp_openflags; /* open flags */ 50 1.1 mrg int sp_carrier; /* software carrier status */ 51 1.1 mrg int sp_flags; /* software state */ 52 1.1 mrg char sp_dtr; /* software dtr status */ 53 1.1 mrg }; 54 1.1 mrg 55 1.1 mrg struct stty_softc { 56 1.4 mrg device_t sc_dev; 57 1.1 mrg int sc_nports; /* number of serial ports */ 58 1.1 mrg struct stty_port sc_port[SPIF_MAX_SERIAL]; 59 1.1 mrg }; 60 1.1 mrg 61 1.1 mrg struct sbpp_softc { 62 1.1 mrg int sc_nports; /* number of parallel ports */ 63 1.1 mrg }; 64 1.1 mrg 65 1.1 mrg struct spif_softc { 66 1.4 mrg device_t sc_dev; 67 1.1 mrg void *sc_stcih; /* stc interrupt vector */ 68 1.5 andvar void *sc_ppcih; /* ppc interrupt vector */ 69 1.1 mrg void *sc_softih; /* soft interrupt vector */ 70 1.1 mrg int sc_rev; /* revision level */ 71 1.1 mrg int sc_osc; /* oscillator speed (hz) */ 72 1.1 mrg int sc_node; /* which sbus node */ 73 1.1 mrg int sc_nser; /* number of serial ports */ 74 1.1 mrg int sc_npar; /* number of parallel ports */ 75 1.1 mrg int sc_rev2; /* cd180 chip revision */ 76 1.1 mrg bus_space_tag_t sc_bustag; /* our bus tag */ 77 1.1 mrg bus_space_handle_t sc_regh; /* whole register map */ 78 1.1 mrg bus_space_handle_t sc_stch; /* STC registers */ 79 1.1 mrg bus_space_handle_t sc_istch; /* IACK STC registers */ 80 1.1 mrg bus_space_handle_t sc_dtrh; /* DTR registers */ 81 1.1 mrg bus_space_handle_t sc_ppch; /* PPC registers */ 82 1.1 mrg struct spifregs *sc_regs; /* registers */ 83 1.1 mrg struct stty_softc *sc_ttys; /* our ttys */ 84 1.1 mrg struct sbpp_softc *sc_bpps; /* our ttys */ 85 1.1 mrg }; 86