stp4020.c revision 1.49.6.3 1 1.49.6.3 ad /* $NetBSD: stp4020.c,v 1.49.6.3 2007/07/15 13:21:43 ad Exp $ */
2 1.1 pk
3 1.1 pk /*-
4 1.1 pk * Copyright (c) 1998 The NetBSD Foundation, Inc.
5 1.1 pk * All rights reserved.
6 1.1 pk *
7 1.1 pk * This code is derived from software contributed to The NetBSD Foundation
8 1.1 pk * by Paul Kranenburg.
9 1.1 pk *
10 1.1 pk * Redistribution and use in source and binary forms, with or without
11 1.1 pk * modification, are permitted provided that the following conditions
12 1.1 pk * are met:
13 1.1 pk * 1. Redistributions of source code must retain the above copyright
14 1.1 pk * notice, this list of conditions and the following disclaimer.
15 1.1 pk * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 pk * notice, this list of conditions and the following disclaimer in the
17 1.1 pk * documentation and/or other materials provided with the distribution.
18 1.1 pk * 3. All advertising materials mentioning features or use of this software
19 1.1 pk * must display the following acknowledgement:
20 1.1 pk * This product includes software developed by the NetBSD
21 1.1 pk * Foundation, Inc. and its contributors.
22 1.1 pk * 4. Neither the name of The NetBSD Foundation nor the names of its
23 1.1 pk * contributors may be used to endorse or promote products derived
24 1.1 pk * from this software without specific prior written permission.
25 1.1 pk *
26 1.1 pk * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 1.1 pk * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 1.1 pk * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 1.1 pk * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 1.1 pk * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 1.1 pk * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 1.1 pk * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 1.1 pk * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 1.1 pk * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 1.1 pk * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 1.1 pk * POSSIBILITY OF SUCH DAMAGE.
37 1.1 pk */
38 1.1 pk
39 1.1 pk /*
40 1.1 pk * STP4020: SBus/PCMCIA bridge supporting two Type-3 PCMCIA cards.
41 1.1 pk */
42 1.12 lukem
43 1.12 lukem #include <sys/cdefs.h>
44 1.49.6.3 ad __KERNEL_RCSID(0, "$NetBSD: stp4020.c,v 1.49.6.3 2007/07/15 13:21:43 ad Exp $");
45 1.1 pk
46 1.1 pk #include <sys/param.h>
47 1.1 pk #include <sys/systm.h>
48 1.1 pk #include <sys/errno.h>
49 1.1 pk #include <sys/malloc.h>
50 1.15 martin #include <sys/extent.h>
51 1.1 pk #include <sys/proc.h>
52 1.1 pk #include <sys/kernel.h>
53 1.1 pk #include <sys/kthread.h>
54 1.1 pk #include <sys/device.h>
55 1.49.6.2 ad #include <sys/intr.h>
56 1.1 pk
57 1.1 pk #include <dev/pcmcia/pcmciareg.h>
58 1.1 pk #include <dev/pcmcia/pcmciavar.h>
59 1.1 pk #include <dev/pcmcia/pcmciachip.h>
60 1.1 pk
61 1.1 pk #include <machine/bus.h>
62 1.1 pk
63 1.1 pk #include <dev/sbus/sbusvar.h>
64 1.1 pk #include <dev/sbus/stp4020reg.h>
65 1.1 pk
66 1.1 pk #define STP4020_DEBUG 1 /* XXX-temp */
67 1.1 pk
68 1.15 martin /*
69 1.15 martin * We use the three available windows per socket in a simple, fixed
70 1.15 martin * arrangement. Each window maps (at full 1 MB size) one of the pcmcia
71 1.15 martin * spaces into sbus space.
72 1.15 martin */
73 1.15 martin #define STP_WIN_ATTR 0 /* index of the attribute memory space window */
74 1.15 martin #define STP_WIN_MEM 1 /* index of the common memory space window */
75 1.15 martin #define STP_WIN_IO 2 /* index of the io space window */
76 1.15 martin
77 1.15 martin
78 1.1 pk #if defined(STP4020_DEBUG)
79 1.1 pk int stp4020_debug = 0;
80 1.1 pk #define DPRINTF(x) do { if (stp4020_debug) printf x; } while(0)
81 1.1 pk #else
82 1.1 pk #define DPRINTF(x)
83 1.1 pk #endif
84 1.1 pk
85 1.1 pk /*
86 1.1 pk * Event queue; events detected in an interrupt context go here
87 1.1 pk * awaiting attention from our event handling thread.
88 1.1 pk */
89 1.1 pk struct stp4020_event {
90 1.1 pk SIMPLEQ_ENTRY(stp4020_event) se_q;
91 1.1 pk int se_type;
92 1.1 pk int se_sock;
93 1.1 pk };
94 1.1 pk /* Defined event types */
95 1.1 pk #define STP4020_EVENT_INSERTION 0
96 1.1 pk #define STP4020_EVENT_REMOVAL 1
97 1.1 pk
98 1.1 pk /*
99 1.1 pk * Per socket data.
100 1.1 pk */
101 1.1 pk struct stp4020_socket {
102 1.1 pk struct stp4020_softc *sc; /* Back link */
103 1.1 pk int flags;
104 1.1 pk #define STP4020_SOCKET_BUSY 0x0001
105 1.1 pk int sock; /* Socket number (0 or 1) */
106 1.28 martin int sbus_intno; /* Do we use first (0) or second (1)
107 1.28 martin interrupt? */
108 1.31 martin int int_enable; /* ICR0 value for interrupt enabled */
109 1.31 martin int int_disable; /* ICR0 value for interrupt disabled */
110 1.33 martin bus_space_tag_t tag; /* socket control io */
111 1.33 martin bus_space_handle_t regs; /* space */
112 1.33 martin bus_space_tag_t pcmciat; /* io space for pcmcia */
113 1.1 pk struct device *pcmcia; /* Associated PCMCIA device */
114 1.1 pk int (*intrhandler) /* Card driver interrupt handler */
115 1.42 perry (void *);
116 1.1 pk void *intrarg; /* Card interrupt handler argument */
117 1.31 martin void *softint; /* cookie for the softintr */
118 1.31 martin
119 1.1 pk struct {
120 1.1 pk bus_space_handle_t winaddr;/* this window's address */
121 1.1 pk } windows[STP4020_NWIN];
122 1.1 pk
123 1.1 pk };
124 1.1 pk
125 1.1 pk struct stp4020_softc {
126 1.1 pk struct device sc_dev; /* Base device */
127 1.1 pk struct sbusdev sc_sd; /* SBus device */
128 1.1 pk pcmcia_chipset_tag_t sc_pct; /* Chipset methods */
129 1.1 pk
130 1.49.6.3 ad struct lwp *event_thread; /* event handling thread */
131 1.1 pk SIMPLEQ_HEAD(, stp4020_event) events; /* Pending events for thread */
132 1.1 pk
133 1.1 pk struct stp4020_socket sc_socks[STP4020_NSOCK];
134 1.1 pk };
135 1.1 pk
136 1.1 pk
137 1.42 perry static int stp4020print(void *, const char *);
138 1.42 perry static int stp4020match(struct device *, struct cfdata *, void *);
139 1.42 perry static void stp4020attach(struct device *, struct device *, void *);
140 1.42 perry static int stp4020_intr(void *);
141 1.16 martin static void stp4020_map_window(struct stp4020_socket *h, int win, int speed);
142 1.44 jdc static void stp4020_calc_speed(int bus_speed, int ns, int *length, int *cmd_delay);
143 1.31 martin static void stp4020_intr_dispatch(void *arg);
144 1.1 pk
145 1.26 thorpej CFATTACH_DECL(nell, sizeof(struct stp4020_softc),
146 1.27 thorpej stp4020match, stp4020attach, NULL, NULL);
147 1.1 pk
148 1.6 pk #ifdef STP4020_DEBUG
149 1.42 perry static void stp4020_dump_regs(struct stp4020_socket *);
150 1.6 pk #endif
151 1.1 pk
152 1.42 perry static int stp4020_rd_sockctl(struct stp4020_socket *, int);
153 1.42 perry static void stp4020_wr_sockctl(struct stp4020_socket *, int, int);
154 1.42 perry static int stp4020_rd_winctl(struct stp4020_socket *, int, int);
155 1.42 perry static void stp4020_wr_winctl(struct stp4020_socket *, int, int, int);
156 1.42 perry
157 1.46 martin void stp4020_delay(struct stp4020_softc *sc, unsigned int);
158 1.42 perry void stp4020_attach_socket(struct stp4020_socket *, int);
159 1.42 perry void stp4020_event_thread(void *);
160 1.42 perry void stp4020_queue_event(struct stp4020_softc *, int, int);
161 1.42 perry
162 1.42 perry int stp4020_chip_mem_alloc(pcmcia_chipset_handle_t, bus_size_t,
163 1.42 perry struct pcmcia_mem_handle *);
164 1.42 perry void stp4020_chip_mem_free(pcmcia_chipset_handle_t,
165 1.42 perry struct pcmcia_mem_handle *);
166 1.42 perry int stp4020_chip_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t,
167 1.1 pk bus_size_t, struct pcmcia_mem_handle *,
168 1.42 perry bus_size_t *, int *);
169 1.42 perry void stp4020_chip_mem_unmap(pcmcia_chipset_handle_t, int);
170 1.1 pk
171 1.42 perry int stp4020_chip_io_alloc(pcmcia_chipset_handle_t,
172 1.1 pk bus_addr_t, bus_size_t, bus_size_t,
173 1.42 perry struct pcmcia_io_handle *);
174 1.42 perry void stp4020_chip_io_free(pcmcia_chipset_handle_t,
175 1.42 perry struct pcmcia_io_handle *);
176 1.42 perry int stp4020_chip_io_map(pcmcia_chipset_handle_t, int, bus_addr_t,
177 1.42 perry bus_size_t, struct pcmcia_io_handle *, int *);
178 1.42 perry void stp4020_chip_io_unmap(pcmcia_chipset_handle_t, int);
179 1.42 perry
180 1.42 perry void stp4020_chip_socket_enable(pcmcia_chipset_handle_t);
181 1.42 perry void stp4020_chip_socket_disable(pcmcia_chipset_handle_t);
182 1.42 perry void stp4020_chip_socket_settype(pcmcia_chipset_handle_t, int);
183 1.42 perry void *stp4020_chip_intr_establish(pcmcia_chipset_handle_t,
184 1.1 pk struct pcmcia_function *, int,
185 1.42 perry int (*)(void *), void *);
186 1.42 perry void stp4020_chip_intr_disestablish(pcmcia_chipset_handle_t, void *);
187 1.1 pk
188 1.1 pk /* Our PCMCIA chipset methods */
189 1.1 pk static struct pcmcia_chip_functions stp4020_functions = {
190 1.1 pk stp4020_chip_mem_alloc,
191 1.1 pk stp4020_chip_mem_free,
192 1.1 pk stp4020_chip_mem_map,
193 1.1 pk stp4020_chip_mem_unmap,
194 1.1 pk
195 1.1 pk stp4020_chip_io_alloc,
196 1.1 pk stp4020_chip_io_free,
197 1.1 pk stp4020_chip_io_map,
198 1.1 pk stp4020_chip_io_unmap,
199 1.1 pk
200 1.1 pk stp4020_chip_intr_establish,
201 1.1 pk stp4020_chip_intr_disestablish,
202 1.1 pk
203 1.1 pk stp4020_chip_socket_enable,
204 1.39 mycroft stp4020_chip_socket_disable,
205 1.39 mycroft stp4020_chip_socket_settype,
206 1.49 jdc NULL
207 1.1 pk };
208 1.1 pk
209 1.1 pk
210 1.47 perry static inline int
211 1.1 pk stp4020_rd_sockctl(h, idx)
212 1.1 pk struct stp4020_socket *h;
213 1.1 pk int idx;
214 1.1 pk {
215 1.1 pk int o = ((STP4020_SOCKREGS_SIZE * (h->sock)) + idx);
216 1.1 pk return (bus_space_read_2(h->tag, h->regs, o));
217 1.1 pk }
218 1.1 pk
219 1.47 perry static inline void
220 1.1 pk stp4020_wr_sockctl(h, idx, v)
221 1.1 pk struct stp4020_socket *h;
222 1.1 pk int idx;
223 1.1 pk int v;
224 1.1 pk {
225 1.1 pk int o = (STP4020_SOCKREGS_SIZE * (h->sock)) + idx;
226 1.1 pk bus_space_write_2(h->tag, h->regs, o, v);
227 1.1 pk }
228 1.1 pk
229 1.47 perry static inline int
230 1.1 pk stp4020_rd_winctl(h, win, idx)
231 1.1 pk struct stp4020_socket *h;
232 1.1 pk int win;
233 1.1 pk int idx;
234 1.1 pk {
235 1.1 pk int o = (STP4020_SOCKREGS_SIZE * (h->sock)) +
236 1.1 pk (STP4020_WINREGS_SIZE * win) + idx;
237 1.1 pk return (bus_space_read_2(h->tag, h->regs, o));
238 1.1 pk }
239 1.1 pk
240 1.47 perry static inline void
241 1.1 pk stp4020_wr_winctl(h, win, idx, v)
242 1.1 pk struct stp4020_socket *h;
243 1.1 pk int win;
244 1.1 pk int idx;
245 1.1 pk int v;
246 1.1 pk {
247 1.1 pk int o = (STP4020_SOCKREGS_SIZE * (h->sock)) +
248 1.1 pk (STP4020_WINREGS_SIZE * win) + idx;
249 1.1 pk
250 1.1 pk bus_space_write_2(h->tag, h->regs, o, v);
251 1.1 pk }
252 1.1 pk
253 1.33 martin #ifndef SUN4U /* XXX - move to SBUS machdep function? */
254 1.33 martin
255 1.32 mrg static u_int16_t stp4020_read_2(bus_space_tag_t,
256 1.32 mrg bus_space_handle_t,
257 1.32 mrg bus_size_t);
258 1.32 mrg static u_int32_t stp4020_read_4(bus_space_tag_t,
259 1.32 mrg bus_space_handle_t,
260 1.32 mrg bus_size_t);
261 1.32 mrg static u_int64_t stp4020_read_8(bus_space_tag_t,
262 1.32 mrg bus_space_handle_t,
263 1.32 mrg bus_size_t);
264 1.32 mrg static void stp4020_write_2(bus_space_tag_t,
265 1.32 mrg bus_space_handle_t,
266 1.32 mrg bus_size_t,
267 1.32 mrg u_int16_t);
268 1.32 mrg static void stp4020_write_4(bus_space_tag_t,
269 1.32 mrg bus_space_handle_t,
270 1.32 mrg bus_size_t,
271 1.32 mrg u_int32_t);
272 1.32 mrg static void stp4020_write_8(bus_space_tag_t,
273 1.32 mrg bus_space_handle_t,
274 1.32 mrg bus_size_t,
275 1.32 mrg u_int64_t);
276 1.32 mrg
277 1.32 mrg static u_int16_t
278 1.32 mrg stp4020_read_2(space, handle, offset)
279 1.32 mrg bus_space_tag_t space;
280 1.32 mrg bus_space_handle_t handle;
281 1.32 mrg bus_size_t offset;
282 1.32 mrg {
283 1.32 mrg return (le16toh(*(volatile u_int16_t *)(handle + offset)));
284 1.32 mrg }
285 1.32 mrg
286 1.32 mrg static u_int32_t
287 1.32 mrg stp4020_read_4(space, handle, offset)
288 1.32 mrg bus_space_tag_t space;
289 1.32 mrg bus_space_handle_t handle;
290 1.32 mrg bus_size_t offset;
291 1.32 mrg {
292 1.32 mrg return (le32toh(*(volatile u_int32_t *)(handle + offset)));
293 1.32 mrg }
294 1.32 mrg
295 1.32 mrg static u_int64_t
296 1.32 mrg stp4020_read_8(space, handle, offset)
297 1.32 mrg bus_space_tag_t space;
298 1.32 mrg bus_space_handle_t handle;
299 1.32 mrg bus_size_t offset;
300 1.32 mrg {
301 1.32 mrg return (le64toh(*(volatile u_int64_t *)(handle + offset)));
302 1.32 mrg }
303 1.32 mrg
304 1.32 mrg static void
305 1.32 mrg stp4020_write_2(space, handle, offset, value)
306 1.32 mrg bus_space_tag_t space;
307 1.32 mrg bus_space_handle_t handle;
308 1.32 mrg bus_size_t offset;
309 1.32 mrg u_int16_t value;
310 1.32 mrg {
311 1.32 mrg (*(volatile u_int16_t *)(handle + offset)) = htole16(value);
312 1.32 mrg }
313 1.32 mrg
314 1.32 mrg static void
315 1.32 mrg stp4020_write_4(space, handle, offset, value)
316 1.32 mrg bus_space_tag_t space;
317 1.32 mrg bus_space_handle_t handle;
318 1.32 mrg bus_size_t offset;
319 1.32 mrg u_int32_t value;
320 1.32 mrg {
321 1.32 mrg (*(volatile u_int32_t *)(handle + offset)) = htole32(value);
322 1.32 mrg }
323 1.32 mrg
324 1.32 mrg static void
325 1.32 mrg stp4020_write_8(space, handle, offset, value)
326 1.32 mrg bus_space_tag_t space;
327 1.32 mrg bus_space_handle_t handle;
328 1.32 mrg bus_size_t offset;
329 1.32 mrg u_int64_t value;
330 1.32 mrg {
331 1.32 mrg (*(volatile u_int64_t *)(handle + offset)) = htole64(value);
332 1.32 mrg }
333 1.33 martin #endif /* SUN4U */
334 1.1 pk
335 1.1 pk int
336 1.1 pk stp4020print(aux, busname)
337 1.1 pk void *aux;
338 1.1 pk const char *busname;
339 1.1 pk {
340 1.4 pk struct pcmciabus_attach_args *paa = aux;
341 1.3 pk struct stp4020_socket *h = paa->pch;
342 1.3 pk
343 1.30 thorpej aprint_normal(" socket %d", h->sock);
344 1.1 pk return (UNCONF);
345 1.1 pk }
346 1.1 pk
347 1.1 pk int
348 1.1 pk stp4020match(parent, cf, aux)
349 1.1 pk struct device *parent;
350 1.1 pk struct cfdata *cf;
351 1.1 pk void *aux;
352 1.1 pk {
353 1.1 pk struct sbus_attach_args *sa = aux;
354 1.1 pk
355 1.2 pk return (strcmp("SUNW,pcmcia", sa->sa_name) == 0);
356 1.1 pk }
357 1.1 pk
358 1.1 pk /*
359 1.1 pk * Attach all the sub-devices we can find
360 1.1 pk */
361 1.1 pk void
362 1.1 pk stp4020attach(parent, self, aux)
363 1.1 pk struct device *parent, *self;
364 1.1 pk void *aux;
365 1.1 pk {
366 1.1 pk struct sbus_attach_args *sa = aux;
367 1.1 pk struct stp4020_softc *sc = (void *)self;
368 1.32 mrg bus_space_tag_t tag;
369 1.31 martin int rev;
370 1.28 martin int i, sbus_intno;
371 1.1 pk bus_space_handle_t bh;
372 1.1 pk
373 1.28 martin /* lsb of our config flags decides which interrupt we use */
374 1.48 thorpej sbus_intno = device_cfdata(&sc->sc_dev)->cf_flags & 1;
375 1.28 martin
376 1.1 pk /* Transfer bus tags */
377 1.37 martin #ifdef SUN4U
378 1.37 martin tag = sa->sa_bustag;
379 1.37 martin #else
380 1.38 pk tag = bus_space_tag_alloc(sa->sa_bustag, sc);
381 1.38 pk if (tag == NULL) {
382 1.38 pk printf("%s: attach: out of memory\n", self->dv_xname);
383 1.38 pk return;
384 1.38 pk }
385 1.32 mrg tag->sparc_read_2 = stp4020_read_2;
386 1.32 mrg tag->sparc_read_4 = stp4020_read_4;
387 1.32 mrg tag->sparc_read_8 = stp4020_read_8;
388 1.32 mrg tag->sparc_write_2 = stp4020_write_2;
389 1.32 mrg tag->sparc_write_4 = stp4020_write_4;
390 1.32 mrg tag->sparc_write_8 = stp4020_write_8;
391 1.38 pk #endif /* SUN4U */
392 1.1 pk
393 1.1 pk /* Set up per-socket static initialization */
394 1.1 pk sc->sc_socks[0].sc = sc->sc_socks[1].sc = sc;
395 1.33 martin sc->sc_socks[0].tag = sc->sc_socks[1].tag = sa->sa_bustag;
396 1.33 martin /*
397 1.33 martin * XXX we rely on "tag" accepting the same handle-domain
398 1.33 martin * as sa->sa_bustag.
399 1.33 martin */
400 1.33 martin sc->sc_socks[0].pcmciat = sc->sc_socks[1].pcmciat = tag;
401 1.28 martin sc->sc_socks[0].sbus_intno =
402 1.28 martin sc->sc_socks[1].sbus_intno = sbus_intno;
403 1.1 pk
404 1.9 pk if (sa->sa_nreg < 8) {
405 1.1 pk printf("%s: only %d register sets\n",
406 1.1 pk self->dv_xname, sa->sa_nreg);
407 1.1 pk return;
408 1.1 pk }
409 1.1 pk
410 1.1 pk if (sa->sa_nintr != 2) {
411 1.1 pk printf("%s: expect 2 interrupt Sbus levels; got %d\n",
412 1.1 pk self->dv_xname, sa->sa_nintr);
413 1.1 pk return;
414 1.1 pk }
415 1.1 pk
416 1.9 pk #define STP4020_BANK_PROM 0
417 1.1 pk #define STP4020_BANK_CTRL 4
418 1.1 pk for (i = 0; i < 8; i++) {
419 1.10 pk
420 1.1 pk /*
421 1.1 pk * STP4020 Register address map:
422 1.1 pk * bank 0: Forth PROM
423 1.1 pk * banks 1-3: socket 0, windows 0-2
424 1.1 pk * bank 4: control registers
425 1.1 pk * banks 5-7: socket 1, windows 0-2
426 1.1 pk */
427 1.10 pk
428 1.9 pk if (i == STP4020_BANK_PROM)
429 1.9 pk /* Skip the PROM */
430 1.9 pk continue;
431 1.9 pk
432 1.1 pk if (sbus_bus_map(sa->sa_bustag,
433 1.24 martin sa->sa_reg[i].oa_space,
434 1.24 martin sa->sa_reg[i].oa_base,
435 1.24 martin sa->sa_reg[i].oa_size,
436 1.21 eeh 0, &bh) != 0) {
437 1.1 pk printf("%s: attach: cannot map registers\n",
438 1.1 pk self->dv_xname);
439 1.1 pk return;
440 1.43 perry }
441 1.10 pk
442 1.10 pk if (i == STP4020_BANK_CTRL) {
443 1.10 pk /*
444 1.10 pk * Copy tag and handle to both socket structures
445 1.10 pk * for easy access in control/status IO functions.
446 1.10 pk */
447 1.10 pk sc->sc_socks[0].regs = sc->sc_socks[1].regs = bh;
448 1.10 pk } else if (i < STP4020_BANK_CTRL) {
449 1.10 pk /* banks 1-3 */
450 1.10 pk sc->sc_socks[0].windows[i-1].winaddr = bh;
451 1.10 pk } else {
452 1.10 pk /* banks 5-7 */
453 1.10 pk sc->sc_socks[1].windows[i-5].winaddr = bh;
454 1.10 pk }
455 1.1 pk }
456 1.1 pk
457 1.1 pk sbus_establish(&sc->sc_sd, &sc->sc_dev);
458 1.1 pk
459 1.28 martin /* We only use one interrupt level. */
460 1.28 martin if (sa->sa_nintr > sbus_intno) {
461 1.28 martin bus_intr_establish(sa->sa_bustag,
462 1.28 martin sa->sa_intr[sbus_intno].oi_pri,
463 1.29 pk IPL_NONE, stp4020_intr, sc);
464 1.7 pk }
465 1.1 pk
466 1.1 pk rev = stp4020_rd_sockctl(&sc->sc_socks[0], STP4020_ISR1_IDX) &
467 1.1 pk STP4020_ISR1_REV_M;
468 1.1 pk printf(": rev %x\n", rev);
469 1.1 pk
470 1.1 pk sc->sc_pct = (pcmcia_chipset_tag_t)&stp4020_functions;
471 1.1 pk
472 1.1 pk SIMPLEQ_INIT(&sc->events);
473 1.1 pk
474 1.1 pk for (i = 0; i < STP4020_NSOCK; i++) {
475 1.1 pk struct stp4020_socket *h = &sc->sc_socks[i];
476 1.1 pk h->sock = i;
477 1.1 pk h->sc = sc;
478 1.6 pk #ifdef STP4020_DEBUG
479 1.18 martin if (stp4020_debug)
480 1.18 martin stp4020_dump_regs(h);
481 1.6 pk #endif
482 1.16 martin stp4020_attach_socket(h, sa->sa_frequency);
483 1.1 pk }
484 1.49.6.1 ad
485 1.49.6.1 ad /*
486 1.49.6.1 ad * Arrange that a kernel thread be created to handle
487 1.49.6.1 ad * insert/removal events.
488 1.49.6.1 ad */
489 1.49.6.1 ad if (kthread_create(PRI_NONE, 0, NULL, stp4020_event_thread, sc,
490 1.49.6.1 ad &sc->event_thread, "%s", name)) {
491 1.49.6.1 ad panic("%s: unable to create event thread", name);
492 1.49.6.1 ad }
493 1.49.6.3 ad
494 1.49.6.3 ad /*
495 1.49.6.3 ad * Arrange that a kernel thread be created to handle
496 1.49.6.3 ad * insert/removal events.
497 1.49.6.3 ad */
498 1.49.6.3 ad if (kthread_create(PRI_NONE, 0, NULL, stp4020_event_thread, sc,
499 1.49.6.3 ad &sc->event_thread, "%s", self->dv_xname)) {
500 1.49.6.3 ad panic("%s: unable to create event thread", self->dv_xname);
501 1.49.6.3 ad }
502 1.1 pk }
503 1.1 pk
504 1.1 pk void
505 1.16 martin stp4020_attach_socket(h, speed)
506 1.1 pk struct stp4020_socket *h;
507 1.16 martin int speed;
508 1.1 pk {
509 1.1 pk struct pcmciabus_attach_args paa;
510 1.1 pk int v;
511 1.1 pk
512 1.31 martin /* no interrupt handlers yet */
513 1.31 martin h->intrhandler = NULL;
514 1.31 martin h->intrarg = NULL;
515 1.31 martin h->softint = NULL;
516 1.31 martin h->int_enable = 0;
517 1.31 martin h->int_disable = 0;
518 1.31 martin
519 1.15 martin /* Map all three windows */
520 1.16 martin stp4020_map_window(h, STP_WIN_ATTR, speed);
521 1.16 martin stp4020_map_window(h, STP_WIN_MEM, speed);
522 1.16 martin stp4020_map_window(h, STP_WIN_IO, speed);
523 1.1 pk
524 1.1 pk /* Configure one pcmcia device per socket */
525 1.9 pk paa.paa_busname = "pcmcia";
526 1.1 pk paa.pct = (pcmcia_chipset_tag_t)h->sc->sc_pct;
527 1.1 pk paa.pch = (pcmcia_chipset_handle_t)h;
528 1.1 pk paa.iobase = 0;
529 1.15 martin paa.iosize = STP4020_WINDOW_SIZE;
530 1.1 pk
531 1.1 pk h->pcmcia = config_found(&h->sc->sc_dev, &paa, stp4020print);
532 1.1 pk
533 1.1 pk if (h->pcmcia == NULL)
534 1.1 pk return;
535 1.1 pk
536 1.1 pk /*
537 1.1 pk * There's actually a pcmcia bus attached; initialize the slot.
538 1.1 pk */
539 1.1 pk
540 1.1 pk /*
541 1.16 martin * Clear things up before we enable status change interrupts.
542 1.16 martin * This seems to not be fully initialized by the PROM.
543 1.16 martin */
544 1.16 martin stp4020_wr_sockctl(h, STP4020_ICR1_IDX, 0);
545 1.16 martin stp4020_wr_sockctl(h, STP4020_ICR0_IDX, 0);
546 1.16 martin stp4020_wr_sockctl(h, STP4020_ISR1_IDX, 0x3fff);
547 1.16 martin stp4020_wr_sockctl(h, STP4020_ISR0_IDX, 0x3fff);
548 1.16 martin
549 1.16 martin /*
550 1.1 pk * Enable socket status change interrupts.
551 1.28 martin * We only use one common interrupt for status change
552 1.28 martin * and IO, to avoid locking issues.
553 1.1 pk */
554 1.28 martin v = STP4020_ICR0_ALL_STATUS_IE
555 1.28 martin | (h->sbus_intno ? STP4020_ICR0_SCILVL_SB1
556 1.28 martin : STP4020_ICR0_SCILVL_SB0);
557 1.1 pk stp4020_wr_sockctl(h, STP4020_ICR0_IDX, v);
558 1.1 pk
559 1.35 martin /* Get live status bits from ISR0 and clear pending interrupts */
560 1.1 pk v = stp4020_rd_sockctl(h, STP4020_ISR0_IDX);
561 1.35 martin stp4020_wr_sockctl(h, STP4020_ISR0_IDX, v);
562 1.35 martin
563 1.1 pk if ((v & (STP4020_ISR0_CD1ST|STP4020_ISR0_CD2ST)) == 0)
564 1.1 pk return;
565 1.1 pk
566 1.1 pk pcmcia_card_attach(h->pcmcia);
567 1.1 pk h->flags |= STP4020_SOCKET_BUSY;
568 1.1 pk }
569 1.1 pk
570 1.1 pk /*
571 1.1 pk * The actual event handling thread.
572 1.1 pk */
573 1.1 pk void
574 1.1 pk stp4020_event_thread(arg)
575 1.1 pk void *arg;
576 1.1 pk {
577 1.1 pk struct stp4020_softc *sc = arg;
578 1.1 pk struct stp4020_event *e;
579 1.1 pk int s;
580 1.1 pk
581 1.1 pk while (1) {
582 1.1 pk struct stp4020_socket *h;
583 1.1 pk int n;
584 1.1 pk
585 1.1 pk s = splhigh();
586 1.1 pk if ((e = SIMPLEQ_FIRST(&sc->events)) == NULL) {
587 1.1 pk splx(s);
588 1.45 martin (void)tsleep(&sc->events, PWAIT, "nellevt", 0);
589 1.1 pk continue;
590 1.1 pk }
591 1.23 lukem SIMPLEQ_REMOVE_HEAD(&sc->events, se_q);
592 1.1 pk splx(s);
593 1.1 pk
594 1.1 pk n = e->se_sock;
595 1.1 pk if (n < 0 || n >= STP4020_NSOCK)
596 1.1 pk panic("stp4020_event_thread: wayward socket number %d",
597 1.1 pk n);
598 1.1 pk
599 1.1 pk h = &sc->sc_socks[n];
600 1.1 pk switch (e->se_type) {
601 1.1 pk case STP4020_EVENT_INSERTION:
602 1.1 pk pcmcia_card_attach(h->pcmcia);
603 1.1 pk break;
604 1.1 pk case STP4020_EVENT_REMOVAL:
605 1.1 pk pcmcia_card_detach(h->pcmcia, DETACH_FORCE);
606 1.1 pk break;
607 1.1 pk default:
608 1.1 pk panic("stp4020_event_thread: unknown event type %d",
609 1.1 pk e->se_type);
610 1.1 pk }
611 1.1 pk free(e, M_TEMP);
612 1.1 pk }
613 1.1 pk }
614 1.1 pk
615 1.1 pk void
616 1.1 pk stp4020_queue_event(sc, sock, event)
617 1.1 pk struct stp4020_softc *sc;
618 1.1 pk int sock, event;
619 1.1 pk {
620 1.1 pk struct stp4020_event *e;
621 1.1 pk int s;
622 1.1 pk
623 1.1 pk e = malloc(sizeof(*e), M_TEMP, M_NOWAIT);
624 1.1 pk if (e == NULL)
625 1.1 pk panic("stp4020_queue_event: can't allocate event");
626 1.1 pk
627 1.1 pk e->se_type = event;
628 1.1 pk e->se_sock = sock;
629 1.1 pk s = splhigh();
630 1.1 pk SIMPLEQ_INSERT_TAIL(&sc->events, e, se_q);
631 1.1 pk splx(s);
632 1.1 pk wakeup(&sc->events);
633 1.1 pk }
634 1.1 pk
635 1.31 martin /*
636 1.31 martin * Softinterrupt called to invoke the real driver interrupt handler.
637 1.31 martin */
638 1.31 martin static void
639 1.31 martin stp4020_intr_dispatch(arg)
640 1.31 martin void *arg;
641 1.31 martin {
642 1.31 martin struct stp4020_socket *h = arg;
643 1.31 martin int s;
644 1.31 martin
645 1.31 martin /* invoke driver handler */
646 1.31 martin h->intrhandler(h->intrarg);
647 1.31 martin
648 1.31 martin /* enable SBUS interrupts for pcmcia interrupts again */
649 1.31 martin s = splhigh();
650 1.31 martin stp4020_wr_sockctl(h, STP4020_ICR0_IDX, h->int_enable);
651 1.31 martin splx(s);
652 1.31 martin }
653 1.31 martin
654 1.1 pk int
655 1.28 martin stp4020_intr(arg)
656 1.1 pk void *arg;
657 1.1 pk {
658 1.1 pk struct stp4020_softc *sc = arg;
659 1.31 martin int i, s, r = 0, cd_change = 0;
660 1.31 martin
661 1.31 martin
662 1.31 martin /* protect hardware access by splhigh against softint */
663 1.31 martin s = splhigh();
664 1.1 pk
665 1.1 pk /*
666 1.1 pk * Check each socket for pending requests.
667 1.1 pk */
668 1.1 pk for (i = 0 ; i < STP4020_NSOCK; i++) {
669 1.1 pk struct stp4020_socket *h;
670 1.28 martin int v;
671 1.1 pk
672 1.1 pk h = &sc->sc_socks[i];
673 1.31 martin
674 1.28 martin v = stp4020_rd_sockctl(h, STP4020_ISR0_IDX);
675 1.1 pk
676 1.31 martin /* Ack all interrupts at once. */
677 1.35 martin stp4020_wr_sockctl(h, STP4020_ISR0_IDX, v);
678 1.1 pk
679 1.1 pk #ifdef STP4020_DEBUG
680 1.1 pk if (stp4020_debug != 0) {
681 1.1 pk char bits[64];
682 1.1 pk bitmask_snprintf(v, STP4020_ISR0_IOBITS,
683 1.1 pk bits, sizeof(bits));
684 1.1 pk printf("stp4020_statintr: ISR0=%s\n", bits);
685 1.1 pk }
686 1.1 pk #endif
687 1.1 pk
688 1.1 pk if ((v & STP4020_ISR0_CDCHG) != 0) {
689 1.1 pk /*
690 1.1 pk * Card status change detect
691 1.1 pk */
692 1.18 martin cd_change = 1;
693 1.18 martin r = 1;
694 1.18 martin if ((v & (STP4020_ISR0_CD1ST|STP4020_ISR0_CD2ST)) == (STP4020_ISR0_CD1ST|STP4020_ISR0_CD2ST)){
695 1.1 pk if ((h->flags & STP4020_SOCKET_BUSY) == 0) {
696 1.1 pk stp4020_queue_event(sc, i,
697 1.1 pk STP4020_EVENT_INSERTION);
698 1.1 pk h->flags |= STP4020_SOCKET_BUSY;
699 1.1 pk }
700 1.1 pk }
701 1.1 pk if ((v & (STP4020_ISR0_CD1ST|STP4020_ISR0_CD2ST)) == 0){
702 1.1 pk if ((h->flags & STP4020_SOCKET_BUSY) != 0) {
703 1.1 pk stp4020_queue_event(sc, i,
704 1.1 pk STP4020_EVENT_REMOVAL);
705 1.1 pk h->flags &= ~STP4020_SOCKET_BUSY;
706 1.1 pk }
707 1.1 pk }
708 1.1 pk }
709 1.43 perry
710 1.28 martin if ((v & STP4020_ISR0_IOINT) != 0) {
711 1.28 martin /* we can not deny this is ours, no matter what the
712 1.28 martin card driver says. */
713 1.28 martin r = 1;
714 1.28 martin
715 1.28 martin /* It's a card interrupt */
716 1.28 martin if ((h->flags & STP4020_SOCKET_BUSY) == 0) {
717 1.28 martin printf("stp4020[%d]: spurious interrupt?\n",
718 1.28 martin h->sock);
719 1.28 martin continue;
720 1.28 martin }
721 1.31 martin
722 1.31 martin /*
723 1.43 perry * Schedule softint to invoke driver interrupt
724 1.31 martin * handler
725 1.31 martin */
726 1.31 martin if (h->softint != NULL)
727 1.49.6.2 ad softint_schedule(h->softint);
728 1.31 martin /*
729 1.31 martin * Disable this sbus interrupt, until the soft-int
730 1.31 martin * handler had a chance to run
731 1.31 martin */
732 1.31 martin stp4020_wr_sockctl(h, STP4020_ICR0_IDX, h->int_disable);
733 1.28 martin }
734 1.1 pk
735 1.18 martin /* informational messages */
736 1.1 pk if ((v & STP4020_ISR0_BVD1CHG) != 0) {
737 1.18 martin /* ignore if this is caused by insert or removal */
738 1.18 martin if (!cd_change)
739 1.18 martin printf("stp4020[%d]: Battery change 1\n", h->sock);
740 1.15 martin r = 1;
741 1.1 pk }
742 1.1 pk
743 1.1 pk if ((v & STP4020_ISR0_BVD2CHG) != 0) {
744 1.18 martin /* ignore if this is caused by insert or removal */
745 1.18 martin if (!cd_change)
746 1.18 martin printf("stp4020[%d]: Battery change 2\n", h->sock);
747 1.15 martin r = 1;
748 1.1 pk }
749 1.1 pk
750 1.36 martin if ((v & STP4020_ISR0_SCINT) != 0) {
751 1.36 martin DPRINTF(("stp4020[%d]: status change\n", h->sock));
752 1.36 martin r = 1;
753 1.36 martin }
754 1.36 martin
755 1.1 pk if ((v & STP4020_ISR0_RDYCHG) != 0) {
756 1.18 martin DPRINTF(("stp4020[%d]: Ready/Busy change\n", h->sock));
757 1.15 martin r = 1;
758 1.1 pk }
759 1.1 pk
760 1.1 pk if ((v & STP4020_ISR0_WPCHG) != 0) {
761 1.18 martin DPRINTF(("stp4020[%d]: Write protect change\n", h->sock));
762 1.15 martin r = 1;
763 1.1 pk }
764 1.1 pk
765 1.1 pk if ((v & STP4020_ISR0_PCTO) != 0) {
766 1.18 martin DPRINTF(("stp4020[%d]: Card access timeout\n", h->sock));
767 1.15 martin r = 1;
768 1.1 pk }
769 1.18 martin
770 1.35 martin if ((v & ~STP4020_ISR0_LIVE) && r == 0)
771 1.35 martin printf("stp4020[%d]: unhandled interrupt: 0x%x\n", h->sock, v);
772 1.35 martin
773 1.1 pk }
774 1.31 martin splx(s);
775 1.1 pk
776 1.1 pk return (r);
777 1.1 pk }
778 1.1 pk
779 1.16 martin /*
780 1.16 martin * The function gets the sbus speed and a access time and calculates
781 1.16 martin * values for the CMDLNG and CMDDLAY registers.
782 1.16 martin */
783 1.15 martin static void
784 1.44 jdc stp4020_calc_speed(int bus_speed, int ns, int *length, int *cmd_delay)
785 1.1 pk {
786 1.16 martin int result;
787 1.16 martin
788 1.16 martin if (ns < STP4020_MEM_SPEED_MIN)
789 1.16 martin ns = STP4020_MEM_SPEED_MIN;
790 1.16 martin else if (ns > STP4020_MEM_SPEED_MAX)
791 1.16 martin ns = STP4020_MEM_SPEED_MAX;
792 1.16 martin result = ns*(bus_speed/1000);
793 1.16 martin if (result % 1000000)
794 1.16 martin result = result/1000000 + 1;
795 1.16 martin else
796 1.16 martin result /= 1000000;
797 1.16 martin *length = result;
798 1.16 martin
799 1.16 martin /* the sbus frequency range is limited, so we can keep this simple */
800 1.44 jdc *cmd_delay = ns <= STP4020_MEM_SPEED_MIN? 1 : 2;
801 1.16 martin }
802 1.15 martin
803 1.16 martin static void
804 1.16 martin stp4020_map_window(struct stp4020_socket *h, int win, int speed)
805 1.16 martin {
806 1.44 jdc int v, length, cmd_delay;
807 1.15 martin
808 1.15 martin /*
809 1.16 martin * According to the PC Card standard 300ns access timing should be
810 1.16 martin * used for attribute memory access. Our pcmcia framework does not
811 1.16 martin * seem to propagate timing information, so we use that
812 1.16 martin * everywhere.
813 1.15 martin */
814 1.44 jdc stp4020_calc_speed(speed, (win==STP_WIN_ATTR)? 300 : 100, &length, &cmd_delay);
815 1.1 pk
816 1.1 pk /*
817 1.15 martin * Fill in the Address Space Select and Base Address
818 1.15 martin * fields of this windows control register 0.
819 1.1 pk */
820 1.44 jdc v = ((cmd_delay << STP4020_WCR0_CMDDLY_S)&STP4020_WCR0_CMDDLY_M)
821 1.16 martin | ((length << STP4020_WCR0_CMDLNG_S)&STP4020_WCR0_CMDLNG_M);
822 1.15 martin switch (win) {
823 1.15 martin case STP_WIN_ATTR:
824 1.15 martin v |= STP4020_WCR0_ASPSEL_AM;
825 1.15 martin break;
826 1.15 martin case STP_WIN_MEM:
827 1.15 martin v |= STP4020_WCR0_ASPSEL_CM;
828 1.15 martin break;
829 1.15 martin case STP_WIN_IO:
830 1.15 martin v |= STP4020_WCR0_ASPSEL_IO;
831 1.15 martin break;
832 1.15 martin }
833 1.15 martin v |= (STP4020_ADDR2PAGE(0) & STP4020_WCR0_BASE_M);
834 1.15 martin stp4020_wr_winctl(h, win, STP4020_WCR0_IDX, v);
835 1.16 martin stp4020_wr_winctl(h, win, STP4020_WCR1_IDX, 1<<STP4020_WCR1_WAITREQ_S);
836 1.15 martin }
837 1.1 pk
838 1.15 martin int
839 1.15 martin stp4020_chip_mem_alloc(pch, size, pcmhp)
840 1.15 martin pcmcia_chipset_handle_t pch;
841 1.15 martin bus_size_t size;
842 1.15 martin struct pcmcia_mem_handle *pcmhp;
843 1.15 martin {
844 1.15 martin struct stp4020_socket *h = (struct stp4020_socket *)pch;
845 1.1 pk
846 1.15 martin /* we can not do much here, defere work to _mem_map */
847 1.33 martin pcmhp->memt = h->pcmciat;
848 1.1 pk pcmhp->size = size;
849 1.19 martin pcmhp->addr = 0;
850 1.19 martin pcmhp->mhandle = 0;
851 1.19 martin pcmhp->realsize = size;
852 1.1 pk
853 1.1 pk return (0);
854 1.1 pk }
855 1.1 pk
856 1.1 pk void
857 1.1 pk stp4020_chip_mem_free(pch, pcmhp)
858 1.1 pk pcmcia_chipset_handle_t pch;
859 1.1 pk struct pcmcia_mem_handle *pcmhp;
860 1.1 pk {
861 1.1 pk }
862 1.1 pk
863 1.1 pk int
864 1.1 pk stp4020_chip_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp)
865 1.1 pk pcmcia_chipset_handle_t pch;
866 1.1 pk int kind;
867 1.1 pk bus_addr_t card_addr;
868 1.1 pk bus_size_t size;
869 1.1 pk struct pcmcia_mem_handle *pcmhp;
870 1.14 soren bus_size_t *offsetp;
871 1.1 pk int *windowp;
872 1.1 pk {
873 1.1 pk struct stp4020_socket *h = (struct stp4020_socket *)pch;
874 1.15 martin int win = (kind&PCMCIA_MEM_ATTR)? STP_WIN_ATTR : STP_WIN_MEM;
875 1.8 joda
876 1.33 martin pcmhp->memt = h->pcmciat;
877 1.33 martin bus_space_subregion(h->pcmciat, h->windows[win].winaddr, card_addr, size, &pcmhp->memh);
878 1.34 martin #ifdef SUN4U
879 1.34 martin if ((u_int8_t)pcmhp->memh._asi == ASI_PHYS_NON_CACHED)
880 1.34 martin pcmhp->memh._asi = ASI_PHYS_NON_CACHED_LITTLE;
881 1.34 martin else if ((u_int8_t)pcmhp->memh._asi == ASI_PRIMARY)
882 1.34 martin pcmhp->memh._asi = ASI_PRIMARY_LITTLE;
883 1.34 martin #endif
884 1.19 martin pcmhp->size = size;
885 1.19 martin pcmhp->realsize = STP4020_WINDOW_SIZE - card_addr;
886 1.15 martin *offsetp = 0;
887 1.15 martin *windowp = 0;
888 1.1 pk
889 1.1 pk return (0);
890 1.1 pk }
891 1.1 pk
892 1.1 pk void
893 1.1 pk stp4020_chip_mem_unmap(pch, win)
894 1.1 pk pcmcia_chipset_handle_t pch;
895 1.1 pk int win;
896 1.1 pk {
897 1.1 pk }
898 1.1 pk
899 1.1 pk int
900 1.1 pk stp4020_chip_io_alloc(pch, start, size, align, pcihp)
901 1.1 pk pcmcia_chipset_handle_t pch;
902 1.1 pk bus_addr_t start;
903 1.1 pk bus_size_t size;
904 1.1 pk bus_size_t align;
905 1.1 pk struct pcmcia_io_handle *pcihp;
906 1.1 pk {
907 1.1 pk struct stp4020_socket *h = (struct stp4020_socket *)pch;
908 1.1 pk
909 1.33 martin pcihp->iot = h->pcmciat;
910 1.15 martin pcihp->ioh = h->windows[STP_WIN_IO].winaddr;
911 1.15 martin return 0;
912 1.1 pk }
913 1.1 pk
914 1.1 pk void
915 1.1 pk stp4020_chip_io_free(pch, pcihp)
916 1.1 pk pcmcia_chipset_handle_t pch;
917 1.1 pk struct pcmcia_io_handle *pcihp;
918 1.1 pk {
919 1.1 pk }
920 1.1 pk
921 1.1 pk int
922 1.1 pk stp4020_chip_io_map(pch, width, offset, size, pcihp, windowp)
923 1.1 pk pcmcia_chipset_handle_t pch;
924 1.1 pk int width;
925 1.1 pk bus_addr_t offset;
926 1.1 pk bus_size_t size;
927 1.1 pk struct pcmcia_io_handle *pcihp;
928 1.1 pk int *windowp;
929 1.1 pk {
930 1.1 pk struct stp4020_socket *h = (struct stp4020_socket *)pch;
931 1.1 pk
932 1.33 martin pcihp->iot = h->pcmciat;
933 1.33 martin bus_space_subregion(h->pcmciat, h->windows[STP_WIN_IO].winaddr, offset, size, &pcihp->ioh);
934 1.34 martin #ifdef SUN4U
935 1.34 martin if ((u_int8_t)pcihp->ioh._asi == ASI_PHYS_NON_CACHED)
936 1.34 martin pcihp->ioh._asi = ASI_PHYS_NON_CACHED_LITTLE;
937 1.34 martin else if ((u_int8_t)pcihp->ioh._asi == ASI_PRIMARY)
938 1.34 martin pcihp->ioh._asi = ASI_PRIMARY_LITTLE;
939 1.34 martin #endif
940 1.15 martin *windowp = 0;
941 1.15 martin return 0;
942 1.1 pk }
943 1.1 pk
944 1.1 pk void
945 1.1 pk stp4020_chip_io_unmap(pch, win)
946 1.1 pk pcmcia_chipset_handle_t pch;
947 1.1 pk int win;
948 1.1 pk {
949 1.1 pk }
950 1.1 pk
951 1.1 pk void
952 1.1 pk stp4020_chip_socket_enable(pch)
953 1.1 pk pcmcia_chipset_handle_t pch;
954 1.1 pk {
955 1.1 pk struct stp4020_socket *h = (struct stp4020_socket *)pch;
956 1.18 martin int i, v;
957 1.1 pk
958 1.1 pk /* this bit is mostly stolen from pcic_attach_card */
959 1.1 pk
960 1.1 pk /* Power down the socket to reset it, clear the card reset pin */
961 1.18 martin stp4020_wr_sockctl(h, STP4020_ICR1_IDX, 0);
962 1.1 pk
963 1.1 pk /*
964 1.1 pk * wait 300ms until power fails (Tpf). Then, wait 100ms since
965 1.1 pk * we are changing Vcc (Toff).
966 1.1 pk */
967 1.46 martin stp4020_delay(h->sc, 300 + 100);
968 1.1 pk
969 1.1 pk /* Power up the socket */
970 1.18 martin v = STP4020_ICR1_MSTPWR;
971 1.1 pk stp4020_wr_sockctl(h, STP4020_ICR1_IDX, v);
972 1.1 pk
973 1.1 pk /*
974 1.1 pk * wait 100ms until power raise (Tpr) and 20ms to become
975 1.1 pk * stable (Tsu(Vcc)).
976 1.1 pk */
977 1.46 martin stp4020_delay(h->sc, 100 + 20);
978 1.1 pk
979 1.18 martin v |= STP4020_ICR1_PCIFOE|STP4020_ICR1_VPP1_VCC;
980 1.1 pk stp4020_wr_sockctl(h, STP4020_ICR1_IDX, v);
981 1.1 pk
982 1.1 pk /*
983 1.1 pk * hold RESET at least 10us.
984 1.1 pk */
985 1.1 pk delay(10);
986 1.1 pk
987 1.40 mycroft /* Clear reset flag, set to memory mode */
988 1.1 pk v = stp4020_rd_sockctl(h, STP4020_ICR0_IDX);
989 1.40 mycroft v &= ~(STP4020_ICR0_IOIE | STP4020_ICR0_IOILVL | STP4020_ICR0_IFTYPE |
990 1.40 mycroft STP4020_ICR0_SPKREN);
991 1.1 pk v &= ~STP4020_ICR0_RESET;
992 1.1 pk stp4020_wr_sockctl(h, STP4020_ICR0_IDX, v);
993 1.1 pk
994 1.1 pk /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */
995 1.46 martin stp4020_delay(h->sc, 20);
996 1.1 pk
997 1.1 pk /* Wait for the chip to finish initializing (5 seconds max) */
998 1.1 pk for (i = 10000; i > 0; i--) {
999 1.1 pk v = stp4020_rd_sockctl(h, STP4020_ISR0_IDX);
1000 1.1 pk if ((v & STP4020_ISR0_RDYST) != 0)
1001 1.1 pk break;
1002 1.1 pk delay(500);
1003 1.1 pk }
1004 1.1 pk if (i <= 0) {
1005 1.1 pk char bits[64];
1006 1.1 pk bitmask_snprintf(stp4020_rd_sockctl(h, STP4020_ISR0_IDX),
1007 1.1 pk STP4020_ISR0_IOBITS, bits, sizeof(bits));
1008 1.1 pk printf("stp4020_chip_socket_enable: not ready: status %s\n",
1009 1.1 pk bits);
1010 1.1 pk return;
1011 1.1 pk }
1012 1.39 mycroft }
1013 1.1 pk
1014 1.39 mycroft void
1015 1.39 mycroft stp4020_chip_socket_settype(pch, type)
1016 1.39 mycroft pcmcia_chipset_handle_t pch;
1017 1.39 mycroft int type;
1018 1.39 mycroft {
1019 1.39 mycroft struct stp4020_socket *h = (struct stp4020_socket *)pch;
1020 1.39 mycroft int v;
1021 1.1 pk
1022 1.1 pk /*
1023 1.18 martin * Check the card type.
1024 1.18 martin * Enable socket I/O interrupts for IO cards.
1025 1.1 pk */
1026 1.39 mycroft v = stp4020_rd_sockctl(h, STP4020_ICR0_IDX);
1027 1.41 mycroft v &= ~(STP4020_ICR0_IOIE | STP4020_ICR0_IOILVL | STP4020_ICR0_IFTYPE |
1028 1.41 mycroft STP4020_ICR0_SPKREN);
1029 1.39 mycroft if (type == PCMCIA_IFTYPE_IO) {
1030 1.18 martin v |= STP4020_ICR0_IFTYPE_IO|STP4020_ICR0_IOIE
1031 1.28 martin |STP4020_ICR0_SPKREN;
1032 1.28 martin v |= h->sbus_intno ? STP4020_ICR0_IOILVL_SB1
1033 1.28 martin : STP4020_ICR0_IOILVL_SB0;
1034 1.31 martin h->int_enable = v;
1035 1.31 martin h->int_disable = v & ~STP4020_ICR0_IOIE;
1036 1.18 martin DPRINTF(("%s: configuring card for IO useage\n", h->sc->sc_dev.dv_xname));
1037 1.18 martin } else {
1038 1.18 martin v |= STP4020_ICR0_IFTYPE_MEM;
1039 1.35 martin h->int_enable = h->int_disable = v;
1040 1.35 martin DPRINTF(("%s: configuring card for IO useage\n", h->sc->sc_dev.dv_xname));
1041 1.18 martin DPRINTF(("%s: configuring card for MEM ONLY useage\n", h->sc->sc_dev.dv_xname));
1042 1.18 martin }
1043 1.1 pk stp4020_wr_sockctl(h, STP4020_ICR0_IDX, v);
1044 1.1 pk }
1045 1.1 pk
1046 1.1 pk void
1047 1.1 pk stp4020_chip_socket_disable(pch)
1048 1.1 pk pcmcia_chipset_handle_t pch;
1049 1.1 pk {
1050 1.1 pk struct stp4020_socket *h = (struct stp4020_socket *)pch;
1051 1.1 pk int v;
1052 1.1 pk
1053 1.1 pk /*
1054 1.1 pk * Disable socket I/O interrupts.
1055 1.1 pk */
1056 1.1 pk v = stp4020_rd_sockctl(h, STP4020_ICR0_IDX);
1057 1.40 mycroft v &= ~(STP4020_ICR0_IOIE | STP4020_ICR0_IOILVL | STP4020_ICR0_IFTYPE |
1058 1.40 mycroft STP4020_ICR0_SPKREN);
1059 1.1 pk stp4020_wr_sockctl(h, STP4020_ICR0_IDX, v);
1060 1.1 pk
1061 1.1 pk /* Power down the socket */
1062 1.18 martin stp4020_wr_sockctl(h, STP4020_ICR1_IDX, 0);
1063 1.1 pk
1064 1.1 pk /*
1065 1.1 pk * wait 300ms until power fails (Tpf).
1066 1.1 pk */
1067 1.46 martin stp4020_delay(h->sc, 300);
1068 1.1 pk }
1069 1.1 pk
1070 1.1 pk void *
1071 1.1 pk stp4020_chip_intr_establish(pch, pf, ipl, handler, arg)
1072 1.1 pk pcmcia_chipset_handle_t pch;
1073 1.1 pk struct pcmcia_function *pf;
1074 1.1 pk int ipl;
1075 1.42 perry int (*handler)(void *);
1076 1.1 pk void *arg;
1077 1.1 pk {
1078 1.1 pk struct stp4020_socket *h = (struct stp4020_socket *)pch;
1079 1.1 pk
1080 1.31 martin /* only one interrupt handler per slot */
1081 1.31 martin if (h->intrhandler != NULL) return NULL;
1082 1.31 martin
1083 1.1 pk h->intrhandler = handler;
1084 1.1 pk h->intrarg = arg;
1085 1.49.6.2 ad h->softint = softint_establish(ipl, stp4020_intr_dispatch, h);
1086 1.31 martin return h->softint;
1087 1.1 pk }
1088 1.1 pk
1089 1.1 pk void
1090 1.1 pk stp4020_chip_intr_disestablish(pch, ih)
1091 1.1 pk pcmcia_chipset_handle_t pch;
1092 1.1 pk void *ih;
1093 1.1 pk {
1094 1.1 pk struct stp4020_socket *h = (struct stp4020_socket *)pch;
1095 1.1 pk
1096 1.1 pk h->intrhandler = NULL;
1097 1.1 pk h->intrarg = NULL;
1098 1.31 martin if (h->softint) {
1099 1.49.6.2 ad softint_disestablish(h->softint);
1100 1.31 martin h->softint = NULL;
1101 1.31 martin }
1102 1.1 pk }
1103 1.1 pk
1104 1.1 pk /*
1105 1.1 pk * Delay and possibly yield CPU.
1106 1.1 pk * XXX - assumes a context
1107 1.1 pk */
1108 1.1 pk void
1109 1.46 martin stp4020_delay(sc, ms)
1110 1.46 martin struct stp4020_softc *sc;
1111 1.1 pk unsigned int ms;
1112 1.1 pk {
1113 1.46 martin unsigned int ticks = mstohz(ms);
1114 1.1 pk
1115 1.1 pk if (cold || ticks == 0) {
1116 1.1 pk delay(ms);
1117 1.1 pk return;
1118 1.1 pk }
1119 1.1 pk
1120 1.1 pk #ifdef DIAGNOSTIC
1121 1.1 pk if (ticks > 60*hz)
1122 1.1 pk panic("stp4020: preposterous delay: %u", ticks);
1123 1.1 pk #endif
1124 1.46 martin tsleep(sc, 0, "nelldel", ticks);
1125 1.1 pk }
1126 1.6 pk
1127 1.6 pk #ifdef STP4020_DEBUG
1128 1.6 pk void
1129 1.6 pk stp4020_dump_regs(h)
1130 1.6 pk struct stp4020_socket *h;
1131 1.6 pk {
1132 1.6 pk char bits[64];
1133 1.6 pk /*
1134 1.6 pk * Dump control and status registers.
1135 1.6 pk */
1136 1.6 pk printf("socket[%d] registers:\n", h->sock);
1137 1.6 pk bitmask_snprintf(stp4020_rd_sockctl(h, STP4020_ICR0_IDX),
1138 1.6 pk STP4020_ICR0_BITS, bits, sizeof(bits));
1139 1.6 pk printf("\tICR0=%s\n", bits);
1140 1.6 pk
1141 1.6 pk bitmask_snprintf(stp4020_rd_sockctl(h, STP4020_ICR1_IDX),
1142 1.6 pk STP4020_ICR1_BITS, bits, sizeof(bits));
1143 1.6 pk printf("\tICR1=%s\n", bits);
1144 1.6 pk
1145 1.6 pk bitmask_snprintf(stp4020_rd_sockctl(h, STP4020_ISR0_IDX),
1146 1.6 pk STP4020_ISR0_IOBITS, bits, sizeof(bits));
1147 1.6 pk printf("\tISR0=%s\n", bits);
1148 1.6 pk
1149 1.6 pk bitmask_snprintf(stp4020_rd_sockctl(h, STP4020_ISR1_IDX),
1150 1.6 pk STP4020_ISR1_BITS, bits, sizeof(bits));
1151 1.6 pk printf("\tISR1=%s\n", bits);
1152 1.6 pk }
1153 1.6 pk #endif /* STP4020_DEBUG */
1154