stp4020.c revision 1.11.4.2
1 /* $NetBSD: stp4020.c,v 1.11.4.2 2002/03/16 16:01:31 jdolecek Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * STP4020: SBus/PCMCIA bridge supporting two Type-3 PCMCIA cards. 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: stp4020.c,v 1.11.4.2 2002/03/16 16:01:31 jdolecek Exp $"); 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/errno.h> 49 #include <sys/malloc.h> 50 #include <sys/extent.h> 51 #include <sys/proc.h> 52 #include <sys/kernel.h> 53 #include <sys/kthread.h> 54 #include <sys/device.h> 55 56 #include <dev/pcmcia/pcmciareg.h> 57 #include <dev/pcmcia/pcmciavar.h> 58 #include <dev/pcmcia/pcmciachip.h> 59 60 #include <machine/bus.h> 61 #include <machine/intr.h> 62 63 #include <dev/sbus/sbusvar.h> 64 #include <dev/sbus/stp4020reg.h> 65 66 #define STP4020_DEBUG 1 /* XXX-temp */ 67 68 /* 69 * We use the three available windows per socket in a simple, fixed 70 * arrangement. Each window maps (at full 1 MB size) one of the pcmcia 71 * spaces into sbus space. 72 */ 73 #define STP_WIN_ATTR 0 /* index of the attribute memory space window */ 74 #define STP_WIN_MEM 1 /* index of the common memory space window */ 75 #define STP_WIN_IO 2 /* index of the io space window */ 76 77 78 #if defined(STP4020_DEBUG) 79 int stp4020_debug = 0; 80 #define DPRINTF(x) do { if (stp4020_debug) printf x; } while(0) 81 #else 82 #define DPRINTF(x) 83 #endif 84 85 /* 86 * Event queue; events detected in an interrupt context go here 87 * awaiting attention from our event handling thread. 88 */ 89 struct stp4020_event { 90 SIMPLEQ_ENTRY(stp4020_event) se_q; 91 int se_type; 92 int se_sock; 93 }; 94 /* Defined event types */ 95 #define STP4020_EVENT_INSERTION 0 96 #define STP4020_EVENT_REMOVAL 1 97 98 /* 99 * Per socket data. 100 */ 101 struct stp4020_socket { 102 struct stp4020_softc *sc; /* Back link */ 103 int flags; 104 #define STP4020_SOCKET_BUSY 0x0001 105 #define STP4020_SOCKET_SHUTDOWN 0x0002 106 int sock; /* Socket number (0 or 1) */ 107 bus_space_tag_t tag; /* socket control space */ 108 bus_space_handle_t regs; /* */ 109 struct device *pcmcia; /* Associated PCMCIA device */ 110 int (*intrhandler) /* Card driver interrupt handler */ 111 __P((void *)); 112 void *intrarg; /* Card interrupt handler argument */ 113 int ipl; /* Interrupt level suggested by card */ 114 struct { 115 bus_space_handle_t winaddr;/* this window's address */ 116 } windows[STP4020_NWIN]; 117 118 }; 119 120 struct stp4020_softc { 121 struct device sc_dev; /* Base device */ 122 struct sbusdev sc_sd; /* SBus device */ 123 bus_space_tag_t sc_bustag; 124 bus_dma_tag_t sc_dmatag; 125 pcmcia_chipset_tag_t sc_pct; /* Chipset methods */ 126 127 struct proc *event_thread; /* event handling thread */ 128 SIMPLEQ_HEAD(, stp4020_event) events; /* Pending events for thread */ 129 130 struct stp4020_socket sc_socks[STP4020_NSOCK]; 131 }; 132 133 134 static int stp4020print __P((void *, const char *)); 135 static int stp4020match __P((struct device *, struct cfdata *, void *)); 136 static void stp4020attach __P((struct device *, struct device *, void *)); 137 static int stp4020_iointr __P((void *)); 138 static int stp4020_statintr __P((void *)); 139 static void stp4020_map_window(struct stp4020_socket *h, int win, int speed); 140 static void stp4020_calc_speed(int bus_speed, int ns, int *length, int *delay); 141 static int dummy_splraise(int ipl); 142 143 struct cfattach nell_ca = { 144 sizeof(struct stp4020_softc), stp4020match, stp4020attach 145 }; 146 147 #ifdef STP4020_DEBUG 148 static void stp4020_dump_regs __P((struct stp4020_socket *)); 149 #endif 150 151 static int stp4020_rd_sockctl __P((struct stp4020_socket *, int)); 152 static void stp4020_wr_sockctl __P((struct stp4020_socket *, int, int)); 153 static int stp4020_rd_winctl __P((struct stp4020_socket *, int, int)); 154 static void stp4020_wr_winctl __P((struct stp4020_socket *, int, int, int)); 155 156 void stp4020_delay __P((unsigned int)); 157 void stp4020_attach_socket __P((struct stp4020_socket *, int)); 158 void stp4020_create_event_thread __P((void *)); 159 void stp4020_event_thread __P((void *)); 160 void stp4020_queue_event __P((struct stp4020_softc *, int, int)); 161 162 int stp4020_chip_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 163 struct pcmcia_mem_handle *)); 164 void stp4020_chip_mem_free __P((pcmcia_chipset_handle_t, 165 struct pcmcia_mem_handle *)); 166 int stp4020_chip_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 167 bus_size_t, struct pcmcia_mem_handle *, 168 bus_size_t *, int *)); 169 void stp4020_chip_mem_unmap __P((pcmcia_chipset_handle_t, int)); 170 171 int stp4020_chip_io_alloc __P((pcmcia_chipset_handle_t, 172 bus_addr_t, bus_size_t, bus_size_t, 173 struct pcmcia_io_handle *)); 174 void stp4020_chip_io_free __P((pcmcia_chipset_handle_t, 175 struct pcmcia_io_handle *)); 176 int stp4020_chip_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 177 bus_size_t, struct pcmcia_io_handle *, int *)); 178 void stp4020_chip_io_unmap __P((pcmcia_chipset_handle_t, int)); 179 180 void stp4020_chip_socket_enable __P((pcmcia_chipset_handle_t)); 181 void stp4020_chip_socket_disable __P((pcmcia_chipset_handle_t)); 182 void *stp4020_chip_intr_establish __P((pcmcia_chipset_handle_t, 183 struct pcmcia_function *, int, 184 int (*) __P((void *)), void *)); 185 void stp4020_chip_intr_disestablish __P((pcmcia_chipset_handle_t, void *)); 186 187 /* Our PCMCIA chipset methods */ 188 static struct pcmcia_chip_functions stp4020_functions = { 189 stp4020_chip_mem_alloc, 190 stp4020_chip_mem_free, 191 stp4020_chip_mem_map, 192 stp4020_chip_mem_unmap, 193 194 stp4020_chip_io_alloc, 195 stp4020_chip_io_free, 196 stp4020_chip_io_map, 197 stp4020_chip_io_unmap, 198 199 stp4020_chip_intr_establish, 200 stp4020_chip_intr_disestablish, 201 202 stp4020_chip_socket_enable, 203 stp4020_chip_socket_disable 204 }; 205 206 207 static __inline__ int 208 stp4020_rd_sockctl(h, idx) 209 struct stp4020_socket *h; 210 int idx; 211 { 212 int o = ((STP4020_SOCKREGS_SIZE * (h->sock)) + idx); 213 return (bus_space_read_2(h->tag, h->regs, o)); 214 } 215 216 static __inline__ void 217 stp4020_wr_sockctl(h, idx, v) 218 struct stp4020_socket *h; 219 int idx; 220 int v; 221 { 222 int o = (STP4020_SOCKREGS_SIZE * (h->sock)) + idx; 223 bus_space_write_2(h->tag, h->regs, o, v); 224 } 225 226 static __inline__ int 227 stp4020_rd_winctl(h, win, idx) 228 struct stp4020_socket *h; 229 int win; 230 int idx; 231 { 232 int o = (STP4020_SOCKREGS_SIZE * (h->sock)) + 233 (STP4020_WINREGS_SIZE * win) + idx; 234 return (bus_space_read_2(h->tag, h->regs, o)); 235 } 236 237 static __inline__ void 238 stp4020_wr_winctl(h, win, idx, v) 239 struct stp4020_socket *h; 240 int win; 241 int idx; 242 int v; 243 { 244 int o = (STP4020_SOCKREGS_SIZE * (h->sock)) + 245 (STP4020_WINREGS_SIZE * win) + idx; 246 247 bus_space_write_2(h->tag, h->regs, o, v); 248 } 249 250 251 int 252 stp4020print(aux, busname) 253 void *aux; 254 const char *busname; 255 { 256 struct pcmciabus_attach_args *paa = aux; 257 struct stp4020_socket *h = paa->pch; 258 259 printf(" socket %d", h->sock); 260 return (UNCONF); 261 } 262 263 int 264 stp4020match(parent, cf, aux) 265 struct device *parent; 266 struct cfdata *cf; 267 void *aux; 268 { 269 struct sbus_attach_args *sa = aux; 270 271 return (strcmp("SUNW,pcmcia", sa->sa_name) == 0); 272 } 273 274 /* 275 * Attach all the sub-devices we can find 276 */ 277 void 278 stp4020attach(parent, self, aux) 279 struct device *parent, *self; 280 void *aux; 281 { 282 struct sbus_attach_args *sa = aux; 283 struct stp4020_softc *sc = (void *)self; 284 int node, rev; 285 int i; 286 bus_space_handle_t bh; 287 288 node = sa->sa_node; 289 290 /* Transfer bus tags */ 291 sc->sc_bustag = sa->sa_bustag; 292 sc->sc_dmatag = sa->sa_dmatag; 293 294 /* Set up per-socket static initialization */ 295 sc->sc_socks[0].sc = sc->sc_socks[1].sc = sc; 296 sc->sc_socks[0].tag = sc->sc_socks[1].tag = sa->sa_bustag; 297 298 if (sa->sa_nreg < 8) { 299 printf("%s: only %d register sets\n", 300 self->dv_xname, sa->sa_nreg); 301 return; 302 } 303 304 if (sa->sa_nintr != 2) { 305 printf("%s: expect 2 interrupt Sbus levels; got %d\n", 306 self->dv_xname, sa->sa_nintr); 307 return; 308 } 309 310 #define STP4020_BANK_PROM 0 311 #define STP4020_BANK_CTRL 4 312 for (i = 0; i < 8; i++) { 313 314 /* 315 * STP4020 Register address map: 316 * bank 0: Forth PROM 317 * banks 1-3: socket 0, windows 0-2 318 * bank 4: control registers 319 * banks 5-7: socket 1, windows 0-2 320 */ 321 322 if (i == STP4020_BANK_PROM) 323 /* Skip the PROM */ 324 continue; 325 326 if (sbus_bus_map(sa->sa_bustag, 327 sa->sa_reg[i].sbr_slot, 328 sa->sa_reg[i].sbr_offset, 329 sa->sa_reg[i].sbr_size, 330 BUS_SPACE_MAP_LINEAR, &bh) != 0) { 331 printf("%s: attach: cannot map registers\n", 332 self->dv_xname); 333 return; 334 } 335 336 if (i == STP4020_BANK_CTRL) { 337 /* 338 * Copy tag and handle to both socket structures 339 * for easy access in control/status IO functions. 340 */ 341 sc->sc_socks[0].regs = sc->sc_socks[1].regs = bh; 342 } else if (i < STP4020_BANK_CTRL) { 343 /* banks 1-3 */ 344 sc->sc_socks[0].windows[i-1].winaddr = bh; 345 } else { 346 /* banks 5-7 */ 347 sc->sc_socks[1].windows[i-5].winaddr = bh; 348 } 349 } 350 351 sbus_establish(&sc->sc_sd, &sc->sc_dev); 352 353 /* 354 * We get to use two SBus interrupt levels. 355 * The higher level we use for status change interrupts; 356 * the lower level for PC card I/O. 357 */ 358 if (sa->sa_nintr != 0) { 359 bus_intr_establish(sa->sa_bustag, sa->sa_intr[1].sbi_pri, 360 IPL_NONE, 0, stp4020_statintr, sc); 361 362 bus_intr_establish(sa->sa_bustag, sa->sa_intr[0].sbi_pri, 363 IPL_NONE, 0, stp4020_iointr, sc); 364 } 365 366 rev = stp4020_rd_sockctl(&sc->sc_socks[0], STP4020_ISR1_IDX) & 367 STP4020_ISR1_REV_M; 368 printf(": rev %x\n", rev); 369 370 sc->sc_pct = (pcmcia_chipset_tag_t)&stp4020_functions; 371 372 /* 373 * Arrange that a kernel thread be created to handle 374 * insert/removal events. 375 */ 376 SIMPLEQ_INIT(&sc->events); 377 kthread_create(stp4020_create_event_thread, sc); 378 379 for (i = 0; i < STP4020_NSOCK; i++) { 380 struct stp4020_socket *h = &sc->sc_socks[i]; 381 h->sock = i; 382 h->sc = sc; 383 #ifdef STP4020_DEBUG 384 if (stp4020_debug) 385 stp4020_dump_regs(h); 386 #endif 387 stp4020_attach_socket(h, sa->sa_frequency); 388 } 389 } 390 391 void 392 stp4020_attach_socket(h, speed) 393 struct stp4020_socket *h; 394 int speed; 395 { 396 struct pcmciabus_attach_args paa; 397 int v; 398 399 /* Map all three windows */ 400 stp4020_map_window(h, STP_WIN_ATTR, speed); 401 stp4020_map_window(h, STP_WIN_MEM, speed); 402 stp4020_map_window(h, STP_WIN_IO, speed); 403 404 /* Configure one pcmcia device per socket */ 405 paa.paa_busname = "pcmcia"; 406 paa.pct = (pcmcia_chipset_tag_t)h->sc->sc_pct; 407 paa.pch = (pcmcia_chipset_handle_t)h; 408 paa.iobase = 0; 409 paa.iosize = STP4020_WINDOW_SIZE; 410 411 h->pcmcia = config_found(&h->sc->sc_dev, &paa, stp4020print); 412 413 if (h->pcmcia == NULL) 414 return; 415 416 /* 417 * There's actually a pcmcia bus attached; initialize the slot. 418 */ 419 420 /* 421 * Clear things up before we enable status change interrupts. 422 * This seems to not be fully initialized by the PROM. 423 */ 424 stp4020_wr_sockctl(h, STP4020_ICR1_IDX, 0); 425 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, 0); 426 stp4020_wr_sockctl(h, STP4020_ISR1_IDX, 0x3fff); 427 stp4020_wr_sockctl(h, STP4020_ISR0_IDX, 0x3fff); 428 429 /* 430 * Enable socket status change interrupts. 431 * We use SB_INT[1] for status change interrupts. 432 */ 433 v = STP4020_ICR0_ALL_STATUS_IE | STP4020_ICR0_SCILVL_SB1; 434 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, v); 435 436 /* Get live status bits from ISR0 */ 437 v = stp4020_rd_sockctl(h, STP4020_ISR0_IDX); 438 if ((v & (STP4020_ISR0_CD1ST|STP4020_ISR0_CD2ST)) == 0) 439 return; 440 441 pcmcia_card_attach(h->pcmcia); 442 h->flags |= STP4020_SOCKET_BUSY; 443 } 444 445 446 /* 447 * Deferred thread creation callback. 448 */ 449 void 450 stp4020_create_event_thread(arg) 451 void *arg; 452 { 453 struct stp4020_softc *sc = arg; 454 const char *name = sc->sc_dev.dv_xname; 455 456 if (kthread_create1(stp4020_event_thread, sc, &sc->event_thread, 457 "%s", name)) { 458 panic("%s: unable to create event thread", name); 459 } 460 } 461 462 /* 463 * The actual event handling thread. 464 */ 465 void 466 stp4020_event_thread(arg) 467 void *arg; 468 { 469 struct stp4020_softc *sc = arg; 470 struct stp4020_event *e; 471 int s; 472 473 while (1) { 474 struct stp4020_socket *h; 475 int n; 476 477 s = splhigh(); 478 if ((e = SIMPLEQ_FIRST(&sc->events)) == NULL) { 479 splx(s); 480 (void)tsleep(&sc->events, PWAIT, "pcicev", 0); 481 continue; 482 } 483 SIMPLEQ_REMOVE_HEAD(&sc->events, e, se_q); 484 splx(s); 485 486 n = e->se_sock; 487 if (n < 0 || n >= STP4020_NSOCK) 488 panic("stp4020_event_thread: wayward socket number %d", 489 n); 490 491 h = &sc->sc_socks[n]; 492 switch (e->se_type) { 493 case STP4020_EVENT_INSERTION: 494 pcmcia_card_attach(h->pcmcia); 495 break; 496 case STP4020_EVENT_REMOVAL: 497 pcmcia_card_detach(h->pcmcia, DETACH_FORCE); 498 break; 499 default: 500 panic("stp4020_event_thread: unknown event type %d", 501 e->se_type); 502 } 503 free(e, M_TEMP); 504 } 505 } 506 507 void 508 stp4020_queue_event(sc, sock, event) 509 struct stp4020_softc *sc; 510 int sock, event; 511 { 512 struct stp4020_event *e; 513 int s; 514 515 e = malloc(sizeof(*e), M_TEMP, M_NOWAIT); 516 if (e == NULL) 517 panic("stp4020_queue_event: can't allocate event"); 518 519 e->se_type = event; 520 e->se_sock = sock; 521 s = splhigh(); 522 SIMPLEQ_INSERT_TAIL(&sc->events, e, se_q); 523 splx(s); 524 wakeup(&sc->events); 525 } 526 527 int 528 stp4020_statintr(arg) 529 void *arg; 530 { 531 struct stp4020_softc *sc = arg; 532 int i, r = 0; 533 534 /* 535 * Check each socket for pending requests. 536 */ 537 for (i = 0 ; i < STP4020_NSOCK; i++) { 538 struct stp4020_socket *h; 539 int v, cd_change = 0; 540 541 h = &sc->sc_socks[i]; 542 543 /* Read socket's ISR0 for the interrupt status bits */ 544 v = stp4020_rd_sockctl(h, STP4020_ISR0_IDX); 545 546 #ifdef STP4020_DEBUG 547 if (stp4020_debug != 0) { 548 char bits[64]; 549 bitmask_snprintf(v, STP4020_ISR0_IOBITS, 550 bits, sizeof(bits)); 551 printf("stp4020_statintr: ISR0=%s\n", bits); 552 } 553 #endif 554 555 /* Ack all interrupts at once */ 556 stp4020_wr_sockctl(h, STP4020_ISR0_IDX, STP4020_ISR0_ALL_STATUS_IRQ); 557 558 if ((v & STP4020_ISR0_CDCHG) != 0) { 559 /* 560 * Card status change detect 561 */ 562 cd_change = 1; 563 r = 1; 564 if ((v & (STP4020_ISR0_CD1ST|STP4020_ISR0_CD2ST)) == (STP4020_ISR0_CD1ST|STP4020_ISR0_CD2ST)){ 565 if ((h->flags & STP4020_SOCKET_BUSY) == 0) { 566 stp4020_queue_event(sc, i, 567 STP4020_EVENT_INSERTION); 568 h->flags |= STP4020_SOCKET_BUSY; 569 } 570 } 571 if ((v & (STP4020_ISR0_CD1ST|STP4020_ISR0_CD2ST)) == 0){ 572 if ((h->flags & STP4020_SOCKET_BUSY) != 0) { 573 stp4020_queue_event(sc, i, 574 STP4020_EVENT_REMOVAL); 575 h->flags &= ~STP4020_SOCKET_BUSY; 576 } 577 } 578 } 579 580 /* informational messages */ 581 if ((v & STP4020_ISR0_BVD1CHG) != 0) { 582 /* ignore if this is caused by insert or removal */ 583 if (!cd_change) 584 printf("stp4020[%d]: Battery change 1\n", h->sock); 585 r = 1; 586 } 587 588 if ((v & STP4020_ISR0_BVD2CHG) != 0) { 589 /* ignore if this is caused by insert or removal */ 590 if (!cd_change) 591 printf("stp4020[%d]: Battery change 2\n", h->sock); 592 r = 1; 593 } 594 595 if ((v & STP4020_ISR0_RDYCHG) != 0) { 596 DPRINTF(("stp4020[%d]: Ready/Busy change\n", h->sock)); 597 r = 1; 598 } 599 600 if ((v & STP4020_ISR0_WPCHG) != 0) { 601 DPRINTF(("stp4020[%d]: Write protect change\n", h->sock)); 602 r = 1; 603 } 604 605 if ((v & STP4020_ISR0_PCTO) != 0) { 606 DPRINTF(("stp4020[%d]: Card access timeout\n", h->sock)); 607 r = 1; 608 } 609 610 } 611 612 return (r); 613 } 614 615 static int 616 dummy_splraise(int ipl) 617 { 618 switch(ipl) { 619 case IPL_SOFTCLOCK: 620 return splsoftclock(); 621 case IPL_BIO: 622 return splbio(); 623 case IPL_NET: 624 return splnet(); 625 case IPL_SOFTSERIAL: 626 return splserial(); /* XXX ? */ 627 case IPL_TTY: 628 return spltty(); 629 case IPL_IMP: 630 return splhigh(); /* XXX ? */ 631 case IPL_AUDIO: 632 return splaudio(); 633 case IPL_CLOCK: 634 return splclock(); 635 case IPL_SERIAL: 636 return splserial(); 637 case IPL_HIGH: 638 return splhigh(); 639 } 640 panic("illegal pcmcia interrupt level"); 641 } 642 643 int 644 stp4020_iointr(arg) 645 void *arg; 646 { 647 struct stp4020_softc *sc = arg; 648 int i, r = 0, s; 649 650 /* 651 * Check each socket for pending requests. 652 */ 653 for (i = 0 ; i < STP4020_NSOCK; i++) { 654 struct stp4020_socket *h; 655 int v; 656 657 h = &sc->sc_socks[i]; 658 v = stp4020_rd_sockctl(h, STP4020_ISR0_IDX); 659 660 if ((v & STP4020_ISR0_IOINT) != 0) { 661 /* we can not deny this is ours, no matter what the 662 card driver says. */ 663 r = 1; 664 /* ack interrupt */ 665 stp4020_wr_sockctl(h, STP4020_ISR0_IDX, v); 666 667 /* It's a card interrupt */ 668 if ((h->flags & STP4020_SOCKET_BUSY) == 0) { 669 printf("stp4020[%d]: spurious interrupt?\n", 670 h->sock); 671 continue; 672 } 673 /* Call card handler, if any */ 674 if (h->intrhandler != NULL) { 675 s = dummy_splraise(h->ipl); 676 (*h->intrhandler)(h->intrarg); 677 splx(s); 678 } 679 } 680 681 } 682 683 return (r); 684 } 685 686 /* 687 * The function gets the sbus speed and a access time and calculates 688 * values for the CMDLNG and CMDDLAY registers. 689 */ 690 static void 691 stp4020_calc_speed(int bus_speed, int ns, int *length, int *delay) 692 { 693 int result; 694 695 if (ns < STP4020_MEM_SPEED_MIN) 696 ns = STP4020_MEM_SPEED_MIN; 697 else if (ns > STP4020_MEM_SPEED_MAX) 698 ns = STP4020_MEM_SPEED_MAX; 699 result = ns*(bus_speed/1000); 700 if (result % 1000000) 701 result = result/1000000 + 1; 702 else 703 result /= 1000000; 704 *length = result; 705 706 /* the sbus frequency range is limited, so we can keep this simple */ 707 *delay = ns <= STP4020_MEM_SPEED_MIN? 1 : 2; 708 } 709 710 static void 711 stp4020_map_window(struct stp4020_socket *h, int win, int speed) 712 { 713 int v, length, delay; 714 715 /* 716 * According to the PC Card standard 300ns access timing should be 717 * used for attribute memory access. Our pcmcia framework does not 718 * seem to propagate timing information, so we use that 719 * everywhere. 720 */ 721 stp4020_calc_speed(speed, 300, &length, &delay); 722 723 /* 724 * Fill in the Address Space Select and Base Address 725 * fields of this windows control register 0. 726 */ 727 v = ((delay << STP4020_WCR0_CMDDLY_S)&STP4020_WCR0_CMDDLY_M) 728 | ((length << STP4020_WCR0_CMDLNG_S)&STP4020_WCR0_CMDLNG_M); 729 switch (win) { 730 case STP_WIN_ATTR: 731 v |= STP4020_WCR0_ASPSEL_AM; 732 break; 733 case STP_WIN_MEM: 734 v |= STP4020_WCR0_ASPSEL_CM; 735 break; 736 case STP_WIN_IO: 737 v |= STP4020_WCR0_ASPSEL_IO; 738 break; 739 } 740 v |= (STP4020_ADDR2PAGE(0) & STP4020_WCR0_BASE_M); 741 stp4020_wr_winctl(h, win, STP4020_WCR0_IDX, v); 742 stp4020_wr_winctl(h, win, STP4020_WCR1_IDX, 1<<STP4020_WCR1_WAITREQ_S); 743 } 744 745 int 746 stp4020_chip_mem_alloc(pch, size, pcmhp) 747 pcmcia_chipset_handle_t pch; 748 bus_size_t size; 749 struct pcmcia_mem_handle *pcmhp; 750 { 751 struct stp4020_socket *h = (struct stp4020_socket *)pch; 752 753 /* we can not do much here, defere work to _mem_map */ 754 pcmhp->memt = h->tag; 755 pcmhp->size = size; 756 pcmhp->addr = 0; 757 pcmhp->mhandle = 0; 758 pcmhp->realsize = size; 759 760 return (0); 761 } 762 763 void 764 stp4020_chip_mem_free(pch, pcmhp) 765 pcmcia_chipset_handle_t pch; 766 struct pcmcia_mem_handle *pcmhp; 767 { 768 } 769 770 int 771 stp4020_chip_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 772 pcmcia_chipset_handle_t pch; 773 int kind; 774 bus_addr_t card_addr; 775 bus_size_t size; 776 struct pcmcia_mem_handle *pcmhp; 777 bus_size_t *offsetp; 778 int *windowp; 779 { 780 struct stp4020_socket *h = (struct stp4020_socket *)pch; 781 int win = (kind&PCMCIA_MEM_ATTR)? STP_WIN_ATTR : STP_WIN_MEM; 782 783 pcmhp->memt = h->tag; 784 bus_space_subregion(h->tag, h->windows[win].winaddr, card_addr, size, &pcmhp->memh); 785 pcmhp->size = size; 786 pcmhp->realsize = STP4020_WINDOW_SIZE - card_addr; 787 *offsetp = 0; 788 *windowp = 0; 789 790 return (0); 791 } 792 793 void 794 stp4020_chip_mem_unmap(pch, win) 795 pcmcia_chipset_handle_t pch; 796 int win; 797 { 798 } 799 800 int 801 stp4020_chip_io_alloc(pch, start, size, align, pcihp) 802 pcmcia_chipset_handle_t pch; 803 bus_addr_t start; 804 bus_size_t size; 805 bus_size_t align; 806 struct pcmcia_io_handle *pcihp; 807 { 808 struct stp4020_socket *h = (struct stp4020_socket *)pch; 809 810 pcihp->iot = h->tag; 811 pcihp->ioh = h->windows[STP_WIN_IO].winaddr; 812 return 0; 813 } 814 815 void 816 stp4020_chip_io_free(pch, pcihp) 817 pcmcia_chipset_handle_t pch; 818 struct pcmcia_io_handle *pcihp; 819 { 820 } 821 822 int 823 stp4020_chip_io_map(pch, width, offset, size, pcihp, windowp) 824 pcmcia_chipset_handle_t pch; 825 int width; 826 bus_addr_t offset; 827 bus_size_t size; 828 struct pcmcia_io_handle *pcihp; 829 int *windowp; 830 { 831 struct stp4020_socket *h = (struct stp4020_socket *)pch; 832 833 pcihp->iot = h->tag; 834 bus_space_subregion(h->tag, h->windows[STP_WIN_IO].winaddr, offset, size, &pcihp->ioh); 835 *windowp = 0; 836 return 0; 837 } 838 839 void 840 stp4020_chip_io_unmap(pch, win) 841 pcmcia_chipset_handle_t pch; 842 int win; 843 { 844 } 845 846 void 847 stp4020_chip_socket_enable(pch) 848 pcmcia_chipset_handle_t pch; 849 { 850 struct stp4020_socket *h = (struct stp4020_socket *)pch; 851 int i, v; 852 853 /* this bit is mostly stolen from pcic_attach_card */ 854 855 /* Power down the socket to reset it, clear the card reset pin */ 856 stp4020_wr_sockctl(h, STP4020_ICR1_IDX, 0); 857 858 /* 859 * wait 300ms until power fails (Tpf). Then, wait 100ms since 860 * we are changing Vcc (Toff). 861 */ 862 stp4020_delay((300 + 100) * 1000); 863 864 /* Power up the socket */ 865 v = STP4020_ICR1_MSTPWR; 866 stp4020_wr_sockctl(h, STP4020_ICR1_IDX, v); 867 868 /* 869 * wait 100ms until power raise (Tpr) and 20ms to become 870 * stable (Tsu(Vcc)). 871 */ 872 stp4020_delay((100 + 20) * 1000); 873 874 v |= STP4020_ICR1_PCIFOE|STP4020_ICR1_VPP1_VCC; 875 stp4020_wr_sockctl(h, STP4020_ICR1_IDX, v); 876 877 /* 878 * hold RESET at least 10us. 879 */ 880 delay(10); 881 882 /* Clear reset flag */ 883 v = stp4020_rd_sockctl(h, STP4020_ICR0_IDX); 884 v &= ~STP4020_ICR0_RESET; 885 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, v); 886 887 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 888 stp4020_delay(20000); 889 890 /* Wait for the chip to finish initializing (5 seconds max) */ 891 for (i = 10000; i > 0; i--) { 892 v = stp4020_rd_sockctl(h, STP4020_ISR0_IDX); 893 if ((v & STP4020_ISR0_RDYST) != 0) 894 break; 895 delay(500); 896 } 897 if (i <= 0) { 898 char bits[64]; 899 bitmask_snprintf(stp4020_rd_sockctl(h, STP4020_ISR0_IDX), 900 STP4020_ISR0_IOBITS, bits, sizeof(bits)); 901 printf("stp4020_chip_socket_enable: not ready: status %s\n", 902 bits); 903 return; 904 } 905 906 v = stp4020_rd_sockctl(h, STP4020_ICR0_IDX); 907 908 /* 909 * Check the card type. 910 * Enable socket I/O interrupts for IO cards. 911 * We use level SB_INT[0] for I/O interrupts. 912 */ 913 if (pcmcia_card_gettype(h->pcmcia) == PCMCIA_IFTYPE_IO) { 914 v &= ~(STP4020_ICR0_IOILVL|STP4020_ICR0_IFTYPE); 915 v |= STP4020_ICR0_IFTYPE_IO|STP4020_ICR0_IOIE 916 |STP4020_ICR0_IOILVL_SB0|STP4020_ICR0_SPKREN; 917 DPRINTF(("%s: configuring card for IO useage\n", h->sc->sc_dev.dv_xname)); 918 } else { 919 v &= ~(STP4020_ICR0_IOILVL|STP4020_ICR0_IFTYPE 920 |STP4020_ICR0_SPKREN|STP4020_ICR0_IOILVL_SB0 921 |STP4020_ICR0_IOILVL_SB1|STP4020_ICR0_SPKREN); 922 v |= STP4020_ICR0_IFTYPE_MEM; 923 DPRINTF(("%s: configuring card for MEM ONLY useage\n", h->sc->sc_dev.dv_xname)); 924 } 925 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, v); 926 } 927 928 void 929 stp4020_chip_socket_disable(pch) 930 pcmcia_chipset_handle_t pch; 931 { 932 struct stp4020_socket *h = (struct stp4020_socket *)pch; 933 int v; 934 935 /* 936 * Disable socket I/O interrupts. 937 */ 938 v = stp4020_rd_sockctl(h, STP4020_ICR0_IDX); 939 v &= ~(STP4020_ICR0_IOIE | STP4020_ICR0_IOILVL); 940 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, v); 941 942 /* Power down the socket */ 943 stp4020_wr_sockctl(h, STP4020_ICR1_IDX, 0); 944 945 /* 946 * wait 300ms until power fails (Tpf). 947 */ 948 stp4020_delay(300 * 1000); 949 } 950 951 void * 952 stp4020_chip_intr_establish(pch, pf, ipl, handler, arg) 953 pcmcia_chipset_handle_t pch; 954 struct pcmcia_function *pf; 955 int ipl; 956 int (*handler) __P((void *)); 957 void *arg; 958 { 959 struct stp4020_socket *h = (struct stp4020_socket *)pch; 960 961 h->intrhandler = handler; 962 h->intrarg = arg; 963 h->ipl = ipl; 964 return h; 965 } 966 967 void 968 stp4020_chip_intr_disestablish(pch, ih) 969 pcmcia_chipset_handle_t pch; 970 void *ih; 971 { 972 struct stp4020_socket *h = (struct stp4020_socket *)pch; 973 974 h->intrhandler = NULL; 975 h->intrarg = NULL; 976 } 977 978 /* 979 * Delay and possibly yield CPU. 980 * XXX - assumes a context 981 */ 982 void 983 stp4020_delay(ms) 984 unsigned int ms; 985 { 986 unsigned int ticks; 987 988 /* Convert to ticks */ 989 ticks = (ms * hz ) / 1000000; 990 991 if (cold || ticks == 0) { 992 delay(ms); 993 return; 994 } 995 996 #ifdef DIAGNOSTIC 997 if (ticks > 60*hz) 998 panic("stp4020: preposterous delay: %u", ticks); 999 #endif 1000 tsleep(&ticks, 0, "stp4020_delay", ticks); 1001 } 1002 1003 #ifdef STP4020_DEBUG 1004 void 1005 stp4020_dump_regs(h) 1006 struct stp4020_socket *h; 1007 { 1008 char bits[64]; 1009 /* 1010 * Dump control and status registers. 1011 */ 1012 printf("socket[%d] registers:\n", h->sock); 1013 bitmask_snprintf(stp4020_rd_sockctl(h, STP4020_ICR0_IDX), 1014 STP4020_ICR0_BITS, bits, sizeof(bits)); 1015 printf("\tICR0=%s\n", bits); 1016 1017 bitmask_snprintf(stp4020_rd_sockctl(h, STP4020_ICR1_IDX), 1018 STP4020_ICR1_BITS, bits, sizeof(bits)); 1019 printf("\tICR1=%s\n", bits); 1020 1021 bitmask_snprintf(stp4020_rd_sockctl(h, STP4020_ISR0_IDX), 1022 STP4020_ISR0_IOBITS, bits, sizeof(bits)); 1023 printf("\tISR0=%s\n", bits); 1024 1025 bitmask_snprintf(stp4020_rd_sockctl(h, STP4020_ISR1_IDX), 1026 STP4020_ISR1_BITS, bits, sizeof(bits)); 1027 printf("\tISR1=%s\n", bits); 1028 } 1029 #endif /* STP4020_DEBUG */ 1030
Indexes created Tue Oct 21 06:10:07 GMT 2025