stp4020.c revision 1.16
1 /* $NetBSD: stp4020.c,v 1.16 2002/03/03 22:47:28 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * STP4020: SBus/PCMCIA bridge supporting two Type-3 PCMCIA cards. 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: stp4020.c,v 1.16 2002/03/03 22:47:28 martin Exp $"); 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/errno.h> 49 #include <sys/malloc.h> 50 #include <sys/extent.h> 51 #include <sys/proc.h> 52 #include <sys/kernel.h> 53 #include <sys/kthread.h> 54 #include <sys/device.h> 55 56 #include <dev/pcmcia/pcmciareg.h> 57 #include <dev/pcmcia/pcmciavar.h> 58 #include <dev/pcmcia/pcmciachip.h> 59 60 #include <machine/bus.h> 61 #include <machine/intr.h> 62 63 #include <dev/sbus/sbusvar.h> 64 #include <dev/sbus/stp4020reg.h> 65 66 #define STP4020_DEBUG 1 /* XXX-temp */ 67 68 /* 69 * We use the three available windows per socket in a simple, fixed 70 * arrangement. Each window maps (at full 1 MB size) one of the pcmcia 71 * spaces into sbus space. 72 */ 73 #define STP_WIN_ATTR 0 /* index of the attribute memory space window */ 74 #define STP_WIN_MEM 1 /* index of the common memory space window */ 75 #define STP_WIN_IO 2 /* index of the io space window */ 76 77 78 #if defined(STP4020_DEBUG) 79 int stp4020_debug = 0; 80 #define DPRINTF(x) do { if (stp4020_debug) printf x; } while(0) 81 #else 82 #define DPRINTF(x) 83 #endif 84 85 /* 86 * Event queue; events detected in an interrupt context go here 87 * awaiting attention from our event handling thread. 88 */ 89 struct stp4020_event { 90 SIMPLEQ_ENTRY(stp4020_event) se_q; 91 int se_type; 92 int se_sock; 93 }; 94 /* Defined event types */ 95 #define STP4020_EVENT_INSERTION 0 96 #define STP4020_EVENT_REMOVAL 1 97 98 /* 99 * Per socket data. 100 */ 101 struct stp4020_socket { 102 struct stp4020_softc *sc; /* Back link */ 103 int flags; 104 #define STP4020_SOCKET_BUSY 0x0001 105 #define STP4020_SOCKET_SHUTDOWN 0x0002 106 int sock; /* Socket number (0 or 1) */ 107 bus_space_tag_t tag; /* socket control space */ 108 bus_space_handle_t regs; /* */ 109 struct device *pcmcia; /* Associated PCMCIA device */ 110 int (*intrhandler) /* Card driver interrupt handler */ 111 __P((void *)); 112 void *intrarg; /* Card interrupt handler argument */ 113 int ipl; /* Interrupt level suggested by card */ 114 struct { 115 bus_space_handle_t winaddr;/* this window's address */ 116 } windows[STP4020_NWIN]; 117 118 }; 119 120 struct stp4020_softc { 121 struct device sc_dev; /* Base device */ 122 struct sbusdev sc_sd; /* SBus device */ 123 bus_space_tag_t sc_bustag; 124 bus_dma_tag_t sc_dmatag; 125 pcmcia_chipset_tag_t sc_pct; /* Chipset methods */ 126 127 struct proc *event_thread; /* event handling thread */ 128 SIMPLEQ_HEAD(, stp4020_event) events; /* Pending events for thread */ 129 130 struct stp4020_socket sc_socks[STP4020_NSOCK]; 131 }; 132 133 134 static int stp4020print __P((void *, const char *)); 135 static int stp4020match __P((struct device *, struct cfdata *, void *)); 136 static void stp4020attach __P((struct device *, struct device *, void *)); 137 static int stp4020_iointr __P((void *)); 138 static int stp4020_statintr __P((void *)); 139 static void stp4020_map_window(struct stp4020_socket *h, int win, int speed); 140 static void stp4020_calc_speed(int bus_speed, int ns, int *length, int *delay); 141 static int dummy_splraise(int ipl); 142 143 struct cfattach nell_ca = { 144 sizeof(struct stp4020_softc), stp4020match, stp4020attach 145 }; 146 147 #ifdef STP4020_DEBUG 148 static void stp4020_dump_regs __P((struct stp4020_socket *)); 149 #endif 150 151 static int stp4020_rd_sockctl __P((struct stp4020_socket *, int)); 152 static void stp4020_wr_sockctl __P((struct stp4020_socket *, int, int)); 153 static int stp4020_rd_winctl __P((struct stp4020_socket *, int, int)); 154 static void stp4020_wr_winctl __P((struct stp4020_socket *, int, int, int)); 155 156 void stp4020_delay __P((unsigned int)); 157 void stp4020_attach_socket __P((struct stp4020_socket *, int)); 158 void stp4020_create_event_thread __P((void *)); 159 void stp4020_event_thread __P((void *)); 160 void stp4020_queue_event __P((struct stp4020_softc *, int, int)); 161 162 int stp4020_chip_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 163 struct pcmcia_mem_handle *)); 164 void stp4020_chip_mem_free __P((pcmcia_chipset_handle_t, 165 struct pcmcia_mem_handle *)); 166 int stp4020_chip_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 167 bus_size_t, struct pcmcia_mem_handle *, 168 bus_size_t *, int *)); 169 void stp4020_chip_mem_unmap __P((pcmcia_chipset_handle_t, int)); 170 171 int stp4020_chip_io_alloc __P((pcmcia_chipset_handle_t, 172 bus_addr_t, bus_size_t, bus_size_t, 173 struct pcmcia_io_handle *)); 174 void stp4020_chip_io_free __P((pcmcia_chipset_handle_t, 175 struct pcmcia_io_handle *)); 176 int stp4020_chip_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 177 bus_size_t, struct pcmcia_io_handle *, int *)); 178 void stp4020_chip_io_unmap __P((pcmcia_chipset_handle_t, int)); 179 180 void stp4020_chip_socket_enable __P((pcmcia_chipset_handle_t)); 181 void stp4020_chip_socket_disable __P((pcmcia_chipset_handle_t)); 182 void *stp4020_chip_intr_establish __P((pcmcia_chipset_handle_t, 183 struct pcmcia_function *, int, 184 int (*) __P((void *)), void *)); 185 void stp4020_chip_intr_disestablish __P((pcmcia_chipset_handle_t, void *)); 186 187 /* Our PCMCIA chipset methods */ 188 static struct pcmcia_chip_functions stp4020_functions = { 189 stp4020_chip_mem_alloc, 190 stp4020_chip_mem_free, 191 stp4020_chip_mem_map, 192 stp4020_chip_mem_unmap, 193 194 stp4020_chip_io_alloc, 195 stp4020_chip_io_free, 196 stp4020_chip_io_map, 197 stp4020_chip_io_unmap, 198 199 stp4020_chip_intr_establish, 200 stp4020_chip_intr_disestablish, 201 202 stp4020_chip_socket_enable, 203 stp4020_chip_socket_disable 204 }; 205 206 207 static __inline__ int 208 stp4020_rd_sockctl(h, idx) 209 struct stp4020_socket *h; 210 int idx; 211 { 212 int o = ((STP4020_SOCKREGS_SIZE * (h->sock)) + idx); 213 return (bus_space_read_2(h->tag, h->regs, o)); 214 } 215 216 static __inline__ void 217 stp4020_wr_sockctl(h, idx, v) 218 struct stp4020_socket *h; 219 int idx; 220 int v; 221 { 222 int o = (STP4020_SOCKREGS_SIZE * (h->sock)) + idx; 223 bus_space_write_2(h->tag, h->regs, o, v); 224 } 225 226 static __inline__ int 227 stp4020_rd_winctl(h, win, idx) 228 struct stp4020_socket *h; 229 int win; 230 int idx; 231 { 232 int o = (STP4020_SOCKREGS_SIZE * (h->sock)) + 233 (STP4020_WINREGS_SIZE * win) + idx; 234 return (bus_space_read_2(h->tag, h->regs, o)); 235 } 236 237 static __inline__ void 238 stp4020_wr_winctl(h, win, idx, v) 239 struct stp4020_socket *h; 240 int win; 241 int idx; 242 int v; 243 { 244 int o = (STP4020_SOCKREGS_SIZE * (h->sock)) + 245 (STP4020_WINREGS_SIZE * win) + idx; 246 247 bus_space_write_2(h->tag, h->regs, o, v); 248 } 249 250 251 int 252 stp4020print(aux, busname) 253 void *aux; 254 const char *busname; 255 { 256 struct pcmciabus_attach_args *paa = aux; 257 struct stp4020_socket *h = paa->pch; 258 259 printf(" socket %d", h->sock); 260 return (UNCONF); 261 } 262 263 int 264 stp4020match(parent, cf, aux) 265 struct device *parent; 266 struct cfdata *cf; 267 void *aux; 268 { 269 struct sbus_attach_args *sa = aux; 270 271 return (strcmp("SUNW,pcmcia", sa->sa_name) == 0); 272 } 273 274 /* 275 * Attach all the sub-devices we can find 276 */ 277 void 278 stp4020attach(parent, self, aux) 279 struct device *parent, *self; 280 void *aux; 281 { 282 struct sbus_attach_args *sa = aux; 283 struct stp4020_softc *sc = (void *)self; 284 int node, rev; 285 int i; 286 bus_space_handle_t bh; 287 288 node = sa->sa_node; 289 290 /* Transfer bus tags */ 291 sc->sc_bustag = sa->sa_bustag; 292 sc->sc_dmatag = sa->sa_dmatag; 293 294 /* Set up per-socket static initialization */ 295 sc->sc_socks[0].sc = sc->sc_socks[1].sc = sc; 296 sc->sc_socks[0].tag = sc->sc_socks[1].tag = sa->sa_bustag; 297 298 if (sa->sa_nreg < 8) { 299 printf("%s: only %d register sets\n", 300 self->dv_xname, sa->sa_nreg); 301 return; 302 } 303 304 if (sa->sa_nintr != 2) { 305 printf("%s: expect 2 interrupt Sbus levels; got %d\n", 306 self->dv_xname, sa->sa_nintr); 307 return; 308 } 309 310 #define STP4020_BANK_PROM 0 311 #define STP4020_BANK_CTRL 4 312 for (i = 0; i < 8; i++) { 313 314 /* 315 * STP4020 Register address map: 316 * bank 0: Forth PROM 317 * banks 1-3: socket 0, windows 0-2 318 * bank 4: control registers 319 * banks 5-7: socket 1, windows 0-2 320 */ 321 322 if (i == STP4020_BANK_PROM) 323 /* Skip the PROM */ 324 continue; 325 326 if (sbus_bus_map(sa->sa_bustag, 327 sa->sa_reg[i].sbr_slot, 328 sa->sa_reg[i].sbr_offset, 329 sa->sa_reg[i].sbr_size, 330 BUS_SPACE_MAP_LINEAR, 0, 331 &bh) != 0) { 332 printf("%s: attach: cannot map registers\n", 333 self->dv_xname); 334 return; 335 } 336 337 if (i == STP4020_BANK_CTRL) { 338 /* 339 * Copy tag and handle to both socket structures 340 * for easy access in control/status IO functions. 341 */ 342 sc->sc_socks[0].regs = sc->sc_socks[1].regs = bh; 343 } else if (i < STP4020_BANK_CTRL) { 344 /* banks 1-3 */ 345 sc->sc_socks[0].windows[i-1].winaddr = bh; 346 } else { 347 /* banks 5-7 */ 348 sc->sc_socks[1].windows[i-5].winaddr = bh; 349 } 350 } 351 352 sbus_establish(&sc->sc_sd, &sc->sc_dev); 353 354 /* 355 * We get to use two SBus interrupt levels. 356 * The higher level we use for status change interrupts; 357 * the lower level for PC card I/O. 358 */ 359 if (sa->sa_nintr != 0) { 360 bus_intr_establish(sa->sa_bustag, sa->sa_intr[1].sbi_pri, 361 IPL_NONE, 0, stp4020_statintr, sc); 362 363 bus_intr_establish(sa->sa_bustag, sa->sa_intr[0].sbi_pri, 364 IPL_NONE, 0, stp4020_iointr, sc); 365 } 366 367 rev = stp4020_rd_sockctl(&sc->sc_socks[0], STP4020_ISR1_IDX) & 368 STP4020_ISR1_REV_M; 369 printf(": rev %x\n", rev); 370 371 sc->sc_pct = (pcmcia_chipset_tag_t)&stp4020_functions; 372 373 /* 374 * Arrange that a kernel thread be created to handle 375 * insert/removal events. 376 */ 377 SIMPLEQ_INIT(&sc->events); 378 kthread_create(stp4020_create_event_thread, sc); 379 380 for (i = 0; i < STP4020_NSOCK; i++) { 381 struct stp4020_socket *h = &sc->sc_socks[i]; 382 h->sock = i; 383 h->sc = sc; 384 #ifdef STP4020_DEBUG 385 stp4020_dump_regs(h); 386 #endif 387 stp4020_attach_socket(h, sa->sa_frequency); 388 } 389 } 390 391 void 392 stp4020_attach_socket(h, speed) 393 struct stp4020_socket *h; 394 int speed; 395 { 396 struct pcmciabus_attach_args paa; 397 int v; 398 399 /* Map all three windows */ 400 stp4020_map_window(h, STP_WIN_ATTR, speed); 401 stp4020_map_window(h, STP_WIN_MEM, speed); 402 stp4020_map_window(h, STP_WIN_IO, speed); 403 404 /* Configure one pcmcia device per socket */ 405 paa.paa_busname = "pcmcia"; 406 paa.pct = (pcmcia_chipset_tag_t)h->sc->sc_pct; 407 paa.pch = (pcmcia_chipset_handle_t)h; 408 paa.iobase = 0; 409 paa.iosize = STP4020_WINDOW_SIZE; 410 411 h->pcmcia = config_found(&h->sc->sc_dev, &paa, stp4020print); 412 413 if (h->pcmcia == NULL) 414 return; 415 416 /* 417 * There's actually a pcmcia bus attached; initialize the slot. 418 */ 419 420 /* 421 * Clear things up before we enable status change interrupts. 422 * This seems to not be fully initialized by the PROM. 423 */ 424 stp4020_wr_sockctl(h, STP4020_ICR1_IDX, 0); 425 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, 0); 426 stp4020_wr_sockctl(h, STP4020_ISR1_IDX, 0x3fff); 427 stp4020_wr_sockctl(h, STP4020_ISR0_IDX, 0x3fff); 428 429 /* 430 * Enable socket status change interrupts. 431 * We use SB_INT[1] for status change interrupts. 432 */ 433 v = stp4020_rd_sockctl(h, STP4020_ICR0_IDX); 434 v |= STP4020_ICR0_ALL_STATUS_IE | STP4020_ICR0_SCILVL_SB1; 435 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, v); 436 437 /* Get live status bits from ISR0 */ 438 v = stp4020_rd_sockctl(h, STP4020_ISR0_IDX); 439 if ((v & (STP4020_ISR0_CD1ST|STP4020_ISR0_CD2ST)) == 0) 440 return; 441 442 pcmcia_card_attach(h->pcmcia); 443 h->flags |= STP4020_SOCKET_BUSY; 444 } 445 446 447 /* 448 * Deferred thread creation callback. 449 */ 450 void 451 stp4020_create_event_thread(arg) 452 void *arg; 453 { 454 struct stp4020_softc *sc = arg; 455 const char *name = sc->sc_dev.dv_xname; 456 457 if (kthread_create1(stp4020_event_thread, sc, &sc->event_thread, 458 "%s", name)) { 459 panic("%s: unable to create event thread", name); 460 } 461 } 462 463 /* 464 * The actual event handling thread. 465 */ 466 void 467 stp4020_event_thread(arg) 468 void *arg; 469 { 470 struct stp4020_softc *sc = arg; 471 struct stp4020_event *e; 472 int s; 473 474 while (1) { 475 struct stp4020_socket *h; 476 int n; 477 478 s = splhigh(); 479 if ((e = SIMPLEQ_FIRST(&sc->events)) == NULL) { 480 splx(s); 481 (void)tsleep(&sc->events, PWAIT, "pcicev", 0); 482 continue; 483 } 484 SIMPLEQ_REMOVE_HEAD(&sc->events, e, se_q); 485 splx(s); 486 487 n = e->se_sock; 488 if (n < 0 || n >= STP4020_NSOCK) 489 panic("stp4020_event_thread: wayward socket number %d", 490 n); 491 492 h = &sc->sc_socks[n]; 493 switch (e->se_type) { 494 case STP4020_EVENT_INSERTION: 495 printf("pcmcia_card_attach for slot #%d\n", n); 496 pcmcia_card_attach(h->pcmcia); 497 break; 498 case STP4020_EVENT_REMOVAL: 499 printf("pcmcia_card_detach for slot #%d\n", n); 500 pcmcia_card_detach(h->pcmcia, DETACH_FORCE); 501 break; 502 default: 503 panic("stp4020_event_thread: unknown event type %d", 504 e->se_type); 505 } 506 free(e, M_TEMP); 507 } 508 } 509 510 void 511 stp4020_queue_event(sc, sock, event) 512 struct stp4020_softc *sc; 513 int sock, event; 514 { 515 struct stp4020_event *e; 516 int s; 517 518 e = malloc(sizeof(*e), M_TEMP, M_NOWAIT); 519 if (e == NULL) 520 panic("stp4020_queue_event: can't allocate event"); 521 522 e->se_type = event; 523 e->se_sock = sock; 524 s = splhigh(); 525 SIMPLEQ_INSERT_TAIL(&sc->events, e, se_q); 526 splx(s); 527 wakeup(&sc->events); 528 } 529 530 int 531 stp4020_statintr(arg) 532 void *arg; 533 { 534 struct stp4020_softc *sc = arg; 535 int i, r = 0; 536 537 /* 538 * Check each socket for pending requests. 539 */ 540 for (i = 0 ; i < STP4020_NSOCK; i++) { 541 struct stp4020_socket *h; 542 int v; 543 544 h = &sc->sc_socks[i]; 545 546 /* Read socket's ISR0 for the interrupt status bits */ 547 v = stp4020_rd_sockctl(h, STP4020_ISR0_IDX); 548 549 #ifdef STP4020_DEBUG 550 if (stp4020_debug != 0) { 551 char bits[64]; 552 bitmask_snprintf(v, STP4020_ISR0_IOBITS, 553 bits, sizeof(bits)); 554 printf("stp4020_statintr: ISR0=%s\n", bits); 555 } 556 #endif 557 558 /* Ack all interrupts at once */ 559 stp4020_wr_sockctl(h, STP4020_ISR0_IDX, 560 STP4020_ISR0_ALL_STATUS_IRQ); 561 562 if ((v & STP4020_ISR0_CDCHG) != 0) { 563 /* 564 * Card status change detect 565 */ 566 if ((v & (STP4020_ISR0_CD1ST|STP4020_ISR0_CD2ST)) != 0){ 567 if ((h->flags & STP4020_SOCKET_BUSY) == 0) { 568 stp4020_queue_event(sc, i, 569 STP4020_EVENT_INSERTION); 570 h->flags |= STP4020_SOCKET_BUSY; 571 } 572 } 573 if ((v & (STP4020_ISR0_CD1ST|STP4020_ISR0_CD2ST)) == 0){ 574 if ((h->flags & STP4020_SOCKET_BUSY) != 0) { 575 stp4020_queue_event(sc, i, 576 STP4020_EVENT_REMOVAL); 577 h->flags &= ~STP4020_SOCKET_BUSY; 578 } 579 } 580 } 581 582 /* XXX - a bunch of unhandled conditions */ 583 if ((v & STP4020_ISR0_BVD1CHG) != 0) { 584 printf("stp4020[%d]: Battery change 1\n", h->sock); 585 r = 1; 586 } 587 588 if ((v & STP4020_ISR0_BVD2CHG) != 0) { 589 printf("stp4020[%d]: Battery change 2\n", h->sock); 590 r = 1; 591 } 592 593 if ((v & STP4020_ISR0_RDYCHG) != 0) { 594 printf("stp4020[%d]: Ready/Busy change\n", h->sock); 595 r = 1; 596 } 597 598 if ((v & STP4020_ISR0_WPCHG) != 0) { 599 printf("stp4020[%d]: Write protect change\n", h->sock); 600 r = 1; 601 } 602 603 if ((v & STP4020_ISR0_PCTO) != 0) { 604 printf("stp4020[%d]: Card access timeout\n", h->sock); 605 r = 1; 606 } 607 } 608 609 return (r); 610 } 611 612 static int 613 dummy_splraise(int ipl) 614 { 615 switch(ipl) { 616 case IPL_SOFTCLOCK: 617 return splsoftclock(); 618 case IPL_BIO: 619 return splbio(); 620 case IPL_NET: 621 return splnet(); 622 case IPL_SOFTSERIAL: 623 return splserial(); /* XXX ? */ 624 case IPL_TTY: 625 return spltty(); 626 case IPL_IMP: 627 return splhigh(); /* XXX ? */ 628 case IPL_AUDIO: 629 return splaudio(); 630 case IPL_CLOCK: 631 return splclock(); 632 case IPL_SERIAL: 633 return splserial(); 634 case IPL_HIGH: 635 return splhigh(); 636 } 637 panic("illegal pcmcia interrupt level"); 638 } 639 640 int 641 stp4020_iointr(arg) 642 void *arg; 643 { 644 struct stp4020_softc *sc = arg; 645 int i, r = 0, s; 646 647 /* 648 * Check each socket for pending requests. 649 */ 650 for (i = 0 ; i < STP4020_NSOCK; i++) { 651 struct stp4020_socket *h; 652 int v; 653 654 h = &sc->sc_socks[i]; 655 v = stp4020_rd_sockctl(h, STP4020_ISR0_IDX); 656 657 if ((v & STP4020_ISR0_IOINT) != 0) { 658 /* It's a card interrupt */ 659 if ((h->flags & STP4020_SOCKET_BUSY) == 0) { 660 printf("stp4020[%d]: spurious interrupt?\n", 661 h->sock); 662 continue; 663 } 664 /* Call card handler, if any */ 665 if (h->intrhandler != NULL) { 666 s = dummy_splraise(h->ipl); 667 r |= (*h->intrhandler)(h->intrarg); 668 splx(s); 669 } 670 } 671 672 } 673 if (r) 674 printf("stp4020_iointr() -> %d\n", r); 675 676 return (r); 677 } 678 679 /* 680 * The function gets the sbus speed and a access time and calculates 681 * values for the CMDLNG and CMDDLAY registers. 682 */ 683 static void 684 stp4020_calc_speed(int bus_speed, int ns, int *length, int *delay) 685 { 686 int result; 687 688 if (ns < STP4020_MEM_SPEED_MIN) 689 ns = STP4020_MEM_SPEED_MIN; 690 else if (ns > STP4020_MEM_SPEED_MAX) 691 ns = STP4020_MEM_SPEED_MAX; 692 result = ns*(bus_speed/1000); 693 if (result % 1000000) 694 result = result/1000000 + 1; 695 else 696 result /= 1000000; 697 *length = result; 698 699 /* the sbus frequency range is limited, so we can keep this simple */ 700 *delay = ns <= STP4020_MEM_SPEED_MIN? 1 : 2; 701 } 702 703 static void 704 stp4020_map_window(struct stp4020_socket *h, int win, int speed) 705 { 706 int v, length, delay; 707 708 /* 709 * According to the PC Card standard 300ns access timing should be 710 * used for attribute memory access. Our pcmcia framework does not 711 * seem to propagate timing information, so we use that 712 * everywhere. 713 */ 714 stp4020_calc_speed(speed, 300, &length, &delay); 715 716 /* 717 * Fill in the Address Space Select and Base Address 718 * fields of this windows control register 0. 719 */ 720 v = ((delay << STP4020_WCR0_CMDDLY_S)&STP4020_WCR0_CMDDLY_M) 721 | ((length << STP4020_WCR0_CMDLNG_S)&STP4020_WCR0_CMDLNG_M); 722 switch (win) { 723 case STP_WIN_ATTR: 724 v |= STP4020_WCR0_ASPSEL_AM; 725 break; 726 case STP_WIN_MEM: 727 v |= STP4020_WCR0_ASPSEL_CM; 728 break; 729 case STP_WIN_IO: 730 v |= STP4020_WCR0_ASPSEL_IO; 731 break; 732 } 733 v |= (STP4020_ADDR2PAGE(0) & STP4020_WCR0_BASE_M); 734 stp4020_wr_winctl(h, win, STP4020_WCR0_IDX, v); 735 stp4020_wr_winctl(h, win, STP4020_WCR1_IDX, 1<<STP4020_WCR1_WAITREQ_S); 736 } 737 738 int 739 stp4020_chip_mem_alloc(pch, size, pcmhp) 740 pcmcia_chipset_handle_t pch; 741 bus_size_t size; 742 struct pcmcia_mem_handle *pcmhp; 743 { 744 struct stp4020_socket *h = (struct stp4020_socket *)pch; 745 746 /* we can not do much here, defere work to _mem_map */ 747 pcmhp->memt = h->tag; 748 pcmhp->size = size; 749 750 return (0); 751 } 752 753 void 754 stp4020_chip_mem_free(pch, pcmhp) 755 pcmcia_chipset_handle_t pch; 756 struct pcmcia_mem_handle *pcmhp; 757 { 758 } 759 760 int 761 stp4020_chip_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 762 pcmcia_chipset_handle_t pch; 763 int kind; 764 bus_addr_t card_addr; 765 bus_size_t size; 766 struct pcmcia_mem_handle *pcmhp; 767 bus_size_t *offsetp; 768 int *windowp; 769 { 770 struct stp4020_socket *h = (struct stp4020_socket *)pch; 771 int win = (kind&PCMCIA_MEM_ATTR)? STP_WIN_ATTR : STP_WIN_MEM; 772 773 pcmhp->memt = h->tag; 774 bus_space_subregion(h->tag, h->windows[win].winaddr, card_addr, size, &pcmhp->memh); 775 *offsetp = 0; 776 *windowp = 0; 777 778 return (0); 779 } 780 781 void 782 stp4020_chip_mem_unmap(pch, win) 783 pcmcia_chipset_handle_t pch; 784 int win; 785 { 786 } 787 788 int 789 stp4020_chip_io_alloc(pch, start, size, align, pcihp) 790 pcmcia_chipset_handle_t pch; 791 bus_addr_t start; 792 bus_size_t size; 793 bus_size_t align; 794 struct pcmcia_io_handle *pcihp; 795 { 796 struct stp4020_socket *h = (struct stp4020_socket *)pch; 797 798 pcihp->iot = h->tag; 799 pcihp->ioh = h->windows[STP_WIN_IO].winaddr; 800 return 0; 801 } 802 803 void 804 stp4020_chip_io_free(pch, pcihp) 805 pcmcia_chipset_handle_t pch; 806 struct pcmcia_io_handle *pcihp; 807 { 808 } 809 810 int 811 stp4020_chip_io_map(pch, width, offset, size, pcihp, windowp) 812 pcmcia_chipset_handle_t pch; 813 int width; 814 bus_addr_t offset; 815 bus_size_t size; 816 struct pcmcia_io_handle *pcihp; 817 int *windowp; 818 { 819 struct stp4020_socket *h = (struct stp4020_socket *)pch; 820 821 pcihp->iot = h->tag; 822 bus_space_subregion(h->tag, h->windows[STP_WIN_IO].winaddr, offset, size, &pcihp->ioh); 823 *windowp = 0; 824 return 0; 825 } 826 827 void 828 stp4020_chip_io_unmap(pch, win) 829 pcmcia_chipset_handle_t pch; 830 int win; 831 { 832 } 833 834 void 835 stp4020_chip_socket_enable(pch) 836 pcmcia_chipset_handle_t pch; 837 { 838 struct stp4020_socket *h = (struct stp4020_socket *)pch; 839 int i, v, cardtype; 840 841 /* this bit is mostly stolen from pcic_attach_card */ 842 843 /* Power down the socket to reset it, clear the card reset pin */ 844 v = stp4020_rd_sockctl(h, STP4020_ICR1_IDX); 845 v &= ~(STP4020_ICR1_MSTPWR|STP4020_ICR1_PCIFOE); 846 stp4020_wr_sockctl(h, STP4020_ICR1_IDX, v); 847 848 /* 849 * wait 300ms until power fails (Tpf). Then, wait 100ms since 850 * we are changing Vcc (Toff). 851 */ 852 stp4020_delay((300 + 100) * 1000); 853 854 /* Power up the socket */ 855 v = stp4020_rd_sockctl(h, STP4020_ICR1_IDX); 856 v |= STP4020_ICR1_MSTPWR|STP4020_ICR1_PCIFOE; 857 stp4020_wr_sockctl(h, STP4020_ICR1_IDX, v); 858 859 /* 860 * wait 100ms until power raise (Tpr) and 20ms to become 861 * stable (Tsu(Vcc)). 862 */ 863 stp4020_delay((100 + 20) * 1000); 864 865 v |= STP4020_ICR1_PCIFOE; 866 stp4020_wr_sockctl(h, STP4020_ICR1_IDX, v); 867 868 /* 869 * hold RESET at least 10us. 870 */ 871 delay(10); 872 873 /* Clear reset flag */ 874 v = stp4020_rd_sockctl(h, STP4020_ICR0_IDX); 875 v &= ~STP4020_ICR0_RESET; 876 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, v); 877 878 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 879 stp4020_delay(20000); 880 881 /* Wait for the chip to finish initializing (5 seconds max) */ 882 for (i = 10000; i > 0; i--) { 883 v = stp4020_rd_sockctl(h, STP4020_ISR0_IDX); 884 if ((v & STP4020_ISR0_RDYST) != 0) 885 break; 886 delay(500); 887 } 888 if (i <= 0) { 889 char bits[64]; 890 bitmask_snprintf(stp4020_rd_sockctl(h, STP4020_ISR0_IDX), 891 STP4020_ISR0_IOBITS, bits, sizeof(bits)); 892 printf("stp4020_chip_socket_enable: not ready: status %s\n", 893 bits); 894 return; 895 } 896 897 /* Set the card type */ 898 cardtype = pcmcia_card_gettype(h->pcmcia); 899 900 v = stp4020_rd_sockctl(h, STP4020_ICR0_IDX); 901 v &= ~STP4020_ICR0_IFTYPE; 902 v |= (cardtype == PCMCIA_IFTYPE_IO) 903 ? STP4020_ICR0_IFTYPE_IO 904 : STP4020_ICR0_IFTYPE_MEM; 905 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, v); 906 907 DPRINTF(("%s: stp4020_chip_socket_enable %02x cardtype %s\n", 908 h->sc->sc_dev.dv_xname, h->sock, 909 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"))); 910 911 /* 912 * Enable socket I/O interrupts. 913 * We use level SB_INT[0] for I/O interrupts. 914 */ 915 v = stp4020_rd_sockctl(h, STP4020_ICR0_IDX); 916 v &= ~STP4020_ICR0_IOILVL; 917 v |= STP4020_ICR0_IOIE | STP4020_ICR0_IOILVL_SB0; 918 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, v); 919 } 920 921 void 922 stp4020_chip_socket_disable(pch) 923 pcmcia_chipset_handle_t pch; 924 { 925 struct stp4020_socket *h = (struct stp4020_socket *)pch; 926 int v; 927 928 DPRINTF(("stp4020_chip_socket_disable\n")); 929 930 /* 931 * Disable socket I/O interrupts. 932 */ 933 v = stp4020_rd_sockctl(h, STP4020_ICR0_IDX); 934 v &= ~(STP4020_ICR0_IOIE | STP4020_ICR0_IOILVL); 935 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, v); 936 937 /* Power down the socket */ 938 v = stp4020_rd_sockctl(h, STP4020_ICR1_IDX); 939 v &= ~(STP4020_ICR1_MSTPWR|STP4020_ICR1_PCIFOE); 940 stp4020_wr_sockctl(h, STP4020_ICR1_IDX, v); 941 942 /* 943 * wait 300ms until power fails (Tpf). 944 */ 945 stp4020_delay(300 * 1000); 946 } 947 948 void * 949 stp4020_chip_intr_establish(pch, pf, ipl, handler, arg) 950 pcmcia_chipset_handle_t pch; 951 struct pcmcia_function *pf; 952 int ipl; 953 int (*handler) __P((void *)); 954 void *arg; 955 { 956 struct stp4020_socket *h = (struct stp4020_socket *)pch; 957 958 h->intrhandler = handler; 959 h->intrarg = arg; 960 h->ipl = ipl; 961 return h; 962 } 963 964 void 965 stp4020_chip_intr_disestablish(pch, ih) 966 pcmcia_chipset_handle_t pch; 967 void *ih; 968 { 969 struct stp4020_socket *h = (struct stp4020_socket *)pch; 970 971 h->intrhandler = NULL; 972 h->intrarg = NULL; 973 } 974 975 /* 976 * Delay and possibly yield CPU. 977 * XXX - assumes a context 978 */ 979 void 980 stp4020_delay(ms) 981 unsigned int ms; 982 { 983 unsigned int ticks; 984 extern int cold; 985 986 /* Convert to ticks */ 987 ticks = (ms * hz ) / 1000000; 988 989 if (cold || ticks == 0) { 990 delay(ms); 991 return; 992 } 993 994 #ifdef DIAGNOSTIC 995 if (ticks > 60*hz) 996 panic("stp4020: preposterous delay: %u", ticks); 997 #endif 998 tsleep(&ticks, 0, "stp4020_delay", ticks); 999 } 1000 1001 #ifdef STP4020_DEBUG 1002 void 1003 stp4020_dump_regs(h) 1004 struct stp4020_socket *h; 1005 { 1006 char bits[64]; 1007 /* 1008 * Dump control and status registers. 1009 */ 1010 printf("socket[%d] registers:\n", h->sock); 1011 bitmask_snprintf(stp4020_rd_sockctl(h, STP4020_ICR0_IDX), 1012 STP4020_ICR0_BITS, bits, sizeof(bits)); 1013 printf("\tICR0=%s\n", bits); 1014 1015 bitmask_snprintf(stp4020_rd_sockctl(h, STP4020_ICR1_IDX), 1016 STP4020_ICR1_BITS, bits, sizeof(bits)); 1017 printf("\tICR1=%s\n", bits); 1018 1019 bitmask_snprintf(stp4020_rd_sockctl(h, STP4020_ISR0_IDX), 1020 STP4020_ISR0_IOBITS, bits, sizeof(bits)); 1021 printf("\tISR0=%s\n", bits); 1022 1023 bitmask_snprintf(stp4020_rd_sockctl(h, STP4020_ISR1_IDX), 1024 STP4020_ISR1_BITS, bits, sizeof(bits)); 1025 printf("\tISR1=%s\n", bits); 1026 } 1027 #endif /* STP4020_DEBUG */ 1028
Indexes created Thu Oct 02 14:10:14 GMT 2025