stp4020.c revision 1.31
1 /* $NetBSD: stp4020.c,v 1.31 2003/01/02 20:01:57 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * STP4020: SBus/PCMCIA bridge supporting two Type-3 PCMCIA cards. 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: stp4020.c,v 1.31 2003/01/02 20:01:57 martin Exp $"); 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/errno.h> 49 #include <sys/malloc.h> 50 #include <sys/extent.h> 51 #include <sys/proc.h> 52 #include <sys/kernel.h> 53 #include <sys/kthread.h> 54 #include <sys/device.h> 55 56 #include <dev/pcmcia/pcmciareg.h> 57 #include <dev/pcmcia/pcmciavar.h> 58 #include <dev/pcmcia/pcmciachip.h> 59 60 #include <machine/bus.h> 61 #include <machine/intr.h> 62 63 #include <dev/sbus/sbusvar.h> 64 #include <dev/sbus/stp4020reg.h> 65 66 #define STP4020_DEBUG 1 /* XXX-temp */ 67 68 /* 69 * We use the three available windows per socket in a simple, fixed 70 * arrangement. Each window maps (at full 1 MB size) one of the pcmcia 71 * spaces into sbus space. 72 */ 73 #define STP_WIN_ATTR 0 /* index of the attribute memory space window */ 74 #define STP_WIN_MEM 1 /* index of the common memory space window */ 75 #define STP_WIN_IO 2 /* index of the io space window */ 76 77 78 #if defined(STP4020_DEBUG) 79 int stp4020_debug = 0; 80 #define DPRINTF(x) do { if (stp4020_debug) printf x; } while(0) 81 #else 82 #define DPRINTF(x) 83 #endif 84 85 /* 86 * Event queue; events detected in an interrupt context go here 87 * awaiting attention from our event handling thread. 88 */ 89 struct stp4020_event { 90 SIMPLEQ_ENTRY(stp4020_event) se_q; 91 int se_type; 92 int se_sock; 93 }; 94 /* Defined event types */ 95 #define STP4020_EVENT_INSERTION 0 96 #define STP4020_EVENT_REMOVAL 1 97 98 /* 99 * Per socket data. 100 */ 101 struct stp4020_socket { 102 struct stp4020_softc *sc; /* Back link */ 103 int flags; 104 #define STP4020_SOCKET_BUSY 0x0001 105 #define STP4020_SOCKET_SHUTDOWN 0x0002 106 int sock; /* Socket number (0 or 1) */ 107 int sbus_intno; /* Do we use first (0) or second (1) 108 interrupt? */ 109 int int_enable; /* ICR0 value for interrupt enabled */ 110 int int_disable; /* ICR0 value for interrupt disabled */ 111 bus_space_tag_t tag; /* socket control space */ 112 bus_space_handle_t regs; /* */ 113 struct device *pcmcia; /* Associated PCMCIA device */ 114 int (*intrhandler) /* Card driver interrupt handler */ 115 __P((void *)); 116 void *intrarg; /* Card interrupt handler argument */ 117 void *softint; /* cookie for the softintr */ 118 119 struct { 120 bus_space_handle_t winaddr;/* this window's address */ 121 } windows[STP4020_NWIN]; 122 123 }; 124 125 struct stp4020_softc { 126 struct device sc_dev; /* Base device */ 127 struct sbusdev sc_sd; /* SBus device */ 128 bus_space_tag_t sc_bustag; 129 bus_dma_tag_t sc_dmatag; 130 pcmcia_chipset_tag_t sc_pct; /* Chipset methods */ 131 132 struct proc *event_thread; /* event handling thread */ 133 SIMPLEQ_HEAD(, stp4020_event) events; /* Pending events for thread */ 134 135 struct stp4020_socket sc_socks[STP4020_NSOCK]; 136 }; 137 138 139 static int stp4020print __P((void *, const char *)); 140 static int stp4020match __P((struct device *, struct cfdata *, void *)); 141 static void stp4020attach __P((struct device *, struct device *, void *)); 142 static int stp4020_intr __P((void *)); 143 static void stp4020_map_window(struct stp4020_socket *h, int win, int speed); 144 static void stp4020_calc_speed(int bus_speed, int ns, int *length, int *delay); 145 static void stp4020_intr_dispatch(void *arg); 146 147 CFATTACH_DECL(nell, sizeof(struct stp4020_softc), 148 stp4020match, stp4020attach, NULL, NULL); 149 150 #ifdef STP4020_DEBUG 151 static void stp4020_dump_regs __P((struct stp4020_socket *)); 152 #endif 153 154 static int stp4020_rd_sockctl __P((struct stp4020_socket *, int)); 155 static void stp4020_wr_sockctl __P((struct stp4020_socket *, int, int)); 156 static int stp4020_rd_winctl __P((struct stp4020_socket *, int, int)); 157 static void stp4020_wr_winctl __P((struct stp4020_socket *, int, int, int)); 158 159 void stp4020_delay __P((unsigned int)); 160 void stp4020_attach_socket __P((struct stp4020_socket *, int)); 161 void stp4020_create_event_thread __P((void *)); 162 void stp4020_event_thread __P((void *)); 163 void stp4020_queue_event __P((struct stp4020_softc *, int, int)); 164 165 int stp4020_chip_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 166 struct pcmcia_mem_handle *)); 167 void stp4020_chip_mem_free __P((pcmcia_chipset_handle_t, 168 struct pcmcia_mem_handle *)); 169 int stp4020_chip_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 170 bus_size_t, struct pcmcia_mem_handle *, 171 bus_size_t *, int *)); 172 void stp4020_chip_mem_unmap __P((pcmcia_chipset_handle_t, int)); 173 174 int stp4020_chip_io_alloc __P((pcmcia_chipset_handle_t, 175 bus_addr_t, bus_size_t, bus_size_t, 176 struct pcmcia_io_handle *)); 177 void stp4020_chip_io_free __P((pcmcia_chipset_handle_t, 178 struct pcmcia_io_handle *)); 179 int stp4020_chip_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 180 bus_size_t, struct pcmcia_io_handle *, int *)); 181 void stp4020_chip_io_unmap __P((pcmcia_chipset_handle_t, int)); 182 183 void stp4020_chip_socket_enable __P((pcmcia_chipset_handle_t)); 184 void stp4020_chip_socket_disable __P((pcmcia_chipset_handle_t)); 185 void *stp4020_chip_intr_establish __P((pcmcia_chipset_handle_t, 186 struct pcmcia_function *, int, 187 int (*) __P((void *)), void *)); 188 void stp4020_chip_intr_disestablish __P((pcmcia_chipset_handle_t, void *)); 189 190 /* Our PCMCIA chipset methods */ 191 static struct pcmcia_chip_functions stp4020_functions = { 192 stp4020_chip_mem_alloc, 193 stp4020_chip_mem_free, 194 stp4020_chip_mem_map, 195 stp4020_chip_mem_unmap, 196 197 stp4020_chip_io_alloc, 198 stp4020_chip_io_free, 199 stp4020_chip_io_map, 200 stp4020_chip_io_unmap, 201 202 stp4020_chip_intr_establish, 203 stp4020_chip_intr_disestablish, 204 205 stp4020_chip_socket_enable, 206 stp4020_chip_socket_disable 207 }; 208 209 210 static __inline__ int 211 stp4020_rd_sockctl(h, idx) 212 struct stp4020_socket *h; 213 int idx; 214 { 215 int o = ((STP4020_SOCKREGS_SIZE * (h->sock)) + idx); 216 return (bus_space_read_2(h->tag, h->regs, o)); 217 } 218 219 static __inline__ void 220 stp4020_wr_sockctl(h, idx, v) 221 struct stp4020_socket *h; 222 int idx; 223 int v; 224 { 225 int o = (STP4020_SOCKREGS_SIZE * (h->sock)) + idx; 226 bus_space_write_2(h->tag, h->regs, o, v); 227 } 228 229 static __inline__ int 230 stp4020_rd_winctl(h, win, idx) 231 struct stp4020_socket *h; 232 int win; 233 int idx; 234 { 235 int o = (STP4020_SOCKREGS_SIZE * (h->sock)) + 236 (STP4020_WINREGS_SIZE * win) + idx; 237 return (bus_space_read_2(h->tag, h->regs, o)); 238 } 239 240 static __inline__ void 241 stp4020_wr_winctl(h, win, idx, v) 242 struct stp4020_socket *h; 243 int win; 244 int idx; 245 int v; 246 { 247 int o = (STP4020_SOCKREGS_SIZE * (h->sock)) + 248 (STP4020_WINREGS_SIZE * win) + idx; 249 250 bus_space_write_2(h->tag, h->regs, o, v); 251 } 252 253 254 int 255 stp4020print(aux, busname) 256 void *aux; 257 const char *busname; 258 { 259 struct pcmciabus_attach_args *paa = aux; 260 struct stp4020_socket *h = paa->pch; 261 262 aprint_normal(" socket %d", h->sock); 263 return (UNCONF); 264 } 265 266 int 267 stp4020match(parent, cf, aux) 268 struct device *parent; 269 struct cfdata *cf; 270 void *aux; 271 { 272 struct sbus_attach_args *sa = aux; 273 274 return (strcmp("SUNW,pcmcia", sa->sa_name) == 0); 275 } 276 277 /* 278 * Attach all the sub-devices we can find 279 */ 280 void 281 stp4020attach(parent, self, aux) 282 struct device *parent, *self; 283 void *aux; 284 { 285 struct sbus_attach_args *sa = aux; 286 struct stp4020_softc *sc = (void *)self; 287 int rev; 288 int i, sbus_intno; 289 bus_space_handle_t bh; 290 291 /* lsb of our config flags decides which interrupt we use */ 292 sbus_intno = sc->sc_dev.dv_cfdata->cf_flags & 1; 293 294 /* Transfer bus tags */ 295 sc->sc_bustag = sa->sa_bustag; 296 sc->sc_dmatag = sa->sa_dmatag; 297 298 /* Set up per-socket static initialization */ 299 sc->sc_socks[0].sc = sc->sc_socks[1].sc = sc; 300 sc->sc_socks[0].tag = sc->sc_socks[1].tag = sa->sa_bustag; 301 sc->sc_socks[0].sbus_intno = 302 sc->sc_socks[1].sbus_intno = sbus_intno; 303 304 if (sa->sa_nreg < 8) { 305 printf("%s: only %d register sets\n", 306 self->dv_xname, sa->sa_nreg); 307 return; 308 } 309 310 if (sa->sa_nintr != 2) { 311 printf("%s: expect 2 interrupt Sbus levels; got %d\n", 312 self->dv_xname, sa->sa_nintr); 313 return; 314 } 315 316 #define STP4020_BANK_PROM 0 317 #define STP4020_BANK_CTRL 4 318 for (i = 0; i < 8; i++) { 319 320 /* 321 * STP4020 Register address map: 322 * bank 0: Forth PROM 323 * banks 1-3: socket 0, windows 0-2 324 * bank 4: control registers 325 * banks 5-7: socket 1, windows 0-2 326 */ 327 328 if (i == STP4020_BANK_PROM) 329 /* Skip the PROM */ 330 continue; 331 332 if (sbus_bus_map(sa->sa_bustag, 333 sa->sa_reg[i].oa_space, 334 sa->sa_reg[i].oa_base, 335 sa->sa_reg[i].oa_size, 336 0, &bh) != 0) { 337 printf("%s: attach: cannot map registers\n", 338 self->dv_xname); 339 return; 340 } 341 342 if (i == STP4020_BANK_CTRL) { 343 /* 344 * Copy tag and handle to both socket structures 345 * for easy access in control/status IO functions. 346 */ 347 sc->sc_socks[0].regs = sc->sc_socks[1].regs = bh; 348 } else if (i < STP4020_BANK_CTRL) { 349 /* banks 1-3 */ 350 sc->sc_socks[0].windows[i-1].winaddr = bh; 351 } else { 352 /* banks 5-7 */ 353 sc->sc_socks[1].windows[i-5].winaddr = bh; 354 } 355 } 356 357 sbus_establish(&sc->sc_sd, &sc->sc_dev); 358 359 /* We only use one interrupt level. */ 360 if (sa->sa_nintr > sbus_intno) { 361 bus_intr_establish(sa->sa_bustag, 362 sa->sa_intr[sbus_intno].oi_pri, 363 IPL_NONE, stp4020_intr, sc); 364 } 365 366 rev = stp4020_rd_sockctl(&sc->sc_socks[0], STP4020_ISR1_IDX) & 367 STP4020_ISR1_REV_M; 368 printf(": rev %x\n", rev); 369 370 sc->sc_pct = (pcmcia_chipset_tag_t)&stp4020_functions; 371 372 /* 373 * Arrange that a kernel thread be created to handle 374 * insert/removal events. 375 */ 376 SIMPLEQ_INIT(&sc->events); 377 kthread_create(stp4020_create_event_thread, sc); 378 379 for (i = 0; i < STP4020_NSOCK; i++) { 380 struct stp4020_socket *h = &sc->sc_socks[i]; 381 h->sock = i; 382 h->sc = sc; 383 #ifdef STP4020_DEBUG 384 if (stp4020_debug) 385 stp4020_dump_regs(h); 386 #endif 387 stp4020_attach_socket(h, sa->sa_frequency); 388 } 389 } 390 391 void 392 stp4020_attach_socket(h, speed) 393 struct stp4020_socket *h; 394 int speed; 395 { 396 struct pcmciabus_attach_args paa; 397 int v; 398 399 /* no interrupt handlers yet */ 400 h->intrhandler = NULL; 401 h->intrarg = NULL; 402 h->softint = NULL; 403 h->int_enable = 0; 404 h->int_disable = 0; 405 406 /* Map all three windows */ 407 stp4020_map_window(h, STP_WIN_ATTR, speed); 408 stp4020_map_window(h, STP_WIN_MEM, speed); 409 stp4020_map_window(h, STP_WIN_IO, speed); 410 411 /* Configure one pcmcia device per socket */ 412 paa.paa_busname = "pcmcia"; 413 paa.pct = (pcmcia_chipset_tag_t)h->sc->sc_pct; 414 paa.pch = (pcmcia_chipset_handle_t)h; 415 paa.iobase = 0; 416 paa.iosize = STP4020_WINDOW_SIZE; 417 418 h->pcmcia = config_found(&h->sc->sc_dev, &paa, stp4020print); 419 420 if (h->pcmcia == NULL) 421 return; 422 423 /* 424 * There's actually a pcmcia bus attached; initialize the slot. 425 */ 426 427 /* 428 * Clear things up before we enable status change interrupts. 429 * This seems to not be fully initialized by the PROM. 430 */ 431 stp4020_wr_sockctl(h, STP4020_ICR1_IDX, 0); 432 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, 0); 433 stp4020_wr_sockctl(h, STP4020_ISR1_IDX, 0x3fff); 434 stp4020_wr_sockctl(h, STP4020_ISR0_IDX, 0x3fff); 435 436 /* 437 * Enable socket status change interrupts. 438 * We only use one common interrupt for status change 439 * and IO, to avoid locking issues. 440 */ 441 v = STP4020_ICR0_ALL_STATUS_IE 442 | (h->sbus_intno ? STP4020_ICR0_SCILVL_SB1 443 : STP4020_ICR0_SCILVL_SB0); 444 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, v); 445 446 /* Get live status bits from ISR0 */ 447 v = stp4020_rd_sockctl(h, STP4020_ISR0_IDX); 448 if ((v & (STP4020_ISR0_CD1ST|STP4020_ISR0_CD2ST)) == 0) 449 return; 450 451 pcmcia_card_attach(h->pcmcia); 452 h->flags |= STP4020_SOCKET_BUSY; 453 } 454 455 456 /* 457 * Deferred thread creation callback. 458 */ 459 void 460 stp4020_create_event_thread(arg) 461 void *arg; 462 { 463 struct stp4020_softc *sc = arg; 464 const char *name = sc->sc_dev.dv_xname; 465 466 if (kthread_create1(stp4020_event_thread, sc, &sc->event_thread, 467 "%s", name)) { 468 panic("%s: unable to create event thread", name); 469 } 470 } 471 472 /* 473 * The actual event handling thread. 474 */ 475 void 476 stp4020_event_thread(arg) 477 void *arg; 478 { 479 struct stp4020_softc *sc = arg; 480 struct stp4020_event *e; 481 int s; 482 483 while (1) { 484 struct stp4020_socket *h; 485 int n; 486 487 s = splhigh(); 488 if ((e = SIMPLEQ_FIRST(&sc->events)) == NULL) { 489 splx(s); 490 (void)tsleep(&sc->events, PWAIT, "pcicev", 0); 491 continue; 492 } 493 SIMPLEQ_REMOVE_HEAD(&sc->events, se_q); 494 splx(s); 495 496 n = e->se_sock; 497 if (n < 0 || n >= STP4020_NSOCK) 498 panic("stp4020_event_thread: wayward socket number %d", 499 n); 500 501 h = &sc->sc_socks[n]; 502 switch (e->se_type) { 503 case STP4020_EVENT_INSERTION: 504 pcmcia_card_attach(h->pcmcia); 505 break; 506 case STP4020_EVENT_REMOVAL: 507 pcmcia_card_detach(h->pcmcia, DETACH_FORCE); 508 break; 509 default: 510 panic("stp4020_event_thread: unknown event type %d", 511 e->se_type); 512 } 513 free(e, M_TEMP); 514 } 515 } 516 517 void 518 stp4020_queue_event(sc, sock, event) 519 struct stp4020_softc *sc; 520 int sock, event; 521 { 522 struct stp4020_event *e; 523 int s; 524 525 e = malloc(sizeof(*e), M_TEMP, M_NOWAIT); 526 if (e == NULL) 527 panic("stp4020_queue_event: can't allocate event"); 528 529 e->se_type = event; 530 e->se_sock = sock; 531 s = splhigh(); 532 SIMPLEQ_INSERT_TAIL(&sc->events, e, se_q); 533 splx(s); 534 wakeup(&sc->events); 535 } 536 537 /* 538 * Softinterrupt called to invoke the real driver interrupt handler. 539 */ 540 static void 541 stp4020_intr_dispatch(arg) 542 void *arg; 543 { 544 struct stp4020_socket *h = arg; 545 int s; 546 547 /* invoke driver handler */ 548 h->intrhandler(h->intrarg); 549 550 /* enable SBUS interrupts for pcmcia interrupts again */ 551 s = splhigh(); 552 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, h->int_enable); 553 splx(s); 554 } 555 556 int 557 stp4020_intr(arg) 558 void *arg; 559 { 560 struct stp4020_softc *sc = arg; 561 int i, s, r = 0, cd_change = 0; 562 563 564 /* protect hardware access by splhigh against softint */ 565 s = splhigh(); 566 567 /* 568 * Check each socket for pending requests. 569 */ 570 for (i = 0 ; i < STP4020_NSOCK; i++) { 571 struct stp4020_socket *h; 572 int v; 573 574 h = &sc->sc_socks[i]; 575 576 v = stp4020_rd_sockctl(h, STP4020_ISR0_IDX); 577 578 /* Ack all interrupts at once. */ 579 stp4020_wr_sockctl(h, STP4020_ISR0_IDX, 580 STP4020_ISR0_ALL_STATUS_IRQ); 581 582 #ifdef STP4020_DEBUG 583 if (stp4020_debug != 0) { 584 char bits[64]; 585 bitmask_snprintf(v, STP4020_ISR0_IOBITS, 586 bits, sizeof(bits)); 587 printf("stp4020_statintr: ISR0=%s\n", bits); 588 } 589 #endif 590 591 if ((v & STP4020_ISR0_CDCHG) != 0) { 592 /* 593 * Card status change detect 594 */ 595 cd_change = 1; 596 r = 1; 597 if ((v & (STP4020_ISR0_CD1ST|STP4020_ISR0_CD2ST)) == (STP4020_ISR0_CD1ST|STP4020_ISR0_CD2ST)){ 598 if ((h->flags & STP4020_SOCKET_BUSY) == 0) { 599 stp4020_queue_event(sc, i, 600 STP4020_EVENT_INSERTION); 601 h->flags |= STP4020_SOCKET_BUSY; 602 } 603 } 604 if ((v & (STP4020_ISR0_CD1ST|STP4020_ISR0_CD2ST)) == 0){ 605 if ((h->flags & STP4020_SOCKET_BUSY) != 0) { 606 stp4020_queue_event(sc, i, 607 STP4020_EVENT_REMOVAL); 608 h->flags &= ~STP4020_SOCKET_BUSY; 609 } 610 } 611 } 612 613 if ((v & STP4020_ISR0_IOINT) != 0) { 614 /* we can not deny this is ours, no matter what the 615 card driver says. */ 616 r = 1; 617 618 /* It's a card interrupt */ 619 if ((h->flags & STP4020_SOCKET_BUSY) == 0) { 620 printf("stp4020[%d]: spurious interrupt?\n", 621 h->sock); 622 continue; 623 } 624 625 /* 626 * Schedule softint to invoke driver interrupt 627 * handler 628 */ 629 if (h->softint != NULL) 630 softintr_schedule(h->softint); 631 /* 632 * Disable this sbus interrupt, until the soft-int 633 * handler had a chance to run 634 */ 635 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, h->int_disable); 636 } 637 638 /* informational messages */ 639 if ((v & STP4020_ISR0_BVD1CHG) != 0) { 640 /* ignore if this is caused by insert or removal */ 641 if (!cd_change) 642 printf("stp4020[%d]: Battery change 1\n", h->sock); 643 r = 1; 644 } 645 646 if ((v & STP4020_ISR0_BVD2CHG) != 0) { 647 /* ignore if this is caused by insert or removal */ 648 if (!cd_change) 649 printf("stp4020[%d]: Battery change 2\n", h->sock); 650 r = 1; 651 } 652 653 if ((v & STP4020_ISR0_RDYCHG) != 0) { 654 DPRINTF(("stp4020[%d]: Ready/Busy change\n", h->sock)); 655 r = 1; 656 } 657 658 if ((v & STP4020_ISR0_WPCHG) != 0) { 659 DPRINTF(("stp4020[%d]: Write protect change\n", h->sock)); 660 r = 1; 661 } 662 663 if ((v & STP4020_ISR0_PCTO) != 0) { 664 DPRINTF(("stp4020[%d]: Card access timeout\n", h->sock)); 665 r = 1; 666 } 667 668 } 669 splx(s); 670 671 return (r); 672 } 673 674 /* 675 * The function gets the sbus speed and a access time and calculates 676 * values for the CMDLNG and CMDDLAY registers. 677 */ 678 static void 679 stp4020_calc_speed(int bus_speed, int ns, int *length, int *delay) 680 { 681 int result; 682 683 if (ns < STP4020_MEM_SPEED_MIN) 684 ns = STP4020_MEM_SPEED_MIN; 685 else if (ns > STP4020_MEM_SPEED_MAX) 686 ns = STP4020_MEM_SPEED_MAX; 687 result = ns*(bus_speed/1000); 688 if (result % 1000000) 689 result = result/1000000 + 1; 690 else 691 result /= 1000000; 692 *length = result; 693 694 /* the sbus frequency range is limited, so we can keep this simple */ 695 *delay = ns <= STP4020_MEM_SPEED_MIN? 1 : 2; 696 } 697 698 static void 699 stp4020_map_window(struct stp4020_socket *h, int win, int speed) 700 { 701 int v, length, delay; 702 703 /* 704 * According to the PC Card standard 300ns access timing should be 705 * used for attribute memory access. Our pcmcia framework does not 706 * seem to propagate timing information, so we use that 707 * everywhere. 708 */ 709 stp4020_calc_speed(speed, (win==STP_WIN_ATTR)? 300 : 100, &length, &delay); 710 711 /* 712 * Fill in the Address Space Select and Base Address 713 * fields of this windows control register 0. 714 */ 715 v = ((delay << STP4020_WCR0_CMDDLY_S)&STP4020_WCR0_CMDDLY_M) 716 | ((length << STP4020_WCR0_CMDLNG_S)&STP4020_WCR0_CMDLNG_M); 717 switch (win) { 718 case STP_WIN_ATTR: 719 v |= STP4020_WCR0_ASPSEL_AM; 720 break; 721 case STP_WIN_MEM: 722 v |= STP4020_WCR0_ASPSEL_CM; 723 break; 724 case STP_WIN_IO: 725 v |= STP4020_WCR0_ASPSEL_IO; 726 break; 727 } 728 v |= (STP4020_ADDR2PAGE(0) & STP4020_WCR0_BASE_M); 729 stp4020_wr_winctl(h, win, STP4020_WCR0_IDX, v); 730 stp4020_wr_winctl(h, win, STP4020_WCR1_IDX, 1<<STP4020_WCR1_WAITREQ_S); 731 } 732 733 int 734 stp4020_chip_mem_alloc(pch, size, pcmhp) 735 pcmcia_chipset_handle_t pch; 736 bus_size_t size; 737 struct pcmcia_mem_handle *pcmhp; 738 { 739 struct stp4020_socket *h = (struct stp4020_socket *)pch; 740 741 /* we can not do much here, defere work to _mem_map */ 742 pcmhp->memt = h->tag; 743 pcmhp->size = size; 744 pcmhp->addr = 0; 745 pcmhp->mhandle = 0; 746 pcmhp->realsize = size; 747 748 return (0); 749 } 750 751 void 752 stp4020_chip_mem_free(pch, pcmhp) 753 pcmcia_chipset_handle_t pch; 754 struct pcmcia_mem_handle *pcmhp; 755 { 756 } 757 758 int 759 stp4020_chip_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 760 pcmcia_chipset_handle_t pch; 761 int kind; 762 bus_addr_t card_addr; 763 bus_size_t size; 764 struct pcmcia_mem_handle *pcmhp; 765 bus_size_t *offsetp; 766 int *windowp; 767 { 768 struct stp4020_socket *h = (struct stp4020_socket *)pch; 769 int win = (kind&PCMCIA_MEM_ATTR)? STP_WIN_ATTR : STP_WIN_MEM; 770 771 pcmhp->memt = h->tag; 772 bus_space_subregion(h->tag, h->windows[win].winaddr, card_addr, size, &pcmhp->memh); 773 pcmhp->size = size; 774 pcmhp->realsize = STP4020_WINDOW_SIZE - card_addr; 775 *offsetp = 0; 776 *windowp = 0; 777 778 return (0); 779 } 780 781 void 782 stp4020_chip_mem_unmap(pch, win) 783 pcmcia_chipset_handle_t pch; 784 int win; 785 { 786 } 787 788 int 789 stp4020_chip_io_alloc(pch, start, size, align, pcihp) 790 pcmcia_chipset_handle_t pch; 791 bus_addr_t start; 792 bus_size_t size; 793 bus_size_t align; 794 struct pcmcia_io_handle *pcihp; 795 { 796 struct stp4020_socket *h = (struct stp4020_socket *)pch; 797 798 pcihp->iot = h->tag; 799 pcihp->ioh = h->windows[STP_WIN_IO].winaddr; 800 return 0; 801 } 802 803 void 804 stp4020_chip_io_free(pch, pcihp) 805 pcmcia_chipset_handle_t pch; 806 struct pcmcia_io_handle *pcihp; 807 { 808 } 809 810 int 811 stp4020_chip_io_map(pch, width, offset, size, pcihp, windowp) 812 pcmcia_chipset_handle_t pch; 813 int width; 814 bus_addr_t offset; 815 bus_size_t size; 816 struct pcmcia_io_handle *pcihp; 817 int *windowp; 818 { 819 struct stp4020_socket *h = (struct stp4020_socket *)pch; 820 821 pcihp->iot = h->tag; 822 bus_space_subregion(h->tag, h->windows[STP_WIN_IO].winaddr, offset, size, &pcihp->ioh); 823 *windowp = 0; 824 return 0; 825 } 826 827 void 828 stp4020_chip_io_unmap(pch, win) 829 pcmcia_chipset_handle_t pch; 830 int win; 831 { 832 } 833 834 void 835 stp4020_chip_socket_enable(pch) 836 pcmcia_chipset_handle_t pch; 837 { 838 struct stp4020_socket *h = (struct stp4020_socket *)pch; 839 int i, v; 840 841 /* this bit is mostly stolen from pcic_attach_card */ 842 843 /* Power down the socket to reset it, clear the card reset pin */ 844 stp4020_wr_sockctl(h, STP4020_ICR1_IDX, 0); 845 846 /* 847 * wait 300ms until power fails (Tpf). Then, wait 100ms since 848 * we are changing Vcc (Toff). 849 */ 850 stp4020_delay((300 + 100) * 1000); 851 852 /* Power up the socket */ 853 v = STP4020_ICR1_MSTPWR; 854 stp4020_wr_sockctl(h, STP4020_ICR1_IDX, v); 855 856 /* 857 * wait 100ms until power raise (Tpr) and 20ms to become 858 * stable (Tsu(Vcc)). 859 */ 860 stp4020_delay((100 + 20) * 1000); 861 862 v |= STP4020_ICR1_PCIFOE|STP4020_ICR1_VPP1_VCC; 863 stp4020_wr_sockctl(h, STP4020_ICR1_IDX, v); 864 865 /* 866 * hold RESET at least 10us. 867 */ 868 delay(10); 869 870 /* Clear reset flag */ 871 v = stp4020_rd_sockctl(h, STP4020_ICR0_IDX); 872 v &= ~STP4020_ICR0_RESET; 873 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, v); 874 875 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 876 stp4020_delay(20000); 877 878 /* Wait for the chip to finish initializing (5 seconds max) */ 879 for (i = 10000; i > 0; i--) { 880 v = stp4020_rd_sockctl(h, STP4020_ISR0_IDX); 881 if ((v & STP4020_ISR0_RDYST) != 0) 882 break; 883 delay(500); 884 } 885 if (i <= 0) { 886 char bits[64]; 887 bitmask_snprintf(stp4020_rd_sockctl(h, STP4020_ISR0_IDX), 888 STP4020_ISR0_IOBITS, bits, sizeof(bits)); 889 printf("stp4020_chip_socket_enable: not ready: status %s\n", 890 bits); 891 return; 892 } 893 894 v = stp4020_rd_sockctl(h, STP4020_ICR0_IDX); 895 896 /* 897 * Check the card type. 898 * Enable socket I/O interrupts for IO cards. 899 * We use level SB_INT[0] for I/O interrupts. 900 */ 901 if (pcmcia_card_gettype(h->pcmcia) == PCMCIA_IFTYPE_IO) { 902 v &= ~(STP4020_ICR0_IOILVL|STP4020_ICR0_IFTYPE); 903 v |= STP4020_ICR0_IFTYPE_IO|STP4020_ICR0_IOIE 904 |STP4020_ICR0_SPKREN; 905 v |= h->sbus_intno ? STP4020_ICR0_IOILVL_SB1 906 : STP4020_ICR0_IOILVL_SB0; 907 h->int_enable = v; 908 h->int_disable = v & ~STP4020_ICR0_IOIE; 909 DPRINTF(("%s: configuring card for IO useage\n", h->sc->sc_dev.dv_xname)); 910 } else { 911 v &= ~(STP4020_ICR0_IOILVL|STP4020_ICR0_IFTYPE 912 |STP4020_ICR0_SPKREN); 913 v |= STP4020_ICR0_IFTYPE_MEM; 914 DPRINTF(("%s: configuring card for MEM ONLY useage\n", h->sc->sc_dev.dv_xname)); 915 } 916 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, v); 917 } 918 919 void 920 stp4020_chip_socket_disable(pch) 921 pcmcia_chipset_handle_t pch; 922 { 923 struct stp4020_socket *h = (struct stp4020_socket *)pch; 924 int v; 925 926 /* 927 * Disable socket I/O interrupts. 928 */ 929 v = stp4020_rd_sockctl(h, STP4020_ICR0_IDX); 930 v &= ~(STP4020_ICR0_IOIE | STP4020_ICR0_IOILVL); 931 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, v); 932 933 /* Power down the socket */ 934 stp4020_wr_sockctl(h, STP4020_ICR1_IDX, 0); 935 936 /* 937 * wait 300ms until power fails (Tpf). 938 */ 939 stp4020_delay(300 * 1000); 940 } 941 942 void * 943 stp4020_chip_intr_establish(pch, pf, ipl, handler, arg) 944 pcmcia_chipset_handle_t pch; 945 struct pcmcia_function *pf; 946 int ipl; 947 int (*handler) __P((void *)); 948 void *arg; 949 { 950 struct stp4020_socket *h = (struct stp4020_socket *)pch; 951 952 /* only one interrupt handler per slot */ 953 if (h->intrhandler != NULL) return NULL; 954 955 h->intrhandler = handler; 956 h->intrarg = arg; 957 h->softint = softintr_establish(ipl, stp4020_intr_dispatch, h); 958 return h->softint; 959 } 960 961 void 962 stp4020_chip_intr_disestablish(pch, ih) 963 pcmcia_chipset_handle_t pch; 964 void *ih; 965 { 966 struct stp4020_socket *h = (struct stp4020_socket *)pch; 967 968 h->intrhandler = NULL; 969 h->intrarg = NULL; 970 if (h->softint) { 971 softintr_disestablish(h->softint); 972 h->softint = NULL; 973 } 974 } 975 976 /* 977 * Delay and possibly yield CPU. 978 * XXX - assumes a context 979 */ 980 void 981 stp4020_delay(ms) 982 unsigned int ms; 983 { 984 unsigned int ticks; 985 986 /* Convert to ticks */ 987 ticks = (ms * hz ) / 1000000; 988 989 if (cold || ticks == 0) { 990 delay(ms); 991 return; 992 } 993 994 #ifdef DIAGNOSTIC 995 if (ticks > 60*hz) 996 panic("stp4020: preposterous delay: %u", ticks); 997 #endif 998 tsleep(&ticks, 0, "stp4020_delay", ticks); 999 } 1000 1001 #ifdef STP4020_DEBUG 1002 void 1003 stp4020_dump_regs(h) 1004 struct stp4020_socket *h; 1005 { 1006 char bits[64]; 1007 /* 1008 * Dump control and status registers. 1009 */ 1010 printf("socket[%d] registers:\n", h->sock); 1011 bitmask_snprintf(stp4020_rd_sockctl(h, STP4020_ICR0_IDX), 1012 STP4020_ICR0_BITS, bits, sizeof(bits)); 1013 printf("\tICR0=%s\n", bits); 1014 1015 bitmask_snprintf(stp4020_rd_sockctl(h, STP4020_ICR1_IDX), 1016 STP4020_ICR1_BITS, bits, sizeof(bits)); 1017 printf("\tICR1=%s\n", bits); 1018 1019 bitmask_snprintf(stp4020_rd_sockctl(h, STP4020_ISR0_IDX), 1020 STP4020_ISR0_IOBITS, bits, sizeof(bits)); 1021 printf("\tISR0=%s\n", bits); 1022 1023 bitmask_snprintf(stp4020_rd_sockctl(h, STP4020_ISR1_IDX), 1024 STP4020_ISR1_BITS, bits, sizeof(bits)); 1025 printf("\tISR1=%s\n", bits); 1026 } 1027 #endif /* STP4020_DEBUG */ 1028
Indexes created Thu Oct 02 14:10:14 GMT 2025