stp4020.c revision 1.49.6.3
1 /* $NetBSD: stp4020.c,v 1.49.6.3 2007/07/15 13:21:43 ad Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * STP4020: SBus/PCMCIA bridge supporting two Type-3 PCMCIA cards. 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: stp4020.c,v 1.49.6.3 2007/07/15 13:21:43 ad Exp $"); 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/errno.h> 49 #include <sys/malloc.h> 50 #include <sys/extent.h> 51 #include <sys/proc.h> 52 #include <sys/kernel.h> 53 #include <sys/kthread.h> 54 #include <sys/device.h> 55 #include <sys/intr.h> 56 57 #include <dev/pcmcia/pcmciareg.h> 58 #include <dev/pcmcia/pcmciavar.h> 59 #include <dev/pcmcia/pcmciachip.h> 60 61 #include <machine/bus.h> 62 63 #include <dev/sbus/sbusvar.h> 64 #include <dev/sbus/stp4020reg.h> 65 66 #define STP4020_DEBUG 1 /* XXX-temp */ 67 68 /* 69 * We use the three available windows per socket in a simple, fixed 70 * arrangement. Each window maps (at full 1 MB size) one of the pcmcia 71 * spaces into sbus space. 72 */ 73 #define STP_WIN_ATTR 0 /* index of the attribute memory space window */ 74 #define STP_WIN_MEM 1 /* index of the common memory space window */ 75 #define STP_WIN_IO 2 /* index of the io space window */ 76 77 78 #if defined(STP4020_DEBUG) 79 int stp4020_debug = 0; 80 #define DPRINTF(x) do { if (stp4020_debug) printf x; } while(0) 81 #else 82 #define DPRINTF(x) 83 #endif 84 85 /* 86 * Event queue; events detected in an interrupt context go here 87 * awaiting attention from our event handling thread. 88 */ 89 struct stp4020_event { 90 SIMPLEQ_ENTRY(stp4020_event) se_q; 91 int se_type; 92 int se_sock; 93 }; 94 /* Defined event types */ 95 #define STP4020_EVENT_INSERTION 0 96 #define STP4020_EVENT_REMOVAL 1 97 98 /* 99 * Per socket data. 100 */ 101 struct stp4020_socket { 102 struct stp4020_softc *sc; /* Back link */ 103 int flags; 104 #define STP4020_SOCKET_BUSY 0x0001 105 int sock; /* Socket number (0 or 1) */ 106 int sbus_intno; /* Do we use first (0) or second (1) 107 interrupt? */ 108 int int_enable; /* ICR0 value for interrupt enabled */ 109 int int_disable; /* ICR0 value for interrupt disabled */ 110 bus_space_tag_t tag; /* socket control io */ 111 bus_space_handle_t regs; /* space */ 112 bus_space_tag_t pcmciat; /* io space for pcmcia */ 113 struct device *pcmcia; /* Associated PCMCIA device */ 114 int (*intrhandler) /* Card driver interrupt handler */ 115 (void *); 116 void *intrarg; /* Card interrupt handler argument */ 117 void *softint; /* cookie for the softintr */ 118 119 struct { 120 bus_space_handle_t winaddr;/* this window's address */ 121 } windows[STP4020_NWIN]; 122 123 }; 124 125 struct stp4020_softc { 126 struct device sc_dev; /* Base device */ 127 struct sbusdev sc_sd; /* SBus device */ 128 pcmcia_chipset_tag_t sc_pct; /* Chipset methods */ 129 130 struct lwp *event_thread; /* event handling thread */ 131 SIMPLEQ_HEAD(, stp4020_event) events; /* Pending events for thread */ 132 133 struct stp4020_socket sc_socks[STP4020_NSOCK]; 134 }; 135 136 137 static int stp4020print(void *, const char *); 138 static int stp4020match(struct device *, struct cfdata *, void *); 139 static void stp4020attach(struct device *, struct device *, void *); 140 static int stp4020_intr(void *); 141 static void stp4020_map_window(struct stp4020_socket *h, int win, int speed); 142 static void stp4020_calc_speed(int bus_speed, int ns, int *length, int *cmd_delay); 143 static void stp4020_intr_dispatch(void *arg); 144 145 CFATTACH_DECL(nell, sizeof(struct stp4020_softc), 146 stp4020match, stp4020attach, NULL, NULL); 147 148 #ifdef STP4020_DEBUG 149 static void stp4020_dump_regs(struct stp4020_socket *); 150 #endif 151 152 static int stp4020_rd_sockctl(struct stp4020_socket *, int); 153 static void stp4020_wr_sockctl(struct stp4020_socket *, int, int); 154 static int stp4020_rd_winctl(struct stp4020_socket *, int, int); 155 static void stp4020_wr_winctl(struct stp4020_socket *, int, int, int); 156 157 void stp4020_delay(struct stp4020_softc *sc, unsigned int); 158 void stp4020_attach_socket(struct stp4020_socket *, int); 159 void stp4020_event_thread(void *); 160 void stp4020_queue_event(struct stp4020_softc *, int, int); 161 162 int stp4020_chip_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 163 struct pcmcia_mem_handle *); 164 void stp4020_chip_mem_free(pcmcia_chipset_handle_t, 165 struct pcmcia_mem_handle *); 166 int stp4020_chip_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 167 bus_size_t, struct pcmcia_mem_handle *, 168 bus_size_t *, int *); 169 void stp4020_chip_mem_unmap(pcmcia_chipset_handle_t, int); 170 171 int stp4020_chip_io_alloc(pcmcia_chipset_handle_t, 172 bus_addr_t, bus_size_t, bus_size_t, 173 struct pcmcia_io_handle *); 174 void stp4020_chip_io_free(pcmcia_chipset_handle_t, 175 struct pcmcia_io_handle *); 176 int stp4020_chip_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 177 bus_size_t, struct pcmcia_io_handle *, int *); 178 void stp4020_chip_io_unmap(pcmcia_chipset_handle_t, int); 179 180 void stp4020_chip_socket_enable(pcmcia_chipset_handle_t); 181 void stp4020_chip_socket_disable(pcmcia_chipset_handle_t); 182 void stp4020_chip_socket_settype(pcmcia_chipset_handle_t, int); 183 void *stp4020_chip_intr_establish(pcmcia_chipset_handle_t, 184 struct pcmcia_function *, int, 185 int (*)(void *), void *); 186 void stp4020_chip_intr_disestablish(pcmcia_chipset_handle_t, void *); 187 188 /* Our PCMCIA chipset methods */ 189 static struct pcmcia_chip_functions stp4020_functions = { 190 stp4020_chip_mem_alloc, 191 stp4020_chip_mem_free, 192 stp4020_chip_mem_map, 193 stp4020_chip_mem_unmap, 194 195 stp4020_chip_io_alloc, 196 stp4020_chip_io_free, 197 stp4020_chip_io_map, 198 stp4020_chip_io_unmap, 199 200 stp4020_chip_intr_establish, 201 stp4020_chip_intr_disestablish, 202 203 stp4020_chip_socket_enable, 204 stp4020_chip_socket_disable, 205 stp4020_chip_socket_settype, 206 NULL 207 }; 208 209 210 static inline int 211 stp4020_rd_sockctl(h, idx) 212 struct stp4020_socket *h; 213 int idx; 214 { 215 int o = ((STP4020_SOCKREGS_SIZE * (h->sock)) + idx); 216 return (bus_space_read_2(h->tag, h->regs, o)); 217 } 218 219 static inline void 220 stp4020_wr_sockctl(h, idx, v) 221 struct stp4020_socket *h; 222 int idx; 223 int v; 224 { 225 int o = (STP4020_SOCKREGS_SIZE * (h->sock)) + idx; 226 bus_space_write_2(h->tag, h->regs, o, v); 227 } 228 229 static inline int 230 stp4020_rd_winctl(h, win, idx) 231 struct stp4020_socket *h; 232 int win; 233 int idx; 234 { 235 int o = (STP4020_SOCKREGS_SIZE * (h->sock)) + 236 (STP4020_WINREGS_SIZE * win) + idx; 237 return (bus_space_read_2(h->tag, h->regs, o)); 238 } 239 240 static inline void 241 stp4020_wr_winctl(h, win, idx, v) 242 struct stp4020_socket *h; 243 int win; 244 int idx; 245 int v; 246 { 247 int o = (STP4020_SOCKREGS_SIZE * (h->sock)) + 248 (STP4020_WINREGS_SIZE * win) + idx; 249 250 bus_space_write_2(h->tag, h->regs, o, v); 251 } 252 253 #ifndef SUN4U /* XXX - move to SBUS machdep function? */ 254 255 static u_int16_t stp4020_read_2(bus_space_tag_t, 256 bus_space_handle_t, 257 bus_size_t); 258 static u_int32_t stp4020_read_4(bus_space_tag_t, 259 bus_space_handle_t, 260 bus_size_t); 261 static u_int64_t stp4020_read_8(bus_space_tag_t, 262 bus_space_handle_t, 263 bus_size_t); 264 static void stp4020_write_2(bus_space_tag_t, 265 bus_space_handle_t, 266 bus_size_t, 267 u_int16_t); 268 static void stp4020_write_4(bus_space_tag_t, 269 bus_space_handle_t, 270 bus_size_t, 271 u_int32_t); 272 static void stp4020_write_8(bus_space_tag_t, 273 bus_space_handle_t, 274 bus_size_t, 275 u_int64_t); 276 277 static u_int16_t 278 stp4020_read_2(space, handle, offset) 279 bus_space_tag_t space; 280 bus_space_handle_t handle; 281 bus_size_t offset; 282 { 283 return (le16toh(*(volatile u_int16_t *)(handle + offset))); 284 } 285 286 static u_int32_t 287 stp4020_read_4(space, handle, offset) 288 bus_space_tag_t space; 289 bus_space_handle_t handle; 290 bus_size_t offset; 291 { 292 return (le32toh(*(volatile u_int32_t *)(handle + offset))); 293 } 294 295 static u_int64_t 296 stp4020_read_8(space, handle, offset) 297 bus_space_tag_t space; 298 bus_space_handle_t handle; 299 bus_size_t offset; 300 { 301 return (le64toh(*(volatile u_int64_t *)(handle + offset))); 302 } 303 304 static void 305 stp4020_write_2(space, handle, offset, value) 306 bus_space_tag_t space; 307 bus_space_handle_t handle; 308 bus_size_t offset; 309 u_int16_t value; 310 { 311 (*(volatile u_int16_t *)(handle + offset)) = htole16(value); 312 } 313 314 static void 315 stp4020_write_4(space, handle, offset, value) 316 bus_space_tag_t space; 317 bus_space_handle_t handle; 318 bus_size_t offset; 319 u_int32_t value; 320 { 321 (*(volatile u_int32_t *)(handle + offset)) = htole32(value); 322 } 323 324 static void 325 stp4020_write_8(space, handle, offset, value) 326 bus_space_tag_t space; 327 bus_space_handle_t handle; 328 bus_size_t offset; 329 u_int64_t value; 330 { 331 (*(volatile u_int64_t *)(handle + offset)) = htole64(value); 332 } 333 #endif /* SUN4U */ 334 335 int 336 stp4020print(aux, busname) 337 void *aux; 338 const char *busname; 339 { 340 struct pcmciabus_attach_args *paa = aux; 341 struct stp4020_socket *h = paa->pch; 342 343 aprint_normal(" socket %d", h->sock); 344 return (UNCONF); 345 } 346 347 int 348 stp4020match(parent, cf, aux) 349 struct device *parent; 350 struct cfdata *cf; 351 void *aux; 352 { 353 struct sbus_attach_args *sa = aux; 354 355 return (strcmp("SUNW,pcmcia", sa->sa_name) == 0); 356 } 357 358 /* 359 * Attach all the sub-devices we can find 360 */ 361 void 362 stp4020attach(parent, self, aux) 363 struct device *parent, *self; 364 void *aux; 365 { 366 struct sbus_attach_args *sa = aux; 367 struct stp4020_softc *sc = (void *)self; 368 bus_space_tag_t tag; 369 int rev; 370 int i, sbus_intno; 371 bus_space_handle_t bh; 372 373 /* lsb of our config flags decides which interrupt we use */ 374 sbus_intno = device_cfdata(&sc->sc_dev)->cf_flags & 1; 375 376 /* Transfer bus tags */ 377 #ifdef SUN4U 378 tag = sa->sa_bustag; 379 #else 380 tag = bus_space_tag_alloc(sa->sa_bustag, sc); 381 if (tag == NULL) { 382 printf("%s: attach: out of memory\n", self->dv_xname); 383 return; 384 } 385 tag->sparc_read_2 = stp4020_read_2; 386 tag->sparc_read_4 = stp4020_read_4; 387 tag->sparc_read_8 = stp4020_read_8; 388 tag->sparc_write_2 = stp4020_write_2; 389 tag->sparc_write_4 = stp4020_write_4; 390 tag->sparc_write_8 = stp4020_write_8; 391 #endif /* SUN4U */ 392 393 /* Set up per-socket static initialization */ 394 sc->sc_socks[0].sc = sc->sc_socks[1].sc = sc; 395 sc->sc_socks[0].tag = sc->sc_socks[1].tag = sa->sa_bustag; 396 /* 397 * XXX we rely on "tag" accepting the same handle-domain 398 * as sa->sa_bustag. 399 */ 400 sc->sc_socks[0].pcmciat = sc->sc_socks[1].pcmciat = tag; 401 sc->sc_socks[0].sbus_intno = 402 sc->sc_socks[1].sbus_intno = sbus_intno; 403 404 if (sa->sa_nreg < 8) { 405 printf("%s: only %d register sets\n", 406 self->dv_xname, sa->sa_nreg); 407 return; 408 } 409 410 if (sa->sa_nintr != 2) { 411 printf("%s: expect 2 interrupt Sbus levels; got %d\n", 412 self->dv_xname, sa->sa_nintr); 413 return; 414 } 415 416 #define STP4020_BANK_PROM 0 417 #define STP4020_BANK_CTRL 4 418 for (i = 0; i < 8; i++) { 419 420 /* 421 * STP4020 Register address map: 422 * bank 0: Forth PROM 423 * banks 1-3: socket 0, windows 0-2 424 * bank 4: control registers 425 * banks 5-7: socket 1, windows 0-2 426 */ 427 428 if (i == STP4020_BANK_PROM) 429 /* Skip the PROM */ 430 continue; 431 432 if (sbus_bus_map(sa->sa_bustag, 433 sa->sa_reg[i].oa_space, 434 sa->sa_reg[i].oa_base, 435 sa->sa_reg[i].oa_size, 436 0, &bh) != 0) { 437 printf("%s: attach: cannot map registers\n", 438 self->dv_xname); 439 return; 440 } 441 442 if (i == STP4020_BANK_CTRL) { 443 /* 444 * Copy tag and handle to both socket structures 445 * for easy access in control/status IO functions. 446 */ 447 sc->sc_socks[0].regs = sc->sc_socks[1].regs = bh; 448 } else if (i < STP4020_BANK_CTRL) { 449 /* banks 1-3 */ 450 sc->sc_socks[0].windows[i-1].winaddr = bh; 451 } else { 452 /* banks 5-7 */ 453 sc->sc_socks[1].windows[i-5].winaddr = bh; 454 } 455 } 456 457 sbus_establish(&sc->sc_sd, &sc->sc_dev); 458 459 /* We only use one interrupt level. */ 460 if (sa->sa_nintr > sbus_intno) { 461 bus_intr_establish(sa->sa_bustag, 462 sa->sa_intr[sbus_intno].oi_pri, 463 IPL_NONE, stp4020_intr, sc); 464 } 465 466 rev = stp4020_rd_sockctl(&sc->sc_socks[0], STP4020_ISR1_IDX) & 467 STP4020_ISR1_REV_M; 468 printf(": rev %x\n", rev); 469 470 sc->sc_pct = (pcmcia_chipset_tag_t)&stp4020_functions; 471 472 SIMPLEQ_INIT(&sc->events); 473 474 for (i = 0; i < STP4020_NSOCK; i++) { 475 struct stp4020_socket *h = &sc->sc_socks[i]; 476 h->sock = i; 477 h->sc = sc; 478 #ifdef STP4020_DEBUG 479 if (stp4020_debug) 480 stp4020_dump_regs(h); 481 #endif 482 stp4020_attach_socket(h, sa->sa_frequency); 483 } 484 485 /* 486 * Arrange that a kernel thread be created to handle 487 * insert/removal events. 488 */ 489 if (kthread_create(PRI_NONE, 0, NULL, stp4020_event_thread, sc, 490 &sc->event_thread, "%s", name)) { 491 panic("%s: unable to create event thread", name); 492 } 493 494 /* 495 * Arrange that a kernel thread be created to handle 496 * insert/removal events. 497 */ 498 if (kthread_create(PRI_NONE, 0, NULL, stp4020_event_thread, sc, 499 &sc->event_thread, "%s", self->dv_xname)) { 500 panic("%s: unable to create event thread", self->dv_xname); 501 } 502 } 503 504 void 505 stp4020_attach_socket(h, speed) 506 struct stp4020_socket *h; 507 int speed; 508 { 509 struct pcmciabus_attach_args paa; 510 int v; 511 512 /* no interrupt handlers yet */ 513 h->intrhandler = NULL; 514 h->intrarg = NULL; 515 h->softint = NULL; 516 h->int_enable = 0; 517 h->int_disable = 0; 518 519 /* Map all three windows */ 520 stp4020_map_window(h, STP_WIN_ATTR, speed); 521 stp4020_map_window(h, STP_WIN_MEM, speed); 522 stp4020_map_window(h, STP_WIN_IO, speed); 523 524 /* Configure one pcmcia device per socket */ 525 paa.paa_busname = "pcmcia"; 526 paa.pct = (pcmcia_chipset_tag_t)h->sc->sc_pct; 527 paa.pch = (pcmcia_chipset_handle_t)h; 528 paa.iobase = 0; 529 paa.iosize = STP4020_WINDOW_SIZE; 530 531 h->pcmcia = config_found(&h->sc->sc_dev, &paa, stp4020print); 532 533 if (h->pcmcia == NULL) 534 return; 535 536 /* 537 * There's actually a pcmcia bus attached; initialize the slot. 538 */ 539 540 /* 541 * Clear things up before we enable status change interrupts. 542 * This seems to not be fully initialized by the PROM. 543 */ 544 stp4020_wr_sockctl(h, STP4020_ICR1_IDX, 0); 545 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, 0); 546 stp4020_wr_sockctl(h, STP4020_ISR1_IDX, 0x3fff); 547 stp4020_wr_sockctl(h, STP4020_ISR0_IDX, 0x3fff); 548 549 /* 550 * Enable socket status change interrupts. 551 * We only use one common interrupt for status change 552 * and IO, to avoid locking issues. 553 */ 554 v = STP4020_ICR0_ALL_STATUS_IE 555 | (h->sbus_intno ? STP4020_ICR0_SCILVL_SB1 556 : STP4020_ICR0_SCILVL_SB0); 557 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, v); 558 559 /* Get live status bits from ISR0 and clear pending interrupts */ 560 v = stp4020_rd_sockctl(h, STP4020_ISR0_IDX); 561 stp4020_wr_sockctl(h, STP4020_ISR0_IDX, v); 562 563 if ((v & (STP4020_ISR0_CD1ST|STP4020_ISR0_CD2ST)) == 0) 564 return; 565 566 pcmcia_card_attach(h->pcmcia); 567 h->flags |= STP4020_SOCKET_BUSY; 568 } 569 570 /* 571 * The actual event handling thread. 572 */ 573 void 574 stp4020_event_thread(arg) 575 void *arg; 576 { 577 struct stp4020_softc *sc = arg; 578 struct stp4020_event *e; 579 int s; 580 581 while (1) { 582 struct stp4020_socket *h; 583 int n; 584 585 s = splhigh(); 586 if ((e = SIMPLEQ_FIRST(&sc->events)) == NULL) { 587 splx(s); 588 (void)tsleep(&sc->events, PWAIT, "nellevt", 0); 589 continue; 590 } 591 SIMPLEQ_REMOVE_HEAD(&sc->events, se_q); 592 splx(s); 593 594 n = e->se_sock; 595 if (n < 0 || n >= STP4020_NSOCK) 596 panic("stp4020_event_thread: wayward socket number %d", 597 n); 598 599 h = &sc->sc_socks[n]; 600 switch (e->se_type) { 601 case STP4020_EVENT_INSERTION: 602 pcmcia_card_attach(h->pcmcia); 603 break; 604 case STP4020_EVENT_REMOVAL: 605 pcmcia_card_detach(h->pcmcia, DETACH_FORCE); 606 break; 607 default: 608 panic("stp4020_event_thread: unknown event type %d", 609 e->se_type); 610 } 611 free(e, M_TEMP); 612 } 613 } 614 615 void 616 stp4020_queue_event(sc, sock, event) 617 struct stp4020_softc *sc; 618 int sock, event; 619 { 620 struct stp4020_event *e; 621 int s; 622 623 e = malloc(sizeof(*e), M_TEMP, M_NOWAIT); 624 if (e == NULL) 625 panic("stp4020_queue_event: can't allocate event"); 626 627 e->se_type = event; 628 e->se_sock = sock; 629 s = splhigh(); 630 SIMPLEQ_INSERT_TAIL(&sc->events, e, se_q); 631 splx(s); 632 wakeup(&sc->events); 633 } 634 635 /* 636 * Softinterrupt called to invoke the real driver interrupt handler. 637 */ 638 static void 639 stp4020_intr_dispatch(arg) 640 void *arg; 641 { 642 struct stp4020_socket *h = arg; 643 int s; 644 645 /* invoke driver handler */ 646 h->intrhandler(h->intrarg); 647 648 /* enable SBUS interrupts for pcmcia interrupts again */ 649 s = splhigh(); 650 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, h->int_enable); 651 splx(s); 652 } 653 654 int 655 stp4020_intr(arg) 656 void *arg; 657 { 658 struct stp4020_softc *sc = arg; 659 int i, s, r = 0, cd_change = 0; 660 661 662 /* protect hardware access by splhigh against softint */ 663 s = splhigh(); 664 665 /* 666 * Check each socket for pending requests. 667 */ 668 for (i = 0 ; i < STP4020_NSOCK; i++) { 669 struct stp4020_socket *h; 670 int v; 671 672 h = &sc->sc_socks[i]; 673 674 v = stp4020_rd_sockctl(h, STP4020_ISR0_IDX); 675 676 /* Ack all interrupts at once. */ 677 stp4020_wr_sockctl(h, STP4020_ISR0_IDX, v); 678 679 #ifdef STP4020_DEBUG 680 if (stp4020_debug != 0) { 681 char bits[64]; 682 bitmask_snprintf(v, STP4020_ISR0_IOBITS, 683 bits, sizeof(bits)); 684 printf("stp4020_statintr: ISR0=%s\n", bits); 685 } 686 #endif 687 688 if ((v & STP4020_ISR0_CDCHG) != 0) { 689 /* 690 * Card status change detect 691 */ 692 cd_change = 1; 693 r = 1; 694 if ((v & (STP4020_ISR0_CD1ST|STP4020_ISR0_CD2ST)) == (STP4020_ISR0_CD1ST|STP4020_ISR0_CD2ST)){ 695 if ((h->flags & STP4020_SOCKET_BUSY) == 0) { 696 stp4020_queue_event(sc, i, 697 STP4020_EVENT_INSERTION); 698 h->flags |= STP4020_SOCKET_BUSY; 699 } 700 } 701 if ((v & (STP4020_ISR0_CD1ST|STP4020_ISR0_CD2ST)) == 0){ 702 if ((h->flags & STP4020_SOCKET_BUSY) != 0) { 703 stp4020_queue_event(sc, i, 704 STP4020_EVENT_REMOVAL); 705 h->flags &= ~STP4020_SOCKET_BUSY; 706 } 707 } 708 } 709 710 if ((v & STP4020_ISR0_IOINT) != 0) { 711 /* we can not deny this is ours, no matter what the 712 card driver says. */ 713 r = 1; 714 715 /* It's a card interrupt */ 716 if ((h->flags & STP4020_SOCKET_BUSY) == 0) { 717 printf("stp4020[%d]: spurious interrupt?\n", 718 h->sock); 719 continue; 720 } 721 722 /* 723 * Schedule softint to invoke driver interrupt 724 * handler 725 */ 726 if (h->softint != NULL) 727 softint_schedule(h->softint); 728 /* 729 * Disable this sbus interrupt, until the soft-int 730 * handler had a chance to run 731 */ 732 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, h->int_disable); 733 } 734 735 /* informational messages */ 736 if ((v & STP4020_ISR0_BVD1CHG) != 0) { 737 /* ignore if this is caused by insert or removal */ 738 if (!cd_change) 739 printf("stp4020[%d]: Battery change 1\n", h->sock); 740 r = 1; 741 } 742 743 if ((v & STP4020_ISR0_BVD2CHG) != 0) { 744 /* ignore if this is caused by insert or removal */ 745 if (!cd_change) 746 printf("stp4020[%d]: Battery change 2\n", h->sock); 747 r = 1; 748 } 749 750 if ((v & STP4020_ISR0_SCINT) != 0) { 751 DPRINTF(("stp4020[%d]: status change\n", h->sock)); 752 r = 1; 753 } 754 755 if ((v & STP4020_ISR0_RDYCHG) != 0) { 756 DPRINTF(("stp4020[%d]: Ready/Busy change\n", h->sock)); 757 r = 1; 758 } 759 760 if ((v & STP4020_ISR0_WPCHG) != 0) { 761 DPRINTF(("stp4020[%d]: Write protect change\n", h->sock)); 762 r = 1; 763 } 764 765 if ((v & STP4020_ISR0_PCTO) != 0) { 766 DPRINTF(("stp4020[%d]: Card access timeout\n", h->sock)); 767 r = 1; 768 } 769 770 if ((v & ~STP4020_ISR0_LIVE) && r == 0) 771 printf("stp4020[%d]: unhandled interrupt: 0x%x\n", h->sock, v); 772 773 } 774 splx(s); 775 776 return (r); 777 } 778 779 /* 780 * The function gets the sbus speed and a access time and calculates 781 * values for the CMDLNG and CMDDLAY registers. 782 */ 783 static void 784 stp4020_calc_speed(int bus_speed, int ns, int *length, int *cmd_delay) 785 { 786 int result; 787 788 if (ns < STP4020_MEM_SPEED_MIN) 789 ns = STP4020_MEM_SPEED_MIN; 790 else if (ns > STP4020_MEM_SPEED_MAX) 791 ns = STP4020_MEM_SPEED_MAX; 792 result = ns*(bus_speed/1000); 793 if (result % 1000000) 794 result = result/1000000 + 1; 795 else 796 result /= 1000000; 797 *length = result; 798 799 /* the sbus frequency range is limited, so we can keep this simple */ 800 *cmd_delay = ns <= STP4020_MEM_SPEED_MIN? 1 : 2; 801 } 802 803 static void 804 stp4020_map_window(struct stp4020_socket *h, int win, int speed) 805 { 806 int v, length, cmd_delay; 807 808 /* 809 * According to the PC Card standard 300ns access timing should be 810 * used for attribute memory access. Our pcmcia framework does not 811 * seem to propagate timing information, so we use that 812 * everywhere. 813 */ 814 stp4020_calc_speed(speed, (win==STP_WIN_ATTR)? 300 : 100, &length, &cmd_delay); 815 816 /* 817 * Fill in the Address Space Select and Base Address 818 * fields of this windows control register 0. 819 */ 820 v = ((cmd_delay << STP4020_WCR0_CMDDLY_S)&STP4020_WCR0_CMDDLY_M) 821 | ((length << STP4020_WCR0_CMDLNG_S)&STP4020_WCR0_CMDLNG_M); 822 switch (win) { 823 case STP_WIN_ATTR: 824 v |= STP4020_WCR0_ASPSEL_AM; 825 break; 826 case STP_WIN_MEM: 827 v |= STP4020_WCR0_ASPSEL_CM; 828 break; 829 case STP_WIN_IO: 830 v |= STP4020_WCR0_ASPSEL_IO; 831 break; 832 } 833 v |= (STP4020_ADDR2PAGE(0) & STP4020_WCR0_BASE_M); 834 stp4020_wr_winctl(h, win, STP4020_WCR0_IDX, v); 835 stp4020_wr_winctl(h, win, STP4020_WCR1_IDX, 1<<STP4020_WCR1_WAITREQ_S); 836 } 837 838 int 839 stp4020_chip_mem_alloc(pch, size, pcmhp) 840 pcmcia_chipset_handle_t pch; 841 bus_size_t size; 842 struct pcmcia_mem_handle *pcmhp; 843 { 844 struct stp4020_socket *h = (struct stp4020_socket *)pch; 845 846 /* we can not do much here, defere work to _mem_map */ 847 pcmhp->memt = h->pcmciat; 848 pcmhp->size = size; 849 pcmhp->addr = 0; 850 pcmhp->mhandle = 0; 851 pcmhp->realsize = size; 852 853 return (0); 854 } 855 856 void 857 stp4020_chip_mem_free(pch, pcmhp) 858 pcmcia_chipset_handle_t pch; 859 struct pcmcia_mem_handle *pcmhp; 860 { 861 } 862 863 int 864 stp4020_chip_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 865 pcmcia_chipset_handle_t pch; 866 int kind; 867 bus_addr_t card_addr; 868 bus_size_t size; 869 struct pcmcia_mem_handle *pcmhp; 870 bus_size_t *offsetp; 871 int *windowp; 872 { 873 struct stp4020_socket *h = (struct stp4020_socket *)pch; 874 int win = (kind&PCMCIA_MEM_ATTR)? STP_WIN_ATTR : STP_WIN_MEM; 875 876 pcmhp->memt = h->pcmciat; 877 bus_space_subregion(h->pcmciat, h->windows[win].winaddr, card_addr, size, &pcmhp->memh); 878 #ifdef SUN4U 879 if ((u_int8_t)pcmhp->memh._asi == ASI_PHYS_NON_CACHED) 880 pcmhp->memh._asi = ASI_PHYS_NON_CACHED_LITTLE; 881 else if ((u_int8_t)pcmhp->memh._asi == ASI_PRIMARY) 882 pcmhp->memh._asi = ASI_PRIMARY_LITTLE; 883 #endif 884 pcmhp->size = size; 885 pcmhp->realsize = STP4020_WINDOW_SIZE - card_addr; 886 *offsetp = 0; 887 *windowp = 0; 888 889 return (0); 890 } 891 892 void 893 stp4020_chip_mem_unmap(pch, win) 894 pcmcia_chipset_handle_t pch; 895 int win; 896 { 897 } 898 899 int 900 stp4020_chip_io_alloc(pch, start, size, align, pcihp) 901 pcmcia_chipset_handle_t pch; 902 bus_addr_t start; 903 bus_size_t size; 904 bus_size_t align; 905 struct pcmcia_io_handle *pcihp; 906 { 907 struct stp4020_socket *h = (struct stp4020_socket *)pch; 908 909 pcihp->iot = h->pcmciat; 910 pcihp->ioh = h->windows[STP_WIN_IO].winaddr; 911 return 0; 912 } 913 914 void 915 stp4020_chip_io_free(pch, pcihp) 916 pcmcia_chipset_handle_t pch; 917 struct pcmcia_io_handle *pcihp; 918 { 919 } 920 921 int 922 stp4020_chip_io_map(pch, width, offset, size, pcihp, windowp) 923 pcmcia_chipset_handle_t pch; 924 int width; 925 bus_addr_t offset; 926 bus_size_t size; 927 struct pcmcia_io_handle *pcihp; 928 int *windowp; 929 { 930 struct stp4020_socket *h = (struct stp4020_socket *)pch; 931 932 pcihp->iot = h->pcmciat; 933 bus_space_subregion(h->pcmciat, h->windows[STP_WIN_IO].winaddr, offset, size, &pcihp->ioh); 934 #ifdef SUN4U 935 if ((u_int8_t)pcihp->ioh._asi == ASI_PHYS_NON_CACHED) 936 pcihp->ioh._asi = ASI_PHYS_NON_CACHED_LITTLE; 937 else if ((u_int8_t)pcihp->ioh._asi == ASI_PRIMARY) 938 pcihp->ioh._asi = ASI_PRIMARY_LITTLE; 939 #endif 940 *windowp = 0; 941 return 0; 942 } 943 944 void 945 stp4020_chip_io_unmap(pch, win) 946 pcmcia_chipset_handle_t pch; 947 int win; 948 { 949 } 950 951 void 952 stp4020_chip_socket_enable(pch) 953 pcmcia_chipset_handle_t pch; 954 { 955 struct stp4020_socket *h = (struct stp4020_socket *)pch; 956 int i, v; 957 958 /* this bit is mostly stolen from pcic_attach_card */ 959 960 /* Power down the socket to reset it, clear the card reset pin */ 961 stp4020_wr_sockctl(h, STP4020_ICR1_IDX, 0); 962 963 /* 964 * wait 300ms until power fails (Tpf). Then, wait 100ms since 965 * we are changing Vcc (Toff). 966 */ 967 stp4020_delay(h->sc, 300 + 100); 968 969 /* Power up the socket */ 970 v = STP4020_ICR1_MSTPWR; 971 stp4020_wr_sockctl(h, STP4020_ICR1_IDX, v); 972 973 /* 974 * wait 100ms until power raise (Tpr) and 20ms to become 975 * stable (Tsu(Vcc)). 976 */ 977 stp4020_delay(h->sc, 100 + 20); 978 979 v |= STP4020_ICR1_PCIFOE|STP4020_ICR1_VPP1_VCC; 980 stp4020_wr_sockctl(h, STP4020_ICR1_IDX, v); 981 982 /* 983 * hold RESET at least 10us. 984 */ 985 delay(10); 986 987 /* Clear reset flag, set to memory mode */ 988 v = stp4020_rd_sockctl(h, STP4020_ICR0_IDX); 989 v &= ~(STP4020_ICR0_IOIE | STP4020_ICR0_IOILVL | STP4020_ICR0_IFTYPE | 990 STP4020_ICR0_SPKREN); 991 v &= ~STP4020_ICR0_RESET; 992 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, v); 993 994 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 995 stp4020_delay(h->sc, 20); 996 997 /* Wait for the chip to finish initializing (5 seconds max) */ 998 for (i = 10000; i > 0; i--) { 999 v = stp4020_rd_sockctl(h, STP4020_ISR0_IDX); 1000 if ((v & STP4020_ISR0_RDYST) != 0) 1001 break; 1002 delay(500); 1003 } 1004 if (i <= 0) { 1005 char bits[64]; 1006 bitmask_snprintf(stp4020_rd_sockctl(h, STP4020_ISR0_IDX), 1007 STP4020_ISR0_IOBITS, bits, sizeof(bits)); 1008 printf("stp4020_chip_socket_enable: not ready: status %s\n", 1009 bits); 1010 return; 1011 } 1012 } 1013 1014 void 1015 stp4020_chip_socket_settype(pch, type) 1016 pcmcia_chipset_handle_t pch; 1017 int type; 1018 { 1019 struct stp4020_socket *h = (struct stp4020_socket *)pch; 1020 int v; 1021 1022 /* 1023 * Check the card type. 1024 * Enable socket I/O interrupts for IO cards. 1025 */ 1026 v = stp4020_rd_sockctl(h, STP4020_ICR0_IDX); 1027 v &= ~(STP4020_ICR0_IOIE | STP4020_ICR0_IOILVL | STP4020_ICR0_IFTYPE | 1028 STP4020_ICR0_SPKREN); 1029 if (type == PCMCIA_IFTYPE_IO) { 1030 v |= STP4020_ICR0_IFTYPE_IO|STP4020_ICR0_IOIE 1031 |STP4020_ICR0_SPKREN; 1032 v |= h->sbus_intno ? STP4020_ICR0_IOILVL_SB1 1033 : STP4020_ICR0_IOILVL_SB0; 1034 h->int_enable = v; 1035 h->int_disable = v & ~STP4020_ICR0_IOIE; 1036 DPRINTF(("%s: configuring card for IO useage\n", h->sc->sc_dev.dv_xname)); 1037 } else { 1038 v |= STP4020_ICR0_IFTYPE_MEM; 1039 h->int_enable = h->int_disable = v; 1040 DPRINTF(("%s: configuring card for IO useage\n", h->sc->sc_dev.dv_xname)); 1041 DPRINTF(("%s: configuring card for MEM ONLY useage\n", h->sc->sc_dev.dv_xname)); 1042 } 1043 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, v); 1044 } 1045 1046 void 1047 stp4020_chip_socket_disable(pch) 1048 pcmcia_chipset_handle_t pch; 1049 { 1050 struct stp4020_socket *h = (struct stp4020_socket *)pch; 1051 int v; 1052 1053 /* 1054 * Disable socket I/O interrupts. 1055 */ 1056 v = stp4020_rd_sockctl(h, STP4020_ICR0_IDX); 1057 v &= ~(STP4020_ICR0_IOIE | STP4020_ICR0_IOILVL | STP4020_ICR0_IFTYPE | 1058 STP4020_ICR0_SPKREN); 1059 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, v); 1060 1061 /* Power down the socket */ 1062 stp4020_wr_sockctl(h, STP4020_ICR1_IDX, 0); 1063 1064 /* 1065 * wait 300ms until power fails (Tpf). 1066 */ 1067 stp4020_delay(h->sc, 300); 1068 } 1069 1070 void * 1071 stp4020_chip_intr_establish(pch, pf, ipl, handler, arg) 1072 pcmcia_chipset_handle_t pch; 1073 struct pcmcia_function *pf; 1074 int ipl; 1075 int (*handler)(void *); 1076 void *arg; 1077 { 1078 struct stp4020_socket *h = (struct stp4020_socket *)pch; 1079 1080 /* only one interrupt handler per slot */ 1081 if (h->intrhandler != NULL) return NULL; 1082 1083 h->intrhandler = handler; 1084 h->intrarg = arg; 1085 h->softint = softint_establish(ipl, stp4020_intr_dispatch, h); 1086 return h->softint; 1087 } 1088 1089 void 1090 stp4020_chip_intr_disestablish(pch, ih) 1091 pcmcia_chipset_handle_t pch; 1092 void *ih; 1093 { 1094 struct stp4020_socket *h = (struct stp4020_socket *)pch; 1095 1096 h->intrhandler = NULL; 1097 h->intrarg = NULL; 1098 if (h->softint) { 1099 softint_disestablish(h->softint); 1100 h->softint = NULL; 1101 } 1102 } 1103 1104 /* 1105 * Delay and possibly yield CPU. 1106 * XXX - assumes a context 1107 */ 1108 void 1109 stp4020_delay(sc, ms) 1110 struct stp4020_softc *sc; 1111 unsigned int ms; 1112 { 1113 unsigned int ticks = mstohz(ms); 1114 1115 if (cold || ticks == 0) { 1116 delay(ms); 1117 return; 1118 } 1119 1120 #ifdef DIAGNOSTIC 1121 if (ticks > 60*hz) 1122 panic("stp4020: preposterous delay: %u", ticks); 1123 #endif 1124 tsleep(sc, 0, "nelldel", ticks); 1125 } 1126 1127 #ifdef STP4020_DEBUG 1128 void 1129 stp4020_dump_regs(h) 1130 struct stp4020_socket *h; 1131 { 1132 char bits[64]; 1133 /* 1134 * Dump control and status registers. 1135 */ 1136 printf("socket[%d] registers:\n", h->sock); 1137 bitmask_snprintf(stp4020_rd_sockctl(h, STP4020_ICR0_IDX), 1138 STP4020_ICR0_BITS, bits, sizeof(bits)); 1139 printf("\tICR0=%s\n", bits); 1140 1141 bitmask_snprintf(stp4020_rd_sockctl(h, STP4020_ICR1_IDX), 1142 STP4020_ICR1_BITS, bits, sizeof(bits)); 1143 printf("\tICR1=%s\n", bits); 1144 1145 bitmask_snprintf(stp4020_rd_sockctl(h, STP4020_ISR0_IDX), 1146 STP4020_ISR0_IOBITS, bits, sizeof(bits)); 1147 printf("\tISR0=%s\n", bits); 1148 1149 bitmask_snprintf(stp4020_rd_sockctl(h, STP4020_ISR1_IDX), 1150 STP4020_ISR1_BITS, bits, sizeof(bits)); 1151 printf("\tISR1=%s\n", bits); 1152 } 1153 #endif /* STP4020_DEBUG */ 1154
Indexes created Mon Oct 20 11:09:49 GMT 2025