stp4020.c revision 1.50
1 /* $NetBSD: stp4020.c,v 1.50 2007/07/09 21:01:21 ad Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * STP4020: SBus/PCMCIA bridge supporting two Type-3 PCMCIA cards. 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: stp4020.c,v 1.50 2007/07/09 21:01:21 ad Exp $"); 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/errno.h> 49 #include <sys/malloc.h> 50 #include <sys/extent.h> 51 #include <sys/proc.h> 52 #include <sys/kernel.h> 53 #include <sys/kthread.h> 54 #include <sys/device.h> 55 56 #include <dev/pcmcia/pcmciareg.h> 57 #include <dev/pcmcia/pcmciavar.h> 58 #include <dev/pcmcia/pcmciachip.h> 59 60 #include <machine/bus.h> 61 #include <machine/intr.h> 62 63 #include <dev/sbus/sbusvar.h> 64 #include <dev/sbus/stp4020reg.h> 65 66 #define STP4020_DEBUG 1 /* XXX-temp */ 67 68 /* 69 * We use the three available windows per socket in a simple, fixed 70 * arrangement. Each window maps (at full 1 MB size) one of the pcmcia 71 * spaces into sbus space. 72 */ 73 #define STP_WIN_ATTR 0 /* index of the attribute memory space window */ 74 #define STP_WIN_MEM 1 /* index of the common memory space window */ 75 #define STP_WIN_IO 2 /* index of the io space window */ 76 77 78 #if defined(STP4020_DEBUG) 79 int stp4020_debug = 0; 80 #define DPRINTF(x) do { if (stp4020_debug) printf x; } while(0) 81 #else 82 #define DPRINTF(x) 83 #endif 84 85 /* 86 * Event queue; events detected in an interrupt context go here 87 * awaiting attention from our event handling thread. 88 */ 89 struct stp4020_event { 90 SIMPLEQ_ENTRY(stp4020_event) se_q; 91 int se_type; 92 int se_sock; 93 }; 94 /* Defined event types */ 95 #define STP4020_EVENT_INSERTION 0 96 #define STP4020_EVENT_REMOVAL 1 97 98 /* 99 * Per socket data. 100 */ 101 struct stp4020_socket { 102 struct stp4020_softc *sc; /* Back link */ 103 int flags; 104 #define STP4020_SOCKET_BUSY 0x0001 105 int sock; /* Socket number (0 or 1) */ 106 int sbus_intno; /* Do we use first (0) or second (1) 107 interrupt? */ 108 int int_enable; /* ICR0 value for interrupt enabled */ 109 int int_disable; /* ICR0 value for interrupt disabled */ 110 bus_space_tag_t tag; /* socket control io */ 111 bus_space_handle_t regs; /* space */ 112 bus_space_tag_t pcmciat; /* io space for pcmcia */ 113 struct device *pcmcia; /* Associated PCMCIA device */ 114 int (*intrhandler) /* Card driver interrupt handler */ 115 (void *); 116 void *intrarg; /* Card interrupt handler argument */ 117 void *softint; /* cookie for the softintr */ 118 119 struct { 120 bus_space_handle_t winaddr;/* this window's address */ 121 } windows[STP4020_NWIN]; 122 123 }; 124 125 struct stp4020_softc { 126 struct device sc_dev; /* Base device */ 127 struct sbusdev sc_sd; /* SBus device */ 128 pcmcia_chipset_tag_t sc_pct; /* Chipset methods */ 129 130 struct lwp *event_thread; /* event handling thread */ 131 SIMPLEQ_HEAD(, stp4020_event) events; /* Pending events for thread */ 132 133 struct stp4020_socket sc_socks[STP4020_NSOCK]; 134 }; 135 136 137 static int stp4020print(void *, const char *); 138 static int stp4020match(struct device *, struct cfdata *, void *); 139 static void stp4020attach(struct device *, struct device *, void *); 140 static int stp4020_intr(void *); 141 static void stp4020_map_window(struct stp4020_socket *h, int win, int speed); 142 static void stp4020_calc_speed(int bus_speed, int ns, int *length, int *cmd_delay); 143 static void stp4020_intr_dispatch(void *arg); 144 145 CFATTACH_DECL(nell, sizeof(struct stp4020_softc), 146 stp4020match, stp4020attach, NULL, NULL); 147 148 #ifdef STP4020_DEBUG 149 static void stp4020_dump_regs(struct stp4020_socket *); 150 #endif 151 152 static int stp4020_rd_sockctl(struct stp4020_socket *, int); 153 static void stp4020_wr_sockctl(struct stp4020_socket *, int, int); 154 static int stp4020_rd_winctl(struct stp4020_socket *, int, int); 155 static void stp4020_wr_winctl(struct stp4020_socket *, int, int, int); 156 157 void stp4020_delay(struct stp4020_softc *sc, unsigned int); 158 void stp4020_attach_socket(struct stp4020_socket *, int); 159 void stp4020_event_thread(void *); 160 void stp4020_queue_event(struct stp4020_softc *, int, int); 161 162 int stp4020_chip_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 163 struct pcmcia_mem_handle *); 164 void stp4020_chip_mem_free(pcmcia_chipset_handle_t, 165 struct pcmcia_mem_handle *); 166 int stp4020_chip_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 167 bus_size_t, struct pcmcia_mem_handle *, 168 bus_size_t *, int *); 169 void stp4020_chip_mem_unmap(pcmcia_chipset_handle_t, int); 170 171 int stp4020_chip_io_alloc(pcmcia_chipset_handle_t, 172 bus_addr_t, bus_size_t, bus_size_t, 173 struct pcmcia_io_handle *); 174 void stp4020_chip_io_free(pcmcia_chipset_handle_t, 175 struct pcmcia_io_handle *); 176 int stp4020_chip_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 177 bus_size_t, struct pcmcia_io_handle *, int *); 178 void stp4020_chip_io_unmap(pcmcia_chipset_handle_t, int); 179 180 void stp4020_chip_socket_enable(pcmcia_chipset_handle_t); 181 void stp4020_chip_socket_disable(pcmcia_chipset_handle_t); 182 void stp4020_chip_socket_settype(pcmcia_chipset_handle_t, int); 183 void *stp4020_chip_intr_establish(pcmcia_chipset_handle_t, 184 struct pcmcia_function *, int, 185 int (*)(void *), void *); 186 void stp4020_chip_intr_disestablish(pcmcia_chipset_handle_t, void *); 187 188 /* Our PCMCIA chipset methods */ 189 static struct pcmcia_chip_functions stp4020_functions = { 190 stp4020_chip_mem_alloc, 191 stp4020_chip_mem_free, 192 stp4020_chip_mem_map, 193 stp4020_chip_mem_unmap, 194 195 stp4020_chip_io_alloc, 196 stp4020_chip_io_free, 197 stp4020_chip_io_map, 198 stp4020_chip_io_unmap, 199 200 stp4020_chip_intr_establish, 201 stp4020_chip_intr_disestablish, 202 203 stp4020_chip_socket_enable, 204 stp4020_chip_socket_disable, 205 stp4020_chip_socket_settype, 206 NULL 207 }; 208 209 210 static inline int 211 stp4020_rd_sockctl(h, idx) 212 struct stp4020_socket *h; 213 int idx; 214 { 215 int o = ((STP4020_SOCKREGS_SIZE * (h->sock)) + idx); 216 return (bus_space_read_2(h->tag, h->regs, o)); 217 } 218 219 static inline void 220 stp4020_wr_sockctl(h, idx, v) 221 struct stp4020_socket *h; 222 int idx; 223 int v; 224 { 225 int o = (STP4020_SOCKREGS_SIZE * (h->sock)) + idx; 226 bus_space_write_2(h->tag, h->regs, o, v); 227 } 228 229 static inline int 230 stp4020_rd_winctl(h, win, idx) 231 struct stp4020_socket *h; 232 int win; 233 int idx; 234 { 235 int o = (STP4020_SOCKREGS_SIZE * (h->sock)) + 236 (STP4020_WINREGS_SIZE * win) + idx; 237 return (bus_space_read_2(h->tag, h->regs, o)); 238 } 239 240 static inline void 241 stp4020_wr_winctl(h, win, idx, v) 242 struct stp4020_socket *h; 243 int win; 244 int idx; 245 int v; 246 { 247 int o = (STP4020_SOCKREGS_SIZE * (h->sock)) + 248 (STP4020_WINREGS_SIZE * win) + idx; 249 250 bus_space_write_2(h->tag, h->regs, o, v); 251 } 252 253 #ifndef SUN4U /* XXX - move to SBUS machdep function? */ 254 255 static u_int16_t stp4020_read_2(bus_space_tag_t, 256 bus_space_handle_t, 257 bus_size_t); 258 static u_int32_t stp4020_read_4(bus_space_tag_t, 259 bus_space_handle_t, 260 bus_size_t); 261 static u_int64_t stp4020_read_8(bus_space_tag_t, 262 bus_space_handle_t, 263 bus_size_t); 264 static void stp4020_write_2(bus_space_tag_t, 265 bus_space_handle_t, 266 bus_size_t, 267 u_int16_t); 268 static void stp4020_write_4(bus_space_tag_t, 269 bus_space_handle_t, 270 bus_size_t, 271 u_int32_t); 272 static void stp4020_write_8(bus_space_tag_t, 273 bus_space_handle_t, 274 bus_size_t, 275 u_int64_t); 276 277 static u_int16_t 278 stp4020_read_2(space, handle, offset) 279 bus_space_tag_t space; 280 bus_space_handle_t handle; 281 bus_size_t offset; 282 { 283 return (le16toh(*(volatile u_int16_t *)(handle + offset))); 284 } 285 286 static u_int32_t 287 stp4020_read_4(space, handle, offset) 288 bus_space_tag_t space; 289 bus_space_handle_t handle; 290 bus_size_t offset; 291 { 292 return (le32toh(*(volatile u_int32_t *)(handle + offset))); 293 } 294 295 static u_int64_t 296 stp4020_read_8(space, handle, offset) 297 bus_space_tag_t space; 298 bus_space_handle_t handle; 299 bus_size_t offset; 300 { 301 return (le64toh(*(volatile u_int64_t *)(handle + offset))); 302 } 303 304 static void 305 stp4020_write_2(space, handle, offset, value) 306 bus_space_tag_t space; 307 bus_space_handle_t handle; 308 bus_size_t offset; 309 u_int16_t value; 310 { 311 (*(volatile u_int16_t *)(handle + offset)) = htole16(value); 312 } 313 314 static void 315 stp4020_write_4(space, handle, offset, value) 316 bus_space_tag_t space; 317 bus_space_handle_t handle; 318 bus_size_t offset; 319 u_int32_t value; 320 { 321 (*(volatile u_int32_t *)(handle + offset)) = htole32(value); 322 } 323 324 static void 325 stp4020_write_8(space, handle, offset, value) 326 bus_space_tag_t space; 327 bus_space_handle_t handle; 328 bus_size_t offset; 329 u_int64_t value; 330 { 331 (*(volatile u_int64_t *)(handle + offset)) = htole64(value); 332 } 333 #endif /* SUN4U */ 334 335 int 336 stp4020print(aux, busname) 337 void *aux; 338 const char *busname; 339 { 340 struct pcmciabus_attach_args *paa = aux; 341 struct stp4020_socket *h = paa->pch; 342 343 aprint_normal(" socket %d", h->sock); 344 return (UNCONF); 345 } 346 347 int 348 stp4020match(parent, cf, aux) 349 struct device *parent; 350 struct cfdata *cf; 351 void *aux; 352 { 353 struct sbus_attach_args *sa = aux; 354 355 return (strcmp("SUNW,pcmcia", sa->sa_name) == 0); 356 } 357 358 /* 359 * Attach all the sub-devices we can find 360 */ 361 void 362 stp4020attach(parent, self, aux) 363 struct device *parent, *self; 364 void *aux; 365 { 366 struct sbus_attach_args *sa = aux; 367 struct stp4020_softc *sc = (void *)self; 368 bus_space_tag_t tag; 369 int rev; 370 int i, sbus_intno; 371 bus_space_handle_t bh; 372 373 /* lsb of our config flags decides which interrupt we use */ 374 sbus_intno = device_cfdata(&sc->sc_dev)->cf_flags & 1; 375 376 /* Transfer bus tags */ 377 #ifdef SUN4U 378 tag = sa->sa_bustag; 379 #else 380 tag = bus_space_tag_alloc(sa->sa_bustag, sc); 381 if (tag == NULL) { 382 printf("%s: attach: out of memory\n", self->dv_xname); 383 return; 384 } 385 tag->sparc_read_2 = stp4020_read_2; 386 tag->sparc_read_4 = stp4020_read_4; 387 tag->sparc_read_8 = stp4020_read_8; 388 tag->sparc_write_2 = stp4020_write_2; 389 tag->sparc_write_4 = stp4020_write_4; 390 tag->sparc_write_8 = stp4020_write_8; 391 #endif /* SUN4U */ 392 393 /* Set up per-socket static initialization */ 394 sc->sc_socks[0].sc = sc->sc_socks[1].sc = sc; 395 sc->sc_socks[0].tag = sc->sc_socks[1].tag = sa->sa_bustag; 396 /* 397 * XXX we rely on "tag" accepting the same handle-domain 398 * as sa->sa_bustag. 399 */ 400 sc->sc_socks[0].pcmciat = sc->sc_socks[1].pcmciat = tag; 401 sc->sc_socks[0].sbus_intno = 402 sc->sc_socks[1].sbus_intno = sbus_intno; 403 404 if (sa->sa_nreg < 8) { 405 printf("%s: only %d register sets\n", 406 self->dv_xname, sa->sa_nreg); 407 return; 408 } 409 410 if (sa->sa_nintr != 2) { 411 printf("%s: expect 2 interrupt Sbus levels; got %d\n", 412 self->dv_xname, sa->sa_nintr); 413 return; 414 } 415 416 #define STP4020_BANK_PROM 0 417 #define STP4020_BANK_CTRL 4 418 for (i = 0; i < 8; i++) { 419 420 /* 421 * STP4020 Register address map: 422 * bank 0: Forth PROM 423 * banks 1-3: socket 0, windows 0-2 424 * bank 4: control registers 425 * banks 5-7: socket 1, windows 0-2 426 */ 427 428 if (i == STP4020_BANK_PROM) 429 /* Skip the PROM */ 430 continue; 431 432 if (sbus_bus_map(sa->sa_bustag, 433 sa->sa_reg[i].oa_space, 434 sa->sa_reg[i].oa_base, 435 sa->sa_reg[i].oa_size, 436 0, &bh) != 0) { 437 printf("%s: attach: cannot map registers\n", 438 self->dv_xname); 439 return; 440 } 441 442 if (i == STP4020_BANK_CTRL) { 443 /* 444 * Copy tag and handle to both socket structures 445 * for easy access in control/status IO functions. 446 */ 447 sc->sc_socks[0].regs = sc->sc_socks[1].regs = bh; 448 } else if (i < STP4020_BANK_CTRL) { 449 /* banks 1-3 */ 450 sc->sc_socks[0].windows[i-1].winaddr = bh; 451 } else { 452 /* banks 5-7 */ 453 sc->sc_socks[1].windows[i-5].winaddr = bh; 454 } 455 } 456 457 sbus_establish(&sc->sc_sd, &sc->sc_dev); 458 459 /* We only use one interrupt level. */ 460 if (sa->sa_nintr > sbus_intno) { 461 bus_intr_establish(sa->sa_bustag, 462 sa->sa_intr[sbus_intno].oi_pri, 463 IPL_NONE, stp4020_intr, sc); 464 } 465 466 rev = stp4020_rd_sockctl(&sc->sc_socks[0], STP4020_ISR1_IDX) & 467 STP4020_ISR1_REV_M; 468 printf(": rev %x\n", rev); 469 470 sc->sc_pct = (pcmcia_chipset_tag_t)&stp4020_functions; 471 472 SIMPLEQ_INIT(&sc->events); 473 474 for (i = 0; i < STP4020_NSOCK; i++) { 475 struct stp4020_socket *h = &sc->sc_socks[i]; 476 h->sock = i; 477 h->sc = sc; 478 #ifdef STP4020_DEBUG 479 if (stp4020_debug) 480 stp4020_dump_regs(h); 481 #endif 482 stp4020_attach_socket(h, sa->sa_frequency); 483 } 484 485 /* 486 * Arrange that a kernel thread be created to handle 487 * insert/removal events. 488 */ 489 if (kthread_create(PRI_NONE, 0, NULL, stp4020_event_thread, sc, 490 &sc->event_thread, "%s", self->dv_xname)) { 491 panic("%s: unable to create event thread", self->dv_xname); 492 } 493 } 494 495 void 496 stp4020_attach_socket(h, speed) 497 struct stp4020_socket *h; 498 int speed; 499 { 500 struct pcmciabus_attach_args paa; 501 int v; 502 503 /* no interrupt handlers yet */ 504 h->intrhandler = NULL; 505 h->intrarg = NULL; 506 h->softint = NULL; 507 h->int_enable = 0; 508 h->int_disable = 0; 509 510 /* Map all three windows */ 511 stp4020_map_window(h, STP_WIN_ATTR, speed); 512 stp4020_map_window(h, STP_WIN_MEM, speed); 513 stp4020_map_window(h, STP_WIN_IO, speed); 514 515 /* Configure one pcmcia device per socket */ 516 paa.paa_busname = "pcmcia"; 517 paa.pct = (pcmcia_chipset_tag_t)h->sc->sc_pct; 518 paa.pch = (pcmcia_chipset_handle_t)h; 519 paa.iobase = 0; 520 paa.iosize = STP4020_WINDOW_SIZE; 521 522 h->pcmcia = config_found(&h->sc->sc_dev, &paa, stp4020print); 523 524 if (h->pcmcia == NULL) 525 return; 526 527 /* 528 * There's actually a pcmcia bus attached; initialize the slot. 529 */ 530 531 /* 532 * Clear things up before we enable status change interrupts. 533 * This seems to not be fully initialized by the PROM. 534 */ 535 stp4020_wr_sockctl(h, STP4020_ICR1_IDX, 0); 536 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, 0); 537 stp4020_wr_sockctl(h, STP4020_ISR1_IDX, 0x3fff); 538 stp4020_wr_sockctl(h, STP4020_ISR0_IDX, 0x3fff); 539 540 /* 541 * Enable socket status change interrupts. 542 * We only use one common interrupt for status change 543 * and IO, to avoid locking issues. 544 */ 545 v = STP4020_ICR0_ALL_STATUS_IE 546 | (h->sbus_intno ? STP4020_ICR0_SCILVL_SB1 547 : STP4020_ICR0_SCILVL_SB0); 548 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, v); 549 550 /* Get live status bits from ISR0 and clear pending interrupts */ 551 v = stp4020_rd_sockctl(h, STP4020_ISR0_IDX); 552 stp4020_wr_sockctl(h, STP4020_ISR0_IDX, v); 553 554 if ((v & (STP4020_ISR0_CD1ST|STP4020_ISR0_CD2ST)) == 0) 555 return; 556 557 pcmcia_card_attach(h->pcmcia); 558 h->flags |= STP4020_SOCKET_BUSY; 559 } 560 561 /* 562 * The actual event handling thread. 563 */ 564 void 565 stp4020_event_thread(arg) 566 void *arg; 567 { 568 struct stp4020_softc *sc = arg; 569 struct stp4020_event *e; 570 int s; 571 572 while (1) { 573 struct stp4020_socket *h; 574 int n; 575 576 s = splhigh(); 577 if ((e = SIMPLEQ_FIRST(&sc->events)) == NULL) { 578 splx(s); 579 (void)tsleep(&sc->events, PWAIT, "nellevt", 0); 580 continue; 581 } 582 SIMPLEQ_REMOVE_HEAD(&sc->events, se_q); 583 splx(s); 584 585 n = e->se_sock; 586 if (n < 0 || n >= STP4020_NSOCK) 587 panic("stp4020_event_thread: wayward socket number %d", 588 n); 589 590 h = &sc->sc_socks[n]; 591 switch (e->se_type) { 592 case STP4020_EVENT_INSERTION: 593 pcmcia_card_attach(h->pcmcia); 594 break; 595 case STP4020_EVENT_REMOVAL: 596 pcmcia_card_detach(h->pcmcia, DETACH_FORCE); 597 break; 598 default: 599 panic("stp4020_event_thread: unknown event type %d", 600 e->se_type); 601 } 602 free(e, M_TEMP); 603 } 604 } 605 606 void 607 stp4020_queue_event(sc, sock, event) 608 struct stp4020_softc *sc; 609 int sock, event; 610 { 611 struct stp4020_event *e; 612 int s; 613 614 e = malloc(sizeof(*e), M_TEMP, M_NOWAIT); 615 if (e == NULL) 616 panic("stp4020_queue_event: can't allocate event"); 617 618 e->se_type = event; 619 e->se_sock = sock; 620 s = splhigh(); 621 SIMPLEQ_INSERT_TAIL(&sc->events, e, se_q); 622 splx(s); 623 wakeup(&sc->events); 624 } 625 626 /* 627 * Softinterrupt called to invoke the real driver interrupt handler. 628 */ 629 static void 630 stp4020_intr_dispatch(arg) 631 void *arg; 632 { 633 struct stp4020_socket *h = arg; 634 int s; 635 636 /* invoke driver handler */ 637 h->intrhandler(h->intrarg); 638 639 /* enable SBUS interrupts for pcmcia interrupts again */ 640 s = splhigh(); 641 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, h->int_enable); 642 splx(s); 643 } 644 645 int 646 stp4020_intr(arg) 647 void *arg; 648 { 649 struct stp4020_softc *sc = arg; 650 int i, s, r = 0, cd_change = 0; 651 652 653 /* protect hardware access by splhigh against softint */ 654 s = splhigh(); 655 656 /* 657 * Check each socket for pending requests. 658 */ 659 for (i = 0 ; i < STP4020_NSOCK; i++) { 660 struct stp4020_socket *h; 661 int v; 662 663 h = &sc->sc_socks[i]; 664 665 v = stp4020_rd_sockctl(h, STP4020_ISR0_IDX); 666 667 /* Ack all interrupts at once. */ 668 stp4020_wr_sockctl(h, STP4020_ISR0_IDX, v); 669 670 #ifdef STP4020_DEBUG 671 if (stp4020_debug != 0) { 672 char bits[64]; 673 bitmask_snprintf(v, STP4020_ISR0_IOBITS, 674 bits, sizeof(bits)); 675 printf("stp4020_statintr: ISR0=%s\n", bits); 676 } 677 #endif 678 679 if ((v & STP4020_ISR0_CDCHG) != 0) { 680 /* 681 * Card status change detect 682 */ 683 cd_change = 1; 684 r = 1; 685 if ((v & (STP4020_ISR0_CD1ST|STP4020_ISR0_CD2ST)) == (STP4020_ISR0_CD1ST|STP4020_ISR0_CD2ST)){ 686 if ((h->flags & STP4020_SOCKET_BUSY) == 0) { 687 stp4020_queue_event(sc, i, 688 STP4020_EVENT_INSERTION); 689 h->flags |= STP4020_SOCKET_BUSY; 690 } 691 } 692 if ((v & (STP4020_ISR0_CD1ST|STP4020_ISR0_CD2ST)) == 0){ 693 if ((h->flags & STP4020_SOCKET_BUSY) != 0) { 694 stp4020_queue_event(sc, i, 695 STP4020_EVENT_REMOVAL); 696 h->flags &= ~STP4020_SOCKET_BUSY; 697 } 698 } 699 } 700 701 if ((v & STP4020_ISR0_IOINT) != 0) { 702 /* we can not deny this is ours, no matter what the 703 card driver says. */ 704 r = 1; 705 706 /* It's a card interrupt */ 707 if ((h->flags & STP4020_SOCKET_BUSY) == 0) { 708 printf("stp4020[%d]: spurious interrupt?\n", 709 h->sock); 710 continue; 711 } 712 713 /* 714 * Schedule softint to invoke driver interrupt 715 * handler 716 */ 717 if (h->softint != NULL) 718 softintr_schedule(h->softint); 719 /* 720 * Disable this sbus interrupt, until the soft-int 721 * handler had a chance to run 722 */ 723 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, h->int_disable); 724 } 725 726 /* informational messages */ 727 if ((v & STP4020_ISR0_BVD1CHG) != 0) { 728 /* ignore if this is caused by insert or removal */ 729 if (!cd_change) 730 printf("stp4020[%d]: Battery change 1\n", h->sock); 731 r = 1; 732 } 733 734 if ((v & STP4020_ISR0_BVD2CHG) != 0) { 735 /* ignore if this is caused by insert or removal */ 736 if (!cd_change) 737 printf("stp4020[%d]: Battery change 2\n", h->sock); 738 r = 1; 739 } 740 741 if ((v & STP4020_ISR0_SCINT) != 0) { 742 DPRINTF(("stp4020[%d]: status change\n", h->sock)); 743 r = 1; 744 } 745 746 if ((v & STP4020_ISR0_RDYCHG) != 0) { 747 DPRINTF(("stp4020[%d]: Ready/Busy change\n", h->sock)); 748 r = 1; 749 } 750 751 if ((v & STP4020_ISR0_WPCHG) != 0) { 752 DPRINTF(("stp4020[%d]: Write protect change\n", h->sock)); 753 r = 1; 754 } 755 756 if ((v & STP4020_ISR0_PCTO) != 0) { 757 DPRINTF(("stp4020[%d]: Card access timeout\n", h->sock)); 758 r = 1; 759 } 760 761 if ((v & ~STP4020_ISR0_LIVE) && r == 0) 762 printf("stp4020[%d]: unhandled interrupt: 0x%x\n", h->sock, v); 763 764 } 765 splx(s); 766 767 return (r); 768 } 769 770 /* 771 * The function gets the sbus speed and a access time and calculates 772 * values for the CMDLNG and CMDDLAY registers. 773 */ 774 static void 775 stp4020_calc_speed(int bus_speed, int ns, int *length, int *cmd_delay) 776 { 777 int result; 778 779 if (ns < STP4020_MEM_SPEED_MIN) 780 ns = STP4020_MEM_SPEED_MIN; 781 else if (ns > STP4020_MEM_SPEED_MAX) 782 ns = STP4020_MEM_SPEED_MAX; 783 result = ns*(bus_speed/1000); 784 if (result % 1000000) 785 result = result/1000000 + 1; 786 else 787 result /= 1000000; 788 *length = result; 789 790 /* the sbus frequency range is limited, so we can keep this simple */ 791 *cmd_delay = ns <= STP4020_MEM_SPEED_MIN? 1 : 2; 792 } 793 794 static void 795 stp4020_map_window(struct stp4020_socket *h, int win, int speed) 796 { 797 int v, length, cmd_delay; 798 799 /* 800 * According to the PC Card standard 300ns access timing should be 801 * used for attribute memory access. Our pcmcia framework does not 802 * seem to propagate timing information, so we use that 803 * everywhere. 804 */ 805 stp4020_calc_speed(speed, (win==STP_WIN_ATTR)? 300 : 100, &length, &cmd_delay); 806 807 /* 808 * Fill in the Address Space Select and Base Address 809 * fields of this windows control register 0. 810 */ 811 v = ((cmd_delay << STP4020_WCR0_CMDDLY_S)&STP4020_WCR0_CMDDLY_M) 812 | ((length << STP4020_WCR0_CMDLNG_S)&STP4020_WCR0_CMDLNG_M); 813 switch (win) { 814 case STP_WIN_ATTR: 815 v |= STP4020_WCR0_ASPSEL_AM; 816 break; 817 case STP_WIN_MEM: 818 v |= STP4020_WCR0_ASPSEL_CM; 819 break; 820 case STP_WIN_IO: 821 v |= STP4020_WCR0_ASPSEL_IO; 822 break; 823 } 824 v |= (STP4020_ADDR2PAGE(0) & STP4020_WCR0_BASE_M); 825 stp4020_wr_winctl(h, win, STP4020_WCR0_IDX, v); 826 stp4020_wr_winctl(h, win, STP4020_WCR1_IDX, 1<<STP4020_WCR1_WAITREQ_S); 827 } 828 829 int 830 stp4020_chip_mem_alloc(pch, size, pcmhp) 831 pcmcia_chipset_handle_t pch; 832 bus_size_t size; 833 struct pcmcia_mem_handle *pcmhp; 834 { 835 struct stp4020_socket *h = (struct stp4020_socket *)pch; 836 837 /* we can not do much here, defere work to _mem_map */ 838 pcmhp->memt = h->pcmciat; 839 pcmhp->size = size; 840 pcmhp->addr = 0; 841 pcmhp->mhandle = 0; 842 pcmhp->realsize = size; 843 844 return (0); 845 } 846 847 void 848 stp4020_chip_mem_free(pch, pcmhp) 849 pcmcia_chipset_handle_t pch; 850 struct pcmcia_mem_handle *pcmhp; 851 { 852 } 853 854 int 855 stp4020_chip_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 856 pcmcia_chipset_handle_t pch; 857 int kind; 858 bus_addr_t card_addr; 859 bus_size_t size; 860 struct pcmcia_mem_handle *pcmhp; 861 bus_size_t *offsetp; 862 int *windowp; 863 { 864 struct stp4020_socket *h = (struct stp4020_socket *)pch; 865 int win = (kind&PCMCIA_MEM_ATTR)? STP_WIN_ATTR : STP_WIN_MEM; 866 867 pcmhp->memt = h->pcmciat; 868 bus_space_subregion(h->pcmciat, h->windows[win].winaddr, card_addr, size, &pcmhp->memh); 869 #ifdef SUN4U 870 if ((u_int8_t)pcmhp->memh._asi == ASI_PHYS_NON_CACHED) 871 pcmhp->memh._asi = ASI_PHYS_NON_CACHED_LITTLE; 872 else if ((u_int8_t)pcmhp->memh._asi == ASI_PRIMARY) 873 pcmhp->memh._asi = ASI_PRIMARY_LITTLE; 874 #endif 875 pcmhp->size = size; 876 pcmhp->realsize = STP4020_WINDOW_SIZE - card_addr; 877 *offsetp = 0; 878 *windowp = 0; 879 880 return (0); 881 } 882 883 void 884 stp4020_chip_mem_unmap(pch, win) 885 pcmcia_chipset_handle_t pch; 886 int win; 887 { 888 } 889 890 int 891 stp4020_chip_io_alloc(pch, start, size, align, pcihp) 892 pcmcia_chipset_handle_t pch; 893 bus_addr_t start; 894 bus_size_t size; 895 bus_size_t align; 896 struct pcmcia_io_handle *pcihp; 897 { 898 struct stp4020_socket *h = (struct stp4020_socket *)pch; 899 900 pcihp->iot = h->pcmciat; 901 pcihp->ioh = h->windows[STP_WIN_IO].winaddr; 902 return 0; 903 } 904 905 void 906 stp4020_chip_io_free(pch, pcihp) 907 pcmcia_chipset_handle_t pch; 908 struct pcmcia_io_handle *pcihp; 909 { 910 } 911 912 int 913 stp4020_chip_io_map(pch, width, offset, size, pcihp, windowp) 914 pcmcia_chipset_handle_t pch; 915 int width; 916 bus_addr_t offset; 917 bus_size_t size; 918 struct pcmcia_io_handle *pcihp; 919 int *windowp; 920 { 921 struct stp4020_socket *h = (struct stp4020_socket *)pch; 922 923 pcihp->iot = h->pcmciat; 924 bus_space_subregion(h->pcmciat, h->windows[STP_WIN_IO].winaddr, offset, size, &pcihp->ioh); 925 #ifdef SUN4U 926 if ((u_int8_t)pcihp->ioh._asi == ASI_PHYS_NON_CACHED) 927 pcihp->ioh._asi = ASI_PHYS_NON_CACHED_LITTLE; 928 else if ((u_int8_t)pcihp->ioh._asi == ASI_PRIMARY) 929 pcihp->ioh._asi = ASI_PRIMARY_LITTLE; 930 #endif 931 *windowp = 0; 932 return 0; 933 } 934 935 void 936 stp4020_chip_io_unmap(pch, win) 937 pcmcia_chipset_handle_t pch; 938 int win; 939 { 940 } 941 942 void 943 stp4020_chip_socket_enable(pch) 944 pcmcia_chipset_handle_t pch; 945 { 946 struct stp4020_socket *h = (struct stp4020_socket *)pch; 947 int i, v; 948 949 /* this bit is mostly stolen from pcic_attach_card */ 950 951 /* Power down the socket to reset it, clear the card reset pin */ 952 stp4020_wr_sockctl(h, STP4020_ICR1_IDX, 0); 953 954 /* 955 * wait 300ms until power fails (Tpf). Then, wait 100ms since 956 * we are changing Vcc (Toff). 957 */ 958 stp4020_delay(h->sc, 300 + 100); 959 960 /* Power up the socket */ 961 v = STP4020_ICR1_MSTPWR; 962 stp4020_wr_sockctl(h, STP4020_ICR1_IDX, v); 963 964 /* 965 * wait 100ms until power raise (Tpr) and 20ms to become 966 * stable (Tsu(Vcc)). 967 */ 968 stp4020_delay(h->sc, 100 + 20); 969 970 v |= STP4020_ICR1_PCIFOE|STP4020_ICR1_VPP1_VCC; 971 stp4020_wr_sockctl(h, STP4020_ICR1_IDX, v); 972 973 /* 974 * hold RESET at least 10us. 975 */ 976 delay(10); 977 978 /* Clear reset flag, set to memory mode */ 979 v = stp4020_rd_sockctl(h, STP4020_ICR0_IDX); 980 v &= ~(STP4020_ICR0_IOIE | STP4020_ICR0_IOILVL | STP4020_ICR0_IFTYPE | 981 STP4020_ICR0_SPKREN); 982 v &= ~STP4020_ICR0_RESET; 983 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, v); 984 985 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 986 stp4020_delay(h->sc, 20); 987 988 /* Wait for the chip to finish initializing (5 seconds max) */ 989 for (i = 10000; i > 0; i--) { 990 v = stp4020_rd_sockctl(h, STP4020_ISR0_IDX); 991 if ((v & STP4020_ISR0_RDYST) != 0) 992 break; 993 delay(500); 994 } 995 if (i <= 0) { 996 char bits[64]; 997 bitmask_snprintf(stp4020_rd_sockctl(h, STP4020_ISR0_IDX), 998 STP4020_ISR0_IOBITS, bits, sizeof(bits)); 999 printf("stp4020_chip_socket_enable: not ready: status %s\n", 1000 bits); 1001 return; 1002 } 1003 } 1004 1005 void 1006 stp4020_chip_socket_settype(pch, type) 1007 pcmcia_chipset_handle_t pch; 1008 int type; 1009 { 1010 struct stp4020_socket *h = (struct stp4020_socket *)pch; 1011 int v; 1012 1013 /* 1014 * Check the card type. 1015 * Enable socket I/O interrupts for IO cards. 1016 */ 1017 v = stp4020_rd_sockctl(h, STP4020_ICR0_IDX); 1018 v &= ~(STP4020_ICR0_IOIE | STP4020_ICR0_IOILVL | STP4020_ICR0_IFTYPE | 1019 STP4020_ICR0_SPKREN); 1020 if (type == PCMCIA_IFTYPE_IO) { 1021 v |= STP4020_ICR0_IFTYPE_IO|STP4020_ICR0_IOIE 1022 |STP4020_ICR0_SPKREN; 1023 v |= h->sbus_intno ? STP4020_ICR0_IOILVL_SB1 1024 : STP4020_ICR0_IOILVL_SB0; 1025 h->int_enable = v; 1026 h->int_disable = v & ~STP4020_ICR0_IOIE; 1027 DPRINTF(("%s: configuring card for IO useage\n", h->sc->sc_dev.dv_xname)); 1028 } else { 1029 v |= STP4020_ICR0_IFTYPE_MEM; 1030 h->int_enable = h->int_disable = v; 1031 DPRINTF(("%s: configuring card for IO useage\n", h->sc->sc_dev.dv_xname)); 1032 DPRINTF(("%s: configuring card for MEM ONLY useage\n", h->sc->sc_dev.dv_xname)); 1033 } 1034 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, v); 1035 } 1036 1037 void 1038 stp4020_chip_socket_disable(pch) 1039 pcmcia_chipset_handle_t pch; 1040 { 1041 struct stp4020_socket *h = (struct stp4020_socket *)pch; 1042 int v; 1043 1044 /* 1045 * Disable socket I/O interrupts. 1046 */ 1047 v = stp4020_rd_sockctl(h, STP4020_ICR0_IDX); 1048 v &= ~(STP4020_ICR0_IOIE | STP4020_ICR0_IOILVL | STP4020_ICR0_IFTYPE | 1049 STP4020_ICR0_SPKREN); 1050 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, v); 1051 1052 /* Power down the socket */ 1053 stp4020_wr_sockctl(h, STP4020_ICR1_IDX, 0); 1054 1055 /* 1056 * wait 300ms until power fails (Tpf). 1057 */ 1058 stp4020_delay(h->sc, 300); 1059 } 1060 1061 void * 1062 stp4020_chip_intr_establish(pch, pf, ipl, handler, arg) 1063 pcmcia_chipset_handle_t pch; 1064 struct pcmcia_function *pf; 1065 int ipl; 1066 int (*handler)(void *); 1067 void *arg; 1068 { 1069 struct stp4020_socket *h = (struct stp4020_socket *)pch; 1070 1071 /* only one interrupt handler per slot */ 1072 if (h->intrhandler != NULL) return NULL; 1073 1074 h->intrhandler = handler; 1075 h->intrarg = arg; 1076 h->softint = softintr_establish(ipl, stp4020_intr_dispatch, h); 1077 return h->softint; 1078 } 1079 1080 void 1081 stp4020_chip_intr_disestablish(pch, ih) 1082 pcmcia_chipset_handle_t pch; 1083 void *ih; 1084 { 1085 struct stp4020_socket *h = (struct stp4020_socket *)pch; 1086 1087 h->intrhandler = NULL; 1088 h->intrarg = NULL; 1089 if (h->softint) { 1090 softintr_disestablish(h->softint); 1091 h->softint = NULL; 1092 } 1093 } 1094 1095 /* 1096 * Delay and possibly yield CPU. 1097 * XXX - assumes a context 1098 */ 1099 void 1100 stp4020_delay(sc, ms) 1101 struct stp4020_softc *sc; 1102 unsigned int ms; 1103 { 1104 unsigned int ticks = mstohz(ms); 1105 1106 if (cold || ticks == 0) { 1107 delay(ms); 1108 return; 1109 } 1110 1111 #ifdef DIAGNOSTIC 1112 if (ticks > 60*hz) 1113 panic("stp4020: preposterous delay: %u", ticks); 1114 #endif 1115 tsleep(sc, 0, "nelldel", ticks); 1116 } 1117 1118 #ifdef STP4020_DEBUG 1119 void 1120 stp4020_dump_regs(h) 1121 struct stp4020_socket *h; 1122 { 1123 char bits[64]; 1124 /* 1125 * Dump control and status registers. 1126 */ 1127 printf("socket[%d] registers:\n", h->sock); 1128 bitmask_snprintf(stp4020_rd_sockctl(h, STP4020_ICR0_IDX), 1129 STP4020_ICR0_BITS, bits, sizeof(bits)); 1130 printf("\tICR0=%s\n", bits); 1131 1132 bitmask_snprintf(stp4020_rd_sockctl(h, STP4020_ICR1_IDX), 1133 STP4020_ICR1_BITS, bits, sizeof(bits)); 1134 printf("\tICR1=%s\n", bits); 1135 1136 bitmask_snprintf(stp4020_rd_sockctl(h, STP4020_ISR0_IDX), 1137 STP4020_ISR0_IOBITS, bits, sizeof(bits)); 1138 printf("\tISR0=%s\n", bits); 1139 1140 bitmask_snprintf(stp4020_rd_sockctl(h, STP4020_ISR1_IDX), 1141 STP4020_ISR1_BITS, bits, sizeof(bits)); 1142 printf("\tISR1=%s\n", bits); 1143 } 1144 #endif /* STP4020_DEBUG */ 1145
Indexes created Thu Oct 02 14:10:14 GMT 2025