stp4020.c revision 1.53
1 /* $NetBSD: stp4020.c,v 1.53 2008/01/06 02:29:58 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * STP4020: SBus/PCMCIA bridge supporting two Type-3 PCMCIA cards. 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: stp4020.c,v 1.53 2008/01/06 02:29:58 martin Exp $"); 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/errno.h> 49 #include <sys/malloc.h> 50 #include <sys/extent.h> 51 #include <sys/proc.h> 52 #include <sys/kernel.h> 53 #include <sys/kthread.h> 54 #include <sys/device.h> 55 #include <sys/intr.h> 56 57 #include <dev/pcmcia/pcmciareg.h> 58 #include <dev/pcmcia/pcmciavar.h> 59 #include <dev/pcmcia/pcmciachip.h> 60 61 #include <sys/bus.h> 62 63 #include <dev/sbus/sbusvar.h> 64 #include <dev/sbus/stp4020reg.h> 65 66 #define STP4020_DEBUG 1 /* XXX-temp */ 67 68 /* 69 * We use the three available windows per socket in a simple, fixed 70 * arrangement. Each window maps (at full 1 MB size) one of the pcmcia 71 * spaces into sbus space. 72 */ 73 #define STP_WIN_ATTR 0 /* index of the attribute memory space window */ 74 #define STP_WIN_MEM 1 /* index of the common memory space window */ 75 #define STP_WIN_IO 2 /* index of the io space window */ 76 77 78 #if defined(STP4020_DEBUG) 79 int stp4020_debug = 0; 80 #define DPRINTF(x) do { if (stp4020_debug) printf x; } while(0) 81 #else 82 #define DPRINTF(x) 83 #endif 84 85 /* 86 * Event queue; events detected in an interrupt context go here 87 * awaiting attention from our event handling thread. 88 */ 89 struct stp4020_event { 90 SIMPLEQ_ENTRY(stp4020_event) se_q; 91 int se_type; 92 int se_sock; 93 }; 94 /* Defined event types */ 95 #define STP4020_EVENT_INSERTION 0 96 #define STP4020_EVENT_REMOVAL 1 97 98 /* 99 * Per socket data. 100 */ 101 struct stp4020_socket { 102 struct stp4020_softc *sc; /* Back link */ 103 int flags; 104 #define STP4020_SOCKET_BUSY 0x0001 105 int sock; /* Socket number (0 or 1) */ 106 int sbus_intno; /* Do we use first (0) or second (1) 107 interrupt? */ 108 #ifndef SUN4U 109 int int_enable; /* ICR0 value for interrupt enabled */ 110 int int_disable; /* ICR0 value for interrupt disabled */ 111 #endif 112 bus_space_tag_t tag; /* socket control io */ 113 bus_space_handle_t regs; /* space */ 114 bus_space_tag_t pcmciat; /* io space for pcmcia */ 115 struct device *pcmcia; /* Associated PCMCIA device */ 116 int (*intrhandler) /* Card driver interrupt handler */ 117 (void *); 118 void *intrarg; /* Card interrupt handler argument */ 119 #ifndef SUN4U 120 void *softint; /* cookie for the softintr */ 121 #endif 122 123 struct { 124 bus_space_handle_t winaddr;/* this window's address */ 125 } windows[STP4020_NWIN]; 126 127 }; 128 129 struct stp4020_softc { 130 struct device sc_dev; /* Base device */ 131 struct sbusdev sc_sd; /* SBus device */ 132 pcmcia_chipset_tag_t sc_pct; /* Chipset methods */ 133 134 struct lwp *event_thread; /* event handling thread */ 135 SIMPLEQ_HEAD(, stp4020_event) events; /* Pending events for thread */ 136 137 struct stp4020_socket sc_socks[STP4020_NSOCK]; 138 #ifndef SUN4U 139 bool sc_use_softint; 140 #endif 141 }; 142 143 144 static int stp4020print(void *, const char *); 145 static int stp4020match(struct device *, struct cfdata *, void *); 146 static void stp4020attach(struct device *, struct device *, void *); 147 static int stp4020_intr(void *); 148 static void stp4020_map_window(struct stp4020_socket *h, int win, int speed); 149 static void stp4020_calc_speed(int bus_speed, int ns, int *length, int *cmd_delay); 150 #ifndef SUN4U 151 static void stp4020_intr_dispatch(void *arg); 152 #endif 153 154 CFATTACH_DECL(nell, sizeof(struct stp4020_softc), 155 stp4020match, stp4020attach, NULL, NULL); 156 157 #ifdef STP4020_DEBUG 158 static void stp4020_dump_regs(struct stp4020_socket *); 159 #endif 160 161 static int stp4020_rd_sockctl(struct stp4020_socket *, int); 162 static void stp4020_wr_sockctl(struct stp4020_socket *, int, int); 163 static int stp4020_rd_winctl(struct stp4020_socket *, int, int); 164 static void stp4020_wr_winctl(struct stp4020_socket *, int, int, int); 165 166 void stp4020_delay(struct stp4020_softc *sc, unsigned int); 167 void stp4020_attach_socket(struct stp4020_socket *, int); 168 void stp4020_event_thread(void *); 169 void stp4020_queue_event(struct stp4020_softc *, int, int); 170 171 int stp4020_chip_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 172 struct pcmcia_mem_handle *); 173 void stp4020_chip_mem_free(pcmcia_chipset_handle_t, 174 struct pcmcia_mem_handle *); 175 int stp4020_chip_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 176 bus_size_t, struct pcmcia_mem_handle *, 177 bus_size_t *, int *); 178 void stp4020_chip_mem_unmap(pcmcia_chipset_handle_t, int); 179 180 int stp4020_chip_io_alloc(pcmcia_chipset_handle_t, 181 bus_addr_t, bus_size_t, bus_size_t, 182 struct pcmcia_io_handle *); 183 void stp4020_chip_io_free(pcmcia_chipset_handle_t, 184 struct pcmcia_io_handle *); 185 int stp4020_chip_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 186 bus_size_t, struct pcmcia_io_handle *, int *); 187 void stp4020_chip_io_unmap(pcmcia_chipset_handle_t, int); 188 189 void stp4020_chip_socket_enable(pcmcia_chipset_handle_t); 190 void stp4020_chip_socket_disable(pcmcia_chipset_handle_t); 191 void stp4020_chip_socket_settype(pcmcia_chipset_handle_t, int); 192 void *stp4020_chip_intr_establish(pcmcia_chipset_handle_t, 193 struct pcmcia_function *, int, 194 int (*)(void *), void *); 195 void stp4020_chip_intr_disestablish(pcmcia_chipset_handle_t, void *); 196 197 /* Our PCMCIA chipset methods */ 198 static struct pcmcia_chip_functions stp4020_functions = { 199 stp4020_chip_mem_alloc, 200 stp4020_chip_mem_free, 201 stp4020_chip_mem_map, 202 stp4020_chip_mem_unmap, 203 204 stp4020_chip_io_alloc, 205 stp4020_chip_io_free, 206 stp4020_chip_io_map, 207 stp4020_chip_io_unmap, 208 209 stp4020_chip_intr_establish, 210 stp4020_chip_intr_disestablish, 211 212 stp4020_chip_socket_enable, 213 stp4020_chip_socket_disable, 214 stp4020_chip_socket_settype, 215 NULL 216 }; 217 218 219 static inline int 220 stp4020_rd_sockctl(h, idx) 221 struct stp4020_socket *h; 222 int idx; 223 { 224 int o = ((STP4020_SOCKREGS_SIZE * (h->sock)) + idx); 225 return (bus_space_read_2(h->tag, h->regs, o)); 226 } 227 228 static inline void 229 stp4020_wr_sockctl(h, idx, v) 230 struct stp4020_socket *h; 231 int idx; 232 int v; 233 { 234 int o = (STP4020_SOCKREGS_SIZE * (h->sock)) + idx; 235 bus_space_write_2(h->tag, h->regs, o, v); 236 } 237 238 static inline int 239 stp4020_rd_winctl(h, win, idx) 240 struct stp4020_socket *h; 241 int win; 242 int idx; 243 { 244 int o = (STP4020_SOCKREGS_SIZE * (h->sock)) + 245 (STP4020_WINREGS_SIZE * win) + idx; 246 return (bus_space_read_2(h->tag, h->regs, o)); 247 } 248 249 static inline void 250 stp4020_wr_winctl(h, win, idx, v) 251 struct stp4020_socket *h; 252 int win; 253 int idx; 254 int v; 255 { 256 int o = (STP4020_SOCKREGS_SIZE * (h->sock)) + 257 (STP4020_WINREGS_SIZE * win) + idx; 258 259 bus_space_write_2(h->tag, h->regs, o, v); 260 } 261 262 #ifndef SUN4U /* XXX - move to SBUS machdep function? */ 263 264 static u_int16_t stp4020_read_2(bus_space_tag_t, 265 bus_space_handle_t, 266 bus_size_t); 267 static u_int32_t stp4020_read_4(bus_space_tag_t, 268 bus_space_handle_t, 269 bus_size_t); 270 static u_int64_t stp4020_read_8(bus_space_tag_t, 271 bus_space_handle_t, 272 bus_size_t); 273 static void stp4020_write_2(bus_space_tag_t, 274 bus_space_handle_t, 275 bus_size_t, 276 u_int16_t); 277 static void stp4020_write_4(bus_space_tag_t, 278 bus_space_handle_t, 279 bus_size_t, 280 u_int32_t); 281 static void stp4020_write_8(bus_space_tag_t, 282 bus_space_handle_t, 283 bus_size_t, 284 u_int64_t); 285 286 static u_int16_t 287 stp4020_read_2(space, handle, offset) 288 bus_space_tag_t space; 289 bus_space_handle_t handle; 290 bus_size_t offset; 291 { 292 return (le16toh(*(volatile u_int16_t *)(handle + offset))); 293 } 294 295 static u_int32_t 296 stp4020_read_4(space, handle, offset) 297 bus_space_tag_t space; 298 bus_space_handle_t handle; 299 bus_size_t offset; 300 { 301 return (le32toh(*(volatile u_int32_t *)(handle + offset))); 302 } 303 304 static u_int64_t 305 stp4020_read_8(space, handle, offset) 306 bus_space_tag_t space; 307 bus_space_handle_t handle; 308 bus_size_t offset; 309 { 310 return (le64toh(*(volatile u_int64_t *)(handle + offset))); 311 } 312 313 static void 314 stp4020_write_2(space, handle, offset, value) 315 bus_space_tag_t space; 316 bus_space_handle_t handle; 317 bus_size_t offset; 318 u_int16_t value; 319 { 320 (*(volatile u_int16_t *)(handle + offset)) = htole16(value); 321 } 322 323 static void 324 stp4020_write_4(space, handle, offset, value) 325 bus_space_tag_t space; 326 bus_space_handle_t handle; 327 bus_size_t offset; 328 u_int32_t value; 329 { 330 (*(volatile u_int32_t *)(handle + offset)) = htole32(value); 331 } 332 333 static void 334 stp4020_write_8(space, handle, offset, value) 335 bus_space_tag_t space; 336 bus_space_handle_t handle; 337 bus_size_t offset; 338 u_int64_t value; 339 { 340 (*(volatile u_int64_t *)(handle + offset)) = htole64(value); 341 } 342 #endif /* SUN4U */ 343 344 int 345 stp4020print(aux, busname) 346 void *aux; 347 const char *busname; 348 { 349 struct pcmciabus_attach_args *paa = aux; 350 struct stp4020_socket *h = paa->pch; 351 352 aprint_normal(" socket %d", h->sock); 353 return (UNCONF); 354 } 355 356 int 357 stp4020match(parent, cf, aux) 358 struct device *parent; 359 struct cfdata *cf; 360 void *aux; 361 { 362 struct sbus_attach_args *sa = aux; 363 364 return (strcmp("SUNW,pcmcia", sa->sa_name) == 0); 365 } 366 367 /* 368 * Attach all the sub-devices we can find 369 */ 370 void 371 stp4020attach(parent, self, aux) 372 struct device *parent, *self; 373 void *aux; 374 { 375 struct sbus_attach_args *sa = aux; 376 struct stp4020_softc *sc = (void *)self; 377 bus_space_tag_t tag; 378 int rev, i, sbus_intno, hw_ipl; 379 bus_space_handle_t bh; 380 381 /* Transfer bus tags */ 382 #ifdef SUN4U 383 tag = sa->sa_bustag; 384 #else 385 tag = bus_space_tag_alloc(sa->sa_bustag, sc); 386 if (tag == NULL) { 387 printf("%s: attach: out of memory\n", self->dv_xname); 388 return; 389 } 390 tag->sparc_read_2 = stp4020_read_2; 391 tag->sparc_read_4 = stp4020_read_4; 392 tag->sparc_read_8 = stp4020_read_8; 393 tag->sparc_write_2 = stp4020_write_2; 394 tag->sparc_write_4 = stp4020_write_4; 395 tag->sparc_write_8 = stp4020_write_8; 396 #endif /* SUN4U */ 397 398 /* check interrupt options, decide if we need a softint */ 399 #ifdef SUN4U 400 /* 401 * On sparc64 the hardware interrupt priority does not restrict 402 * the IPL we run our interrupt handler on, so we can always just 403 * use the first interrupt and reqest the handler to run at 404 * IPL_VM. 405 */ 406 sbus_intno = 0; 407 hw_ipl = IPL_VM; 408 #else 409 /* 410 * We need to check if one of the available interrupts has 411 * a priority that allows us to establish a handler at IPL_VM. 412 * If not (hard to imagine), use a soft interrupt. 413 */ 414 sbus_intno = -1; 415 for (i = 0; i < sa->sa_nintr; i++) { 416 struct sbus_softc *bus = 417 (struct sbus_softc *) sa->sa_bustag->cookie; 418 int ipl = bus->sc_intr2ipl[sa->sa_intr[i].oi_pri]; 419 if (ipl <= IPL_VM) { 420 sbus_intno = i; 421 sc->sc_use_softint = false; 422 hw_ipl = IPL_VM; 423 break; 424 } 425 } 426 if (sbus_intno == -1) { 427 /* 428 * We have not found a usable hardware interrupt - so 429 * use a softint to bounce to the proper IPL. 430 */ 431 printf("no usable HW interrupt found, using softint\n"); 432 sbus_intno = 0; 433 sc->sc_use_softint = true; 434 hw_ipl = IPL_NONE; 435 } 436 #endif 437 438 /* Set up per-socket static initialization */ 439 sc->sc_socks[0].sc = sc->sc_socks[1].sc = sc; 440 sc->sc_socks[0].tag = sc->sc_socks[1].tag = sa->sa_bustag; 441 /* 442 * XXX we rely on "tag" accepting the same handle-domain 443 * as sa->sa_bustag. 444 */ 445 sc->sc_socks[0].pcmciat = sc->sc_socks[1].pcmciat = tag; 446 sc->sc_socks[0].sbus_intno = 447 sc->sc_socks[1].sbus_intno = sbus_intno; 448 449 if (sa->sa_nreg < 8) { 450 printf("%s: only %d register sets\n", 451 self->dv_xname, sa->sa_nreg); 452 return; 453 } 454 455 if (sa->sa_nintr != 2) { 456 printf("%s: expect 2 interrupt Sbus levels; got %d\n", 457 self->dv_xname, sa->sa_nintr); 458 return; 459 } 460 461 #define STP4020_BANK_PROM 0 462 #define STP4020_BANK_CTRL 4 463 for (i = 0; i < 8; i++) { 464 465 /* 466 * STP4020 Register address map: 467 * bank 0: Forth PROM 468 * banks 1-3: socket 0, windows 0-2 469 * bank 4: control registers 470 * banks 5-7: socket 1, windows 0-2 471 */ 472 473 if (i == STP4020_BANK_PROM) 474 /* Skip the PROM */ 475 continue; 476 477 if (sbus_bus_map(sa->sa_bustag, 478 sa->sa_reg[i].oa_space, 479 sa->sa_reg[i].oa_base, 480 sa->sa_reg[i].oa_size, 481 0, &bh) != 0) { 482 printf("%s: attach: cannot map registers\n", 483 self->dv_xname); 484 return; 485 } 486 487 if (i == STP4020_BANK_CTRL) { 488 /* 489 * Copy tag and handle to both socket structures 490 * for easy access in control/status IO functions. 491 */ 492 sc->sc_socks[0].regs = sc->sc_socks[1].regs = bh; 493 } else if (i < STP4020_BANK_CTRL) { 494 /* banks 1-3 */ 495 sc->sc_socks[0].windows[i-1].winaddr = bh; 496 } else { 497 /* banks 5-7 */ 498 sc->sc_socks[1].windows[i-5].winaddr = bh; 499 } 500 } 501 502 sbus_establish(&sc->sc_sd, &sc->sc_dev); 503 504 /* We only use one interrupt level. */ 505 if (sa->sa_nintr > sbus_intno) { 506 bus_intr_establish(sa->sa_bustag, 507 sa->sa_intr[sbus_intno].oi_pri, 508 hw_ipl, stp4020_intr, sc); 509 } 510 511 rev = stp4020_rd_sockctl(&sc->sc_socks[0], STP4020_ISR1_IDX) & 512 STP4020_ISR1_REV_M; 513 printf(": rev %x\n", rev); 514 515 sc->sc_pct = (pcmcia_chipset_tag_t)&stp4020_functions; 516 517 SIMPLEQ_INIT(&sc->events); 518 519 for (i = 0; i < STP4020_NSOCK; i++) { 520 struct stp4020_socket *h = &sc->sc_socks[i]; 521 h->sock = i; 522 h->sc = sc; 523 #ifdef STP4020_DEBUG 524 if (stp4020_debug) 525 stp4020_dump_regs(h); 526 #endif 527 stp4020_attach_socket(h, sa->sa_frequency); 528 } 529 530 /* 531 * Arrange that a kernel thread be created to handle 532 * insert/removal events. 533 */ 534 if (kthread_create(PRI_NONE, 0, NULL, stp4020_event_thread, sc, 535 &sc->event_thread, "%s", self->dv_xname)) { 536 panic("%s: unable to create event thread", self->dv_xname); 537 } 538 } 539 540 void 541 stp4020_attach_socket(h, speed) 542 struct stp4020_socket *h; 543 int speed; 544 { 545 struct pcmciabus_attach_args paa; 546 int v; 547 548 /* no interrupt handlers yet */ 549 h->intrhandler = NULL; 550 h->intrarg = NULL; 551 #ifndef SUN4U 552 h->softint = NULL; 553 h->int_enable = 0; 554 h->int_disable = 0; 555 #endif 556 557 /* Map all three windows */ 558 stp4020_map_window(h, STP_WIN_ATTR, speed); 559 stp4020_map_window(h, STP_WIN_MEM, speed); 560 stp4020_map_window(h, STP_WIN_IO, speed); 561 562 /* Configure one pcmcia device per socket */ 563 paa.paa_busname = "pcmcia"; 564 paa.pct = (pcmcia_chipset_tag_t)h->sc->sc_pct; 565 paa.pch = (pcmcia_chipset_handle_t)h; 566 paa.iobase = 0; 567 paa.iosize = STP4020_WINDOW_SIZE; 568 569 h->pcmcia = config_found(&h->sc->sc_dev, &paa, stp4020print); 570 571 if (h->pcmcia == NULL) 572 return; 573 574 /* 575 * There's actually a pcmcia bus attached; initialize the slot. 576 */ 577 578 /* 579 * Clear things up before we enable status change interrupts. 580 * This seems to not be fully initialized by the PROM. 581 */ 582 stp4020_wr_sockctl(h, STP4020_ICR1_IDX, 0); 583 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, 0); 584 stp4020_wr_sockctl(h, STP4020_ISR1_IDX, 0x3fff); 585 stp4020_wr_sockctl(h, STP4020_ISR0_IDX, 0x3fff); 586 587 /* 588 * Enable socket status change interrupts. 589 * We only use one common interrupt for status change 590 * and IO, to avoid locking issues. 591 */ 592 v = STP4020_ICR0_ALL_STATUS_IE 593 | (h->sbus_intno ? STP4020_ICR0_SCILVL_SB1 594 : STP4020_ICR0_SCILVL_SB0); 595 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, v); 596 597 /* Get live status bits from ISR0 and clear pending interrupts */ 598 v = stp4020_rd_sockctl(h, STP4020_ISR0_IDX); 599 stp4020_wr_sockctl(h, STP4020_ISR0_IDX, v); 600 601 if ((v & (STP4020_ISR0_CD1ST|STP4020_ISR0_CD2ST)) == 0) 602 return; 603 604 pcmcia_card_attach(h->pcmcia); 605 h->flags |= STP4020_SOCKET_BUSY; 606 } 607 608 /* 609 * The actual event handling thread. 610 */ 611 void 612 stp4020_event_thread(arg) 613 void *arg; 614 { 615 struct stp4020_softc *sc = arg; 616 struct stp4020_event *e; 617 int s; 618 619 while (1) { 620 struct stp4020_socket *h; 621 int n; 622 623 s = splhigh(); 624 if ((e = SIMPLEQ_FIRST(&sc->events)) == NULL) { 625 splx(s); 626 (void)tsleep(&sc->events, PWAIT, "nellevt", 0); 627 continue; 628 } 629 SIMPLEQ_REMOVE_HEAD(&sc->events, se_q); 630 splx(s); 631 632 n = e->se_sock; 633 if (n < 0 || n >= STP4020_NSOCK) 634 panic("stp4020_event_thread: wayward socket number %d", 635 n); 636 637 h = &sc->sc_socks[n]; 638 switch (e->se_type) { 639 case STP4020_EVENT_INSERTION: 640 pcmcia_card_attach(h->pcmcia); 641 break; 642 case STP4020_EVENT_REMOVAL: 643 pcmcia_card_detach(h->pcmcia, DETACH_FORCE); 644 break; 645 default: 646 panic("stp4020_event_thread: unknown event type %d", 647 e->se_type); 648 } 649 free(e, M_TEMP); 650 } 651 } 652 653 void 654 stp4020_queue_event(sc, sock, event) 655 struct stp4020_softc *sc; 656 int sock, event; 657 { 658 struct stp4020_event *e; 659 int s; 660 661 e = malloc(sizeof(*e), M_TEMP, M_NOWAIT); 662 if (e == NULL) 663 panic("stp4020_queue_event: can't allocate event"); 664 665 e->se_type = event; 666 e->se_sock = sock; 667 s = splhigh(); 668 SIMPLEQ_INSERT_TAIL(&sc->events, e, se_q); 669 splx(s); 670 wakeup(&sc->events); 671 } 672 673 #ifndef SUN4U 674 /* 675 * Softinterrupt called to invoke the real driver interrupt handler. 676 */ 677 static void 678 stp4020_intr_dispatch(arg) 679 void *arg; 680 { 681 struct stp4020_socket *h = arg; 682 int s; 683 684 /* invoke driver handler */ 685 h->intrhandler(h->intrarg); 686 687 /* enable SBUS interrupts for pcmcia interrupts again */ 688 s = splhigh(); 689 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, h->int_enable); 690 splx(s); 691 } 692 #endif 693 694 int 695 stp4020_intr(arg) 696 void *arg; 697 { 698 struct stp4020_softc *sc = arg; 699 #ifndef SUN4U 700 int s; 701 #endif 702 int i, r = 0, cd_change = 0; 703 704 705 #ifndef SUN4U 706 /* protect hardware access by splhigh against softint */ 707 s = splhigh(); 708 #endif 709 710 /* 711 * Check each socket for pending requests. 712 */ 713 for (i = 0 ; i < STP4020_NSOCK; i++) { 714 struct stp4020_socket *h; 715 int v; 716 717 h = &sc->sc_socks[i]; 718 719 v = stp4020_rd_sockctl(h, STP4020_ISR0_IDX); 720 721 /* Ack all interrupts at once. */ 722 stp4020_wr_sockctl(h, STP4020_ISR0_IDX, v); 723 724 #ifdef STP4020_DEBUG 725 if (stp4020_debug != 0) { 726 char bits[64]; 727 bitmask_snprintf(v, STP4020_ISR0_IOBITS, 728 bits, sizeof(bits)); 729 printf("stp4020_statintr: ISR0=%s\n", bits); 730 } 731 #endif 732 733 if ((v & STP4020_ISR0_CDCHG) != 0) { 734 /* 735 * Card status change detect 736 */ 737 cd_change = 1; 738 r = 1; 739 if ((v & (STP4020_ISR0_CD1ST|STP4020_ISR0_CD2ST)) == (STP4020_ISR0_CD1ST|STP4020_ISR0_CD2ST)){ 740 if ((h->flags & STP4020_SOCKET_BUSY) == 0) { 741 stp4020_queue_event(sc, i, 742 STP4020_EVENT_INSERTION); 743 h->flags |= STP4020_SOCKET_BUSY; 744 } 745 } 746 if ((v & (STP4020_ISR0_CD1ST|STP4020_ISR0_CD2ST)) == 0){ 747 if ((h->flags & STP4020_SOCKET_BUSY) != 0) { 748 stp4020_queue_event(sc, i, 749 STP4020_EVENT_REMOVAL); 750 h->flags &= ~STP4020_SOCKET_BUSY; 751 } 752 } 753 } 754 755 if ((v & STP4020_ISR0_IOINT) != 0) { 756 /* we can not deny this is ours, no matter what the 757 card driver says. */ 758 r = 1; 759 760 /* It's a card interrupt */ 761 if ((h->flags & STP4020_SOCKET_BUSY) == 0) { 762 printf("stp4020[%d]: spurious interrupt?\n", 763 h->sock); 764 continue; 765 } 766 767 #ifndef SUN4U 768 /* 769 * Schedule softint to invoke driver interrupt 770 * handler 771 */ 772 if (h->softint != NULL) 773 sparc_softintr_schedule(h->softint); 774 /* 775 * Disable this sbus interrupt, until the soft-int 776 * handler had a chance to run 777 */ 778 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, h->int_disable); 779 #else 780 (*h->intrhandler)(h->intrarg); 781 #endif 782 } 783 784 /* informational messages */ 785 if ((v & STP4020_ISR0_BVD1CHG) != 0) { 786 /* ignore if this is caused by insert or removal */ 787 if (!cd_change) 788 printf("stp4020[%d]: Battery change 1\n", h->sock); 789 r = 1; 790 } 791 792 if ((v & STP4020_ISR0_BVD2CHG) != 0) { 793 /* ignore if this is caused by insert or removal */ 794 if (!cd_change) 795 printf("stp4020[%d]: Battery change 2\n", h->sock); 796 r = 1; 797 } 798 799 if ((v & STP4020_ISR0_SCINT) != 0) { 800 DPRINTF(("stp4020[%d]: status change\n", h->sock)); 801 r = 1; 802 } 803 804 if ((v & STP4020_ISR0_RDYCHG) != 0) { 805 DPRINTF(("stp4020[%d]: Ready/Busy change\n", h->sock)); 806 r = 1; 807 } 808 809 if ((v & STP4020_ISR0_WPCHG) != 0) { 810 DPRINTF(("stp4020[%d]: Write protect change\n", h->sock)); 811 r = 1; 812 } 813 814 if ((v & STP4020_ISR0_PCTO) != 0) { 815 DPRINTF(("stp4020[%d]: Card access timeout\n", h->sock)); 816 r = 1; 817 } 818 819 if ((v & ~STP4020_ISR0_LIVE) && r == 0) 820 printf("stp4020[%d]: unhandled interrupt: 0x%x\n", h->sock, v); 821 822 } 823 #ifndef SUN4U 824 splx(s); 825 #endif 826 827 return (r); 828 } 829 830 /* 831 * The function gets the sbus speed and a access time and calculates 832 * values for the CMDLNG and CMDDLAY registers. 833 */ 834 static void 835 stp4020_calc_speed(int bus_speed, int ns, int *length, int *cmd_delay) 836 { 837 int result; 838 839 if (ns < STP4020_MEM_SPEED_MIN) 840 ns = STP4020_MEM_SPEED_MIN; 841 else if (ns > STP4020_MEM_SPEED_MAX) 842 ns = STP4020_MEM_SPEED_MAX; 843 result = ns*(bus_speed/1000); 844 if (result % 1000000) 845 result = result/1000000 + 1; 846 else 847 result /= 1000000; 848 *length = result; 849 850 /* the sbus frequency range is limited, so we can keep this simple */ 851 *cmd_delay = ns <= STP4020_MEM_SPEED_MIN? 1 : 2; 852 } 853 854 static void 855 stp4020_map_window(struct stp4020_socket *h, int win, int speed) 856 { 857 int v, length, cmd_delay; 858 859 /* 860 * According to the PC Card standard 300ns access timing should be 861 * used for attribute memory access. Our pcmcia framework does not 862 * seem to propagate timing information, so we use that 863 * everywhere. 864 */ 865 stp4020_calc_speed(speed, (win==STP_WIN_ATTR)? 300 : 100, &length, &cmd_delay); 866 867 /* 868 * Fill in the Address Space Select and Base Address 869 * fields of this windows control register 0. 870 */ 871 v = ((cmd_delay << STP4020_WCR0_CMDDLY_S)&STP4020_WCR0_CMDDLY_M) 872 | ((length << STP4020_WCR0_CMDLNG_S)&STP4020_WCR0_CMDLNG_M); 873 switch (win) { 874 case STP_WIN_ATTR: 875 v |= STP4020_WCR0_ASPSEL_AM; 876 break; 877 case STP_WIN_MEM: 878 v |= STP4020_WCR0_ASPSEL_CM; 879 break; 880 case STP_WIN_IO: 881 v |= STP4020_WCR0_ASPSEL_IO; 882 break; 883 } 884 v |= (STP4020_ADDR2PAGE(0) & STP4020_WCR0_BASE_M); 885 stp4020_wr_winctl(h, win, STP4020_WCR0_IDX, v); 886 stp4020_wr_winctl(h, win, STP4020_WCR1_IDX, 1<<STP4020_WCR1_WAITREQ_S); 887 } 888 889 int 890 stp4020_chip_mem_alloc(pch, size, pcmhp) 891 pcmcia_chipset_handle_t pch; 892 bus_size_t size; 893 struct pcmcia_mem_handle *pcmhp; 894 { 895 struct stp4020_socket *h = (struct stp4020_socket *)pch; 896 897 /* we can not do much here, defere work to _mem_map */ 898 pcmhp->memt = h->pcmciat; 899 pcmhp->size = size; 900 pcmhp->addr = 0; 901 pcmhp->mhandle = 0; 902 pcmhp->realsize = size; 903 904 return (0); 905 } 906 907 void 908 stp4020_chip_mem_free(pch, pcmhp) 909 pcmcia_chipset_handle_t pch; 910 struct pcmcia_mem_handle *pcmhp; 911 { 912 } 913 914 int 915 stp4020_chip_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 916 pcmcia_chipset_handle_t pch; 917 int kind; 918 bus_addr_t card_addr; 919 bus_size_t size; 920 struct pcmcia_mem_handle *pcmhp; 921 bus_size_t *offsetp; 922 int *windowp; 923 { 924 struct stp4020_socket *h = (struct stp4020_socket *)pch; 925 int win = (kind&PCMCIA_MEM_ATTR)? STP_WIN_ATTR : STP_WIN_MEM; 926 927 pcmhp->memt = h->pcmciat; 928 bus_space_subregion(h->pcmciat, h->windows[win].winaddr, card_addr, size, &pcmhp->memh); 929 #ifdef SUN4U 930 if ((u_int8_t)pcmhp->memh._asi == ASI_PHYS_NON_CACHED) 931 pcmhp->memh._asi = ASI_PHYS_NON_CACHED_LITTLE; 932 else if ((u_int8_t)pcmhp->memh._asi == ASI_PRIMARY) 933 pcmhp->memh._asi = ASI_PRIMARY_LITTLE; 934 #endif 935 pcmhp->size = size; 936 pcmhp->realsize = STP4020_WINDOW_SIZE - card_addr; 937 *offsetp = 0; 938 *windowp = 0; 939 940 return (0); 941 } 942 943 void 944 stp4020_chip_mem_unmap(pch, win) 945 pcmcia_chipset_handle_t pch; 946 int win; 947 { 948 } 949 950 int 951 stp4020_chip_io_alloc(pch, start, size, align, pcihp) 952 pcmcia_chipset_handle_t pch; 953 bus_addr_t start; 954 bus_size_t size; 955 bus_size_t align; 956 struct pcmcia_io_handle *pcihp; 957 { 958 struct stp4020_socket *h = (struct stp4020_socket *)pch; 959 960 pcihp->iot = h->pcmciat; 961 pcihp->ioh = h->windows[STP_WIN_IO].winaddr; 962 return 0; 963 } 964 965 void 966 stp4020_chip_io_free(pch, pcihp) 967 pcmcia_chipset_handle_t pch; 968 struct pcmcia_io_handle *pcihp; 969 { 970 } 971 972 int 973 stp4020_chip_io_map(pch, width, offset, size, pcihp, windowp) 974 pcmcia_chipset_handle_t pch; 975 int width; 976 bus_addr_t offset; 977 bus_size_t size; 978 struct pcmcia_io_handle *pcihp; 979 int *windowp; 980 { 981 struct stp4020_socket *h = (struct stp4020_socket *)pch; 982 983 pcihp->iot = h->pcmciat; 984 bus_space_subregion(h->pcmciat, h->windows[STP_WIN_IO].winaddr, offset, size, &pcihp->ioh); 985 #ifdef SUN4U 986 if ((u_int8_t)pcihp->ioh._asi == ASI_PHYS_NON_CACHED) 987 pcihp->ioh._asi = ASI_PHYS_NON_CACHED_LITTLE; 988 else if ((u_int8_t)pcihp->ioh._asi == ASI_PRIMARY) 989 pcihp->ioh._asi = ASI_PRIMARY_LITTLE; 990 #endif 991 *windowp = 0; 992 return 0; 993 } 994 995 void 996 stp4020_chip_io_unmap(pch, win) 997 pcmcia_chipset_handle_t pch; 998 int win; 999 { 1000 } 1001 1002 void 1003 stp4020_chip_socket_enable(pch) 1004 pcmcia_chipset_handle_t pch; 1005 { 1006 struct stp4020_socket *h = (struct stp4020_socket *)pch; 1007 int i, v; 1008 1009 /* this bit is mostly stolen from pcic_attach_card */ 1010 1011 /* Power down the socket to reset it, clear the card reset pin */ 1012 stp4020_wr_sockctl(h, STP4020_ICR1_IDX, 0); 1013 1014 /* 1015 * wait 300ms until power fails (Tpf). Then, wait 100ms since 1016 * we are changing Vcc (Toff). 1017 */ 1018 stp4020_delay(h->sc, 300 + 100); 1019 1020 /* Power up the socket */ 1021 v = STP4020_ICR1_MSTPWR; 1022 stp4020_wr_sockctl(h, STP4020_ICR1_IDX, v); 1023 1024 /* 1025 * wait 100ms until power raise (Tpr) and 20ms to become 1026 * stable (Tsu(Vcc)). 1027 */ 1028 stp4020_delay(h->sc, 100 + 20); 1029 1030 v |= STP4020_ICR1_PCIFOE|STP4020_ICR1_VPP1_VCC; 1031 stp4020_wr_sockctl(h, STP4020_ICR1_IDX, v); 1032 1033 /* 1034 * hold RESET at least 10us. 1035 */ 1036 delay(10); 1037 1038 /* Clear reset flag, set to memory mode */ 1039 v = stp4020_rd_sockctl(h, STP4020_ICR0_IDX); 1040 v &= ~(STP4020_ICR0_IOIE | STP4020_ICR0_IOILVL | STP4020_ICR0_IFTYPE | 1041 STP4020_ICR0_SPKREN); 1042 v &= ~STP4020_ICR0_RESET; 1043 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, v); 1044 1045 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 1046 stp4020_delay(h->sc, 20); 1047 1048 /* Wait for the chip to finish initializing (5 seconds max) */ 1049 for (i = 10000; i > 0; i--) { 1050 v = stp4020_rd_sockctl(h, STP4020_ISR0_IDX); 1051 if ((v & STP4020_ISR0_RDYST) != 0) 1052 break; 1053 delay(500); 1054 } 1055 if (i <= 0) { 1056 char bits[64]; 1057 bitmask_snprintf(stp4020_rd_sockctl(h, STP4020_ISR0_IDX), 1058 STP4020_ISR0_IOBITS, bits, sizeof(bits)); 1059 printf("stp4020_chip_socket_enable: not ready: status %s\n", 1060 bits); 1061 return; 1062 } 1063 } 1064 1065 void 1066 stp4020_chip_socket_settype(pch, type) 1067 pcmcia_chipset_handle_t pch; 1068 int type; 1069 { 1070 struct stp4020_socket *h = (struct stp4020_socket *)pch; 1071 int v; 1072 1073 /* 1074 * Check the card type. 1075 * Enable socket I/O interrupts for IO cards. 1076 */ 1077 v = stp4020_rd_sockctl(h, STP4020_ICR0_IDX); 1078 v &= ~(STP4020_ICR0_IOIE | STP4020_ICR0_IOILVL | STP4020_ICR0_IFTYPE | 1079 STP4020_ICR0_SPKREN); 1080 if (type == PCMCIA_IFTYPE_IO) { 1081 v |= STP4020_ICR0_IFTYPE_IO|STP4020_ICR0_IOIE 1082 |STP4020_ICR0_SPKREN; 1083 v |= h->sbus_intno ? STP4020_ICR0_IOILVL_SB1 1084 : STP4020_ICR0_IOILVL_SB0; 1085 #ifndef SUN4U 1086 h->int_enable = v; 1087 h->int_disable = v & ~STP4020_ICR0_IOIE; 1088 #endif 1089 DPRINTF(("%s: configuring card for IO useage\n", h->sc->sc_dev.dv_xname)); 1090 } else { 1091 v |= STP4020_ICR0_IFTYPE_MEM; 1092 #ifndef SUN4U 1093 h->int_enable = h->int_disable = v; 1094 #endif 1095 DPRINTF(("%s: configuring card for IO useage\n", h->sc->sc_dev.dv_xname)); 1096 DPRINTF(("%s: configuring card for MEM ONLY useage\n", h->sc->sc_dev.dv_xname)); 1097 } 1098 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, v); 1099 } 1100 1101 void 1102 stp4020_chip_socket_disable(pch) 1103 pcmcia_chipset_handle_t pch; 1104 { 1105 struct stp4020_socket *h = (struct stp4020_socket *)pch; 1106 int v; 1107 1108 /* 1109 * Disable socket I/O interrupts. 1110 */ 1111 v = stp4020_rd_sockctl(h, STP4020_ICR0_IDX); 1112 v &= ~(STP4020_ICR0_IOIE | STP4020_ICR0_IOILVL | STP4020_ICR0_IFTYPE | 1113 STP4020_ICR0_SPKREN); 1114 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, v); 1115 1116 /* Power down the socket */ 1117 stp4020_wr_sockctl(h, STP4020_ICR1_IDX, 0); 1118 1119 /* 1120 * wait 300ms until power fails (Tpf). 1121 */ 1122 stp4020_delay(h->sc, 300); 1123 } 1124 1125 void * 1126 stp4020_chip_intr_establish(pch, pf, ipl, handler, arg) 1127 pcmcia_chipset_handle_t pch; 1128 struct pcmcia_function *pf; 1129 int ipl; 1130 int (*handler)(void *); 1131 void *arg; 1132 { 1133 struct stp4020_socket *h = (struct stp4020_socket *)pch; 1134 1135 /* only one interrupt handler per slot */ 1136 if (h->intrhandler != NULL) return NULL; 1137 1138 h->intrhandler = handler; 1139 h->intrarg = arg; 1140 #ifndef SUN4U 1141 if (h->sc->sc_use_softint) { 1142 h->softint = sparc_softintr_establish(ipl, stp4020_intr_dispatch, h); 1143 return h->softint; 1144 } 1145 #endif 1146 return h; 1147 } 1148 1149 void 1150 stp4020_chip_intr_disestablish(pch, ih) 1151 pcmcia_chipset_handle_t pch; 1152 void *ih; 1153 { 1154 struct stp4020_socket *h = (struct stp4020_socket *)pch; 1155 1156 h->intrhandler = NULL; 1157 h->intrarg = NULL; 1158 #ifndef SUN4U 1159 if (h->softint) { 1160 sparc_softintr_disestablish(h->softint); 1161 h->softint = NULL; 1162 } 1163 #endif 1164 } 1165 1166 /* 1167 * Delay and possibly yield CPU. 1168 * XXX - assumes a context 1169 */ 1170 void 1171 stp4020_delay(sc, ms) 1172 struct stp4020_softc *sc; 1173 unsigned int ms; 1174 { 1175 unsigned int ticks = mstohz(ms); 1176 1177 if (cold || ticks == 0) { 1178 delay(ms); 1179 return; 1180 } 1181 1182 #ifdef DIAGNOSTIC 1183 if (ticks > 60*hz) 1184 panic("stp4020: preposterous delay: %u", ticks); 1185 #endif 1186 tsleep(sc, 0, "nelldel", ticks); 1187 } 1188 1189 #ifdef STP4020_DEBUG 1190 void 1191 stp4020_dump_regs(h) 1192 struct stp4020_socket *h; 1193 { 1194 char bits[64]; 1195 /* 1196 * Dump control and status registers. 1197 */ 1198 printf("socket[%d] registers:\n", h->sock); 1199 bitmask_snprintf(stp4020_rd_sockctl(h, STP4020_ICR0_IDX), 1200 STP4020_ICR0_BITS, bits, sizeof(bits)); 1201 printf("\tICR0=%s\n", bits); 1202 1203 bitmask_snprintf(stp4020_rd_sockctl(h, STP4020_ICR1_IDX), 1204 STP4020_ICR1_BITS, bits, sizeof(bits)); 1205 printf("\tICR1=%s\n", bits); 1206 1207 bitmask_snprintf(stp4020_rd_sockctl(h, STP4020_ISR0_IDX), 1208 STP4020_ISR0_IOBITS, bits, sizeof(bits)); 1209 printf("\tISR0=%s\n", bits); 1210 1211 bitmask_snprintf(stp4020_rd_sockctl(h, STP4020_ISR1_IDX), 1212 STP4020_ISR1_BITS, bits, sizeof(bits)); 1213 printf("\tISR1=%s\n", bits); 1214 } 1215 #endif /* STP4020_DEBUG */ 1216
Indexes created Fri Oct 03 02:09:57 GMT 2025