stp4020.c revision 1.53.6.1
1 /* $NetBSD: stp4020.c,v 1.53.6.1 2008/06/02 13:23:50 mjf Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * STP4020: SBus/PCMCIA bridge supporting two Type-3 PCMCIA cards. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: stp4020.c,v 1.53.6.1 2008/06/02 13:23:50 mjf Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/errno.h> 42 #include <sys/malloc.h> 43 #include <sys/extent.h> 44 #include <sys/proc.h> 45 #include <sys/kernel.h> 46 #include <sys/kthread.h> 47 #include <sys/device.h> 48 #include <sys/intr.h> 49 50 #include <dev/pcmcia/pcmciareg.h> 51 #include <dev/pcmcia/pcmciavar.h> 52 #include <dev/pcmcia/pcmciachip.h> 53 54 #include <sys/bus.h> 55 56 #include <dev/sbus/sbusvar.h> 57 #include <dev/sbus/stp4020reg.h> 58 59 #define STP4020_DEBUG 1 /* XXX-temp */ 60 61 /* 62 * We use the three available windows per socket in a simple, fixed 63 * arrangement. Each window maps (at full 1 MB size) one of the pcmcia 64 * spaces into sbus space. 65 */ 66 #define STP_WIN_ATTR 0 /* index of the attribute memory space window */ 67 #define STP_WIN_MEM 1 /* index of the common memory space window */ 68 #define STP_WIN_IO 2 /* index of the io space window */ 69 70 71 #if defined(STP4020_DEBUG) 72 int stp4020_debug = 0; 73 #define DPRINTF(x) do { if (stp4020_debug) printf x; } while(0) 74 #else 75 #define DPRINTF(x) 76 #endif 77 78 /* 79 * Event queue; events detected in an interrupt context go here 80 * awaiting attention from our event handling thread. 81 */ 82 struct stp4020_event { 83 SIMPLEQ_ENTRY(stp4020_event) se_q; 84 int se_type; 85 int se_sock; 86 }; 87 /* Defined event types */ 88 #define STP4020_EVENT_INSERTION 0 89 #define STP4020_EVENT_REMOVAL 1 90 91 /* 92 * Per socket data. 93 */ 94 struct stp4020_socket { 95 struct stp4020_softc *sc; /* Back link */ 96 int flags; 97 #define STP4020_SOCKET_BUSY 0x0001 98 int sock; /* Socket number (0 or 1) */ 99 int sbus_intno; /* Do we use first (0) or second (1) 100 interrupt? */ 101 #ifndef SUN4U 102 int int_enable; /* ICR0 value for interrupt enabled */ 103 int int_disable; /* ICR0 value for interrupt disabled */ 104 #endif 105 bus_space_tag_t tag; /* socket control io */ 106 bus_space_handle_t regs; /* space */ 107 bus_space_tag_t pcmciat; /* io space for pcmcia */ 108 struct device *pcmcia; /* Associated PCMCIA device */ 109 int (*intrhandler) /* Card driver interrupt handler */ 110 (void *); 111 void *intrarg; /* Card interrupt handler argument */ 112 #ifndef SUN4U 113 void *softint; /* cookie for the softintr */ 114 #endif 115 116 struct { 117 bus_space_handle_t winaddr;/* this window's address */ 118 } windows[STP4020_NWIN]; 119 120 }; 121 122 struct stp4020_softc { 123 struct device sc_dev; /* Base device */ 124 struct sbusdev sc_sd; /* SBus device */ 125 pcmcia_chipset_tag_t sc_pct; /* Chipset methods */ 126 127 struct lwp *event_thread; /* event handling thread */ 128 SIMPLEQ_HEAD(, stp4020_event) events; /* Pending events for thread */ 129 130 struct stp4020_socket sc_socks[STP4020_NSOCK]; 131 #ifndef SUN4U 132 bool sc_use_softint; 133 #endif 134 }; 135 136 137 static int stp4020print(void *, const char *); 138 static int stp4020match(struct device *, struct cfdata *, void *); 139 static void stp4020attach(struct device *, struct device *, void *); 140 static int stp4020_intr(void *); 141 static void stp4020_map_window(struct stp4020_socket *h, int win, int speed); 142 static void stp4020_calc_speed(int bus_speed, int ns, int *length, int *cmd_delay); 143 #ifndef SUN4U 144 static void stp4020_intr_dispatch(void *arg); 145 #endif 146 147 CFATTACH_DECL(nell, sizeof(struct stp4020_softc), 148 stp4020match, stp4020attach, NULL, NULL); 149 150 #ifdef STP4020_DEBUG 151 static void stp4020_dump_regs(struct stp4020_socket *); 152 #endif 153 154 static int stp4020_rd_sockctl(struct stp4020_socket *, int); 155 static void stp4020_wr_sockctl(struct stp4020_socket *, int, int); 156 static int stp4020_rd_winctl(struct stp4020_socket *, int, int); 157 static void stp4020_wr_winctl(struct stp4020_socket *, int, int, int); 158 159 void stp4020_delay(struct stp4020_softc *sc, unsigned int); 160 void stp4020_attach_socket(struct stp4020_socket *, int); 161 void stp4020_event_thread(void *); 162 void stp4020_queue_event(struct stp4020_softc *, int, int); 163 164 int stp4020_chip_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 165 struct pcmcia_mem_handle *); 166 void stp4020_chip_mem_free(pcmcia_chipset_handle_t, 167 struct pcmcia_mem_handle *); 168 int stp4020_chip_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 169 bus_size_t, struct pcmcia_mem_handle *, 170 bus_size_t *, int *); 171 void stp4020_chip_mem_unmap(pcmcia_chipset_handle_t, int); 172 173 int stp4020_chip_io_alloc(pcmcia_chipset_handle_t, 174 bus_addr_t, bus_size_t, bus_size_t, 175 struct pcmcia_io_handle *); 176 void stp4020_chip_io_free(pcmcia_chipset_handle_t, 177 struct pcmcia_io_handle *); 178 int stp4020_chip_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 179 bus_size_t, struct pcmcia_io_handle *, int *); 180 void stp4020_chip_io_unmap(pcmcia_chipset_handle_t, int); 181 182 void stp4020_chip_socket_enable(pcmcia_chipset_handle_t); 183 void stp4020_chip_socket_disable(pcmcia_chipset_handle_t); 184 void stp4020_chip_socket_settype(pcmcia_chipset_handle_t, int); 185 void *stp4020_chip_intr_establish(pcmcia_chipset_handle_t, 186 struct pcmcia_function *, int, 187 int (*)(void *), void *); 188 void stp4020_chip_intr_disestablish(pcmcia_chipset_handle_t, void *); 189 190 /* Our PCMCIA chipset methods */ 191 static struct pcmcia_chip_functions stp4020_functions = { 192 stp4020_chip_mem_alloc, 193 stp4020_chip_mem_free, 194 stp4020_chip_mem_map, 195 stp4020_chip_mem_unmap, 196 197 stp4020_chip_io_alloc, 198 stp4020_chip_io_free, 199 stp4020_chip_io_map, 200 stp4020_chip_io_unmap, 201 202 stp4020_chip_intr_establish, 203 stp4020_chip_intr_disestablish, 204 205 stp4020_chip_socket_enable, 206 stp4020_chip_socket_disable, 207 stp4020_chip_socket_settype, 208 NULL 209 }; 210 211 212 static inline int 213 stp4020_rd_sockctl(h, idx) 214 struct stp4020_socket *h; 215 int idx; 216 { 217 int o = ((STP4020_SOCKREGS_SIZE * (h->sock)) + idx); 218 return (bus_space_read_2(h->tag, h->regs, o)); 219 } 220 221 static inline void 222 stp4020_wr_sockctl(h, idx, v) 223 struct stp4020_socket *h; 224 int idx; 225 int v; 226 { 227 int o = (STP4020_SOCKREGS_SIZE * (h->sock)) + idx; 228 bus_space_write_2(h->tag, h->regs, o, v); 229 } 230 231 static inline int 232 stp4020_rd_winctl(h, win, idx) 233 struct stp4020_socket *h; 234 int win; 235 int idx; 236 { 237 int o = (STP4020_SOCKREGS_SIZE * (h->sock)) + 238 (STP4020_WINREGS_SIZE * win) + idx; 239 return (bus_space_read_2(h->tag, h->regs, o)); 240 } 241 242 static inline void 243 stp4020_wr_winctl(h, win, idx, v) 244 struct stp4020_socket *h; 245 int win; 246 int idx; 247 int v; 248 { 249 int o = (STP4020_SOCKREGS_SIZE * (h->sock)) + 250 (STP4020_WINREGS_SIZE * win) + idx; 251 252 bus_space_write_2(h->tag, h->regs, o, v); 253 } 254 255 #ifndef SUN4U /* XXX - move to SBUS machdep function? */ 256 257 static u_int16_t stp4020_read_2(bus_space_tag_t, 258 bus_space_handle_t, 259 bus_size_t); 260 static u_int32_t stp4020_read_4(bus_space_tag_t, 261 bus_space_handle_t, 262 bus_size_t); 263 static u_int64_t stp4020_read_8(bus_space_tag_t, 264 bus_space_handle_t, 265 bus_size_t); 266 static void stp4020_write_2(bus_space_tag_t, 267 bus_space_handle_t, 268 bus_size_t, 269 u_int16_t); 270 static void stp4020_write_4(bus_space_tag_t, 271 bus_space_handle_t, 272 bus_size_t, 273 u_int32_t); 274 static void stp4020_write_8(bus_space_tag_t, 275 bus_space_handle_t, 276 bus_size_t, 277 u_int64_t); 278 279 static u_int16_t 280 stp4020_read_2(space, handle, offset) 281 bus_space_tag_t space; 282 bus_space_handle_t handle; 283 bus_size_t offset; 284 { 285 return (le16toh(*(volatile u_int16_t *)(handle + offset))); 286 } 287 288 static u_int32_t 289 stp4020_read_4(space, handle, offset) 290 bus_space_tag_t space; 291 bus_space_handle_t handle; 292 bus_size_t offset; 293 { 294 return (le32toh(*(volatile u_int32_t *)(handle + offset))); 295 } 296 297 static u_int64_t 298 stp4020_read_8(space, handle, offset) 299 bus_space_tag_t space; 300 bus_space_handle_t handle; 301 bus_size_t offset; 302 { 303 return (le64toh(*(volatile u_int64_t *)(handle + offset))); 304 } 305 306 static void 307 stp4020_write_2(space, handle, offset, value) 308 bus_space_tag_t space; 309 bus_space_handle_t handle; 310 bus_size_t offset; 311 u_int16_t value; 312 { 313 (*(volatile u_int16_t *)(handle + offset)) = htole16(value); 314 } 315 316 static void 317 stp4020_write_4(space, handle, offset, value) 318 bus_space_tag_t space; 319 bus_space_handle_t handle; 320 bus_size_t offset; 321 u_int32_t value; 322 { 323 (*(volatile u_int32_t *)(handle + offset)) = htole32(value); 324 } 325 326 static void 327 stp4020_write_8(space, handle, offset, value) 328 bus_space_tag_t space; 329 bus_space_handle_t handle; 330 bus_size_t offset; 331 u_int64_t value; 332 { 333 (*(volatile u_int64_t *)(handle + offset)) = htole64(value); 334 } 335 #endif /* SUN4U */ 336 337 int 338 stp4020print(aux, busname) 339 void *aux; 340 const char *busname; 341 { 342 struct pcmciabus_attach_args *paa = aux; 343 struct stp4020_socket *h = paa->pch; 344 345 aprint_normal(" socket %d", h->sock); 346 return (UNCONF); 347 } 348 349 int 350 stp4020match(parent, cf, aux) 351 struct device *parent; 352 struct cfdata *cf; 353 void *aux; 354 { 355 struct sbus_attach_args *sa = aux; 356 357 return (strcmp("SUNW,pcmcia", sa->sa_name) == 0); 358 } 359 360 /* 361 * Attach all the sub-devices we can find 362 */ 363 void 364 stp4020attach(parent, self, aux) 365 struct device *parent, *self; 366 void *aux; 367 { 368 struct sbus_attach_args *sa = aux; 369 struct stp4020_softc *sc = (void *)self; 370 bus_space_tag_t tag; 371 int rev, i, sbus_intno, hw_ipl; 372 bus_space_handle_t bh; 373 374 /* Transfer bus tags */ 375 #ifdef SUN4U 376 tag = sa->sa_bustag; 377 #else 378 tag = bus_space_tag_alloc(sa->sa_bustag, sc); 379 if (tag == NULL) { 380 aprint_error_dev(self, "attach: out of memory\n"); 381 return; 382 } 383 tag->sparc_read_2 = stp4020_read_2; 384 tag->sparc_read_4 = stp4020_read_4; 385 tag->sparc_read_8 = stp4020_read_8; 386 tag->sparc_write_2 = stp4020_write_2; 387 tag->sparc_write_4 = stp4020_write_4; 388 tag->sparc_write_8 = stp4020_write_8; 389 #endif /* SUN4U */ 390 391 /* check interrupt options, decide if we need a softint */ 392 #ifdef SUN4U 393 /* 394 * On sparc64 the hardware interrupt priority does not restrict 395 * the IPL we run our interrupt handler on, so we can always just 396 * use the first interrupt and reqest the handler to run at 397 * IPL_VM. 398 */ 399 sbus_intno = 0; 400 hw_ipl = IPL_VM; 401 #else 402 /* 403 * We need to check if one of the available interrupts has 404 * a priority that allows us to establish a handler at IPL_VM. 405 * If not (hard to imagine), use a soft interrupt. 406 */ 407 sbus_intno = -1; 408 for (i = 0; i < sa->sa_nintr; i++) { 409 struct sbus_softc *bus = 410 (struct sbus_softc *) sa->sa_bustag->cookie; 411 int ipl = bus->sc_intr2ipl[sa->sa_intr[i].oi_pri]; 412 if (ipl <= IPL_VM) { 413 sbus_intno = i; 414 sc->sc_use_softint = false; 415 hw_ipl = IPL_VM; 416 break; 417 } 418 } 419 if (sbus_intno == -1) { 420 /* 421 * We have not found a usable hardware interrupt - so 422 * use a softint to bounce to the proper IPL. 423 */ 424 printf("no usable HW interrupt found, using softint\n"); 425 sbus_intno = 0; 426 sc->sc_use_softint = true; 427 hw_ipl = IPL_NONE; 428 } 429 #endif 430 431 /* Set up per-socket static initialization */ 432 sc->sc_socks[0].sc = sc->sc_socks[1].sc = sc; 433 sc->sc_socks[0].tag = sc->sc_socks[1].tag = sa->sa_bustag; 434 /* 435 * XXX we rely on "tag" accepting the same handle-domain 436 * as sa->sa_bustag. 437 */ 438 sc->sc_socks[0].pcmciat = sc->sc_socks[1].pcmciat = tag; 439 sc->sc_socks[0].sbus_intno = 440 sc->sc_socks[1].sbus_intno = sbus_intno; 441 442 if (sa->sa_nreg < 8) { 443 printf("%s: only %d register sets\n", 444 device_xname(self), sa->sa_nreg); 445 return; 446 } 447 448 if (sa->sa_nintr != 2) { 449 printf("%s: expect 2 interrupt Sbus levels; got %d\n", 450 device_xname(self), sa->sa_nintr); 451 return; 452 } 453 454 #define STP4020_BANK_PROM 0 455 #define STP4020_BANK_CTRL 4 456 for (i = 0; i < 8; i++) { 457 458 /* 459 * STP4020 Register address map: 460 * bank 0: Forth PROM 461 * banks 1-3: socket 0, windows 0-2 462 * bank 4: control registers 463 * banks 5-7: socket 1, windows 0-2 464 */ 465 466 if (i == STP4020_BANK_PROM) 467 /* Skip the PROM */ 468 continue; 469 470 if (sbus_bus_map(sa->sa_bustag, 471 sa->sa_reg[i].oa_space, 472 sa->sa_reg[i].oa_base, 473 sa->sa_reg[i].oa_size, 474 0, &bh) != 0) { 475 aprint_error_dev(self, "attach: cannot map registers\n"); 476 return; 477 } 478 479 if (i == STP4020_BANK_CTRL) { 480 /* 481 * Copy tag and handle to both socket structures 482 * for easy access in control/status IO functions. 483 */ 484 sc->sc_socks[0].regs = sc->sc_socks[1].regs = bh; 485 } else if (i < STP4020_BANK_CTRL) { 486 /* banks 1-3 */ 487 sc->sc_socks[0].windows[i-1].winaddr = bh; 488 } else { 489 /* banks 5-7 */ 490 sc->sc_socks[1].windows[i-5].winaddr = bh; 491 } 492 } 493 494 sbus_establish(&sc->sc_sd, &sc->sc_dev); 495 496 /* We only use one interrupt level. */ 497 if (sa->sa_nintr > sbus_intno) { 498 bus_intr_establish(sa->sa_bustag, 499 sa->sa_intr[sbus_intno].oi_pri, 500 hw_ipl, stp4020_intr, sc); 501 } 502 503 rev = stp4020_rd_sockctl(&sc->sc_socks[0], STP4020_ISR1_IDX) & 504 STP4020_ISR1_REV_M; 505 printf(": rev %x\n", rev); 506 507 sc->sc_pct = (pcmcia_chipset_tag_t)&stp4020_functions; 508 509 SIMPLEQ_INIT(&sc->events); 510 511 for (i = 0; i < STP4020_NSOCK; i++) { 512 struct stp4020_socket *h = &sc->sc_socks[i]; 513 h->sock = i; 514 h->sc = sc; 515 #ifdef STP4020_DEBUG 516 if (stp4020_debug) 517 stp4020_dump_regs(h); 518 #endif 519 stp4020_attach_socket(h, sa->sa_frequency); 520 } 521 522 /* 523 * Arrange that a kernel thread be created to handle 524 * insert/removal events. 525 */ 526 if (kthread_create(PRI_NONE, 0, NULL, stp4020_event_thread, sc, 527 &sc->event_thread, "%s", device_xname(self))) { 528 panic("%s: unable to create event thread", device_xname(self)); 529 } 530 } 531 532 void 533 stp4020_attach_socket(h, speed) 534 struct stp4020_socket *h; 535 int speed; 536 { 537 struct pcmciabus_attach_args paa; 538 int v; 539 540 /* no interrupt handlers yet */ 541 h->intrhandler = NULL; 542 h->intrarg = NULL; 543 #ifndef SUN4U 544 h->softint = NULL; 545 h->int_enable = 0; 546 h->int_disable = 0; 547 #endif 548 549 /* Map all three windows */ 550 stp4020_map_window(h, STP_WIN_ATTR, speed); 551 stp4020_map_window(h, STP_WIN_MEM, speed); 552 stp4020_map_window(h, STP_WIN_IO, speed); 553 554 /* Configure one pcmcia device per socket */ 555 paa.paa_busname = "pcmcia"; 556 paa.pct = (pcmcia_chipset_tag_t)h->sc->sc_pct; 557 paa.pch = (pcmcia_chipset_handle_t)h; 558 paa.iobase = 0; 559 paa.iosize = STP4020_WINDOW_SIZE; 560 561 h->pcmcia = config_found(&h->sc->sc_dev, &paa, stp4020print); 562 563 if (h->pcmcia == NULL) 564 return; 565 566 /* 567 * There's actually a pcmcia bus attached; initialize the slot. 568 */ 569 570 /* 571 * Clear things up before we enable status change interrupts. 572 * This seems to not be fully initialized by the PROM. 573 */ 574 stp4020_wr_sockctl(h, STP4020_ICR1_IDX, 0); 575 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, 0); 576 stp4020_wr_sockctl(h, STP4020_ISR1_IDX, 0x3fff); 577 stp4020_wr_sockctl(h, STP4020_ISR0_IDX, 0x3fff); 578 579 /* 580 * Enable socket status change interrupts. 581 * We only use one common interrupt for status change 582 * and IO, to avoid locking issues. 583 */ 584 v = STP4020_ICR0_ALL_STATUS_IE 585 | (h->sbus_intno ? STP4020_ICR0_SCILVL_SB1 586 : STP4020_ICR0_SCILVL_SB0); 587 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, v); 588 589 /* Get live status bits from ISR0 and clear pending interrupts */ 590 v = stp4020_rd_sockctl(h, STP4020_ISR0_IDX); 591 stp4020_wr_sockctl(h, STP4020_ISR0_IDX, v); 592 593 if ((v & (STP4020_ISR0_CD1ST|STP4020_ISR0_CD2ST)) == 0) 594 return; 595 596 pcmcia_card_attach(h->pcmcia); 597 h->flags |= STP4020_SOCKET_BUSY; 598 } 599 600 /* 601 * The actual event handling thread. 602 */ 603 void 604 stp4020_event_thread(arg) 605 void *arg; 606 { 607 struct stp4020_softc *sc = arg; 608 struct stp4020_event *e; 609 int s; 610 611 while (1) { 612 struct stp4020_socket *h; 613 int n; 614 615 s = splhigh(); 616 if ((e = SIMPLEQ_FIRST(&sc->events)) == NULL) { 617 splx(s); 618 (void)tsleep(&sc->events, PWAIT, "nellevt", 0); 619 continue; 620 } 621 SIMPLEQ_REMOVE_HEAD(&sc->events, se_q); 622 splx(s); 623 624 n = e->se_sock; 625 if (n < 0 || n >= STP4020_NSOCK) 626 panic("stp4020_event_thread: wayward socket number %d", 627 n); 628 629 h = &sc->sc_socks[n]; 630 switch (e->se_type) { 631 case STP4020_EVENT_INSERTION: 632 pcmcia_card_attach(h->pcmcia); 633 break; 634 case STP4020_EVENT_REMOVAL: 635 pcmcia_card_detach(h->pcmcia, DETACH_FORCE); 636 break; 637 default: 638 panic("stp4020_event_thread: unknown event type %d", 639 e->se_type); 640 } 641 free(e, M_TEMP); 642 } 643 } 644 645 void 646 stp4020_queue_event(sc, sock, event) 647 struct stp4020_softc *sc; 648 int sock, event; 649 { 650 struct stp4020_event *e; 651 int s; 652 653 e = malloc(sizeof(*e), M_TEMP, M_NOWAIT); 654 if (e == NULL) 655 panic("stp4020_queue_event: can't allocate event"); 656 657 e->se_type = event; 658 e->se_sock = sock; 659 s = splhigh(); 660 SIMPLEQ_INSERT_TAIL(&sc->events, e, se_q); 661 splx(s); 662 wakeup(&sc->events); 663 } 664 665 #ifndef SUN4U 666 /* 667 * Softinterrupt called to invoke the real driver interrupt handler. 668 */ 669 static void 670 stp4020_intr_dispatch(arg) 671 void *arg; 672 { 673 struct stp4020_socket *h = arg; 674 int s; 675 676 /* invoke driver handler */ 677 h->intrhandler(h->intrarg); 678 679 /* enable SBUS interrupts for pcmcia interrupts again */ 680 s = splhigh(); 681 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, h->int_enable); 682 splx(s); 683 } 684 #endif 685 686 int 687 stp4020_intr(arg) 688 void *arg; 689 { 690 struct stp4020_softc *sc = arg; 691 #ifndef SUN4U 692 int s; 693 #endif 694 int i, r = 0, cd_change = 0; 695 696 697 #ifndef SUN4U 698 /* protect hardware access by splhigh against softint */ 699 s = splhigh(); 700 #endif 701 702 /* 703 * Check each socket for pending requests. 704 */ 705 for (i = 0 ; i < STP4020_NSOCK; i++) { 706 struct stp4020_socket *h; 707 int v; 708 709 h = &sc->sc_socks[i]; 710 711 v = stp4020_rd_sockctl(h, STP4020_ISR0_IDX); 712 713 /* Ack all interrupts at once. */ 714 stp4020_wr_sockctl(h, STP4020_ISR0_IDX, v); 715 716 #ifdef STP4020_DEBUG 717 if (stp4020_debug != 0) { 718 char bits[64]; 719 bitmask_snprintf(v, STP4020_ISR0_IOBITS, 720 bits, sizeof(bits)); 721 printf("stp4020_statintr: ISR0=%s\n", bits); 722 } 723 #endif 724 725 if ((v & STP4020_ISR0_CDCHG) != 0) { 726 /* 727 * Card status change detect 728 */ 729 cd_change = 1; 730 r = 1; 731 if ((v & (STP4020_ISR0_CD1ST|STP4020_ISR0_CD2ST)) == (STP4020_ISR0_CD1ST|STP4020_ISR0_CD2ST)){ 732 if ((h->flags & STP4020_SOCKET_BUSY) == 0) { 733 stp4020_queue_event(sc, i, 734 STP4020_EVENT_INSERTION); 735 h->flags |= STP4020_SOCKET_BUSY; 736 } 737 } 738 if ((v & (STP4020_ISR0_CD1ST|STP4020_ISR0_CD2ST)) == 0){ 739 if ((h->flags & STP4020_SOCKET_BUSY) != 0) { 740 stp4020_queue_event(sc, i, 741 STP4020_EVENT_REMOVAL); 742 h->flags &= ~STP4020_SOCKET_BUSY; 743 } 744 } 745 } 746 747 if ((v & STP4020_ISR0_IOINT) != 0) { 748 /* we can not deny this is ours, no matter what the 749 card driver says. */ 750 r = 1; 751 752 /* It's a card interrupt */ 753 if ((h->flags & STP4020_SOCKET_BUSY) == 0) { 754 printf("stp4020[%d]: spurious interrupt?\n", 755 h->sock); 756 continue; 757 } 758 759 #ifndef SUN4U 760 /* 761 * Schedule softint to invoke driver interrupt 762 * handler 763 */ 764 if (h->softint != NULL) 765 sparc_softintr_schedule(h->softint); 766 /* 767 * Disable this sbus interrupt, until the soft-int 768 * handler had a chance to run 769 */ 770 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, h->int_disable); 771 #else 772 (*h->intrhandler)(h->intrarg); 773 #endif 774 } 775 776 /* informational messages */ 777 if ((v & STP4020_ISR0_BVD1CHG) != 0) { 778 /* ignore if this is caused by insert or removal */ 779 if (!cd_change) 780 printf("stp4020[%d]: Battery change 1\n", h->sock); 781 r = 1; 782 } 783 784 if ((v & STP4020_ISR0_BVD2CHG) != 0) { 785 /* ignore if this is caused by insert or removal */ 786 if (!cd_change) 787 printf("stp4020[%d]: Battery change 2\n", h->sock); 788 r = 1; 789 } 790 791 if ((v & STP4020_ISR0_SCINT) != 0) { 792 DPRINTF(("stp4020[%d]: status change\n", h->sock)); 793 r = 1; 794 } 795 796 if ((v & STP4020_ISR0_RDYCHG) != 0) { 797 DPRINTF(("stp4020[%d]: Ready/Busy change\n", h->sock)); 798 r = 1; 799 } 800 801 if ((v & STP4020_ISR0_WPCHG) != 0) { 802 DPRINTF(("stp4020[%d]: Write protect change\n", h->sock)); 803 r = 1; 804 } 805 806 if ((v & STP4020_ISR0_PCTO) != 0) { 807 DPRINTF(("stp4020[%d]: Card access timeout\n", h->sock)); 808 r = 1; 809 } 810 811 if ((v & ~STP4020_ISR0_LIVE) && r == 0) 812 printf("stp4020[%d]: unhandled interrupt: 0x%x\n", h->sock, v); 813 814 } 815 #ifndef SUN4U 816 splx(s); 817 #endif 818 819 return (r); 820 } 821 822 /* 823 * The function gets the sbus speed and a access time and calculates 824 * values for the CMDLNG and CMDDLAY registers. 825 */ 826 static void 827 stp4020_calc_speed(int bus_speed, int ns, int *length, int *cmd_delay) 828 { 829 int result; 830 831 if (ns < STP4020_MEM_SPEED_MIN) 832 ns = STP4020_MEM_SPEED_MIN; 833 else if (ns > STP4020_MEM_SPEED_MAX) 834 ns = STP4020_MEM_SPEED_MAX; 835 result = ns*(bus_speed/1000); 836 if (result % 1000000) 837 result = result/1000000 + 1; 838 else 839 result /= 1000000; 840 *length = result; 841 842 /* the sbus frequency range is limited, so we can keep this simple */ 843 *cmd_delay = ns <= STP4020_MEM_SPEED_MIN? 1 : 2; 844 } 845 846 static void 847 stp4020_map_window(struct stp4020_socket *h, int win, int speed) 848 { 849 int v, length, cmd_delay; 850 851 /* 852 * According to the PC Card standard 300ns access timing should be 853 * used for attribute memory access. Our pcmcia framework does not 854 * seem to propagate timing information, so we use that 855 * everywhere. 856 */ 857 stp4020_calc_speed(speed, (win==STP_WIN_ATTR)? 300 : 100, &length, &cmd_delay); 858 859 /* 860 * Fill in the Address Space Select and Base Address 861 * fields of this windows control register 0. 862 */ 863 v = ((cmd_delay << STP4020_WCR0_CMDDLY_S)&STP4020_WCR0_CMDDLY_M) 864 | ((length << STP4020_WCR0_CMDLNG_S)&STP4020_WCR0_CMDLNG_M); 865 switch (win) { 866 case STP_WIN_ATTR: 867 v |= STP4020_WCR0_ASPSEL_AM; 868 break; 869 case STP_WIN_MEM: 870 v |= STP4020_WCR0_ASPSEL_CM; 871 break; 872 case STP_WIN_IO: 873 v |= STP4020_WCR0_ASPSEL_IO; 874 break; 875 } 876 v |= (STP4020_ADDR2PAGE(0) & STP4020_WCR0_BASE_M); 877 stp4020_wr_winctl(h, win, STP4020_WCR0_IDX, v); 878 stp4020_wr_winctl(h, win, STP4020_WCR1_IDX, 1<<STP4020_WCR1_WAITREQ_S); 879 } 880 881 int 882 stp4020_chip_mem_alloc(pch, size, pcmhp) 883 pcmcia_chipset_handle_t pch; 884 bus_size_t size; 885 struct pcmcia_mem_handle *pcmhp; 886 { 887 struct stp4020_socket *h = (struct stp4020_socket *)pch; 888 889 /* we can not do much here, defere work to _mem_map */ 890 pcmhp->memt = h->pcmciat; 891 pcmhp->size = size; 892 pcmhp->addr = 0; 893 pcmhp->mhandle = 0; 894 pcmhp->realsize = size; 895 896 return (0); 897 } 898 899 void 900 stp4020_chip_mem_free(pch, pcmhp) 901 pcmcia_chipset_handle_t pch; 902 struct pcmcia_mem_handle *pcmhp; 903 { 904 } 905 906 int 907 stp4020_chip_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 908 pcmcia_chipset_handle_t pch; 909 int kind; 910 bus_addr_t card_addr; 911 bus_size_t size; 912 struct pcmcia_mem_handle *pcmhp; 913 bus_size_t *offsetp; 914 int *windowp; 915 { 916 struct stp4020_socket *h = (struct stp4020_socket *)pch; 917 int win = (kind&PCMCIA_MEM_ATTR)? STP_WIN_ATTR : STP_WIN_MEM; 918 919 pcmhp->memt = h->pcmciat; 920 bus_space_subregion(h->pcmciat, h->windows[win].winaddr, card_addr, size, &pcmhp->memh); 921 #ifdef SUN4U 922 if ((u_int8_t)pcmhp->memh._asi == ASI_PHYS_NON_CACHED) 923 pcmhp->memh._asi = ASI_PHYS_NON_CACHED_LITTLE; 924 else if ((u_int8_t)pcmhp->memh._asi == ASI_PRIMARY) 925 pcmhp->memh._asi = ASI_PRIMARY_LITTLE; 926 #endif 927 pcmhp->size = size; 928 pcmhp->realsize = STP4020_WINDOW_SIZE - card_addr; 929 *offsetp = 0; 930 *windowp = 0; 931 932 return (0); 933 } 934 935 void 936 stp4020_chip_mem_unmap(pch, win) 937 pcmcia_chipset_handle_t pch; 938 int win; 939 { 940 } 941 942 int 943 stp4020_chip_io_alloc(pch, start, size, align, pcihp) 944 pcmcia_chipset_handle_t pch; 945 bus_addr_t start; 946 bus_size_t size; 947 bus_size_t align; 948 struct pcmcia_io_handle *pcihp; 949 { 950 struct stp4020_socket *h = (struct stp4020_socket *)pch; 951 952 pcihp->iot = h->pcmciat; 953 pcihp->ioh = h->windows[STP_WIN_IO].winaddr; 954 return 0; 955 } 956 957 void 958 stp4020_chip_io_free(pch, pcihp) 959 pcmcia_chipset_handle_t pch; 960 struct pcmcia_io_handle *pcihp; 961 { 962 } 963 964 int 965 stp4020_chip_io_map(pch, width, offset, size, pcihp, windowp) 966 pcmcia_chipset_handle_t pch; 967 int width; 968 bus_addr_t offset; 969 bus_size_t size; 970 struct pcmcia_io_handle *pcihp; 971 int *windowp; 972 { 973 struct stp4020_socket *h = (struct stp4020_socket *)pch; 974 975 pcihp->iot = h->pcmciat; 976 bus_space_subregion(h->pcmciat, h->windows[STP_WIN_IO].winaddr, offset, size, &pcihp->ioh); 977 #ifdef SUN4U 978 if ((u_int8_t)pcihp->ioh._asi == ASI_PHYS_NON_CACHED) 979 pcihp->ioh._asi = ASI_PHYS_NON_CACHED_LITTLE; 980 else if ((u_int8_t)pcihp->ioh._asi == ASI_PRIMARY) 981 pcihp->ioh._asi = ASI_PRIMARY_LITTLE; 982 #endif 983 *windowp = 0; 984 return 0; 985 } 986 987 void 988 stp4020_chip_io_unmap(pch, win) 989 pcmcia_chipset_handle_t pch; 990 int win; 991 { 992 } 993 994 void 995 stp4020_chip_socket_enable(pch) 996 pcmcia_chipset_handle_t pch; 997 { 998 struct stp4020_socket *h = (struct stp4020_socket *)pch; 999 int i, v; 1000 1001 /* this bit is mostly stolen from pcic_attach_card */ 1002 1003 /* Power down the socket to reset it, clear the card reset pin */ 1004 stp4020_wr_sockctl(h, STP4020_ICR1_IDX, 0); 1005 1006 /* 1007 * wait 300ms until power fails (Tpf). Then, wait 100ms since 1008 * we are changing Vcc (Toff). 1009 */ 1010 stp4020_delay(h->sc, 300 + 100); 1011 1012 /* Power up the socket */ 1013 v = STP4020_ICR1_MSTPWR; 1014 stp4020_wr_sockctl(h, STP4020_ICR1_IDX, v); 1015 1016 /* 1017 * wait 100ms until power raise (Tpr) and 20ms to become 1018 * stable (Tsu(Vcc)). 1019 */ 1020 stp4020_delay(h->sc, 100 + 20); 1021 1022 v |= STP4020_ICR1_PCIFOE|STP4020_ICR1_VPP1_VCC; 1023 stp4020_wr_sockctl(h, STP4020_ICR1_IDX, v); 1024 1025 /* 1026 * hold RESET at least 10us. 1027 */ 1028 delay(10); 1029 1030 /* Clear reset flag, set to memory mode */ 1031 v = stp4020_rd_sockctl(h, STP4020_ICR0_IDX); 1032 v &= ~(STP4020_ICR0_IOIE | STP4020_ICR0_IOILVL | STP4020_ICR0_IFTYPE | 1033 STP4020_ICR0_SPKREN); 1034 v &= ~STP4020_ICR0_RESET; 1035 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, v); 1036 1037 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 1038 stp4020_delay(h->sc, 20); 1039 1040 /* Wait for the chip to finish initializing (5 seconds max) */ 1041 for (i = 10000; i > 0; i--) { 1042 v = stp4020_rd_sockctl(h, STP4020_ISR0_IDX); 1043 if ((v & STP4020_ISR0_RDYST) != 0) 1044 break; 1045 delay(500); 1046 } 1047 if (i <= 0) { 1048 char bits[64]; 1049 bitmask_snprintf(stp4020_rd_sockctl(h, STP4020_ISR0_IDX), 1050 STP4020_ISR0_IOBITS, bits, sizeof(bits)); 1051 printf("stp4020_chip_socket_enable: not ready: status %s\n", 1052 bits); 1053 return; 1054 } 1055 } 1056 1057 void 1058 stp4020_chip_socket_settype(pch, type) 1059 pcmcia_chipset_handle_t pch; 1060 int type; 1061 { 1062 struct stp4020_socket *h = (struct stp4020_socket *)pch; 1063 int v; 1064 1065 /* 1066 * Check the card type. 1067 * Enable socket I/O interrupts for IO cards. 1068 */ 1069 v = stp4020_rd_sockctl(h, STP4020_ICR0_IDX); 1070 v &= ~(STP4020_ICR0_IOIE | STP4020_ICR0_IOILVL | STP4020_ICR0_IFTYPE | 1071 STP4020_ICR0_SPKREN); 1072 if (type == PCMCIA_IFTYPE_IO) { 1073 v |= STP4020_ICR0_IFTYPE_IO|STP4020_ICR0_IOIE 1074 |STP4020_ICR0_SPKREN; 1075 v |= h->sbus_intno ? STP4020_ICR0_IOILVL_SB1 1076 : STP4020_ICR0_IOILVL_SB0; 1077 #ifndef SUN4U 1078 h->int_enable = v; 1079 h->int_disable = v & ~STP4020_ICR0_IOIE; 1080 #endif 1081 DPRINTF(("%s: configuring card for IO useage\n", device_xname(&h->sc->sc_dev))); 1082 } else { 1083 v |= STP4020_ICR0_IFTYPE_MEM; 1084 #ifndef SUN4U 1085 h->int_enable = h->int_disable = v; 1086 #endif 1087 DPRINTF(("%s: configuring card for IO useage\n", device_xname(&h->sc->sc_dev))); 1088 DPRINTF(("%s: configuring card for MEM ONLY useage\n", device_xname(&h->sc->sc_dev))); 1089 } 1090 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, v); 1091 } 1092 1093 void 1094 stp4020_chip_socket_disable(pch) 1095 pcmcia_chipset_handle_t pch; 1096 { 1097 struct stp4020_socket *h = (struct stp4020_socket *)pch; 1098 int v; 1099 1100 /* 1101 * Disable socket I/O interrupts. 1102 */ 1103 v = stp4020_rd_sockctl(h, STP4020_ICR0_IDX); 1104 v &= ~(STP4020_ICR0_IOIE | STP4020_ICR0_IOILVL | STP4020_ICR0_IFTYPE | 1105 STP4020_ICR0_SPKREN); 1106 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, v); 1107 1108 /* Power down the socket */ 1109 stp4020_wr_sockctl(h, STP4020_ICR1_IDX, 0); 1110 1111 /* 1112 * wait 300ms until power fails (Tpf). 1113 */ 1114 stp4020_delay(h->sc, 300); 1115 } 1116 1117 void * 1118 stp4020_chip_intr_establish(pch, pf, ipl, handler, arg) 1119 pcmcia_chipset_handle_t pch; 1120 struct pcmcia_function *pf; 1121 int ipl; 1122 int (*handler)(void *); 1123 void *arg; 1124 { 1125 struct stp4020_socket *h = (struct stp4020_socket *)pch; 1126 1127 /* only one interrupt handler per slot */ 1128 if (h->intrhandler != NULL) return NULL; 1129 1130 h->intrhandler = handler; 1131 h->intrarg = arg; 1132 #ifndef SUN4U 1133 if (h->sc->sc_use_softint) { 1134 h->softint = sparc_softintr_establish(ipl, stp4020_intr_dispatch, h); 1135 return h->softint; 1136 } 1137 #endif 1138 return h; 1139 } 1140 1141 void 1142 stp4020_chip_intr_disestablish(pch, ih) 1143 pcmcia_chipset_handle_t pch; 1144 void *ih; 1145 { 1146 struct stp4020_socket *h = (struct stp4020_socket *)pch; 1147 1148 h->intrhandler = NULL; 1149 h->intrarg = NULL; 1150 #ifndef SUN4U 1151 if (h->softint) { 1152 sparc_softintr_disestablish(h->softint); 1153 h->softint = NULL; 1154 } 1155 #endif 1156 } 1157 1158 /* 1159 * Delay and possibly yield CPU. 1160 * XXX - assumes a context 1161 */ 1162 void 1163 stp4020_delay(sc, ms) 1164 struct stp4020_softc *sc; 1165 unsigned int ms; 1166 { 1167 unsigned int ticks = mstohz(ms); 1168 1169 if (cold || ticks == 0) { 1170 delay(ms); 1171 return; 1172 } 1173 1174 #ifdef DIAGNOSTIC 1175 if (ticks > 60*hz) 1176 panic("stp4020: preposterous delay: %u", ticks); 1177 #endif 1178 tsleep(sc, 0, "nelldel", ticks); 1179 } 1180 1181 #ifdef STP4020_DEBUG 1182 void 1183 stp4020_dump_regs(h) 1184 struct stp4020_socket *h; 1185 { 1186 char bits[64]; 1187 /* 1188 * Dump control and status registers. 1189 */ 1190 printf("socket[%d] registers:\n", h->sock); 1191 bitmask_snprintf(stp4020_rd_sockctl(h, STP4020_ICR0_IDX), 1192 STP4020_ICR0_BITS, bits, sizeof(bits)); 1193 printf("\tICR0=%s\n", bits); 1194 1195 bitmask_snprintf(stp4020_rd_sockctl(h, STP4020_ICR1_IDX), 1196 STP4020_ICR1_BITS, bits, sizeof(bits)); 1197 printf("\tICR1=%s\n", bits); 1198 1199 bitmask_snprintf(stp4020_rd_sockctl(h, STP4020_ISR0_IDX), 1200 STP4020_ISR0_IOBITS, bits, sizeof(bits)); 1201 printf("\tISR0=%s\n", bits); 1202 1203 bitmask_snprintf(stp4020_rd_sockctl(h, STP4020_ISR1_IDX), 1204 STP4020_ISR1_BITS, bits, sizeof(bits)); 1205 printf("\tISR1=%s\n", bits); 1206 } 1207 #endif /* STP4020_DEBUG */ 1208
Indexes created Mon Oct 20 05:10:11 GMT 2025