stp4020.c revision 1.54
1 /* $NetBSD: stp4020.c,v 1.54 2008/04/05 18:35:32 cegger Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * STP4020: SBus/PCMCIA bridge supporting two Type-3 PCMCIA cards. 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: stp4020.c,v 1.54 2008/04/05 18:35:32 cegger Exp $"); 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/errno.h> 49 #include <sys/malloc.h> 50 #include <sys/extent.h> 51 #include <sys/proc.h> 52 #include <sys/kernel.h> 53 #include <sys/kthread.h> 54 #include <sys/device.h> 55 #include <sys/intr.h> 56 57 #include <dev/pcmcia/pcmciareg.h> 58 #include <dev/pcmcia/pcmciavar.h> 59 #include <dev/pcmcia/pcmciachip.h> 60 61 #include <sys/bus.h> 62 63 #include <dev/sbus/sbusvar.h> 64 #include <dev/sbus/stp4020reg.h> 65 66 #define STP4020_DEBUG 1 /* XXX-temp */ 67 68 /* 69 * We use the three available windows per socket in a simple, fixed 70 * arrangement. Each window maps (at full 1 MB size) one of the pcmcia 71 * spaces into sbus space. 72 */ 73 #define STP_WIN_ATTR 0 /* index of the attribute memory space window */ 74 #define STP_WIN_MEM 1 /* index of the common memory space window */ 75 #define STP_WIN_IO 2 /* index of the io space window */ 76 77 78 #if defined(STP4020_DEBUG) 79 int stp4020_debug = 0; 80 #define DPRINTF(x) do { if (stp4020_debug) printf x; } while(0) 81 #else 82 #define DPRINTF(x) 83 #endif 84 85 /* 86 * Event queue; events detected in an interrupt context go here 87 * awaiting attention from our event handling thread. 88 */ 89 struct stp4020_event { 90 SIMPLEQ_ENTRY(stp4020_event) se_q; 91 int se_type; 92 int se_sock; 93 }; 94 /* Defined event types */ 95 #define STP4020_EVENT_INSERTION 0 96 #define STP4020_EVENT_REMOVAL 1 97 98 /* 99 * Per socket data. 100 */ 101 struct stp4020_socket { 102 struct stp4020_softc *sc; /* Back link */ 103 int flags; 104 #define STP4020_SOCKET_BUSY 0x0001 105 int sock; /* Socket number (0 or 1) */ 106 int sbus_intno; /* Do we use first (0) or second (1) 107 interrupt? */ 108 #ifndef SUN4U 109 int int_enable; /* ICR0 value for interrupt enabled */ 110 int int_disable; /* ICR0 value for interrupt disabled */ 111 #endif 112 bus_space_tag_t tag; /* socket control io */ 113 bus_space_handle_t regs; /* space */ 114 bus_space_tag_t pcmciat; /* io space for pcmcia */ 115 struct device *pcmcia; /* Associated PCMCIA device */ 116 int (*intrhandler) /* Card driver interrupt handler */ 117 (void *); 118 void *intrarg; /* Card interrupt handler argument */ 119 #ifndef SUN4U 120 void *softint; /* cookie for the softintr */ 121 #endif 122 123 struct { 124 bus_space_handle_t winaddr;/* this window's address */ 125 } windows[STP4020_NWIN]; 126 127 }; 128 129 struct stp4020_softc { 130 struct device sc_dev; /* Base device */ 131 struct sbusdev sc_sd; /* SBus device */ 132 pcmcia_chipset_tag_t sc_pct; /* Chipset methods */ 133 134 struct lwp *event_thread; /* event handling thread */ 135 SIMPLEQ_HEAD(, stp4020_event) events; /* Pending events for thread */ 136 137 struct stp4020_socket sc_socks[STP4020_NSOCK]; 138 #ifndef SUN4U 139 bool sc_use_softint; 140 #endif 141 }; 142 143 144 static int stp4020print(void *, const char *); 145 static int stp4020match(struct device *, struct cfdata *, void *); 146 static void stp4020attach(struct device *, struct device *, void *); 147 static int stp4020_intr(void *); 148 static void stp4020_map_window(struct stp4020_socket *h, int win, int speed); 149 static void stp4020_calc_speed(int bus_speed, int ns, int *length, int *cmd_delay); 150 #ifndef SUN4U 151 static void stp4020_intr_dispatch(void *arg); 152 #endif 153 154 CFATTACH_DECL(nell, sizeof(struct stp4020_softc), 155 stp4020match, stp4020attach, NULL, NULL); 156 157 #ifdef STP4020_DEBUG 158 static void stp4020_dump_regs(struct stp4020_socket *); 159 #endif 160 161 static int stp4020_rd_sockctl(struct stp4020_socket *, int); 162 static void stp4020_wr_sockctl(struct stp4020_socket *, int, int); 163 static int stp4020_rd_winctl(struct stp4020_socket *, int, int); 164 static void stp4020_wr_winctl(struct stp4020_socket *, int, int, int); 165 166 void stp4020_delay(struct stp4020_softc *sc, unsigned int); 167 void stp4020_attach_socket(struct stp4020_socket *, int); 168 void stp4020_event_thread(void *); 169 void stp4020_queue_event(struct stp4020_softc *, int, int); 170 171 int stp4020_chip_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 172 struct pcmcia_mem_handle *); 173 void stp4020_chip_mem_free(pcmcia_chipset_handle_t, 174 struct pcmcia_mem_handle *); 175 int stp4020_chip_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 176 bus_size_t, struct pcmcia_mem_handle *, 177 bus_size_t *, int *); 178 void stp4020_chip_mem_unmap(pcmcia_chipset_handle_t, int); 179 180 int stp4020_chip_io_alloc(pcmcia_chipset_handle_t, 181 bus_addr_t, bus_size_t, bus_size_t, 182 struct pcmcia_io_handle *); 183 void stp4020_chip_io_free(pcmcia_chipset_handle_t, 184 struct pcmcia_io_handle *); 185 int stp4020_chip_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 186 bus_size_t, struct pcmcia_io_handle *, int *); 187 void stp4020_chip_io_unmap(pcmcia_chipset_handle_t, int); 188 189 void stp4020_chip_socket_enable(pcmcia_chipset_handle_t); 190 void stp4020_chip_socket_disable(pcmcia_chipset_handle_t); 191 void stp4020_chip_socket_settype(pcmcia_chipset_handle_t, int); 192 void *stp4020_chip_intr_establish(pcmcia_chipset_handle_t, 193 struct pcmcia_function *, int, 194 int (*)(void *), void *); 195 void stp4020_chip_intr_disestablish(pcmcia_chipset_handle_t, void *); 196 197 /* Our PCMCIA chipset methods */ 198 static struct pcmcia_chip_functions stp4020_functions = { 199 stp4020_chip_mem_alloc, 200 stp4020_chip_mem_free, 201 stp4020_chip_mem_map, 202 stp4020_chip_mem_unmap, 203 204 stp4020_chip_io_alloc, 205 stp4020_chip_io_free, 206 stp4020_chip_io_map, 207 stp4020_chip_io_unmap, 208 209 stp4020_chip_intr_establish, 210 stp4020_chip_intr_disestablish, 211 212 stp4020_chip_socket_enable, 213 stp4020_chip_socket_disable, 214 stp4020_chip_socket_settype, 215 NULL 216 }; 217 218 219 static inline int 220 stp4020_rd_sockctl(h, idx) 221 struct stp4020_socket *h; 222 int idx; 223 { 224 int o = ((STP4020_SOCKREGS_SIZE * (h->sock)) + idx); 225 return (bus_space_read_2(h->tag, h->regs, o)); 226 } 227 228 static inline void 229 stp4020_wr_sockctl(h, idx, v) 230 struct stp4020_socket *h; 231 int idx; 232 int v; 233 { 234 int o = (STP4020_SOCKREGS_SIZE * (h->sock)) + idx; 235 bus_space_write_2(h->tag, h->regs, o, v); 236 } 237 238 static inline int 239 stp4020_rd_winctl(h, win, idx) 240 struct stp4020_socket *h; 241 int win; 242 int idx; 243 { 244 int o = (STP4020_SOCKREGS_SIZE * (h->sock)) + 245 (STP4020_WINREGS_SIZE * win) + idx; 246 return (bus_space_read_2(h->tag, h->regs, o)); 247 } 248 249 static inline void 250 stp4020_wr_winctl(h, win, idx, v) 251 struct stp4020_socket *h; 252 int win; 253 int idx; 254 int v; 255 { 256 int o = (STP4020_SOCKREGS_SIZE * (h->sock)) + 257 (STP4020_WINREGS_SIZE * win) + idx; 258 259 bus_space_write_2(h->tag, h->regs, o, v); 260 } 261 262 #ifndef SUN4U /* XXX - move to SBUS machdep function? */ 263 264 static u_int16_t stp4020_read_2(bus_space_tag_t, 265 bus_space_handle_t, 266 bus_size_t); 267 static u_int32_t stp4020_read_4(bus_space_tag_t, 268 bus_space_handle_t, 269 bus_size_t); 270 static u_int64_t stp4020_read_8(bus_space_tag_t, 271 bus_space_handle_t, 272 bus_size_t); 273 static void stp4020_write_2(bus_space_tag_t, 274 bus_space_handle_t, 275 bus_size_t, 276 u_int16_t); 277 static void stp4020_write_4(bus_space_tag_t, 278 bus_space_handle_t, 279 bus_size_t, 280 u_int32_t); 281 static void stp4020_write_8(bus_space_tag_t, 282 bus_space_handle_t, 283 bus_size_t, 284 u_int64_t); 285 286 static u_int16_t 287 stp4020_read_2(space, handle, offset) 288 bus_space_tag_t space; 289 bus_space_handle_t handle; 290 bus_size_t offset; 291 { 292 return (le16toh(*(volatile u_int16_t *)(handle + offset))); 293 } 294 295 static u_int32_t 296 stp4020_read_4(space, handle, offset) 297 bus_space_tag_t space; 298 bus_space_handle_t handle; 299 bus_size_t offset; 300 { 301 return (le32toh(*(volatile u_int32_t *)(handle + offset))); 302 } 303 304 static u_int64_t 305 stp4020_read_8(space, handle, offset) 306 bus_space_tag_t space; 307 bus_space_handle_t handle; 308 bus_size_t offset; 309 { 310 return (le64toh(*(volatile u_int64_t *)(handle + offset))); 311 } 312 313 static void 314 stp4020_write_2(space, handle, offset, value) 315 bus_space_tag_t space; 316 bus_space_handle_t handle; 317 bus_size_t offset; 318 u_int16_t value; 319 { 320 (*(volatile u_int16_t *)(handle + offset)) = htole16(value); 321 } 322 323 static void 324 stp4020_write_4(space, handle, offset, value) 325 bus_space_tag_t space; 326 bus_space_handle_t handle; 327 bus_size_t offset; 328 u_int32_t value; 329 { 330 (*(volatile u_int32_t *)(handle + offset)) = htole32(value); 331 } 332 333 static void 334 stp4020_write_8(space, handle, offset, value) 335 bus_space_tag_t space; 336 bus_space_handle_t handle; 337 bus_size_t offset; 338 u_int64_t value; 339 { 340 (*(volatile u_int64_t *)(handle + offset)) = htole64(value); 341 } 342 #endif /* SUN4U */ 343 344 int 345 stp4020print(aux, busname) 346 void *aux; 347 const char *busname; 348 { 349 struct pcmciabus_attach_args *paa = aux; 350 struct stp4020_socket *h = paa->pch; 351 352 aprint_normal(" socket %d", h->sock); 353 return (UNCONF); 354 } 355 356 int 357 stp4020match(parent, cf, aux) 358 struct device *parent; 359 struct cfdata *cf; 360 void *aux; 361 { 362 struct sbus_attach_args *sa = aux; 363 364 return (strcmp("SUNW,pcmcia", sa->sa_name) == 0); 365 } 366 367 /* 368 * Attach all the sub-devices we can find 369 */ 370 void 371 stp4020attach(parent, self, aux) 372 struct device *parent, *self; 373 void *aux; 374 { 375 struct sbus_attach_args *sa = aux; 376 struct stp4020_softc *sc = (void *)self; 377 bus_space_tag_t tag; 378 int rev, i, sbus_intno, hw_ipl; 379 bus_space_handle_t bh; 380 381 /* Transfer bus tags */ 382 #ifdef SUN4U 383 tag = sa->sa_bustag; 384 #else 385 tag = bus_space_tag_alloc(sa->sa_bustag, sc); 386 if (tag == NULL) { 387 aprint_error_dev(self, "attach: out of memory\n"); 388 return; 389 } 390 tag->sparc_read_2 = stp4020_read_2; 391 tag->sparc_read_4 = stp4020_read_4; 392 tag->sparc_read_8 = stp4020_read_8; 393 tag->sparc_write_2 = stp4020_write_2; 394 tag->sparc_write_4 = stp4020_write_4; 395 tag->sparc_write_8 = stp4020_write_8; 396 #endif /* SUN4U */ 397 398 /* check interrupt options, decide if we need a softint */ 399 #ifdef SUN4U 400 /* 401 * On sparc64 the hardware interrupt priority does not restrict 402 * the IPL we run our interrupt handler on, so we can always just 403 * use the first interrupt and reqest the handler to run at 404 * IPL_VM. 405 */ 406 sbus_intno = 0; 407 hw_ipl = IPL_VM; 408 #else 409 /* 410 * We need to check if one of the available interrupts has 411 * a priority that allows us to establish a handler at IPL_VM. 412 * If not (hard to imagine), use a soft interrupt. 413 */ 414 sbus_intno = -1; 415 for (i = 0; i < sa->sa_nintr; i++) { 416 struct sbus_softc *bus = 417 (struct sbus_softc *) sa->sa_bustag->cookie; 418 int ipl = bus->sc_intr2ipl[sa->sa_intr[i].oi_pri]; 419 if (ipl <= IPL_VM) { 420 sbus_intno = i; 421 sc->sc_use_softint = false; 422 hw_ipl = IPL_VM; 423 break; 424 } 425 } 426 if (sbus_intno == -1) { 427 /* 428 * We have not found a usable hardware interrupt - so 429 * use a softint to bounce to the proper IPL. 430 */ 431 printf("no usable HW interrupt found, using softint\n"); 432 sbus_intno = 0; 433 sc->sc_use_softint = true; 434 hw_ipl = IPL_NONE; 435 } 436 #endif 437 438 /* Set up per-socket static initialization */ 439 sc->sc_socks[0].sc = sc->sc_socks[1].sc = sc; 440 sc->sc_socks[0].tag = sc->sc_socks[1].tag = sa->sa_bustag; 441 /* 442 * XXX we rely on "tag" accepting the same handle-domain 443 * as sa->sa_bustag. 444 */ 445 sc->sc_socks[0].pcmciat = sc->sc_socks[1].pcmciat = tag; 446 sc->sc_socks[0].sbus_intno = 447 sc->sc_socks[1].sbus_intno = sbus_intno; 448 449 if (sa->sa_nreg < 8) { 450 printf("%s: only %d register sets\n", 451 device_xname(self), sa->sa_nreg); 452 return; 453 } 454 455 if (sa->sa_nintr != 2) { 456 printf("%s: expect 2 interrupt Sbus levels; got %d\n", 457 device_xname(self), sa->sa_nintr); 458 return; 459 } 460 461 #define STP4020_BANK_PROM 0 462 #define STP4020_BANK_CTRL 4 463 for (i = 0; i < 8; i++) { 464 465 /* 466 * STP4020 Register address map: 467 * bank 0: Forth PROM 468 * banks 1-3: socket 0, windows 0-2 469 * bank 4: control registers 470 * banks 5-7: socket 1, windows 0-2 471 */ 472 473 if (i == STP4020_BANK_PROM) 474 /* Skip the PROM */ 475 continue; 476 477 if (sbus_bus_map(sa->sa_bustag, 478 sa->sa_reg[i].oa_space, 479 sa->sa_reg[i].oa_base, 480 sa->sa_reg[i].oa_size, 481 0, &bh) != 0) { 482 aprint_error_dev(self, "attach: cannot map registers\n"); 483 return; 484 } 485 486 if (i == STP4020_BANK_CTRL) { 487 /* 488 * Copy tag and handle to both socket structures 489 * for easy access in control/status IO functions. 490 */ 491 sc->sc_socks[0].regs = sc->sc_socks[1].regs = bh; 492 } else if (i < STP4020_BANK_CTRL) { 493 /* banks 1-3 */ 494 sc->sc_socks[0].windows[i-1].winaddr = bh; 495 } else { 496 /* banks 5-7 */ 497 sc->sc_socks[1].windows[i-5].winaddr = bh; 498 } 499 } 500 501 sbus_establish(&sc->sc_sd, &sc->sc_dev); 502 503 /* We only use one interrupt level. */ 504 if (sa->sa_nintr > sbus_intno) { 505 bus_intr_establish(sa->sa_bustag, 506 sa->sa_intr[sbus_intno].oi_pri, 507 hw_ipl, stp4020_intr, sc); 508 } 509 510 rev = stp4020_rd_sockctl(&sc->sc_socks[0], STP4020_ISR1_IDX) & 511 STP4020_ISR1_REV_M; 512 printf(": rev %x\n", rev); 513 514 sc->sc_pct = (pcmcia_chipset_tag_t)&stp4020_functions; 515 516 SIMPLEQ_INIT(&sc->events); 517 518 for (i = 0; i < STP4020_NSOCK; i++) { 519 struct stp4020_socket *h = &sc->sc_socks[i]; 520 h->sock = i; 521 h->sc = sc; 522 #ifdef STP4020_DEBUG 523 if (stp4020_debug) 524 stp4020_dump_regs(h); 525 #endif 526 stp4020_attach_socket(h, sa->sa_frequency); 527 } 528 529 /* 530 * Arrange that a kernel thread be created to handle 531 * insert/removal events. 532 */ 533 if (kthread_create(PRI_NONE, 0, NULL, stp4020_event_thread, sc, 534 &sc->event_thread, "%s", device_xname(self))) { 535 panic("%s: unable to create event thread", device_xname(self)); 536 } 537 } 538 539 void 540 stp4020_attach_socket(h, speed) 541 struct stp4020_socket *h; 542 int speed; 543 { 544 struct pcmciabus_attach_args paa; 545 int v; 546 547 /* no interrupt handlers yet */ 548 h->intrhandler = NULL; 549 h->intrarg = NULL; 550 #ifndef SUN4U 551 h->softint = NULL; 552 h->int_enable = 0; 553 h->int_disable = 0; 554 #endif 555 556 /* Map all three windows */ 557 stp4020_map_window(h, STP_WIN_ATTR, speed); 558 stp4020_map_window(h, STP_WIN_MEM, speed); 559 stp4020_map_window(h, STP_WIN_IO, speed); 560 561 /* Configure one pcmcia device per socket */ 562 paa.paa_busname = "pcmcia"; 563 paa.pct = (pcmcia_chipset_tag_t)h->sc->sc_pct; 564 paa.pch = (pcmcia_chipset_handle_t)h; 565 paa.iobase = 0; 566 paa.iosize = STP4020_WINDOW_SIZE; 567 568 h->pcmcia = config_found(&h->sc->sc_dev, &paa, stp4020print); 569 570 if (h->pcmcia == NULL) 571 return; 572 573 /* 574 * There's actually a pcmcia bus attached; initialize the slot. 575 */ 576 577 /* 578 * Clear things up before we enable status change interrupts. 579 * This seems to not be fully initialized by the PROM. 580 */ 581 stp4020_wr_sockctl(h, STP4020_ICR1_IDX, 0); 582 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, 0); 583 stp4020_wr_sockctl(h, STP4020_ISR1_IDX, 0x3fff); 584 stp4020_wr_sockctl(h, STP4020_ISR0_IDX, 0x3fff); 585 586 /* 587 * Enable socket status change interrupts. 588 * We only use one common interrupt for status change 589 * and IO, to avoid locking issues. 590 */ 591 v = STP4020_ICR0_ALL_STATUS_IE 592 | (h->sbus_intno ? STP4020_ICR0_SCILVL_SB1 593 : STP4020_ICR0_SCILVL_SB0); 594 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, v); 595 596 /* Get live status bits from ISR0 and clear pending interrupts */ 597 v = stp4020_rd_sockctl(h, STP4020_ISR0_IDX); 598 stp4020_wr_sockctl(h, STP4020_ISR0_IDX, v); 599 600 if ((v & (STP4020_ISR0_CD1ST|STP4020_ISR0_CD2ST)) == 0) 601 return; 602 603 pcmcia_card_attach(h->pcmcia); 604 h->flags |= STP4020_SOCKET_BUSY; 605 } 606 607 /* 608 * The actual event handling thread. 609 */ 610 void 611 stp4020_event_thread(arg) 612 void *arg; 613 { 614 struct stp4020_softc *sc = arg; 615 struct stp4020_event *e; 616 int s; 617 618 while (1) { 619 struct stp4020_socket *h; 620 int n; 621 622 s = splhigh(); 623 if ((e = SIMPLEQ_FIRST(&sc->events)) == NULL) { 624 splx(s); 625 (void)tsleep(&sc->events, PWAIT, "nellevt", 0); 626 continue; 627 } 628 SIMPLEQ_REMOVE_HEAD(&sc->events, se_q); 629 splx(s); 630 631 n = e->se_sock; 632 if (n < 0 || n >= STP4020_NSOCK) 633 panic("stp4020_event_thread: wayward socket number %d", 634 n); 635 636 h = &sc->sc_socks[n]; 637 switch (e->se_type) { 638 case STP4020_EVENT_INSERTION: 639 pcmcia_card_attach(h->pcmcia); 640 break; 641 case STP4020_EVENT_REMOVAL: 642 pcmcia_card_detach(h->pcmcia, DETACH_FORCE); 643 break; 644 default: 645 panic("stp4020_event_thread: unknown event type %d", 646 e->se_type); 647 } 648 free(e, M_TEMP); 649 } 650 } 651 652 void 653 stp4020_queue_event(sc, sock, event) 654 struct stp4020_softc *sc; 655 int sock, event; 656 { 657 struct stp4020_event *e; 658 int s; 659 660 e = malloc(sizeof(*e), M_TEMP, M_NOWAIT); 661 if (e == NULL) 662 panic("stp4020_queue_event: can't allocate event"); 663 664 e->se_type = event; 665 e->se_sock = sock; 666 s = splhigh(); 667 SIMPLEQ_INSERT_TAIL(&sc->events, e, se_q); 668 splx(s); 669 wakeup(&sc->events); 670 } 671 672 #ifndef SUN4U 673 /* 674 * Softinterrupt called to invoke the real driver interrupt handler. 675 */ 676 static void 677 stp4020_intr_dispatch(arg) 678 void *arg; 679 { 680 struct stp4020_socket *h = arg; 681 int s; 682 683 /* invoke driver handler */ 684 h->intrhandler(h->intrarg); 685 686 /* enable SBUS interrupts for pcmcia interrupts again */ 687 s = splhigh(); 688 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, h->int_enable); 689 splx(s); 690 } 691 #endif 692 693 int 694 stp4020_intr(arg) 695 void *arg; 696 { 697 struct stp4020_softc *sc = arg; 698 #ifndef SUN4U 699 int s; 700 #endif 701 int i, r = 0, cd_change = 0; 702 703 704 #ifndef SUN4U 705 /* protect hardware access by splhigh against softint */ 706 s = splhigh(); 707 #endif 708 709 /* 710 * Check each socket for pending requests. 711 */ 712 for (i = 0 ; i < STP4020_NSOCK; i++) { 713 struct stp4020_socket *h; 714 int v; 715 716 h = &sc->sc_socks[i]; 717 718 v = stp4020_rd_sockctl(h, STP4020_ISR0_IDX); 719 720 /* Ack all interrupts at once. */ 721 stp4020_wr_sockctl(h, STP4020_ISR0_IDX, v); 722 723 #ifdef STP4020_DEBUG 724 if (stp4020_debug != 0) { 725 char bits[64]; 726 bitmask_snprintf(v, STP4020_ISR0_IOBITS, 727 bits, sizeof(bits)); 728 printf("stp4020_statintr: ISR0=%s\n", bits); 729 } 730 #endif 731 732 if ((v & STP4020_ISR0_CDCHG) != 0) { 733 /* 734 * Card status change detect 735 */ 736 cd_change = 1; 737 r = 1; 738 if ((v & (STP4020_ISR0_CD1ST|STP4020_ISR0_CD2ST)) == (STP4020_ISR0_CD1ST|STP4020_ISR0_CD2ST)){ 739 if ((h->flags & STP4020_SOCKET_BUSY) == 0) { 740 stp4020_queue_event(sc, i, 741 STP4020_EVENT_INSERTION); 742 h->flags |= STP4020_SOCKET_BUSY; 743 } 744 } 745 if ((v & (STP4020_ISR0_CD1ST|STP4020_ISR0_CD2ST)) == 0){ 746 if ((h->flags & STP4020_SOCKET_BUSY) != 0) { 747 stp4020_queue_event(sc, i, 748 STP4020_EVENT_REMOVAL); 749 h->flags &= ~STP4020_SOCKET_BUSY; 750 } 751 } 752 } 753 754 if ((v & STP4020_ISR0_IOINT) != 0) { 755 /* we can not deny this is ours, no matter what the 756 card driver says. */ 757 r = 1; 758 759 /* It's a card interrupt */ 760 if ((h->flags & STP4020_SOCKET_BUSY) == 0) { 761 printf("stp4020[%d]: spurious interrupt?\n", 762 h->sock); 763 continue; 764 } 765 766 #ifndef SUN4U 767 /* 768 * Schedule softint to invoke driver interrupt 769 * handler 770 */ 771 if (h->softint != NULL) 772 sparc_softintr_schedule(h->softint); 773 /* 774 * Disable this sbus interrupt, until the soft-int 775 * handler had a chance to run 776 */ 777 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, h->int_disable); 778 #else 779 (*h->intrhandler)(h->intrarg); 780 #endif 781 } 782 783 /* informational messages */ 784 if ((v & STP4020_ISR0_BVD1CHG) != 0) { 785 /* ignore if this is caused by insert or removal */ 786 if (!cd_change) 787 printf("stp4020[%d]: Battery change 1\n", h->sock); 788 r = 1; 789 } 790 791 if ((v & STP4020_ISR0_BVD2CHG) != 0) { 792 /* ignore if this is caused by insert or removal */ 793 if (!cd_change) 794 printf("stp4020[%d]: Battery change 2\n", h->sock); 795 r = 1; 796 } 797 798 if ((v & STP4020_ISR0_SCINT) != 0) { 799 DPRINTF(("stp4020[%d]: status change\n", h->sock)); 800 r = 1; 801 } 802 803 if ((v & STP4020_ISR0_RDYCHG) != 0) { 804 DPRINTF(("stp4020[%d]: Ready/Busy change\n", h->sock)); 805 r = 1; 806 } 807 808 if ((v & STP4020_ISR0_WPCHG) != 0) { 809 DPRINTF(("stp4020[%d]: Write protect change\n", h->sock)); 810 r = 1; 811 } 812 813 if ((v & STP4020_ISR0_PCTO) != 0) { 814 DPRINTF(("stp4020[%d]: Card access timeout\n", h->sock)); 815 r = 1; 816 } 817 818 if ((v & ~STP4020_ISR0_LIVE) && r == 0) 819 printf("stp4020[%d]: unhandled interrupt: 0x%x\n", h->sock, v); 820 821 } 822 #ifndef SUN4U 823 splx(s); 824 #endif 825 826 return (r); 827 } 828 829 /* 830 * The function gets the sbus speed and a access time and calculates 831 * values for the CMDLNG and CMDDLAY registers. 832 */ 833 static void 834 stp4020_calc_speed(int bus_speed, int ns, int *length, int *cmd_delay) 835 { 836 int result; 837 838 if (ns < STP4020_MEM_SPEED_MIN) 839 ns = STP4020_MEM_SPEED_MIN; 840 else if (ns > STP4020_MEM_SPEED_MAX) 841 ns = STP4020_MEM_SPEED_MAX; 842 result = ns*(bus_speed/1000); 843 if (result % 1000000) 844 result = result/1000000 + 1; 845 else 846 result /= 1000000; 847 *length = result; 848 849 /* the sbus frequency range is limited, so we can keep this simple */ 850 *cmd_delay = ns <= STP4020_MEM_SPEED_MIN? 1 : 2; 851 } 852 853 static void 854 stp4020_map_window(struct stp4020_socket *h, int win, int speed) 855 { 856 int v, length, cmd_delay; 857 858 /* 859 * According to the PC Card standard 300ns access timing should be 860 * used for attribute memory access. Our pcmcia framework does not 861 * seem to propagate timing information, so we use that 862 * everywhere. 863 */ 864 stp4020_calc_speed(speed, (win==STP_WIN_ATTR)? 300 : 100, &length, &cmd_delay); 865 866 /* 867 * Fill in the Address Space Select and Base Address 868 * fields of this windows control register 0. 869 */ 870 v = ((cmd_delay << STP4020_WCR0_CMDDLY_S)&STP4020_WCR0_CMDDLY_M) 871 | ((length << STP4020_WCR0_CMDLNG_S)&STP4020_WCR0_CMDLNG_M); 872 switch (win) { 873 case STP_WIN_ATTR: 874 v |= STP4020_WCR0_ASPSEL_AM; 875 break; 876 case STP_WIN_MEM: 877 v |= STP4020_WCR0_ASPSEL_CM; 878 break; 879 case STP_WIN_IO: 880 v |= STP4020_WCR0_ASPSEL_IO; 881 break; 882 } 883 v |= (STP4020_ADDR2PAGE(0) & STP4020_WCR0_BASE_M); 884 stp4020_wr_winctl(h, win, STP4020_WCR0_IDX, v); 885 stp4020_wr_winctl(h, win, STP4020_WCR1_IDX, 1<<STP4020_WCR1_WAITREQ_S); 886 } 887 888 int 889 stp4020_chip_mem_alloc(pch, size, pcmhp) 890 pcmcia_chipset_handle_t pch; 891 bus_size_t size; 892 struct pcmcia_mem_handle *pcmhp; 893 { 894 struct stp4020_socket *h = (struct stp4020_socket *)pch; 895 896 /* we can not do much here, defere work to _mem_map */ 897 pcmhp->memt = h->pcmciat; 898 pcmhp->size = size; 899 pcmhp->addr = 0; 900 pcmhp->mhandle = 0; 901 pcmhp->realsize = size; 902 903 return (0); 904 } 905 906 void 907 stp4020_chip_mem_free(pch, pcmhp) 908 pcmcia_chipset_handle_t pch; 909 struct pcmcia_mem_handle *pcmhp; 910 { 911 } 912 913 int 914 stp4020_chip_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 915 pcmcia_chipset_handle_t pch; 916 int kind; 917 bus_addr_t card_addr; 918 bus_size_t size; 919 struct pcmcia_mem_handle *pcmhp; 920 bus_size_t *offsetp; 921 int *windowp; 922 { 923 struct stp4020_socket *h = (struct stp4020_socket *)pch; 924 int win = (kind&PCMCIA_MEM_ATTR)? STP_WIN_ATTR : STP_WIN_MEM; 925 926 pcmhp->memt = h->pcmciat; 927 bus_space_subregion(h->pcmciat, h->windows[win].winaddr, card_addr, size, &pcmhp->memh); 928 #ifdef SUN4U 929 if ((u_int8_t)pcmhp->memh._asi == ASI_PHYS_NON_CACHED) 930 pcmhp->memh._asi = ASI_PHYS_NON_CACHED_LITTLE; 931 else if ((u_int8_t)pcmhp->memh._asi == ASI_PRIMARY) 932 pcmhp->memh._asi = ASI_PRIMARY_LITTLE; 933 #endif 934 pcmhp->size = size; 935 pcmhp->realsize = STP4020_WINDOW_SIZE - card_addr; 936 *offsetp = 0; 937 *windowp = 0; 938 939 return (0); 940 } 941 942 void 943 stp4020_chip_mem_unmap(pch, win) 944 pcmcia_chipset_handle_t pch; 945 int win; 946 { 947 } 948 949 int 950 stp4020_chip_io_alloc(pch, start, size, align, pcihp) 951 pcmcia_chipset_handle_t pch; 952 bus_addr_t start; 953 bus_size_t size; 954 bus_size_t align; 955 struct pcmcia_io_handle *pcihp; 956 { 957 struct stp4020_socket *h = (struct stp4020_socket *)pch; 958 959 pcihp->iot = h->pcmciat; 960 pcihp->ioh = h->windows[STP_WIN_IO].winaddr; 961 return 0; 962 } 963 964 void 965 stp4020_chip_io_free(pch, pcihp) 966 pcmcia_chipset_handle_t pch; 967 struct pcmcia_io_handle *pcihp; 968 { 969 } 970 971 int 972 stp4020_chip_io_map(pch, width, offset, size, pcihp, windowp) 973 pcmcia_chipset_handle_t pch; 974 int width; 975 bus_addr_t offset; 976 bus_size_t size; 977 struct pcmcia_io_handle *pcihp; 978 int *windowp; 979 { 980 struct stp4020_socket *h = (struct stp4020_socket *)pch; 981 982 pcihp->iot = h->pcmciat; 983 bus_space_subregion(h->pcmciat, h->windows[STP_WIN_IO].winaddr, offset, size, &pcihp->ioh); 984 #ifdef SUN4U 985 if ((u_int8_t)pcihp->ioh._asi == ASI_PHYS_NON_CACHED) 986 pcihp->ioh._asi = ASI_PHYS_NON_CACHED_LITTLE; 987 else if ((u_int8_t)pcihp->ioh._asi == ASI_PRIMARY) 988 pcihp->ioh._asi = ASI_PRIMARY_LITTLE; 989 #endif 990 *windowp = 0; 991 return 0; 992 } 993 994 void 995 stp4020_chip_io_unmap(pch, win) 996 pcmcia_chipset_handle_t pch; 997 int win; 998 { 999 } 1000 1001 void 1002 stp4020_chip_socket_enable(pch) 1003 pcmcia_chipset_handle_t pch; 1004 { 1005 struct stp4020_socket *h = (struct stp4020_socket *)pch; 1006 int i, v; 1007 1008 /* this bit is mostly stolen from pcic_attach_card */ 1009 1010 /* Power down the socket to reset it, clear the card reset pin */ 1011 stp4020_wr_sockctl(h, STP4020_ICR1_IDX, 0); 1012 1013 /* 1014 * wait 300ms until power fails (Tpf). Then, wait 100ms since 1015 * we are changing Vcc (Toff). 1016 */ 1017 stp4020_delay(h->sc, 300 + 100); 1018 1019 /* Power up the socket */ 1020 v = STP4020_ICR1_MSTPWR; 1021 stp4020_wr_sockctl(h, STP4020_ICR1_IDX, v); 1022 1023 /* 1024 * wait 100ms until power raise (Tpr) and 20ms to become 1025 * stable (Tsu(Vcc)). 1026 */ 1027 stp4020_delay(h->sc, 100 + 20); 1028 1029 v |= STP4020_ICR1_PCIFOE|STP4020_ICR1_VPP1_VCC; 1030 stp4020_wr_sockctl(h, STP4020_ICR1_IDX, v); 1031 1032 /* 1033 * hold RESET at least 10us. 1034 */ 1035 delay(10); 1036 1037 /* Clear reset flag, set to memory mode */ 1038 v = stp4020_rd_sockctl(h, STP4020_ICR0_IDX); 1039 v &= ~(STP4020_ICR0_IOIE | STP4020_ICR0_IOILVL | STP4020_ICR0_IFTYPE | 1040 STP4020_ICR0_SPKREN); 1041 v &= ~STP4020_ICR0_RESET; 1042 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, v); 1043 1044 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 1045 stp4020_delay(h->sc, 20); 1046 1047 /* Wait for the chip to finish initializing (5 seconds max) */ 1048 for (i = 10000; i > 0; i--) { 1049 v = stp4020_rd_sockctl(h, STP4020_ISR0_IDX); 1050 if ((v & STP4020_ISR0_RDYST) != 0) 1051 break; 1052 delay(500); 1053 } 1054 if (i <= 0) { 1055 char bits[64]; 1056 bitmask_snprintf(stp4020_rd_sockctl(h, STP4020_ISR0_IDX), 1057 STP4020_ISR0_IOBITS, bits, sizeof(bits)); 1058 printf("stp4020_chip_socket_enable: not ready: status %s\n", 1059 bits); 1060 return; 1061 } 1062 } 1063 1064 void 1065 stp4020_chip_socket_settype(pch, type) 1066 pcmcia_chipset_handle_t pch; 1067 int type; 1068 { 1069 struct stp4020_socket *h = (struct stp4020_socket *)pch; 1070 int v; 1071 1072 /* 1073 * Check the card type. 1074 * Enable socket I/O interrupts for IO cards. 1075 */ 1076 v = stp4020_rd_sockctl(h, STP4020_ICR0_IDX); 1077 v &= ~(STP4020_ICR0_IOIE | STP4020_ICR0_IOILVL | STP4020_ICR0_IFTYPE | 1078 STP4020_ICR0_SPKREN); 1079 if (type == PCMCIA_IFTYPE_IO) { 1080 v |= STP4020_ICR0_IFTYPE_IO|STP4020_ICR0_IOIE 1081 |STP4020_ICR0_SPKREN; 1082 v |= h->sbus_intno ? STP4020_ICR0_IOILVL_SB1 1083 : STP4020_ICR0_IOILVL_SB0; 1084 #ifndef SUN4U 1085 h->int_enable = v; 1086 h->int_disable = v & ~STP4020_ICR0_IOIE; 1087 #endif 1088 DPRINTF(("%s: configuring card for IO useage\n", device_xname(&h->sc->sc_dev))); 1089 } else { 1090 v |= STP4020_ICR0_IFTYPE_MEM; 1091 #ifndef SUN4U 1092 h->int_enable = h->int_disable = v; 1093 #endif 1094 DPRINTF(("%s: configuring card for IO useage\n", device_xname(&h->sc->sc_dev))); 1095 DPRINTF(("%s: configuring card for MEM ONLY useage\n", device_xname(&h->sc->sc_dev))); 1096 } 1097 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, v); 1098 } 1099 1100 void 1101 stp4020_chip_socket_disable(pch) 1102 pcmcia_chipset_handle_t pch; 1103 { 1104 struct stp4020_socket *h = (struct stp4020_socket *)pch; 1105 int v; 1106 1107 /* 1108 * Disable socket I/O interrupts. 1109 */ 1110 v = stp4020_rd_sockctl(h, STP4020_ICR0_IDX); 1111 v &= ~(STP4020_ICR0_IOIE | STP4020_ICR0_IOILVL | STP4020_ICR0_IFTYPE | 1112 STP4020_ICR0_SPKREN); 1113 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, v); 1114 1115 /* Power down the socket */ 1116 stp4020_wr_sockctl(h, STP4020_ICR1_IDX, 0); 1117 1118 /* 1119 * wait 300ms until power fails (Tpf). 1120 */ 1121 stp4020_delay(h->sc, 300); 1122 } 1123 1124 void * 1125 stp4020_chip_intr_establish(pch, pf, ipl, handler, arg) 1126 pcmcia_chipset_handle_t pch; 1127 struct pcmcia_function *pf; 1128 int ipl; 1129 int (*handler)(void *); 1130 void *arg; 1131 { 1132 struct stp4020_socket *h = (struct stp4020_socket *)pch; 1133 1134 /* only one interrupt handler per slot */ 1135 if (h->intrhandler != NULL) return NULL; 1136 1137 h->intrhandler = handler; 1138 h->intrarg = arg; 1139 #ifndef SUN4U 1140 if (h->sc->sc_use_softint) { 1141 h->softint = sparc_softintr_establish(ipl, stp4020_intr_dispatch, h); 1142 return h->softint; 1143 } 1144 #endif 1145 return h; 1146 } 1147 1148 void 1149 stp4020_chip_intr_disestablish(pch, ih) 1150 pcmcia_chipset_handle_t pch; 1151 void *ih; 1152 { 1153 struct stp4020_socket *h = (struct stp4020_socket *)pch; 1154 1155 h->intrhandler = NULL; 1156 h->intrarg = NULL; 1157 #ifndef SUN4U 1158 if (h->softint) { 1159 sparc_softintr_disestablish(h->softint); 1160 h->softint = NULL; 1161 } 1162 #endif 1163 } 1164 1165 /* 1166 * Delay and possibly yield CPU. 1167 * XXX - assumes a context 1168 */ 1169 void 1170 stp4020_delay(sc, ms) 1171 struct stp4020_softc *sc; 1172 unsigned int ms; 1173 { 1174 unsigned int ticks = mstohz(ms); 1175 1176 if (cold || ticks == 0) { 1177 delay(ms); 1178 return; 1179 } 1180 1181 #ifdef DIAGNOSTIC 1182 if (ticks > 60*hz) 1183 panic("stp4020: preposterous delay: %u", ticks); 1184 #endif 1185 tsleep(sc, 0, "nelldel", ticks); 1186 } 1187 1188 #ifdef STP4020_DEBUG 1189 void 1190 stp4020_dump_regs(h) 1191 struct stp4020_socket *h; 1192 { 1193 char bits[64]; 1194 /* 1195 * Dump control and status registers. 1196 */ 1197 printf("socket[%d] registers:\n", h->sock); 1198 bitmask_snprintf(stp4020_rd_sockctl(h, STP4020_ICR0_IDX), 1199 STP4020_ICR0_BITS, bits, sizeof(bits)); 1200 printf("\tICR0=%s\n", bits); 1201 1202 bitmask_snprintf(stp4020_rd_sockctl(h, STP4020_ICR1_IDX), 1203 STP4020_ICR1_BITS, bits, sizeof(bits)); 1204 printf("\tICR1=%s\n", bits); 1205 1206 bitmask_snprintf(stp4020_rd_sockctl(h, STP4020_ISR0_IDX), 1207 STP4020_ISR0_IOBITS, bits, sizeof(bits)); 1208 printf("\tISR0=%s\n", bits); 1209 1210 bitmask_snprintf(stp4020_rd_sockctl(h, STP4020_ISR1_IDX), 1211 STP4020_ISR1_BITS, bits, sizeof(bits)); 1212 printf("\tISR1=%s\n", bits); 1213 } 1214 #endif /* STP4020_DEBUG */ 1215
Indexes created Fri Oct 03 02:09:57 GMT 2025