stp4020.c revision 1.57
1 /* $NetBSD: stp4020.c,v 1.57 2009/03/14 15:36:21 dsl Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * STP4020: SBus/PCMCIA bridge supporting two Type-3 PCMCIA cards. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: stp4020.c,v 1.57 2009/03/14 15:36:21 dsl Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/errno.h> 42 #include <sys/malloc.h> 43 #include <sys/extent.h> 44 #include <sys/proc.h> 45 #include <sys/kernel.h> 46 #include <sys/kthread.h> 47 #include <sys/device.h> 48 #include <sys/intr.h> 49 50 #include <dev/pcmcia/pcmciareg.h> 51 #include <dev/pcmcia/pcmciavar.h> 52 #include <dev/pcmcia/pcmciachip.h> 53 54 #include <sys/bus.h> 55 56 #include <dev/sbus/sbusvar.h> 57 #include <dev/sbus/stp4020reg.h> 58 59 #define STP4020_DEBUG 1 /* XXX-temp */ 60 61 /* 62 * We use the three available windows per socket in a simple, fixed 63 * arrangement. Each window maps (at full 1 MB size) one of the pcmcia 64 * spaces into sbus space. 65 */ 66 #define STP_WIN_ATTR 0 /* index of the attribute memory space window */ 67 #define STP_WIN_MEM 1 /* index of the common memory space window */ 68 #define STP_WIN_IO 2 /* index of the io space window */ 69 70 71 #if defined(STP4020_DEBUG) 72 int stp4020_debug = 0; 73 #define DPRINTF(x) do { if (stp4020_debug) printf x; } while(0) 74 #else 75 #define DPRINTF(x) 76 #endif 77 78 /* 79 * Event queue; events detected in an interrupt context go here 80 * awaiting attention from our event handling thread. 81 */ 82 struct stp4020_event { 83 SIMPLEQ_ENTRY(stp4020_event) se_q; 84 int se_type; 85 int se_sock; 86 }; 87 /* Defined event types */ 88 #define STP4020_EVENT_INSERTION 0 89 #define STP4020_EVENT_REMOVAL 1 90 91 /* 92 * Per socket data. 93 */ 94 struct stp4020_socket { 95 struct stp4020_softc *sc; /* Back link */ 96 int flags; 97 #define STP4020_SOCKET_BUSY 0x0001 98 int sock; /* Socket number (0 or 1) */ 99 int sbus_intno; /* Do we use first (0) or second (1) 100 interrupt? */ 101 #ifndef SUN4U 102 int int_enable; /* ICR0 value for interrupt enabled */ 103 int int_disable; /* ICR0 value for interrupt disabled */ 104 #endif 105 bus_space_tag_t tag; /* socket control io */ 106 bus_space_handle_t regs; /* space */ 107 bus_space_tag_t pcmciat; /* io space for pcmcia */ 108 struct device *pcmcia; /* Associated PCMCIA device */ 109 int (*intrhandler) /* Card driver interrupt handler */ 110 (void *); 111 void *intrarg; /* Card interrupt handler argument */ 112 #ifndef SUN4U 113 void *softint; /* cookie for the softintr */ 114 #endif 115 116 struct { 117 bus_space_handle_t winaddr;/* this window's address */ 118 } windows[STP4020_NWIN]; 119 120 }; 121 122 struct stp4020_softc { 123 struct device sc_dev; /* Base device */ 124 struct sbusdev sc_sd; /* SBus device */ 125 pcmcia_chipset_tag_t sc_pct; /* Chipset methods */ 126 127 struct lwp *event_thread; /* event handling thread */ 128 SIMPLEQ_HEAD(, stp4020_event) events; /* Pending events for thread */ 129 130 struct stp4020_socket sc_socks[STP4020_NSOCK]; 131 #ifndef SUN4U 132 bool sc_use_softint; 133 #endif 134 }; 135 136 137 static int stp4020print(void *, const char *); 138 static int stp4020match(struct device *, struct cfdata *, void *); 139 static void stp4020attach(struct device *, struct device *, void *); 140 static int stp4020_intr(void *); 141 static void stp4020_map_window(struct stp4020_socket *h, int win, int speed); 142 static void stp4020_calc_speed(int bus_speed, int ns, int *length, int *cmd_delay); 143 #ifndef SUN4U 144 static void stp4020_intr_dispatch(void *arg); 145 #endif 146 147 CFATTACH_DECL(nell, sizeof(struct stp4020_softc), 148 stp4020match, stp4020attach, NULL, NULL); 149 150 #ifdef STP4020_DEBUG 151 static void stp4020_dump_regs(struct stp4020_socket *); 152 #endif 153 154 static int stp4020_rd_sockctl(struct stp4020_socket *, int); 155 static void stp4020_wr_sockctl(struct stp4020_socket *, int, int); 156 static int stp4020_rd_winctl(struct stp4020_socket *, int, int); 157 static void stp4020_wr_winctl(struct stp4020_socket *, int, int, int); 158 159 void stp4020_delay(struct stp4020_softc *sc, unsigned int); 160 void stp4020_attach_socket(struct stp4020_socket *, int); 161 void stp4020_event_thread(void *); 162 void stp4020_queue_event(struct stp4020_softc *, int, int); 163 164 int stp4020_chip_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 165 struct pcmcia_mem_handle *); 166 void stp4020_chip_mem_free(pcmcia_chipset_handle_t, 167 struct pcmcia_mem_handle *); 168 int stp4020_chip_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 169 bus_size_t, struct pcmcia_mem_handle *, 170 bus_size_t *, int *); 171 void stp4020_chip_mem_unmap(pcmcia_chipset_handle_t, int); 172 173 int stp4020_chip_io_alloc(pcmcia_chipset_handle_t, 174 bus_addr_t, bus_size_t, bus_size_t, 175 struct pcmcia_io_handle *); 176 void stp4020_chip_io_free(pcmcia_chipset_handle_t, 177 struct pcmcia_io_handle *); 178 int stp4020_chip_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 179 bus_size_t, struct pcmcia_io_handle *, int *); 180 void stp4020_chip_io_unmap(pcmcia_chipset_handle_t, int); 181 182 void stp4020_chip_socket_enable(pcmcia_chipset_handle_t); 183 void stp4020_chip_socket_disable(pcmcia_chipset_handle_t); 184 void stp4020_chip_socket_settype(pcmcia_chipset_handle_t, int); 185 void *stp4020_chip_intr_establish(pcmcia_chipset_handle_t, 186 struct pcmcia_function *, int, 187 int (*)(void *), void *); 188 void stp4020_chip_intr_disestablish(pcmcia_chipset_handle_t, void *); 189 190 /* Our PCMCIA chipset methods */ 191 static struct pcmcia_chip_functions stp4020_functions = { 192 stp4020_chip_mem_alloc, 193 stp4020_chip_mem_free, 194 stp4020_chip_mem_map, 195 stp4020_chip_mem_unmap, 196 197 stp4020_chip_io_alloc, 198 stp4020_chip_io_free, 199 stp4020_chip_io_map, 200 stp4020_chip_io_unmap, 201 202 stp4020_chip_intr_establish, 203 stp4020_chip_intr_disestablish, 204 205 stp4020_chip_socket_enable, 206 stp4020_chip_socket_disable, 207 stp4020_chip_socket_settype, 208 NULL 209 }; 210 211 212 static inline int 213 stp4020_rd_sockctl(struct stp4020_socket *h, int idx) 214 { 215 int o = ((STP4020_SOCKREGS_SIZE * (h->sock)) + idx); 216 return (bus_space_read_2(h->tag, h->regs, o)); 217 } 218 219 static inline void 220 stp4020_wr_sockctl(struct stp4020_socket *h, int idx, int v) 221 { 222 int o = (STP4020_SOCKREGS_SIZE * (h->sock)) + idx; 223 bus_space_write_2(h->tag, h->regs, o, v); 224 } 225 226 static inline int 227 stp4020_rd_winctl(struct stp4020_socket *h, int win, int idx) 228 { 229 int o = (STP4020_SOCKREGS_SIZE * (h->sock)) + 230 (STP4020_WINREGS_SIZE * win) + idx; 231 return (bus_space_read_2(h->tag, h->regs, o)); 232 } 233 234 static inline void 235 stp4020_wr_winctl(struct stp4020_socket *h, int win, int idx, int v) 236 { 237 int o = (STP4020_SOCKREGS_SIZE * (h->sock)) + 238 (STP4020_WINREGS_SIZE * win) + idx; 239 240 bus_space_write_2(h->tag, h->regs, o, v); 241 } 242 243 #ifndef SUN4U /* XXX - move to SBUS machdep function? */ 244 245 static u_int16_t stp4020_read_2(bus_space_tag_t, 246 bus_space_handle_t, 247 bus_size_t); 248 static u_int32_t stp4020_read_4(bus_space_tag_t, 249 bus_space_handle_t, 250 bus_size_t); 251 static u_int64_t stp4020_read_8(bus_space_tag_t, 252 bus_space_handle_t, 253 bus_size_t); 254 static void stp4020_write_2(bus_space_tag_t, 255 bus_space_handle_t, 256 bus_size_t, 257 u_int16_t); 258 static void stp4020_write_4(bus_space_tag_t, 259 bus_space_handle_t, 260 bus_size_t, 261 u_int32_t); 262 static void stp4020_write_8(bus_space_tag_t, 263 bus_space_handle_t, 264 bus_size_t, 265 u_int64_t); 266 267 static u_int16_t 268 stp4020_read_2(bus_space_tag_t space, bus_space_handle_t handle, bus_size_t offset) 269 { 270 return (le16toh(*(volatile u_int16_t *)(handle + offset))); 271 } 272 273 static u_int32_t 274 stp4020_read_4(bus_space_tag_t space, bus_space_handle_t handle, bus_size_t offset) 275 { 276 return (le32toh(*(volatile u_int32_t *)(handle + offset))); 277 } 278 279 static u_int64_t 280 stp4020_read_8(bus_space_tag_t space, bus_space_handle_t handle, bus_size_t offset) 281 { 282 return (le64toh(*(volatile u_int64_t *)(handle + offset))); 283 } 284 285 static void 286 stp4020_write_2(bus_space_tag_t space, bus_space_handle_t handle, bus_size_t offset, u_int16_t value) 287 { 288 (*(volatile u_int16_t *)(handle + offset)) = htole16(value); 289 } 290 291 static void 292 stp4020_write_4(bus_space_tag_t space, bus_space_handle_t handle, bus_size_t offset, u_int32_t value) 293 { 294 (*(volatile u_int32_t *)(handle + offset)) = htole32(value); 295 } 296 297 static void 298 stp4020_write_8(bus_space_tag_t space, bus_space_handle_t handle, bus_size_t offset, u_int64_t value) 299 { 300 (*(volatile u_int64_t *)(handle + offset)) = htole64(value); 301 } 302 #endif /* SUN4U */ 303 304 int 305 stp4020print(void *aux, const char *busname) 306 { 307 struct pcmciabus_attach_args *paa = aux; 308 struct stp4020_socket *h = paa->pch; 309 310 aprint_normal(" socket %d", h->sock); 311 return (UNCONF); 312 } 313 314 int 315 stp4020match(struct device *parent, struct cfdata *cf, void *aux) 316 { 317 struct sbus_attach_args *sa = aux; 318 319 return (strcmp("SUNW,pcmcia", sa->sa_name) == 0); 320 } 321 322 /* 323 * Attach all the sub-devices we can find 324 */ 325 void 326 stp4020attach(parent, self, aux) 327 struct device *parent, *self; 328 void *aux; 329 { 330 struct sbus_attach_args *sa = aux; 331 struct stp4020_softc *sc = (void *)self; 332 bus_space_tag_t tag; 333 int rev, i, sbus_intno, hw_ipl; 334 bus_space_handle_t bh; 335 336 /* Transfer bus tags */ 337 #ifdef SUN4U 338 tag = sa->sa_bustag; 339 #else 340 tag = bus_space_tag_alloc(sa->sa_bustag, sc); 341 if (tag == NULL) { 342 aprint_error_dev(self, "attach: out of memory\n"); 343 return; 344 } 345 tag->sparc_read_2 = stp4020_read_2; 346 tag->sparc_read_4 = stp4020_read_4; 347 tag->sparc_read_8 = stp4020_read_8; 348 tag->sparc_write_2 = stp4020_write_2; 349 tag->sparc_write_4 = stp4020_write_4; 350 tag->sparc_write_8 = stp4020_write_8; 351 #endif /* SUN4U */ 352 353 /* check interrupt options, decide if we need a softint */ 354 #ifdef SUN4U 355 /* 356 * On sparc64 the hardware interrupt priority does not restrict 357 * the IPL we run our interrupt handler on, so we can always just 358 * use the first interrupt and reqest the handler to run at 359 * IPL_VM. 360 */ 361 sbus_intno = 0; 362 hw_ipl = IPL_VM; 363 #else 364 /* 365 * We need to check if one of the available interrupts has 366 * a priority that allows us to establish a handler at IPL_VM. 367 * If not (hard to imagine), use a soft interrupt. 368 */ 369 sbus_intno = -1; 370 for (i = 0; i < sa->sa_nintr; i++) { 371 struct sbus_softc *bus = 372 (struct sbus_softc *) sa->sa_bustag->cookie; 373 int ipl = bus->sc_intr2ipl[sa->sa_intr[i].oi_pri]; 374 if (ipl <= IPL_VM) { 375 sbus_intno = i; 376 sc->sc_use_softint = false; 377 hw_ipl = IPL_VM; 378 break; 379 } 380 } 381 if (sbus_intno == -1) { 382 /* 383 * We have not found a usable hardware interrupt - so 384 * use a softint to bounce to the proper IPL. 385 */ 386 printf("no usable HW interrupt found, using softint\n"); 387 sbus_intno = 0; 388 sc->sc_use_softint = true; 389 hw_ipl = IPL_NONE; 390 } 391 #endif 392 393 /* Set up per-socket static initialization */ 394 sc->sc_socks[0].sc = sc->sc_socks[1].sc = sc; 395 sc->sc_socks[0].tag = sc->sc_socks[1].tag = sa->sa_bustag; 396 /* 397 * XXX we rely on "tag" accepting the same handle-domain 398 * as sa->sa_bustag. 399 */ 400 sc->sc_socks[0].pcmciat = sc->sc_socks[1].pcmciat = tag; 401 sc->sc_socks[0].sbus_intno = 402 sc->sc_socks[1].sbus_intno = sbus_intno; 403 404 if (sa->sa_nreg < 8) { 405 printf("%s: only %d register sets\n", 406 device_xname(self), sa->sa_nreg); 407 return; 408 } 409 410 if (sa->sa_nintr != 2) { 411 printf("%s: expect 2 interrupt Sbus levels; got %d\n", 412 device_xname(self), sa->sa_nintr); 413 return; 414 } 415 416 #define STP4020_BANK_PROM 0 417 #define STP4020_BANK_CTRL 4 418 for (i = 0; i < 8; i++) { 419 420 /* 421 * STP4020 Register address map: 422 * bank 0: Forth PROM 423 * banks 1-3: socket 0, windows 0-2 424 * bank 4: control registers 425 * banks 5-7: socket 1, windows 0-2 426 */ 427 428 if (i == STP4020_BANK_PROM) 429 /* Skip the PROM */ 430 continue; 431 432 if (sbus_bus_map(sa->sa_bustag, 433 sa->sa_reg[i].oa_space, 434 sa->sa_reg[i].oa_base, 435 sa->sa_reg[i].oa_size, 436 0, &bh) != 0) { 437 aprint_error_dev(self, "attach: cannot map registers\n"); 438 return; 439 } 440 441 if (i == STP4020_BANK_CTRL) { 442 /* 443 * Copy tag and handle to both socket structures 444 * for easy access in control/status IO functions. 445 */ 446 sc->sc_socks[0].regs = sc->sc_socks[1].regs = bh; 447 } else if (i < STP4020_BANK_CTRL) { 448 /* banks 1-3 */ 449 sc->sc_socks[0].windows[i-1].winaddr = bh; 450 } else { 451 /* banks 5-7 */ 452 sc->sc_socks[1].windows[i-5].winaddr = bh; 453 } 454 } 455 456 sbus_establish(&sc->sc_sd, &sc->sc_dev); 457 458 /* We only use one interrupt level. */ 459 if (sa->sa_nintr > sbus_intno) { 460 bus_intr_establish(sa->sa_bustag, 461 sa->sa_intr[sbus_intno].oi_pri, 462 hw_ipl, stp4020_intr, sc); 463 } 464 465 rev = stp4020_rd_sockctl(&sc->sc_socks[0], STP4020_ISR1_IDX) & 466 STP4020_ISR1_REV_M; 467 printf(": rev %x\n", rev); 468 469 sc->sc_pct = (pcmcia_chipset_tag_t)&stp4020_functions; 470 471 SIMPLEQ_INIT(&sc->events); 472 473 for (i = 0; i < STP4020_NSOCK; i++) { 474 struct stp4020_socket *h = &sc->sc_socks[i]; 475 h->sock = i; 476 h->sc = sc; 477 #ifdef STP4020_DEBUG 478 if (stp4020_debug) 479 stp4020_dump_regs(h); 480 #endif 481 stp4020_attach_socket(h, sa->sa_frequency); 482 } 483 484 /* 485 * Arrange that a kernel thread be created to handle 486 * insert/removal events. 487 */ 488 if (kthread_create(PRI_NONE, 0, NULL, stp4020_event_thread, sc, 489 &sc->event_thread, "%s", device_xname(self))) { 490 panic("%s: unable to create event thread", device_xname(self)); 491 } 492 } 493 494 void 495 stp4020_attach_socket(struct stp4020_socket *h, int speed) 496 { 497 struct pcmciabus_attach_args paa; 498 int v; 499 500 /* no interrupt handlers yet */ 501 h->intrhandler = NULL; 502 h->intrarg = NULL; 503 #ifndef SUN4U 504 h->softint = NULL; 505 h->int_enable = 0; 506 h->int_disable = 0; 507 #endif 508 509 /* Map all three windows */ 510 stp4020_map_window(h, STP_WIN_ATTR, speed); 511 stp4020_map_window(h, STP_WIN_MEM, speed); 512 stp4020_map_window(h, STP_WIN_IO, speed); 513 514 /* Configure one pcmcia device per socket */ 515 paa.paa_busname = "pcmcia"; 516 paa.pct = (pcmcia_chipset_tag_t)h->sc->sc_pct; 517 paa.pch = (pcmcia_chipset_handle_t)h; 518 paa.iobase = 0; 519 paa.iosize = STP4020_WINDOW_SIZE; 520 521 h->pcmcia = config_found(&h->sc->sc_dev, &paa, stp4020print); 522 523 if (h->pcmcia == NULL) 524 return; 525 526 /* 527 * There's actually a pcmcia bus attached; initialize the slot. 528 */ 529 530 /* 531 * Clear things up before we enable status change interrupts. 532 * This seems to not be fully initialized by the PROM. 533 */ 534 stp4020_wr_sockctl(h, STP4020_ICR1_IDX, 0); 535 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, 0); 536 stp4020_wr_sockctl(h, STP4020_ISR1_IDX, 0x3fff); 537 stp4020_wr_sockctl(h, STP4020_ISR0_IDX, 0x3fff); 538 539 /* 540 * Enable socket status change interrupts. 541 * We only use one common interrupt for status change 542 * and IO, to avoid locking issues. 543 */ 544 v = STP4020_ICR0_ALL_STATUS_IE 545 | (h->sbus_intno ? STP4020_ICR0_SCILVL_SB1 546 : STP4020_ICR0_SCILVL_SB0); 547 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, v); 548 549 /* Get live status bits from ISR0 and clear pending interrupts */ 550 v = stp4020_rd_sockctl(h, STP4020_ISR0_IDX); 551 stp4020_wr_sockctl(h, STP4020_ISR0_IDX, v); 552 553 if ((v & (STP4020_ISR0_CD1ST|STP4020_ISR0_CD2ST)) == 0) 554 return; 555 556 pcmcia_card_attach(h->pcmcia); 557 h->flags |= STP4020_SOCKET_BUSY; 558 } 559 560 /* 561 * The actual event handling thread. 562 */ 563 void 564 stp4020_event_thread(void *arg) 565 { 566 struct stp4020_softc *sc = arg; 567 struct stp4020_event *e; 568 int s; 569 570 while (1) { 571 struct stp4020_socket *h; 572 int n; 573 574 s = splhigh(); 575 if ((e = SIMPLEQ_FIRST(&sc->events)) == NULL) { 576 splx(s); 577 (void)tsleep(&sc->events, PWAIT, "nellevt", 0); 578 continue; 579 } 580 SIMPLEQ_REMOVE_HEAD(&sc->events, se_q); 581 splx(s); 582 583 n = e->se_sock; 584 if (n < 0 || n >= STP4020_NSOCK) 585 panic("stp4020_event_thread: wayward socket number %d", 586 n); 587 588 h = &sc->sc_socks[n]; 589 switch (e->se_type) { 590 case STP4020_EVENT_INSERTION: 591 pcmcia_card_attach(h->pcmcia); 592 break; 593 case STP4020_EVENT_REMOVAL: 594 pcmcia_card_detach(h->pcmcia, DETACH_FORCE); 595 break; 596 default: 597 panic("stp4020_event_thread: unknown event type %d", 598 e->se_type); 599 } 600 free(e, M_TEMP); 601 } 602 } 603 604 void 605 stp4020_queue_event(sc, sock, event) 606 struct stp4020_softc *sc; 607 int sock, event; 608 { 609 struct stp4020_event *e; 610 int s; 611 612 e = malloc(sizeof(*e), M_TEMP, M_NOWAIT); 613 if (e == NULL) 614 panic("stp4020_queue_event: can't allocate event"); 615 616 e->se_type = event; 617 e->se_sock = sock; 618 s = splhigh(); 619 SIMPLEQ_INSERT_TAIL(&sc->events, e, se_q); 620 splx(s); 621 wakeup(&sc->events); 622 } 623 624 #ifndef SUN4U 625 /* 626 * Softinterrupt called to invoke the real driver interrupt handler. 627 */ 628 static void 629 stp4020_intr_dispatch(void *arg) 630 { 631 struct stp4020_socket *h = arg; 632 int s; 633 634 /* invoke driver handler */ 635 h->intrhandler(h->intrarg); 636 637 /* enable SBUS interrupts for pcmcia interrupts again */ 638 s = splhigh(); 639 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, h->int_enable); 640 splx(s); 641 } 642 #endif 643 644 int 645 stp4020_intr(void *arg) 646 { 647 struct stp4020_softc *sc = arg; 648 #ifndef SUN4U 649 int s; 650 #endif 651 int i, r = 0, cd_change = 0; 652 653 654 #ifndef SUN4U 655 /* protect hardware access by splhigh against softint */ 656 s = splhigh(); 657 #endif 658 659 /* 660 * Check each socket for pending requests. 661 */ 662 for (i = 0 ; i < STP4020_NSOCK; i++) { 663 struct stp4020_socket *h; 664 int v; 665 666 h = &sc->sc_socks[i]; 667 668 v = stp4020_rd_sockctl(h, STP4020_ISR0_IDX); 669 670 /* Ack all interrupts at once. */ 671 stp4020_wr_sockctl(h, STP4020_ISR0_IDX, v); 672 673 #ifdef STP4020_DEBUG 674 if (stp4020_debug != 0) { 675 char bits[64]; 676 snprintb(bits, sizeof(bits), STP4020_ISR0_IOBITS, v); 677 printf("stp4020_statintr: ISR0=%s\n", bits); 678 } 679 #endif 680 681 if ((v & STP4020_ISR0_CDCHG) != 0) { 682 /* 683 * Card status change detect 684 */ 685 cd_change = 1; 686 r = 1; 687 if ((v & (STP4020_ISR0_CD1ST|STP4020_ISR0_CD2ST)) == (STP4020_ISR0_CD1ST|STP4020_ISR0_CD2ST)){ 688 if ((h->flags & STP4020_SOCKET_BUSY) == 0) { 689 stp4020_queue_event(sc, i, 690 STP4020_EVENT_INSERTION); 691 h->flags |= STP4020_SOCKET_BUSY; 692 } 693 } 694 if ((v & (STP4020_ISR0_CD1ST|STP4020_ISR0_CD2ST)) == 0){ 695 if ((h->flags & STP4020_SOCKET_BUSY) != 0) { 696 stp4020_queue_event(sc, i, 697 STP4020_EVENT_REMOVAL); 698 h->flags &= ~STP4020_SOCKET_BUSY; 699 } 700 } 701 } 702 703 if ((v & STP4020_ISR0_IOINT) != 0) { 704 /* we can not deny this is ours, no matter what the 705 card driver says. */ 706 r = 1; 707 708 /* It's a card interrupt */ 709 if ((h->flags & STP4020_SOCKET_BUSY) == 0) { 710 printf("stp4020[%d]: spurious interrupt?\n", 711 h->sock); 712 continue; 713 } 714 715 #ifndef SUN4U 716 /* 717 * Schedule softint to invoke driver interrupt 718 * handler 719 */ 720 if (h->softint != NULL) 721 sparc_softintr_schedule(h->softint); 722 /* 723 * Disable this sbus interrupt, until the soft-int 724 * handler had a chance to run 725 */ 726 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, h->int_disable); 727 #else 728 (*h->intrhandler)(h->intrarg); 729 #endif 730 } 731 732 /* informational messages */ 733 if ((v & STP4020_ISR0_BVD1CHG) != 0) { 734 /* ignore if this is caused by insert or removal */ 735 if (!cd_change) 736 printf("stp4020[%d]: Battery change 1\n", h->sock); 737 r = 1; 738 } 739 740 if ((v & STP4020_ISR0_BVD2CHG) != 0) { 741 /* ignore if this is caused by insert or removal */ 742 if (!cd_change) 743 printf("stp4020[%d]: Battery change 2\n", h->sock); 744 r = 1; 745 } 746 747 if ((v & STP4020_ISR0_SCINT) != 0) { 748 DPRINTF(("stp4020[%d]: status change\n", h->sock)); 749 r = 1; 750 } 751 752 if ((v & STP4020_ISR0_RDYCHG) != 0) { 753 DPRINTF(("stp4020[%d]: Ready/Busy change\n", h->sock)); 754 r = 1; 755 } 756 757 if ((v & STP4020_ISR0_WPCHG) != 0) { 758 DPRINTF(("stp4020[%d]: Write protect change\n", h->sock)); 759 r = 1; 760 } 761 762 if ((v & STP4020_ISR0_PCTO) != 0) { 763 DPRINTF(("stp4020[%d]: Card access timeout\n", h->sock)); 764 r = 1; 765 } 766 767 if ((v & ~STP4020_ISR0_LIVE) && r == 0) 768 printf("stp4020[%d]: unhandled interrupt: 0x%x\n", h->sock, v); 769 770 } 771 #ifndef SUN4U 772 splx(s); 773 #endif 774 775 return (r); 776 } 777 778 /* 779 * The function gets the sbus speed and a access time and calculates 780 * values for the CMDLNG and CMDDLAY registers. 781 */ 782 static void 783 stp4020_calc_speed(int bus_speed, int ns, int *length, int *cmd_delay) 784 { 785 int result; 786 787 if (ns < STP4020_MEM_SPEED_MIN) 788 ns = STP4020_MEM_SPEED_MIN; 789 else if (ns > STP4020_MEM_SPEED_MAX) 790 ns = STP4020_MEM_SPEED_MAX; 791 result = ns*(bus_speed/1000); 792 if (result % 1000000) 793 result = result/1000000 + 1; 794 else 795 result /= 1000000; 796 *length = result; 797 798 /* the sbus frequency range is limited, so we can keep this simple */ 799 *cmd_delay = ns <= STP4020_MEM_SPEED_MIN? 1 : 2; 800 } 801 802 static void 803 stp4020_map_window(struct stp4020_socket *h, int win, int speed) 804 { 805 int v, length, cmd_delay; 806 807 /* 808 * According to the PC Card standard 300ns access timing should be 809 * used for attribute memory access. Our pcmcia framework does not 810 * seem to propagate timing information, so we use that 811 * everywhere. 812 */ 813 stp4020_calc_speed(speed, (win==STP_WIN_ATTR)? 300 : 100, &length, &cmd_delay); 814 815 /* 816 * Fill in the Address Space Select and Base Address 817 * fields of this windows control register 0. 818 */ 819 v = ((cmd_delay << STP4020_WCR0_CMDDLY_S)&STP4020_WCR0_CMDDLY_M) 820 | ((length << STP4020_WCR0_CMDLNG_S)&STP4020_WCR0_CMDLNG_M); 821 switch (win) { 822 case STP_WIN_ATTR: 823 v |= STP4020_WCR0_ASPSEL_AM; 824 break; 825 case STP_WIN_MEM: 826 v |= STP4020_WCR0_ASPSEL_CM; 827 break; 828 case STP_WIN_IO: 829 v |= STP4020_WCR0_ASPSEL_IO; 830 break; 831 } 832 v |= (STP4020_ADDR2PAGE(0) & STP4020_WCR0_BASE_M); 833 stp4020_wr_winctl(h, win, STP4020_WCR0_IDX, v); 834 stp4020_wr_winctl(h, win, STP4020_WCR1_IDX, 1<<STP4020_WCR1_WAITREQ_S); 835 } 836 837 int 838 stp4020_chip_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, struct pcmcia_mem_handle *pcmhp) 839 { 840 struct stp4020_socket *h = (struct stp4020_socket *)pch; 841 842 /* we can not do much here, defere work to _mem_map */ 843 pcmhp->memt = h->pcmciat; 844 pcmhp->size = size; 845 pcmhp->addr = 0; 846 pcmhp->mhandle = 0; 847 pcmhp->realsize = size; 848 849 return (0); 850 } 851 852 void 853 stp4020_chip_mem_free(pcmcia_chipset_handle_t pch, struct pcmcia_mem_handle *pcmhp) 854 { 855 } 856 857 int 858 stp4020_chip_mem_map(pcmcia_chipset_handle_t pch, int kind, bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, bus_size_t *offsetp, int *windowp) 859 { 860 struct stp4020_socket *h = (struct stp4020_socket *)pch; 861 int win = (kind&PCMCIA_MEM_ATTR)? STP_WIN_ATTR : STP_WIN_MEM; 862 863 pcmhp->memt = h->pcmciat; 864 bus_space_subregion(h->pcmciat, h->windows[win].winaddr, card_addr, size, &pcmhp->memh); 865 #ifdef SUN4U 866 if ((u_int8_t)pcmhp->memh._asi == ASI_PHYS_NON_CACHED) 867 pcmhp->memh._asi = ASI_PHYS_NON_CACHED_LITTLE; 868 else if ((u_int8_t)pcmhp->memh._asi == ASI_PRIMARY) 869 pcmhp->memh._asi = ASI_PRIMARY_LITTLE; 870 #endif 871 pcmhp->size = size; 872 pcmhp->realsize = STP4020_WINDOW_SIZE - card_addr; 873 *offsetp = 0; 874 *windowp = 0; 875 876 return (0); 877 } 878 879 void 880 stp4020_chip_mem_unmap(pcmcia_chipset_handle_t pch, int win) 881 { 882 } 883 884 int 885 stp4020_chip_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 886 { 887 struct stp4020_socket *h = (struct stp4020_socket *)pch; 888 889 pcihp->iot = h->pcmciat; 890 pcihp->ioh = h->windows[STP_WIN_IO].winaddr; 891 return 0; 892 } 893 894 void 895 stp4020_chip_io_free(pcmcia_chipset_handle_t pch, struct pcmcia_io_handle *pcihp) 896 { 897 } 898 899 int 900 stp4020_chip_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 901 { 902 struct stp4020_socket *h = (struct stp4020_socket *)pch; 903 904 pcihp->iot = h->pcmciat; 905 bus_space_subregion(h->pcmciat, h->windows[STP_WIN_IO].winaddr, offset, size, &pcihp->ioh); 906 #ifdef SUN4U 907 if ((u_int8_t)pcihp->ioh._asi == ASI_PHYS_NON_CACHED) 908 pcihp->ioh._asi = ASI_PHYS_NON_CACHED_LITTLE; 909 else if ((u_int8_t)pcihp->ioh._asi == ASI_PRIMARY) 910 pcihp->ioh._asi = ASI_PRIMARY_LITTLE; 911 #endif 912 *windowp = 0; 913 return 0; 914 } 915 916 void 917 stp4020_chip_io_unmap(pcmcia_chipset_handle_t pch, int win) 918 { 919 } 920 921 void 922 stp4020_chip_socket_enable(pcmcia_chipset_handle_t pch) 923 { 924 struct stp4020_socket *h = (struct stp4020_socket *)pch; 925 int i, v; 926 927 /* this bit is mostly stolen from pcic_attach_card */ 928 929 /* Power down the socket to reset it, clear the card reset pin */ 930 stp4020_wr_sockctl(h, STP4020_ICR1_IDX, 0); 931 932 /* 933 * wait 300ms until power fails (Tpf). Then, wait 100ms since 934 * we are changing Vcc (Toff). 935 */ 936 stp4020_delay(h->sc, 300 + 100); 937 938 /* Power up the socket */ 939 v = STP4020_ICR1_MSTPWR; 940 stp4020_wr_sockctl(h, STP4020_ICR1_IDX, v); 941 942 /* 943 * wait 100ms until power raise (Tpr) and 20ms to become 944 * stable (Tsu(Vcc)). 945 */ 946 stp4020_delay(h->sc, 100 + 20); 947 948 v |= STP4020_ICR1_PCIFOE|STP4020_ICR1_VPP1_VCC; 949 stp4020_wr_sockctl(h, STP4020_ICR1_IDX, v); 950 951 /* 952 * hold RESET at least 10us. 953 */ 954 delay(10); 955 956 /* Clear reset flag, set to memory mode */ 957 v = stp4020_rd_sockctl(h, STP4020_ICR0_IDX); 958 v &= ~(STP4020_ICR0_IOIE | STP4020_ICR0_IOILVL | STP4020_ICR0_IFTYPE | 959 STP4020_ICR0_SPKREN); 960 v &= ~STP4020_ICR0_RESET; 961 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, v); 962 963 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 964 stp4020_delay(h->sc, 20); 965 966 /* Wait for the chip to finish initializing (5 seconds max) */ 967 for (i = 10000; i > 0; i--) { 968 v = stp4020_rd_sockctl(h, STP4020_ISR0_IDX); 969 if ((v & STP4020_ISR0_RDYST) != 0) 970 break; 971 delay(500); 972 } 973 if (i <= 0) { 974 char bits[64]; 975 snprintb(bits, sizeof(bits), 976 STP4020_ISR0_IOBITS, 977 stp4020_rd_sockctl(h, STP4020_ISR0_IDX)); 978 printf("stp4020_chip_socket_enable: not ready: status %s\n", 979 bits); 980 return; 981 } 982 } 983 984 void 985 stp4020_chip_socket_settype(pcmcia_chipset_handle_t pch, int type) 986 { 987 struct stp4020_socket *h = (struct stp4020_socket *)pch; 988 int v; 989 990 /* 991 * Check the card type. 992 * Enable socket I/O interrupts for IO cards. 993 */ 994 v = stp4020_rd_sockctl(h, STP4020_ICR0_IDX); 995 v &= ~(STP4020_ICR0_IOIE | STP4020_ICR0_IOILVL | STP4020_ICR0_IFTYPE | 996 STP4020_ICR0_SPKREN); 997 if (type == PCMCIA_IFTYPE_IO) { 998 v |= STP4020_ICR0_IFTYPE_IO|STP4020_ICR0_IOIE 999 |STP4020_ICR0_SPKREN; 1000 v |= h->sbus_intno ? STP4020_ICR0_IOILVL_SB1 1001 : STP4020_ICR0_IOILVL_SB0; 1002 #ifndef SUN4U 1003 h->int_enable = v; 1004 h->int_disable = v & ~STP4020_ICR0_IOIE; 1005 #endif 1006 DPRINTF(("%s: configuring card for IO useage\n", device_xname(&h->sc->sc_dev))); 1007 } else { 1008 v |= STP4020_ICR0_IFTYPE_MEM; 1009 #ifndef SUN4U 1010 h->int_enable = h->int_disable = v; 1011 #endif 1012 DPRINTF(("%s: configuring card for IO useage\n", device_xname(&h->sc->sc_dev))); 1013 DPRINTF(("%s: configuring card for MEM ONLY useage\n", device_xname(&h->sc->sc_dev))); 1014 } 1015 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, v); 1016 } 1017 1018 void 1019 stp4020_chip_socket_disable(pcmcia_chipset_handle_t pch) 1020 { 1021 struct stp4020_socket *h = (struct stp4020_socket *)pch; 1022 int v; 1023 1024 /* 1025 * Disable socket I/O interrupts. 1026 */ 1027 v = stp4020_rd_sockctl(h, STP4020_ICR0_IDX); 1028 v &= ~(STP4020_ICR0_IOIE | STP4020_ICR0_IOILVL | STP4020_ICR0_IFTYPE | 1029 STP4020_ICR0_SPKREN); 1030 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, v); 1031 1032 /* Power down the socket */ 1033 stp4020_wr_sockctl(h, STP4020_ICR1_IDX, 0); 1034 1035 /* 1036 * wait 300ms until power fails (Tpf). 1037 */ 1038 stp4020_delay(h->sc, 300); 1039 } 1040 1041 void * 1042 stp4020_chip_intr_establish(pch, pf, ipl, handler, arg) 1043 pcmcia_chipset_handle_t pch; 1044 struct pcmcia_function *pf; 1045 int ipl; 1046 int (*handler)(void *); 1047 void *arg; 1048 { 1049 struct stp4020_socket *h = (struct stp4020_socket *)pch; 1050 1051 /* only one interrupt handler per slot */ 1052 if (h->intrhandler != NULL) return NULL; 1053 1054 h->intrhandler = handler; 1055 h->intrarg = arg; 1056 #ifndef SUN4U 1057 if (h->sc->sc_use_softint) { 1058 h->softint = sparc_softintr_establish(ipl, stp4020_intr_dispatch, h); 1059 return h->softint; 1060 } 1061 #endif 1062 return h; 1063 } 1064 1065 void 1066 stp4020_chip_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 1067 { 1068 struct stp4020_socket *h = (struct stp4020_socket *)pch; 1069 1070 h->intrhandler = NULL; 1071 h->intrarg = NULL; 1072 #ifndef SUN4U 1073 if (h->softint) { 1074 sparc_softintr_disestablish(h->softint); 1075 h->softint = NULL; 1076 } 1077 #endif 1078 } 1079 1080 /* 1081 * Delay and possibly yield CPU. 1082 * XXX - assumes a context 1083 */ 1084 void 1085 stp4020_delay(struct stp4020_softc *sc, unsigned int ms) 1086 { 1087 unsigned int ticks = mstohz(ms); 1088 1089 if (cold || ticks == 0) { 1090 delay(ms); 1091 return; 1092 } 1093 1094 #ifdef DIAGNOSTIC 1095 if (ticks > 60*hz) 1096 panic("stp4020: preposterous delay: %u", ticks); 1097 #endif 1098 tsleep(sc, 0, "nelldel", ticks); 1099 } 1100 1101 #ifdef STP4020_DEBUG 1102 void 1103 stp4020_dump_regs(struct stp4020_socket *h) 1104 { 1105 char bits[64]; 1106 /* 1107 * Dump control and status registers. 1108 */ 1109 printf("socket[%d] registers:\n", h->sock); 1110 snprintb(bits, sizeof(bits), STP4020_ICR0_BITS, 1111 stp4020_rd_sockctl(h, STP4020_ICR0_IDX)); 1112 printf("\tICR0=%s\n", bits); 1113 1114 snprintb(bits, sizeof(bits), STP4020_ICR1_BITS, 1115 stp4020_rd_sockctl(h, STP4020_ICR1_IDX)); 1116 printf("\tICR1=%s\n", bits); 1117 1118 snprintb(bits, sizeof(bits), STP4020_ISR0_IOBITS, 1119 stp4020_rd_sockctl(h, STP4020_ISR0_IDX)); 1120 printf("\tISR0=%s\n", bits); 1121 1122 snprintb(bits, sizeof(bits), STP4020_ISR1_BITS, 1123 stp4020_rd_sockctl(h, STP4020_ISR1_IDX)); 1124 printf("\tISR1=%s\n", bits); 1125 } 1126 #endif /* STP4020_DEBUG */ 1127
Indexes created Thu Oct 02 14:10:14 GMT 2025