stp4020.c revision 1.59
1 /* $NetBSD: stp4020.c,v 1.59 2009/03/16 23:11:16 dsl Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * STP4020: SBus/PCMCIA bridge supporting two Type-3 PCMCIA cards. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: stp4020.c,v 1.59 2009/03/16 23:11:16 dsl Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/errno.h> 42 #include <sys/malloc.h> 43 #include <sys/extent.h> 44 #include <sys/proc.h> 45 #include <sys/kernel.h> 46 #include <sys/kthread.h> 47 #include <sys/device.h> 48 #include <sys/intr.h> 49 50 #include <dev/pcmcia/pcmciareg.h> 51 #include <dev/pcmcia/pcmciavar.h> 52 #include <dev/pcmcia/pcmciachip.h> 53 54 #include <sys/bus.h> 55 56 #include <dev/sbus/sbusvar.h> 57 #include <dev/sbus/stp4020reg.h> 58 59 #define STP4020_DEBUG 1 /* XXX-temp */ 60 61 /* 62 * We use the three available windows per socket in a simple, fixed 63 * arrangement. Each window maps (at full 1 MB size) one of the pcmcia 64 * spaces into sbus space. 65 */ 66 #define STP_WIN_ATTR 0 /* index of the attribute memory space window */ 67 #define STP_WIN_MEM 1 /* index of the common memory space window */ 68 #define STP_WIN_IO 2 /* index of the io space window */ 69 70 71 #if defined(STP4020_DEBUG) 72 int stp4020_debug = 0; 73 #define DPRINTF(x) do { if (stp4020_debug) printf x; } while(0) 74 #else 75 #define DPRINTF(x) 76 #endif 77 78 /* 79 * Event queue; events detected in an interrupt context go here 80 * awaiting attention from our event handling thread. 81 */ 82 struct stp4020_event { 83 SIMPLEQ_ENTRY(stp4020_event) se_q; 84 int se_type; 85 int se_sock; 86 }; 87 /* Defined event types */ 88 #define STP4020_EVENT_INSERTION 0 89 #define STP4020_EVENT_REMOVAL 1 90 91 /* 92 * Per socket data. 93 */ 94 struct stp4020_socket { 95 struct stp4020_softc *sc; /* Back link */ 96 int flags; 97 #define STP4020_SOCKET_BUSY 0x0001 98 int sock; /* Socket number (0 or 1) */ 99 int sbus_intno; /* Do we use first (0) or second (1) 100 interrupt? */ 101 #ifndef SUN4U 102 int int_enable; /* ICR0 value for interrupt enabled */ 103 int int_disable; /* ICR0 value for interrupt disabled */ 104 #endif 105 bus_space_tag_t tag; /* socket control io */ 106 bus_space_handle_t regs; /* space */ 107 bus_space_tag_t pcmciat; /* io space for pcmcia */ 108 struct device *pcmcia; /* Associated PCMCIA device */ 109 int (*intrhandler) /* Card driver interrupt handler */ 110 (void *); 111 void *intrarg; /* Card interrupt handler argument */ 112 #ifndef SUN4U 113 void *softint; /* cookie for the softintr */ 114 #endif 115 116 struct { 117 bus_space_handle_t winaddr;/* this window's address */ 118 } windows[STP4020_NWIN]; 119 120 }; 121 122 struct stp4020_softc { 123 struct device sc_dev; /* Base device */ 124 struct sbusdev sc_sd; /* SBus device */ 125 pcmcia_chipset_tag_t sc_pct; /* Chipset methods */ 126 127 struct lwp *event_thread; /* event handling thread */ 128 SIMPLEQ_HEAD(, stp4020_event) events; /* Pending events for thread */ 129 130 struct stp4020_socket sc_socks[STP4020_NSOCK]; 131 #ifndef SUN4U 132 bool sc_use_softint; 133 #endif 134 }; 135 136 137 static int stp4020print(void *, const char *); 138 static int stp4020match(struct device *, struct cfdata *, void *); 139 static void stp4020attach(struct device *, struct device *, void *); 140 static int stp4020_intr(void *); 141 static void stp4020_map_window(struct stp4020_socket *h, int win, int speed); 142 static void stp4020_calc_speed(int bus_speed, int ns, int *length, int *cmd_delay); 143 #ifndef SUN4U 144 static void stp4020_intr_dispatch(void *arg); 145 #endif 146 147 CFATTACH_DECL(nell, sizeof(struct stp4020_softc), 148 stp4020match, stp4020attach, NULL, NULL); 149 150 #ifdef STP4020_DEBUG 151 static void stp4020_dump_regs(struct stp4020_socket *); 152 #endif 153 154 static int stp4020_rd_sockctl(struct stp4020_socket *, int); 155 static void stp4020_wr_sockctl(struct stp4020_socket *, int, int); 156 static int stp4020_rd_winctl(struct stp4020_socket *, int, int); 157 static void stp4020_wr_winctl(struct stp4020_socket *, int, int, int); 158 159 void stp4020_delay(struct stp4020_softc *sc, unsigned int); 160 void stp4020_attach_socket(struct stp4020_socket *, int); 161 void stp4020_event_thread(void *); 162 void stp4020_queue_event(struct stp4020_softc *, int, int); 163 164 int stp4020_chip_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 165 struct pcmcia_mem_handle *); 166 void stp4020_chip_mem_free(pcmcia_chipset_handle_t, 167 struct pcmcia_mem_handle *); 168 int stp4020_chip_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 169 bus_size_t, struct pcmcia_mem_handle *, 170 bus_size_t *, int *); 171 void stp4020_chip_mem_unmap(pcmcia_chipset_handle_t, int); 172 173 int stp4020_chip_io_alloc(pcmcia_chipset_handle_t, 174 bus_addr_t, bus_size_t, bus_size_t, 175 struct pcmcia_io_handle *); 176 void stp4020_chip_io_free(pcmcia_chipset_handle_t, 177 struct pcmcia_io_handle *); 178 int stp4020_chip_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 179 bus_size_t, struct pcmcia_io_handle *, int *); 180 void stp4020_chip_io_unmap(pcmcia_chipset_handle_t, int); 181 182 void stp4020_chip_socket_enable(pcmcia_chipset_handle_t); 183 void stp4020_chip_socket_disable(pcmcia_chipset_handle_t); 184 void stp4020_chip_socket_settype(pcmcia_chipset_handle_t, int); 185 void *stp4020_chip_intr_establish(pcmcia_chipset_handle_t, 186 struct pcmcia_function *, int, 187 int (*)(void *), void *); 188 void stp4020_chip_intr_disestablish(pcmcia_chipset_handle_t, void *); 189 190 /* Our PCMCIA chipset methods */ 191 static struct pcmcia_chip_functions stp4020_functions = { 192 stp4020_chip_mem_alloc, 193 stp4020_chip_mem_free, 194 stp4020_chip_mem_map, 195 stp4020_chip_mem_unmap, 196 197 stp4020_chip_io_alloc, 198 stp4020_chip_io_free, 199 stp4020_chip_io_map, 200 stp4020_chip_io_unmap, 201 202 stp4020_chip_intr_establish, 203 stp4020_chip_intr_disestablish, 204 205 stp4020_chip_socket_enable, 206 stp4020_chip_socket_disable, 207 stp4020_chip_socket_settype, 208 NULL 209 }; 210 211 212 static inline int 213 stp4020_rd_sockctl(struct stp4020_socket *h, int idx) 214 { 215 int o = ((STP4020_SOCKREGS_SIZE * (h->sock)) + idx); 216 return (bus_space_read_2(h->tag, h->regs, o)); 217 } 218 219 static inline void 220 stp4020_wr_sockctl(struct stp4020_socket *h, int idx, int v) 221 { 222 int o = (STP4020_SOCKREGS_SIZE * (h->sock)) + idx; 223 bus_space_write_2(h->tag, h->regs, o, v); 224 } 225 226 static inline int 227 stp4020_rd_winctl(struct stp4020_socket *h, int win, int idx) 228 { 229 int o = (STP4020_SOCKREGS_SIZE * (h->sock)) + 230 (STP4020_WINREGS_SIZE * win) + idx; 231 return (bus_space_read_2(h->tag, h->regs, o)); 232 } 233 234 static inline void 235 stp4020_wr_winctl(struct stp4020_socket *h, int win, int idx, int v) 236 { 237 int o = (STP4020_SOCKREGS_SIZE * (h->sock)) + 238 (STP4020_WINREGS_SIZE * win) + idx; 239 240 bus_space_write_2(h->tag, h->regs, o, v); 241 } 242 243 #ifndef SUN4U /* XXX - move to SBUS machdep function? */ 244 245 static u_int16_t stp4020_read_2(bus_space_tag_t, 246 bus_space_handle_t, 247 bus_size_t); 248 static u_int32_t stp4020_read_4(bus_space_tag_t, 249 bus_space_handle_t, 250 bus_size_t); 251 static u_int64_t stp4020_read_8(bus_space_tag_t, 252 bus_space_handle_t, 253 bus_size_t); 254 static void stp4020_write_2(bus_space_tag_t, 255 bus_space_handle_t, 256 bus_size_t, 257 u_int16_t); 258 static void stp4020_write_4(bus_space_tag_t, 259 bus_space_handle_t, 260 bus_size_t, 261 u_int32_t); 262 static void stp4020_write_8(bus_space_tag_t, 263 bus_space_handle_t, 264 bus_size_t, 265 u_int64_t); 266 267 static u_int16_t 268 stp4020_read_2(bus_space_tag_t space, bus_space_handle_t handle, bus_size_t offset) 269 { 270 return (le16toh(*(volatile u_int16_t *)(handle + offset))); 271 } 272 273 static u_int32_t 274 stp4020_read_4(bus_space_tag_t space, bus_space_handle_t handle, bus_size_t offset) 275 { 276 return (le32toh(*(volatile u_int32_t *)(handle + offset))); 277 } 278 279 static u_int64_t 280 stp4020_read_8(bus_space_tag_t space, bus_space_handle_t handle, bus_size_t offset) 281 { 282 return (le64toh(*(volatile u_int64_t *)(handle + offset))); 283 } 284 285 static void 286 stp4020_write_2(bus_space_tag_t space, bus_space_handle_t handle, bus_size_t offset, u_int16_t value) 287 { 288 (*(volatile u_int16_t *)(handle + offset)) = htole16(value); 289 } 290 291 static void 292 stp4020_write_4(bus_space_tag_t space, bus_space_handle_t handle, bus_size_t offset, u_int32_t value) 293 { 294 (*(volatile u_int32_t *)(handle + offset)) = htole32(value); 295 } 296 297 static void 298 stp4020_write_8(bus_space_tag_t space, bus_space_handle_t handle, bus_size_t offset, u_int64_t value) 299 { 300 (*(volatile u_int64_t *)(handle + offset)) = htole64(value); 301 } 302 #endif /* SUN4U */ 303 304 int 305 stp4020print(void *aux, const char *busname) 306 { 307 struct pcmciabus_attach_args *paa = aux; 308 struct stp4020_socket *h = paa->pch; 309 310 aprint_normal(" socket %d", h->sock); 311 return (UNCONF); 312 } 313 314 int 315 stp4020match(struct device *parent, struct cfdata *cf, void *aux) 316 { 317 struct sbus_attach_args *sa = aux; 318 319 return (strcmp("SUNW,pcmcia", sa->sa_name) == 0); 320 } 321 322 /* 323 * Attach all the sub-devices we can find 324 */ 325 void 326 stp4020attach(struct device *parent, struct device *self, void *aux) 327 { 328 struct sbus_attach_args *sa = aux; 329 struct stp4020_softc *sc = (void *)self; 330 bus_space_tag_t tag; 331 int rev, i, sbus_intno, hw_ipl; 332 bus_space_handle_t bh; 333 334 /* Transfer bus tags */ 335 #ifdef SUN4U 336 tag = sa->sa_bustag; 337 #else 338 tag = bus_space_tag_alloc(sa->sa_bustag, sc); 339 if (tag == NULL) { 340 aprint_error_dev(self, "attach: out of memory\n"); 341 return; 342 } 343 tag->sparc_read_2 = stp4020_read_2; 344 tag->sparc_read_4 = stp4020_read_4; 345 tag->sparc_read_8 = stp4020_read_8; 346 tag->sparc_write_2 = stp4020_write_2; 347 tag->sparc_write_4 = stp4020_write_4; 348 tag->sparc_write_8 = stp4020_write_8; 349 #endif /* SUN4U */ 350 351 /* check interrupt options, decide if we need a softint */ 352 #ifdef SUN4U 353 /* 354 * On sparc64 the hardware interrupt priority does not restrict 355 * the IPL we run our interrupt handler on, so we can always just 356 * use the first interrupt and reqest the handler to run at 357 * IPL_VM. 358 */ 359 sbus_intno = 0; 360 hw_ipl = IPL_VM; 361 #else 362 /* 363 * We need to check if one of the available interrupts has 364 * a priority that allows us to establish a handler at IPL_VM. 365 * If not (hard to imagine), use a soft interrupt. 366 */ 367 sbus_intno = -1; 368 for (i = 0; i < sa->sa_nintr; i++) { 369 struct sbus_softc *bus = 370 (struct sbus_softc *) sa->sa_bustag->cookie; 371 int ipl = bus->sc_intr2ipl[sa->sa_intr[i].oi_pri]; 372 if (ipl <= IPL_VM) { 373 sbus_intno = i; 374 sc->sc_use_softint = false; 375 hw_ipl = IPL_VM; 376 break; 377 } 378 } 379 if (sbus_intno == -1) { 380 /* 381 * We have not found a usable hardware interrupt - so 382 * use a softint to bounce to the proper IPL. 383 */ 384 printf("no usable HW interrupt found, using softint\n"); 385 sbus_intno = 0; 386 sc->sc_use_softint = true; 387 hw_ipl = IPL_NONE; 388 } 389 #endif 390 391 /* Set up per-socket static initialization */ 392 sc->sc_socks[0].sc = sc->sc_socks[1].sc = sc; 393 sc->sc_socks[0].tag = sc->sc_socks[1].tag = sa->sa_bustag; 394 /* 395 * XXX we rely on "tag" accepting the same handle-domain 396 * as sa->sa_bustag. 397 */ 398 sc->sc_socks[0].pcmciat = sc->sc_socks[1].pcmciat = tag; 399 sc->sc_socks[0].sbus_intno = 400 sc->sc_socks[1].sbus_intno = sbus_intno; 401 402 if (sa->sa_nreg < 8) { 403 printf("%s: only %d register sets\n", 404 device_xname(self), sa->sa_nreg); 405 return; 406 } 407 408 if (sa->sa_nintr != 2) { 409 printf("%s: expect 2 interrupt Sbus levels; got %d\n", 410 device_xname(self), sa->sa_nintr); 411 return; 412 } 413 414 #define STP4020_BANK_PROM 0 415 #define STP4020_BANK_CTRL 4 416 for (i = 0; i < 8; i++) { 417 418 /* 419 * STP4020 Register address map: 420 * bank 0: Forth PROM 421 * banks 1-3: socket 0, windows 0-2 422 * bank 4: control registers 423 * banks 5-7: socket 1, windows 0-2 424 */ 425 426 if (i == STP4020_BANK_PROM) 427 /* Skip the PROM */ 428 continue; 429 430 if (sbus_bus_map(sa->sa_bustag, 431 sa->sa_reg[i].oa_space, 432 sa->sa_reg[i].oa_base, 433 sa->sa_reg[i].oa_size, 434 0, &bh) != 0) { 435 aprint_error_dev(self, "attach: cannot map registers\n"); 436 return; 437 } 438 439 if (i == STP4020_BANK_CTRL) { 440 /* 441 * Copy tag and handle to both socket structures 442 * for easy access in control/status IO functions. 443 */ 444 sc->sc_socks[0].regs = sc->sc_socks[1].regs = bh; 445 } else if (i < STP4020_BANK_CTRL) { 446 /* banks 1-3 */ 447 sc->sc_socks[0].windows[i-1].winaddr = bh; 448 } else { 449 /* banks 5-7 */ 450 sc->sc_socks[1].windows[i-5].winaddr = bh; 451 } 452 } 453 454 sbus_establish(&sc->sc_sd, &sc->sc_dev); 455 456 /* We only use one interrupt level. */ 457 if (sa->sa_nintr > sbus_intno) { 458 bus_intr_establish(sa->sa_bustag, 459 sa->sa_intr[sbus_intno].oi_pri, 460 hw_ipl, stp4020_intr, sc); 461 } 462 463 rev = stp4020_rd_sockctl(&sc->sc_socks[0], STP4020_ISR1_IDX) & 464 STP4020_ISR1_REV_M; 465 printf(": rev %x\n", rev); 466 467 sc->sc_pct = (pcmcia_chipset_tag_t)&stp4020_functions; 468 469 SIMPLEQ_INIT(&sc->events); 470 471 for (i = 0; i < STP4020_NSOCK; i++) { 472 struct stp4020_socket *h = &sc->sc_socks[i]; 473 h->sock = i; 474 h->sc = sc; 475 #ifdef STP4020_DEBUG 476 if (stp4020_debug) 477 stp4020_dump_regs(h); 478 #endif 479 stp4020_attach_socket(h, sa->sa_frequency); 480 } 481 482 /* 483 * Arrange that a kernel thread be created to handle 484 * insert/removal events. 485 */ 486 if (kthread_create(PRI_NONE, 0, NULL, stp4020_event_thread, sc, 487 &sc->event_thread, "%s", device_xname(self))) { 488 panic("%s: unable to create event thread", device_xname(self)); 489 } 490 } 491 492 void 493 stp4020_attach_socket(struct stp4020_socket *h, int speed) 494 { 495 struct pcmciabus_attach_args paa; 496 int v; 497 498 /* no interrupt handlers yet */ 499 h->intrhandler = NULL; 500 h->intrarg = NULL; 501 #ifndef SUN4U 502 h->softint = NULL; 503 h->int_enable = 0; 504 h->int_disable = 0; 505 #endif 506 507 /* Map all three windows */ 508 stp4020_map_window(h, STP_WIN_ATTR, speed); 509 stp4020_map_window(h, STP_WIN_MEM, speed); 510 stp4020_map_window(h, STP_WIN_IO, speed); 511 512 /* Configure one pcmcia device per socket */ 513 paa.paa_busname = "pcmcia"; 514 paa.pct = (pcmcia_chipset_tag_t)h->sc->sc_pct; 515 paa.pch = (pcmcia_chipset_handle_t)h; 516 paa.iobase = 0; 517 paa.iosize = STP4020_WINDOW_SIZE; 518 519 h->pcmcia = config_found(&h->sc->sc_dev, &paa, stp4020print); 520 521 if (h->pcmcia == NULL) 522 return; 523 524 /* 525 * There's actually a pcmcia bus attached; initialize the slot. 526 */ 527 528 /* 529 * Clear things up before we enable status change interrupts. 530 * This seems to not be fully initialized by the PROM. 531 */ 532 stp4020_wr_sockctl(h, STP4020_ICR1_IDX, 0); 533 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, 0); 534 stp4020_wr_sockctl(h, STP4020_ISR1_IDX, 0x3fff); 535 stp4020_wr_sockctl(h, STP4020_ISR0_IDX, 0x3fff); 536 537 /* 538 * Enable socket status change interrupts. 539 * We only use one common interrupt for status change 540 * and IO, to avoid locking issues. 541 */ 542 v = STP4020_ICR0_ALL_STATUS_IE 543 | (h->sbus_intno ? STP4020_ICR0_SCILVL_SB1 544 : STP4020_ICR0_SCILVL_SB0); 545 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, v); 546 547 /* Get live status bits from ISR0 and clear pending interrupts */ 548 v = stp4020_rd_sockctl(h, STP4020_ISR0_IDX); 549 stp4020_wr_sockctl(h, STP4020_ISR0_IDX, v); 550 551 if ((v & (STP4020_ISR0_CD1ST|STP4020_ISR0_CD2ST)) == 0) 552 return; 553 554 pcmcia_card_attach(h->pcmcia); 555 h->flags |= STP4020_SOCKET_BUSY; 556 } 557 558 /* 559 * The actual event handling thread. 560 */ 561 void 562 stp4020_event_thread(void *arg) 563 { 564 struct stp4020_softc *sc = arg; 565 struct stp4020_event *e; 566 int s; 567 568 while (1) { 569 struct stp4020_socket *h; 570 int n; 571 572 s = splhigh(); 573 if ((e = SIMPLEQ_FIRST(&sc->events)) == NULL) { 574 splx(s); 575 (void)tsleep(&sc->events, PWAIT, "nellevt", 0); 576 continue; 577 } 578 SIMPLEQ_REMOVE_HEAD(&sc->events, se_q); 579 splx(s); 580 581 n = e->se_sock; 582 if (n < 0 || n >= STP4020_NSOCK) 583 panic("stp4020_event_thread: wayward socket number %d", 584 n); 585 586 h = &sc->sc_socks[n]; 587 switch (e->se_type) { 588 case STP4020_EVENT_INSERTION: 589 pcmcia_card_attach(h->pcmcia); 590 break; 591 case STP4020_EVENT_REMOVAL: 592 pcmcia_card_detach(h->pcmcia, DETACH_FORCE); 593 break; 594 default: 595 panic("stp4020_event_thread: unknown event type %d", 596 e->se_type); 597 } 598 free(e, M_TEMP); 599 } 600 } 601 602 void 603 stp4020_queue_event(struct stp4020_softc *sc, int sock, int event) 604 { 605 struct stp4020_event *e; 606 int s; 607 608 e = malloc(sizeof(*e), M_TEMP, M_NOWAIT); 609 if (e == NULL) 610 panic("stp4020_queue_event: can't allocate event"); 611 612 e->se_type = event; 613 e->se_sock = sock; 614 s = splhigh(); 615 SIMPLEQ_INSERT_TAIL(&sc->events, e, se_q); 616 splx(s); 617 wakeup(&sc->events); 618 } 619 620 #ifndef SUN4U 621 /* 622 * Softinterrupt called to invoke the real driver interrupt handler. 623 */ 624 static void 625 stp4020_intr_dispatch(void *arg) 626 { 627 struct stp4020_socket *h = arg; 628 int s; 629 630 /* invoke driver handler */ 631 h->intrhandler(h->intrarg); 632 633 /* enable SBUS interrupts for pcmcia interrupts again */ 634 s = splhigh(); 635 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, h->int_enable); 636 splx(s); 637 } 638 #endif 639 640 int 641 stp4020_intr(void *arg) 642 { 643 struct stp4020_softc *sc = arg; 644 #ifndef SUN4U 645 int s; 646 #endif 647 int i, r = 0, cd_change = 0; 648 649 650 #ifndef SUN4U 651 /* protect hardware access by splhigh against softint */ 652 s = splhigh(); 653 #endif 654 655 /* 656 * Check each socket for pending requests. 657 */ 658 for (i = 0 ; i < STP4020_NSOCK; i++) { 659 struct stp4020_socket *h; 660 int v; 661 662 h = &sc->sc_socks[i]; 663 664 v = stp4020_rd_sockctl(h, STP4020_ISR0_IDX); 665 666 /* Ack all interrupts at once. */ 667 stp4020_wr_sockctl(h, STP4020_ISR0_IDX, v); 668 669 #ifdef STP4020_DEBUG 670 if (stp4020_debug != 0) { 671 char bits[64]; 672 snprintb(bits, sizeof(bits), STP4020_ISR0_IOBITS, v); 673 printf("stp4020_statintr: ISR0=%s\n", bits); 674 } 675 #endif 676 677 if ((v & STP4020_ISR0_CDCHG) != 0) { 678 /* 679 * Card status change detect 680 */ 681 cd_change = 1; 682 r = 1; 683 if ((v & (STP4020_ISR0_CD1ST|STP4020_ISR0_CD2ST)) == (STP4020_ISR0_CD1ST|STP4020_ISR0_CD2ST)){ 684 if ((h->flags & STP4020_SOCKET_BUSY) == 0) { 685 stp4020_queue_event(sc, i, 686 STP4020_EVENT_INSERTION); 687 h->flags |= STP4020_SOCKET_BUSY; 688 } 689 } 690 if ((v & (STP4020_ISR0_CD1ST|STP4020_ISR0_CD2ST)) == 0){ 691 if ((h->flags & STP4020_SOCKET_BUSY) != 0) { 692 stp4020_queue_event(sc, i, 693 STP4020_EVENT_REMOVAL); 694 h->flags &= ~STP4020_SOCKET_BUSY; 695 } 696 } 697 } 698 699 if ((v & STP4020_ISR0_IOINT) != 0) { 700 /* we can not deny this is ours, no matter what the 701 card driver says. */ 702 r = 1; 703 704 /* It's a card interrupt */ 705 if ((h->flags & STP4020_SOCKET_BUSY) == 0) { 706 printf("stp4020[%d]: spurious interrupt?\n", 707 h->sock); 708 continue; 709 } 710 711 #ifndef SUN4U 712 /* 713 * Schedule softint to invoke driver interrupt 714 * handler 715 */ 716 if (h->softint != NULL) 717 sparc_softintr_schedule(h->softint); 718 /* 719 * Disable this sbus interrupt, until the soft-int 720 * handler had a chance to run 721 */ 722 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, h->int_disable); 723 #else 724 (*h->intrhandler)(h->intrarg); 725 #endif 726 } 727 728 /* informational messages */ 729 if ((v & STP4020_ISR0_BVD1CHG) != 0) { 730 /* ignore if this is caused by insert or removal */ 731 if (!cd_change) 732 printf("stp4020[%d]: Battery change 1\n", h->sock); 733 r = 1; 734 } 735 736 if ((v & STP4020_ISR0_BVD2CHG) != 0) { 737 /* ignore if this is caused by insert or removal */ 738 if (!cd_change) 739 printf("stp4020[%d]: Battery change 2\n", h->sock); 740 r = 1; 741 } 742 743 if ((v & STP4020_ISR0_SCINT) != 0) { 744 DPRINTF(("stp4020[%d]: status change\n", h->sock)); 745 r = 1; 746 } 747 748 if ((v & STP4020_ISR0_RDYCHG) != 0) { 749 DPRINTF(("stp4020[%d]: Ready/Busy change\n", h->sock)); 750 r = 1; 751 } 752 753 if ((v & STP4020_ISR0_WPCHG) != 0) { 754 DPRINTF(("stp4020[%d]: Write protect change\n", h->sock)); 755 r = 1; 756 } 757 758 if ((v & STP4020_ISR0_PCTO) != 0) { 759 DPRINTF(("stp4020[%d]: Card access timeout\n", h->sock)); 760 r = 1; 761 } 762 763 if ((v & ~STP4020_ISR0_LIVE) && r == 0) 764 printf("stp4020[%d]: unhandled interrupt: 0x%x\n", h->sock, v); 765 766 } 767 #ifndef SUN4U 768 splx(s); 769 #endif 770 771 return (r); 772 } 773 774 /* 775 * The function gets the sbus speed and a access time and calculates 776 * values for the CMDLNG and CMDDLAY registers. 777 */ 778 static void 779 stp4020_calc_speed(int bus_speed, int ns, int *length, int *cmd_delay) 780 { 781 int result; 782 783 if (ns < STP4020_MEM_SPEED_MIN) 784 ns = STP4020_MEM_SPEED_MIN; 785 else if (ns > STP4020_MEM_SPEED_MAX) 786 ns = STP4020_MEM_SPEED_MAX; 787 result = ns*(bus_speed/1000); 788 if (result % 1000000) 789 result = result/1000000 + 1; 790 else 791 result /= 1000000; 792 *length = result; 793 794 /* the sbus frequency range is limited, so we can keep this simple */ 795 *cmd_delay = ns <= STP4020_MEM_SPEED_MIN? 1 : 2; 796 } 797 798 static void 799 stp4020_map_window(struct stp4020_socket *h, int win, int speed) 800 { 801 int v, length, cmd_delay; 802 803 /* 804 * According to the PC Card standard 300ns access timing should be 805 * used for attribute memory access. Our pcmcia framework does not 806 * seem to propagate timing information, so we use that 807 * everywhere. 808 */ 809 stp4020_calc_speed(speed, (win==STP_WIN_ATTR)? 300 : 100, &length, &cmd_delay); 810 811 /* 812 * Fill in the Address Space Select and Base Address 813 * fields of this windows control register 0. 814 */ 815 v = ((cmd_delay << STP4020_WCR0_CMDDLY_S)&STP4020_WCR0_CMDDLY_M) 816 | ((length << STP4020_WCR0_CMDLNG_S)&STP4020_WCR0_CMDLNG_M); 817 switch (win) { 818 case STP_WIN_ATTR: 819 v |= STP4020_WCR0_ASPSEL_AM; 820 break; 821 case STP_WIN_MEM: 822 v |= STP4020_WCR0_ASPSEL_CM; 823 break; 824 case STP_WIN_IO: 825 v |= STP4020_WCR0_ASPSEL_IO; 826 break; 827 } 828 v |= (STP4020_ADDR2PAGE(0) & STP4020_WCR0_BASE_M); 829 stp4020_wr_winctl(h, win, STP4020_WCR0_IDX, v); 830 stp4020_wr_winctl(h, win, STP4020_WCR1_IDX, 1<<STP4020_WCR1_WAITREQ_S); 831 } 832 833 int 834 stp4020_chip_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, struct pcmcia_mem_handle *pcmhp) 835 { 836 struct stp4020_socket *h = (struct stp4020_socket *)pch; 837 838 /* we can not do much here, defere work to _mem_map */ 839 pcmhp->memt = h->pcmciat; 840 pcmhp->size = size; 841 pcmhp->addr = 0; 842 pcmhp->mhandle = 0; 843 pcmhp->realsize = size; 844 845 return (0); 846 } 847 848 void 849 stp4020_chip_mem_free(pcmcia_chipset_handle_t pch, struct pcmcia_mem_handle *pcmhp) 850 { 851 } 852 853 int 854 stp4020_chip_mem_map(pcmcia_chipset_handle_t pch, int kind, bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, bus_size_t *offsetp, int *windowp) 855 { 856 struct stp4020_socket *h = (struct stp4020_socket *)pch; 857 int win = (kind&PCMCIA_MEM_ATTR)? STP_WIN_ATTR : STP_WIN_MEM; 858 859 pcmhp->memt = h->pcmciat; 860 bus_space_subregion(h->pcmciat, h->windows[win].winaddr, card_addr, size, &pcmhp->memh); 861 #ifdef SUN4U 862 if ((u_int8_t)pcmhp->memh._asi == ASI_PHYS_NON_CACHED) 863 pcmhp->memh._asi = ASI_PHYS_NON_CACHED_LITTLE; 864 else if ((u_int8_t)pcmhp->memh._asi == ASI_PRIMARY) 865 pcmhp->memh._asi = ASI_PRIMARY_LITTLE; 866 #endif 867 pcmhp->size = size; 868 pcmhp->realsize = STP4020_WINDOW_SIZE - card_addr; 869 *offsetp = 0; 870 *windowp = 0; 871 872 return (0); 873 } 874 875 void 876 stp4020_chip_mem_unmap(pcmcia_chipset_handle_t pch, int win) 877 { 878 } 879 880 int 881 stp4020_chip_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 882 { 883 struct stp4020_socket *h = (struct stp4020_socket *)pch; 884 885 pcihp->iot = h->pcmciat; 886 pcihp->ioh = h->windows[STP_WIN_IO].winaddr; 887 return 0; 888 } 889 890 void 891 stp4020_chip_io_free(pcmcia_chipset_handle_t pch, struct pcmcia_io_handle *pcihp) 892 { 893 } 894 895 int 896 stp4020_chip_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 897 { 898 struct stp4020_socket *h = (struct stp4020_socket *)pch; 899 900 pcihp->iot = h->pcmciat; 901 bus_space_subregion(h->pcmciat, h->windows[STP_WIN_IO].winaddr, offset, size, &pcihp->ioh); 902 #ifdef SUN4U 903 if ((u_int8_t)pcihp->ioh._asi == ASI_PHYS_NON_CACHED) 904 pcihp->ioh._asi = ASI_PHYS_NON_CACHED_LITTLE; 905 else if ((u_int8_t)pcihp->ioh._asi == ASI_PRIMARY) 906 pcihp->ioh._asi = ASI_PRIMARY_LITTLE; 907 #endif 908 *windowp = 0; 909 return 0; 910 } 911 912 void 913 stp4020_chip_io_unmap(pcmcia_chipset_handle_t pch, int win) 914 { 915 } 916 917 void 918 stp4020_chip_socket_enable(pcmcia_chipset_handle_t pch) 919 { 920 struct stp4020_socket *h = (struct stp4020_socket *)pch; 921 int i, v; 922 923 /* this bit is mostly stolen from pcic_attach_card */ 924 925 /* Power down the socket to reset it, clear the card reset pin */ 926 stp4020_wr_sockctl(h, STP4020_ICR1_IDX, 0); 927 928 /* 929 * wait 300ms until power fails (Tpf). Then, wait 100ms since 930 * we are changing Vcc (Toff). 931 */ 932 stp4020_delay(h->sc, 300 + 100); 933 934 /* Power up the socket */ 935 v = STP4020_ICR1_MSTPWR; 936 stp4020_wr_sockctl(h, STP4020_ICR1_IDX, v); 937 938 /* 939 * wait 100ms until power raise (Tpr) and 20ms to become 940 * stable (Tsu(Vcc)). 941 */ 942 stp4020_delay(h->sc, 100 + 20); 943 944 v |= STP4020_ICR1_PCIFOE|STP4020_ICR1_VPP1_VCC; 945 stp4020_wr_sockctl(h, STP4020_ICR1_IDX, v); 946 947 /* 948 * hold RESET at least 10us. 949 */ 950 delay(10); 951 952 /* Clear reset flag, set to memory mode */ 953 v = stp4020_rd_sockctl(h, STP4020_ICR0_IDX); 954 v &= ~(STP4020_ICR0_IOIE | STP4020_ICR0_IOILVL | STP4020_ICR0_IFTYPE | 955 STP4020_ICR0_SPKREN); 956 v &= ~STP4020_ICR0_RESET; 957 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, v); 958 959 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 960 stp4020_delay(h->sc, 20); 961 962 /* Wait for the chip to finish initializing (5 seconds max) */ 963 for (i = 10000; i > 0; i--) { 964 v = stp4020_rd_sockctl(h, STP4020_ISR0_IDX); 965 if ((v & STP4020_ISR0_RDYST) != 0) 966 break; 967 delay(500); 968 } 969 if (i <= 0) { 970 char bits[64]; 971 snprintb(bits, sizeof(bits), 972 STP4020_ISR0_IOBITS, 973 stp4020_rd_sockctl(h, STP4020_ISR0_IDX)); 974 printf("stp4020_chip_socket_enable: not ready: status %s\n", 975 bits); 976 return; 977 } 978 } 979 980 void 981 stp4020_chip_socket_settype(pcmcia_chipset_handle_t pch, int type) 982 { 983 struct stp4020_socket *h = (struct stp4020_socket *)pch; 984 int v; 985 986 /* 987 * Check the card type. 988 * Enable socket I/O interrupts for IO cards. 989 */ 990 v = stp4020_rd_sockctl(h, STP4020_ICR0_IDX); 991 v &= ~(STP4020_ICR0_IOIE | STP4020_ICR0_IOILVL | STP4020_ICR0_IFTYPE | 992 STP4020_ICR0_SPKREN); 993 if (type == PCMCIA_IFTYPE_IO) { 994 v |= STP4020_ICR0_IFTYPE_IO|STP4020_ICR0_IOIE 995 |STP4020_ICR0_SPKREN; 996 v |= h->sbus_intno ? STP4020_ICR0_IOILVL_SB1 997 : STP4020_ICR0_IOILVL_SB0; 998 #ifndef SUN4U 999 h->int_enable = v; 1000 h->int_disable = v & ~STP4020_ICR0_IOIE; 1001 #endif 1002 DPRINTF(("%s: configuring card for IO useage\n", device_xname(&h->sc->sc_dev))); 1003 } else { 1004 v |= STP4020_ICR0_IFTYPE_MEM; 1005 #ifndef SUN4U 1006 h->int_enable = h->int_disable = v; 1007 #endif 1008 DPRINTF(("%s: configuring card for IO useage\n", device_xname(&h->sc->sc_dev))); 1009 DPRINTF(("%s: configuring card for MEM ONLY useage\n", device_xname(&h->sc->sc_dev))); 1010 } 1011 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, v); 1012 } 1013 1014 void 1015 stp4020_chip_socket_disable(pcmcia_chipset_handle_t pch) 1016 { 1017 struct stp4020_socket *h = (struct stp4020_socket *)pch; 1018 int v; 1019 1020 /* 1021 * Disable socket I/O interrupts. 1022 */ 1023 v = stp4020_rd_sockctl(h, STP4020_ICR0_IDX); 1024 v &= ~(STP4020_ICR0_IOIE | STP4020_ICR0_IOILVL | STP4020_ICR0_IFTYPE | 1025 STP4020_ICR0_SPKREN); 1026 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, v); 1027 1028 /* Power down the socket */ 1029 stp4020_wr_sockctl(h, STP4020_ICR1_IDX, 0); 1030 1031 /* 1032 * wait 300ms until power fails (Tpf). 1033 */ 1034 stp4020_delay(h->sc, 300); 1035 } 1036 1037 void * 1038 stp4020_chip_intr_establish(pcmcia_chipset_handle_t pch, struct pcmcia_function *pf, int ipl, int (*handler)(void *), void *arg) 1039 { 1040 struct stp4020_socket *h = (struct stp4020_socket *)pch; 1041 1042 /* only one interrupt handler per slot */ 1043 if (h->intrhandler != NULL) return NULL; 1044 1045 h->intrhandler = handler; 1046 h->intrarg = arg; 1047 #ifndef SUN4U 1048 if (h->sc->sc_use_softint) { 1049 h->softint = sparc_softintr_establish(ipl, stp4020_intr_dispatch, h); 1050 return h->softint; 1051 } 1052 #endif 1053 return h; 1054 } 1055 1056 void 1057 stp4020_chip_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 1058 { 1059 struct stp4020_socket *h = (struct stp4020_socket *)pch; 1060 1061 h->intrhandler = NULL; 1062 h->intrarg = NULL; 1063 #ifndef SUN4U 1064 if (h->softint) { 1065 sparc_softintr_disestablish(h->softint); 1066 h->softint = NULL; 1067 } 1068 #endif 1069 } 1070 1071 /* 1072 * Delay and possibly yield CPU. 1073 * XXX - assumes a context 1074 */ 1075 void 1076 stp4020_delay(struct stp4020_softc *sc, unsigned int ms) 1077 { 1078 unsigned int ticks = mstohz(ms); 1079 1080 if (cold || ticks == 0) { 1081 delay(ms); 1082 return; 1083 } 1084 1085 #ifdef DIAGNOSTIC 1086 if (ticks > 60*hz) 1087 panic("stp4020: preposterous delay: %u", ticks); 1088 #endif 1089 tsleep(sc, 0, "nelldel", ticks); 1090 } 1091 1092 #ifdef STP4020_DEBUG 1093 void 1094 stp4020_dump_regs(struct stp4020_socket *h) 1095 { 1096 char bits[64]; 1097 /* 1098 * Dump control and status registers. 1099 */ 1100 printf("socket[%d] registers:\n", h->sock); 1101 snprintb(bits, sizeof(bits), STP4020_ICR0_BITS, 1102 stp4020_rd_sockctl(h, STP4020_ICR0_IDX)); 1103 printf("\tICR0=%s\n", bits); 1104 1105 snprintb(bits, sizeof(bits), STP4020_ICR1_BITS, 1106 stp4020_rd_sockctl(h, STP4020_ICR1_IDX)); 1107 printf("\tICR1=%s\n", bits); 1108 1109 snprintb(bits, sizeof(bits), STP4020_ISR0_IOBITS, 1110 stp4020_rd_sockctl(h, STP4020_ISR0_IDX)); 1111 printf("\tISR0=%s\n", bits); 1112 1113 snprintb(bits, sizeof(bits), STP4020_ISR1_BITS, 1114 stp4020_rd_sockctl(h, STP4020_ISR1_IDX)); 1115 printf("\tISR1=%s\n", bits); 1116 } 1117 #endif /* STP4020_DEBUG */ 1118
Indexes created Thu Oct 02 14:10:14 GMT 2025