stp4020.c revision 1.65
1 /* $NetBSD: stp4020.c,v 1.65 2011/07/18 00:58:52 mrg Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * STP4020: SBus/PCMCIA bridge supporting two Type-3 PCMCIA cards. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: stp4020.c,v 1.65 2011/07/18 00:58:52 mrg Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/errno.h> 42 #include <sys/malloc.h> 43 #include <sys/extent.h> 44 #include <sys/proc.h> 45 #include <sys/kernel.h> 46 #include <sys/kthread.h> 47 #include <sys/device.h> 48 #include <sys/intr.h> 49 50 #include <dev/pcmcia/pcmciareg.h> 51 #include <dev/pcmcia/pcmciavar.h> 52 #include <dev/pcmcia/pcmciachip.h> 53 54 #include <sys/bus.h> 55 56 #include <dev/sbus/sbusvar.h> 57 #include <dev/sbus/stp4020reg.h> 58 59 #define STP4020_DEBUG 1 /* XXX-temp */ 60 61 /* 62 * We use the three available windows per socket in a simple, fixed 63 * arrangement. Each window maps (at full 1 MB size) one of the pcmcia 64 * spaces into sbus space. 65 */ 66 #define STP_WIN_ATTR 0 /* index of the attribute memory space window */ 67 #define STP_WIN_MEM 1 /* index of the common memory space window */ 68 #define STP_WIN_IO 2 /* index of the io space window */ 69 70 71 #if defined(STP4020_DEBUG) 72 int stp4020_debug = 0; 73 #define DPRINTF(x) do { if (stp4020_debug) printf x; } while(0) 74 #else 75 #define DPRINTF(x) 76 #endif 77 78 /* 79 * Event queue; events detected in an interrupt context go here 80 * awaiting attention from our event handling thread. 81 */ 82 struct stp4020_event { 83 SIMPLEQ_ENTRY(stp4020_event) se_q; 84 int se_type; 85 int se_sock; 86 }; 87 /* Defined event types */ 88 #define STP4020_EVENT_INSERTION 0 89 #define STP4020_EVENT_REMOVAL 1 90 91 /* 92 * Per socket data. 93 */ 94 struct stp4020_socket { 95 struct stp4020_softc *sc; /* Back link */ 96 int flags; 97 #define STP4020_SOCKET_BUSY 0x0001 98 int sock; /* Socket number (0 or 1) */ 99 int sbus_intno; /* Do we use first (0) or second (1) 100 interrupt? */ 101 #ifndef SUN4U 102 int int_enable; /* ICR0 value for interrupt enabled */ 103 int int_disable; /* ICR0 value for interrupt disabled */ 104 #endif 105 bus_space_tag_t tag; /* socket control io */ 106 bus_space_handle_t regs; /* space */ 107 bus_space_tag_t pcmciat; /* io space for pcmcia */ 108 struct device *pcmcia; /* Associated PCMCIA device */ 109 int (*intrhandler) /* Card driver interrupt handler */ 110 (void *); 111 void *intrarg; /* Card interrupt handler argument */ 112 #ifndef SUN4U 113 void *softint; /* cookie for the softintr */ 114 #endif 115 116 struct { 117 bus_space_handle_t winaddr;/* this window's address */ 118 } windows[STP4020_NWIN]; 119 120 }; 121 122 struct stp4020_softc { 123 device_t sc_dev; 124 pcmcia_chipset_tag_t sc_pct; /* Chipset methods */ 125 126 struct lwp *event_thread; /* event handling thread */ 127 SIMPLEQ_HEAD(, stp4020_event) events; /* Pending events for thread */ 128 129 struct stp4020_socket sc_socks[STP4020_NSOCK]; 130 #ifndef SUN4U 131 bool sc_use_softint; 132 #endif 133 }; 134 135 136 static int stp4020print(void *, const char *); 137 static int stp4020match(device_t, cfdata_t, void *); 138 static void stp4020attach(device_t, device_t, void *); 139 static int stp4020_intr(void *); 140 static void stp4020_map_window(struct stp4020_socket *h, int win, int speed); 141 static void stp4020_calc_speed(int bus_speed, int ns, int *length, int *cmd_delay); 142 #ifndef SUN4U 143 static void stp4020_intr_dispatch(void *arg); 144 #endif 145 146 CFATTACH_DECL_NEW(nell, sizeof(struct stp4020_softc), 147 stp4020match, stp4020attach, NULL, NULL); 148 149 #ifdef STP4020_DEBUG 150 static void stp4020_dump_regs(struct stp4020_socket *); 151 #endif 152 153 static int stp4020_rd_sockctl(struct stp4020_socket *, int); 154 static void stp4020_wr_sockctl(struct stp4020_socket *, int, int); 155 static int stp4020_rd_winctl(struct stp4020_socket *, int, int); 156 static void stp4020_wr_winctl(struct stp4020_socket *, int, int, int); 157 158 void stp4020_delay(struct stp4020_softc *sc, unsigned int); 159 void stp4020_attach_socket(struct stp4020_socket *, int); 160 void stp4020_event_thread(void *); 161 void stp4020_queue_event(struct stp4020_softc *, int, int); 162 163 int stp4020_chip_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 164 struct pcmcia_mem_handle *); 165 void stp4020_chip_mem_free(pcmcia_chipset_handle_t, 166 struct pcmcia_mem_handle *); 167 int stp4020_chip_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 168 bus_size_t, struct pcmcia_mem_handle *, 169 bus_size_t *, int *); 170 void stp4020_chip_mem_unmap(pcmcia_chipset_handle_t, int); 171 172 int stp4020_chip_io_alloc(pcmcia_chipset_handle_t, 173 bus_addr_t, bus_size_t, bus_size_t, 174 struct pcmcia_io_handle *); 175 void stp4020_chip_io_free(pcmcia_chipset_handle_t, 176 struct pcmcia_io_handle *); 177 int stp4020_chip_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 178 bus_size_t, struct pcmcia_io_handle *, int *); 179 void stp4020_chip_io_unmap(pcmcia_chipset_handle_t, int); 180 181 void stp4020_chip_socket_enable(pcmcia_chipset_handle_t); 182 void stp4020_chip_socket_disable(pcmcia_chipset_handle_t); 183 void stp4020_chip_socket_settype(pcmcia_chipset_handle_t, int); 184 void *stp4020_chip_intr_establish(pcmcia_chipset_handle_t, 185 struct pcmcia_function *, int, 186 int (*)(void *), void *); 187 void stp4020_chip_intr_disestablish(pcmcia_chipset_handle_t, void *); 188 189 /* Our PCMCIA chipset methods */ 190 static struct pcmcia_chip_functions stp4020_functions = { 191 stp4020_chip_mem_alloc, 192 stp4020_chip_mem_free, 193 stp4020_chip_mem_map, 194 stp4020_chip_mem_unmap, 195 196 stp4020_chip_io_alloc, 197 stp4020_chip_io_free, 198 stp4020_chip_io_map, 199 stp4020_chip_io_unmap, 200 201 stp4020_chip_intr_establish, 202 stp4020_chip_intr_disestablish, 203 204 stp4020_chip_socket_enable, 205 stp4020_chip_socket_disable, 206 stp4020_chip_socket_settype, 207 NULL 208 }; 209 210 211 static inline int 212 stp4020_rd_sockctl(struct stp4020_socket *h, int idx) 213 { 214 int o = ((STP4020_SOCKREGS_SIZE * (h->sock)) + idx); 215 return (bus_space_read_2(h->tag, h->regs, o)); 216 } 217 218 static inline void 219 stp4020_wr_sockctl(struct stp4020_socket *h, int idx, int v) 220 { 221 int o = (STP4020_SOCKREGS_SIZE * (h->sock)) + idx; 222 bus_space_write_2(h->tag, h->regs, o, v); 223 } 224 225 static inline int 226 stp4020_rd_winctl(struct stp4020_socket *h, int win, int idx) 227 { 228 int o = (STP4020_SOCKREGS_SIZE * (h->sock)) + 229 (STP4020_WINREGS_SIZE * win) + idx; 230 return (bus_space_read_2(h->tag, h->regs, o)); 231 } 232 233 static inline void 234 stp4020_wr_winctl(struct stp4020_socket *h, int win, int idx, int v) 235 { 236 int o = (STP4020_SOCKREGS_SIZE * (h->sock)) + 237 (STP4020_WINREGS_SIZE * win) + idx; 238 239 bus_space_write_2(h->tag, h->regs, o, v); 240 } 241 242 #ifndef SUN4U /* XXX - move to SBUS machdep function? */ 243 244 static uint16_t stp4020_read_2(bus_space_tag_t, 245 bus_space_handle_t, 246 bus_size_t); 247 static uint32_t stp4020_read_4(bus_space_tag_t, 248 bus_space_handle_t, 249 bus_size_t); 250 static uint64_t stp4020_read_8(bus_space_tag_t, 251 bus_space_handle_t, 252 bus_size_t); 253 static void stp4020_write_2(bus_space_tag_t, 254 bus_space_handle_t, 255 bus_size_t, 256 uint16_t); 257 static void stp4020_write_4(bus_space_tag_t, 258 bus_space_handle_t, 259 bus_size_t, 260 uint32_t); 261 static void stp4020_write_8(bus_space_tag_t, 262 bus_space_handle_t, 263 bus_size_t, 264 uint64_t); 265 266 static uint16_t 267 stp4020_read_2(bus_space_tag_t space, bus_space_handle_t handle, bus_size_t offset) 268 { 269 return (le16toh(*(volatile uint16_t *)(handle + offset))); 270 } 271 272 static uint32_t 273 stp4020_read_4(bus_space_tag_t space, bus_space_handle_t handle, bus_size_t offset) 274 { 275 return (le32toh(*(volatile uint32_t *)(handle + offset))); 276 } 277 278 static uint64_t 279 stp4020_read_8(bus_space_tag_t space, bus_space_handle_t handle, bus_size_t offset) 280 { 281 return (le64toh(*(volatile uint64_t *)(handle + offset))); 282 } 283 284 static void 285 stp4020_write_2(bus_space_tag_t space, bus_space_handle_t handle, bus_size_t offset, uint16_t value) 286 { 287 (*(volatile uint16_t *)(handle + offset)) = htole16(value); 288 } 289 290 static void 291 stp4020_write_4(bus_space_tag_t space, bus_space_handle_t handle, bus_size_t offset, uint32_t value) 292 { 293 (*(volatile uint32_t *)(handle + offset)) = htole32(value); 294 } 295 296 static void 297 stp4020_write_8(bus_space_tag_t space, bus_space_handle_t handle, bus_size_t offset, uint64_t value) 298 { 299 (*(volatile uint64_t *)(handle + offset)) = htole64(value); 300 } 301 #endif /* SUN4U */ 302 303 int 304 stp4020print(void *aux, const char *busname) 305 { 306 struct pcmciabus_attach_args *paa = aux; 307 struct stp4020_socket *h = paa->pch; 308 309 aprint_normal(" socket %d", h->sock); 310 return (UNCONF); 311 } 312 313 int 314 stp4020match(device_t parent, cfdata_t cf, void *aux) 315 { 316 struct sbus_attach_args *sa = aux; 317 318 return (strcmp("SUNW,pcmcia", sa->sa_name) == 0); 319 } 320 321 /* 322 * Attach all the sub-devices we can find 323 */ 324 void 325 stp4020attach(device_t parent, device_t self, void *aux) 326 { 327 struct sbus_attach_args *sa = aux; 328 struct stp4020_softc *sc = device_private(self); 329 bus_space_tag_t tag; 330 int rev, i, sbus_intno, hw_ipl; 331 bus_space_handle_t bh; 332 333 sc->sc_dev = self; 334 335 /* Transfer bus tags */ 336 #ifdef SUN4U 337 tag = sa->sa_bustag; 338 #else 339 tag = bus_space_tag_alloc(sa->sa_bustag, sc); 340 if (tag == NULL) { 341 aprint_error_dev(self, "attach: out of memory\n"); 342 return; 343 } 344 tag->sparc_read_2 = stp4020_read_2; 345 tag->sparc_read_4 = stp4020_read_4; 346 tag->sparc_read_8 = stp4020_read_8; 347 tag->sparc_write_2 = stp4020_write_2; 348 tag->sparc_write_4 = stp4020_write_4; 349 tag->sparc_write_8 = stp4020_write_8; 350 #endif /* SUN4U */ 351 352 /* check interrupt options, decide if we need a softint */ 353 #ifdef SUN4U 354 /* 355 * On sparc64 the hardware interrupt priority does not restrict 356 * the IPL we run our interrupt handler on, so we can always just 357 * use the first interrupt and reqest the handler to run at 358 * IPL_VM. 359 */ 360 sbus_intno = 0; 361 hw_ipl = IPL_VM; 362 #else 363 /* 364 * We need to check if one of the available interrupts has 365 * a priority that allows us to establish a handler at IPL_VM. 366 * If not (hard to imagine), use a soft interrupt. 367 */ 368 sbus_intno = -1; 369 for (i = 0; i < sa->sa_nintr; i++) { 370 struct sbus_softc *bus = 371 (struct sbus_softc *) sa->sa_bustag->cookie; 372 int ipl = bus->sc_intr2ipl[sa->sa_intr[i].oi_pri]; 373 if (ipl <= IPL_VM) { 374 sbus_intno = i; 375 sc->sc_use_softint = false; 376 hw_ipl = IPL_VM; 377 break; 378 } 379 } 380 if (sbus_intno == -1) { 381 /* 382 * We have not found a usable hardware interrupt - so 383 * use a softint to bounce to the proper IPL. 384 */ 385 printf("no usable HW interrupt found, using softint\n"); 386 sbus_intno = 0; 387 sc->sc_use_softint = true; 388 hw_ipl = IPL_NONE; 389 } 390 #endif 391 392 /* Set up per-socket static initialization */ 393 sc->sc_socks[0].sc = sc->sc_socks[1].sc = sc; 394 sc->sc_socks[0].tag = sc->sc_socks[1].tag = sa->sa_bustag; 395 /* 396 * XXX we rely on "tag" accepting the same handle-domain 397 * as sa->sa_bustag. 398 */ 399 sc->sc_socks[0].pcmciat = sc->sc_socks[1].pcmciat = tag; 400 sc->sc_socks[0].sbus_intno = 401 sc->sc_socks[1].sbus_intno = sbus_intno; 402 403 if (sa->sa_nreg < 8) { 404 printf("%s: only %d register sets\n", 405 device_xname(self), sa->sa_nreg); 406 return; 407 } 408 409 if (sa->sa_nintr != 2) { 410 printf("%s: expect 2 interrupt Sbus levels; got %d\n", 411 device_xname(self), sa->sa_nintr); 412 return; 413 } 414 415 #define STP4020_BANK_PROM 0 416 #define STP4020_BANK_CTRL 4 417 for (i = 0; i < 8; i++) { 418 419 /* 420 * STP4020 Register address map: 421 * bank 0: Forth PROM 422 * banks 1-3: socket 0, windows 0-2 423 * bank 4: control registers 424 * banks 5-7: socket 1, windows 0-2 425 */ 426 427 if (i == STP4020_BANK_PROM) 428 /* Skip the PROM */ 429 continue; 430 431 if (sbus_bus_map(sa->sa_bustag, 432 sa->sa_reg[i].oa_space, 433 sa->sa_reg[i].oa_base, 434 sa->sa_reg[i].oa_size, 435 0, &bh) != 0) { 436 aprint_error_dev(self, "attach: cannot map registers\n"); 437 return; 438 } 439 440 if (i == STP4020_BANK_CTRL) { 441 /* 442 * Copy tag and handle to both socket structures 443 * for easy access in control/status IO functions. 444 */ 445 sc->sc_socks[0].regs = sc->sc_socks[1].regs = bh; 446 } else if (i < STP4020_BANK_CTRL) { 447 /* banks 1-3 */ 448 sc->sc_socks[0].windows[i-1].winaddr = bh; 449 } else { 450 /* banks 5-7 */ 451 sc->sc_socks[1].windows[i-5].winaddr = bh; 452 } 453 } 454 455 /* We only use one interrupt level. */ 456 if (sa->sa_nintr > sbus_intno) { 457 bus_intr_establish(sa->sa_bustag, 458 sa->sa_intr[sbus_intno].oi_pri, 459 hw_ipl, stp4020_intr, sc); 460 } 461 462 rev = stp4020_rd_sockctl(&sc->sc_socks[0], STP4020_ISR1_IDX) & 463 STP4020_ISR1_REV_M; 464 printf(": rev %x\n", rev); 465 466 sc->sc_pct = (pcmcia_chipset_tag_t)&stp4020_functions; 467 468 SIMPLEQ_INIT(&sc->events); 469 470 for (i = 0; i < STP4020_NSOCK; i++) { 471 struct stp4020_socket *h = &sc->sc_socks[i]; 472 h->sock = i; 473 h->sc = sc; 474 #ifdef STP4020_DEBUG 475 if (stp4020_debug) 476 stp4020_dump_regs(h); 477 #endif 478 stp4020_attach_socket(h, sa->sa_frequency); 479 } 480 481 /* 482 * Arrange that a kernel thread be created to handle 483 * insert/removal events. 484 */ 485 if (kthread_create(PRI_NONE, 0, NULL, stp4020_event_thread, sc, 486 &sc->event_thread, "%s", device_xname(self))) { 487 panic("%s: unable to create event thread", device_xname(self)); 488 } 489 } 490 491 void 492 stp4020_attach_socket(struct stp4020_socket *h, int speed) 493 { 494 struct pcmciabus_attach_args paa; 495 int v; 496 497 /* no interrupt handlers yet */ 498 h->intrhandler = NULL; 499 h->intrarg = NULL; 500 #ifndef SUN4U 501 h->softint = NULL; 502 h->int_enable = 0; 503 h->int_disable = 0; 504 #endif 505 506 /* Map all three windows */ 507 stp4020_map_window(h, STP_WIN_ATTR, speed); 508 stp4020_map_window(h, STP_WIN_MEM, speed); 509 stp4020_map_window(h, STP_WIN_IO, speed); 510 511 /* Configure one pcmcia device per socket */ 512 paa.paa_busname = "pcmcia"; 513 paa.pct = (pcmcia_chipset_tag_t)h->sc->sc_pct; 514 paa.pch = (pcmcia_chipset_handle_t)h; 515 paa.iobase = 0; 516 paa.iosize = STP4020_WINDOW_SIZE; 517 518 h->pcmcia = config_found(h->sc->sc_dev, &paa, stp4020print); 519 520 if (h->pcmcia == NULL) 521 return; 522 523 /* 524 * There's actually a pcmcia bus attached; initialize the slot. 525 */ 526 527 /* 528 * Clear things up before we enable status change interrupts. 529 * This seems to not be fully initialized by the PROM. 530 */ 531 stp4020_wr_sockctl(h, STP4020_ICR1_IDX, 0); 532 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, 0); 533 stp4020_wr_sockctl(h, STP4020_ISR1_IDX, 0x3fff); 534 stp4020_wr_sockctl(h, STP4020_ISR0_IDX, 0x3fff); 535 536 /* 537 * Enable socket status change interrupts. 538 * We only use one common interrupt for status change 539 * and IO, to avoid locking issues. 540 */ 541 v = STP4020_ICR0_ALL_STATUS_IE 542 | (h->sbus_intno ? STP4020_ICR0_SCILVL_SB1 543 : STP4020_ICR0_SCILVL_SB0); 544 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, v); 545 546 /* Get live status bits from ISR0 and clear pending interrupts */ 547 v = stp4020_rd_sockctl(h, STP4020_ISR0_IDX); 548 stp4020_wr_sockctl(h, STP4020_ISR0_IDX, v); 549 550 if ((v & (STP4020_ISR0_CD1ST|STP4020_ISR0_CD2ST)) == 0) 551 return; 552 553 pcmcia_card_attach(h->pcmcia); 554 h->flags |= STP4020_SOCKET_BUSY; 555 } 556 557 /* 558 * The actual event handling thread. 559 */ 560 void 561 stp4020_event_thread(void *arg) 562 { 563 struct stp4020_softc *sc = arg; 564 struct stp4020_event *e; 565 int s; 566 567 while (1) { 568 struct stp4020_socket *h; 569 int n; 570 571 s = splhigh(); 572 if ((e = SIMPLEQ_FIRST(&sc->events)) == NULL) { 573 splx(s); 574 (void)tsleep(&sc->events, PWAIT, "nellevt", 0); 575 continue; 576 } 577 SIMPLEQ_REMOVE_HEAD(&sc->events, se_q); 578 splx(s); 579 580 n = e->se_sock; 581 if (n < 0 || n >= STP4020_NSOCK) 582 panic("stp4020_event_thread: wayward socket number %d", 583 n); 584 585 h = &sc->sc_socks[n]; 586 switch (e->se_type) { 587 case STP4020_EVENT_INSERTION: 588 pcmcia_card_attach(h->pcmcia); 589 break; 590 case STP4020_EVENT_REMOVAL: 591 pcmcia_card_detach(h->pcmcia, DETACH_FORCE); 592 break; 593 default: 594 panic("stp4020_event_thread: unknown event type %d", 595 e->se_type); 596 } 597 free(e, M_TEMP); 598 } 599 } 600 601 void 602 stp4020_queue_event(struct stp4020_softc *sc, int sock, int event) 603 { 604 struct stp4020_event *e; 605 int s; 606 607 e = malloc(sizeof(*e), M_TEMP, M_NOWAIT); 608 if (e == NULL) 609 panic("stp4020_queue_event: can't allocate event"); 610 611 e->se_type = event; 612 e->se_sock = sock; 613 s = splhigh(); 614 SIMPLEQ_INSERT_TAIL(&sc->events, e, se_q); 615 splx(s); 616 wakeup(&sc->events); 617 } 618 619 #ifndef SUN4U 620 /* 621 * Softinterrupt called to invoke the real driver interrupt handler. 622 */ 623 static void 624 stp4020_intr_dispatch(void *arg) 625 { 626 struct stp4020_socket *h = arg; 627 int s; 628 629 /* invoke driver handler */ 630 h->intrhandler(h->intrarg); 631 632 /* enable SBUS interrupts for pcmcia interrupts again */ 633 s = splhigh(); 634 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, h->int_enable); 635 splx(s); 636 } 637 #endif 638 639 int 640 stp4020_intr(void *arg) 641 { 642 struct stp4020_softc *sc = arg; 643 #ifndef SUN4U 644 int s; 645 #endif 646 int i, r = 0, cd_change = 0; 647 648 649 #ifndef SUN4U 650 /* protect hardware access by splhigh against softint */ 651 s = splhigh(); 652 #endif 653 654 /* 655 * Check each socket for pending requests. 656 */ 657 for (i = 0 ; i < STP4020_NSOCK; i++) { 658 struct stp4020_socket *h; 659 int v; 660 661 h = &sc->sc_socks[i]; 662 663 v = stp4020_rd_sockctl(h, STP4020_ISR0_IDX); 664 665 /* Ack all interrupts at once. */ 666 stp4020_wr_sockctl(h, STP4020_ISR0_IDX, v); 667 668 #ifdef STP4020_DEBUG 669 if (stp4020_debug != 0) { 670 char bits[64]; 671 snprintb(bits, sizeof(bits), STP4020_ISR0_IOBITS, v); 672 printf("stp4020_statintr: ISR0=%s\n", bits); 673 } 674 #endif 675 676 if ((v & STP4020_ISR0_CDCHG) != 0) { 677 /* 678 * Card status change detect 679 */ 680 cd_change = 1; 681 r = 1; 682 if ((v & (STP4020_ISR0_CD1ST|STP4020_ISR0_CD2ST)) == (STP4020_ISR0_CD1ST|STP4020_ISR0_CD2ST)){ 683 if ((h->flags & STP4020_SOCKET_BUSY) == 0) { 684 stp4020_queue_event(sc, i, 685 STP4020_EVENT_INSERTION); 686 h->flags |= STP4020_SOCKET_BUSY; 687 } 688 } 689 if ((v & (STP4020_ISR0_CD1ST|STP4020_ISR0_CD2ST)) == 0){ 690 if ((h->flags & STP4020_SOCKET_BUSY) != 0) { 691 stp4020_queue_event(sc, i, 692 STP4020_EVENT_REMOVAL); 693 h->flags &= ~STP4020_SOCKET_BUSY; 694 } 695 } 696 } 697 698 if ((v & STP4020_ISR0_IOINT) != 0) { 699 /* we can not deny this is ours, no matter what the 700 card driver says. */ 701 r = 1; 702 703 /* It's a card interrupt */ 704 if ((h->flags & STP4020_SOCKET_BUSY) == 0) { 705 printf("stp4020[%d]: spurious interrupt?\n", 706 h->sock); 707 continue; 708 } 709 710 #ifndef SUN4U 711 /* 712 * Schedule softint to invoke driver interrupt 713 * handler 714 */ 715 if (h->softint != NULL) 716 sparc_softintr_schedule(h->softint); 717 /* 718 * Disable this sbus interrupt, until the soft-int 719 * handler had a chance to run 720 */ 721 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, h->int_disable); 722 #else 723 (*h->intrhandler)(h->intrarg); 724 #endif 725 } 726 727 /* informational messages */ 728 if ((v & STP4020_ISR0_BVD1CHG) != 0) { 729 /* ignore if this is caused by insert or removal */ 730 if (!cd_change) 731 printf("stp4020[%d]: Battery change 1\n", h->sock); 732 r = 1; 733 } 734 735 if ((v & STP4020_ISR0_BVD2CHG) != 0) { 736 /* ignore if this is caused by insert or removal */ 737 if (!cd_change) 738 printf("stp4020[%d]: Battery change 2\n", h->sock); 739 r = 1; 740 } 741 742 if ((v & STP4020_ISR0_SCINT) != 0) { 743 DPRINTF(("stp4020[%d]: status change\n", h->sock)); 744 r = 1; 745 } 746 747 if ((v & STP4020_ISR0_RDYCHG) != 0) { 748 DPRINTF(("stp4020[%d]: Ready/Busy change\n", h->sock)); 749 r = 1; 750 } 751 752 if ((v & STP4020_ISR0_WPCHG) != 0) { 753 DPRINTF(("stp4020[%d]: Write protect change\n", h->sock)); 754 r = 1; 755 } 756 757 if ((v & STP4020_ISR0_PCTO) != 0) { 758 DPRINTF(("stp4020[%d]: Card access timeout\n", h->sock)); 759 r = 1; 760 } 761 762 if ((v & ~STP4020_ISR0_LIVE) && r == 0) 763 printf("stp4020[%d]: unhandled interrupt: 0x%x\n", h->sock, v); 764 765 } 766 #ifndef SUN4U 767 splx(s); 768 #endif 769 770 return (r); 771 } 772 773 /* 774 * The function gets the sbus speed and a access time and calculates 775 * values for the CMDLNG and CMDDLAY registers. 776 */ 777 static void 778 stp4020_calc_speed(int bus_speed, int ns, int *length, int *cmd_delay) 779 { 780 int result; 781 782 if (ns < STP4020_MEM_SPEED_MIN) 783 ns = STP4020_MEM_SPEED_MIN; 784 else if (ns > STP4020_MEM_SPEED_MAX) 785 ns = STP4020_MEM_SPEED_MAX; 786 result = ns*(bus_speed/1000); 787 if (result % 1000000) 788 result = result/1000000 + 1; 789 else 790 result /= 1000000; 791 *length = result; 792 793 /* the sbus frequency range is limited, so we can keep this simple */ 794 *cmd_delay = ns <= STP4020_MEM_SPEED_MIN? 1 : 2; 795 } 796 797 static void 798 stp4020_map_window(struct stp4020_socket *h, int win, int speed) 799 { 800 int v, length, cmd_delay; 801 802 /* 803 * According to the PC Card standard 300ns access timing should be 804 * used for attribute memory access. Our pcmcia framework does not 805 * seem to propagate timing information, so we use that 806 * everywhere. 807 */ 808 stp4020_calc_speed(speed, (win==STP_WIN_ATTR)? 300 : 100, &length, &cmd_delay); 809 810 /* 811 * Fill in the Address Space Select and Base Address 812 * fields of this windows control register 0. 813 */ 814 v = ((cmd_delay << STP4020_WCR0_CMDDLY_S)&STP4020_WCR0_CMDDLY_M) 815 | ((length << STP4020_WCR0_CMDLNG_S)&STP4020_WCR0_CMDLNG_M); 816 switch (win) { 817 case STP_WIN_ATTR: 818 v |= STP4020_WCR0_ASPSEL_AM; 819 break; 820 case STP_WIN_MEM: 821 v |= STP4020_WCR0_ASPSEL_CM; 822 break; 823 case STP_WIN_IO: 824 v |= STP4020_WCR0_ASPSEL_IO; 825 break; 826 } 827 v |= (STP4020_ADDR2PAGE(0) & STP4020_WCR0_BASE_M); 828 stp4020_wr_winctl(h, win, STP4020_WCR0_IDX, v); 829 stp4020_wr_winctl(h, win, STP4020_WCR1_IDX, 1<<STP4020_WCR1_WAITREQ_S); 830 } 831 832 int 833 stp4020_chip_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, struct pcmcia_mem_handle *pcmhp) 834 { 835 struct stp4020_socket *h = (struct stp4020_socket *)pch; 836 837 /* we can not do much here, defere work to _mem_map */ 838 pcmhp->memt = h->pcmciat; 839 pcmhp->size = size; 840 pcmhp->addr = 0; 841 pcmhp->mhandle = 0; 842 pcmhp->realsize = size; 843 844 return (0); 845 } 846 847 void 848 stp4020_chip_mem_free(pcmcia_chipset_handle_t pch, struct pcmcia_mem_handle *pcmhp) 849 { 850 } 851 852 int 853 stp4020_chip_mem_map(pcmcia_chipset_handle_t pch, int kind, bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, bus_size_t *offsetp, int *windowp) 854 { 855 struct stp4020_socket *h = (struct stp4020_socket *)pch; 856 int win = (kind&PCMCIA_MEM_ATTR)? STP_WIN_ATTR : STP_WIN_MEM; 857 858 pcmhp->memt = h->pcmciat; 859 bus_space_subregion(h->pcmciat, h->windows[win].winaddr, card_addr, size, &pcmhp->memh); 860 #ifdef SUN4U 861 if ((uint8_t)pcmhp->memh._asi == ASI_PHYS_NON_CACHED) 862 pcmhp->memh._asi = ASI_PHYS_NON_CACHED_LITTLE; 863 else if ((uint8_t)pcmhp->memh._asi == ASI_PRIMARY) 864 pcmhp->memh._asi = ASI_PRIMARY_LITTLE; 865 #endif 866 pcmhp->size = size; 867 pcmhp->realsize = STP4020_WINDOW_SIZE - card_addr; 868 *offsetp = 0; 869 *windowp = 0; 870 871 return (0); 872 } 873 874 void 875 stp4020_chip_mem_unmap(pcmcia_chipset_handle_t pch, int win) 876 { 877 } 878 879 int 880 stp4020_chip_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 881 { 882 struct stp4020_socket *h = (struct stp4020_socket *)pch; 883 884 pcihp->iot = h->pcmciat; 885 pcihp->ioh = h->windows[STP_WIN_IO].winaddr; 886 return 0; 887 } 888 889 void 890 stp4020_chip_io_free(pcmcia_chipset_handle_t pch, struct pcmcia_io_handle *pcihp) 891 { 892 } 893 894 int 895 stp4020_chip_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 896 { 897 struct stp4020_socket *h = (struct stp4020_socket *)pch; 898 899 pcihp->iot = h->pcmciat; 900 bus_space_subregion(h->pcmciat, h->windows[STP_WIN_IO].winaddr, offset, size, &pcihp->ioh); 901 #ifdef SUN4U 902 if ((uint8_t)pcihp->ioh._asi == ASI_PHYS_NON_CACHED) 903 pcihp->ioh._asi = ASI_PHYS_NON_CACHED_LITTLE; 904 else if ((uint8_t)pcihp->ioh._asi == ASI_PRIMARY) 905 pcihp->ioh._asi = ASI_PRIMARY_LITTLE; 906 #endif 907 *windowp = 0; 908 return 0; 909 } 910 911 void 912 stp4020_chip_io_unmap(pcmcia_chipset_handle_t pch, int win) 913 { 914 } 915 916 void 917 stp4020_chip_socket_enable(pcmcia_chipset_handle_t pch) 918 { 919 struct stp4020_socket *h = (struct stp4020_socket *)pch; 920 int i, v; 921 922 /* this bit is mostly stolen from pcic_attach_card */ 923 924 /* Power down the socket to reset it, clear the card reset pin */ 925 stp4020_wr_sockctl(h, STP4020_ICR1_IDX, 0); 926 927 /* 928 * wait 300ms until power fails (Tpf). Then, wait 100ms since 929 * we are changing Vcc (Toff). 930 */ 931 stp4020_delay(h->sc, 300 + 100); 932 933 /* Power up the socket */ 934 v = STP4020_ICR1_MSTPWR; 935 stp4020_wr_sockctl(h, STP4020_ICR1_IDX, v); 936 937 /* 938 * wait 100ms until power raise (Tpr) and 20ms to become 939 * stable (Tsu(Vcc)). 940 */ 941 stp4020_delay(h->sc, 100 + 20); 942 943 v |= STP4020_ICR1_PCIFOE|STP4020_ICR1_VPP1_VCC; 944 stp4020_wr_sockctl(h, STP4020_ICR1_IDX, v); 945 946 /* 947 * hold RESET at least 10us. 948 */ 949 delay(10); 950 951 /* Clear reset flag, set to memory mode */ 952 v = stp4020_rd_sockctl(h, STP4020_ICR0_IDX); 953 v &= ~(STP4020_ICR0_IOIE | STP4020_ICR0_IOILVL | STP4020_ICR0_IFTYPE | 954 STP4020_ICR0_SPKREN); 955 v &= ~STP4020_ICR0_RESET; 956 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, v); 957 958 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 959 stp4020_delay(h->sc, 20); 960 961 /* Wait for the chip to finish initializing (5 seconds max) */ 962 for (i = 10000; i > 0; i--) { 963 v = stp4020_rd_sockctl(h, STP4020_ISR0_IDX); 964 if ((v & STP4020_ISR0_RDYST) != 0) 965 break; 966 delay(500); 967 } 968 if (i <= 0) { 969 char bits[64]; 970 snprintb(bits, sizeof(bits), 971 STP4020_ISR0_IOBITS, 972 stp4020_rd_sockctl(h, STP4020_ISR0_IDX)); 973 printf("stp4020_chip_socket_enable: not ready: status %s\n", 974 bits); 975 return; 976 } 977 } 978 979 void 980 stp4020_chip_socket_settype(pcmcia_chipset_handle_t pch, int type) 981 { 982 struct stp4020_socket *h = (struct stp4020_socket *)pch; 983 int v; 984 985 /* 986 * Check the card type. 987 * Enable socket I/O interrupts for IO cards. 988 */ 989 v = stp4020_rd_sockctl(h, STP4020_ICR0_IDX); 990 v &= ~(STP4020_ICR0_IOIE | STP4020_ICR0_IOILVL | STP4020_ICR0_IFTYPE | 991 STP4020_ICR0_SPKREN); 992 if (type == PCMCIA_IFTYPE_IO) { 993 v |= STP4020_ICR0_IFTYPE_IO|STP4020_ICR0_IOIE 994 |STP4020_ICR0_SPKREN; 995 v |= h->sbus_intno ? STP4020_ICR0_IOILVL_SB1 996 : STP4020_ICR0_IOILVL_SB0; 997 #ifndef SUN4U 998 h->int_enable = v; 999 h->int_disable = v & ~STP4020_ICR0_IOIE; 1000 #endif 1001 DPRINTF(("%s: configuring card for IO useage\n", device_xname(h->sc->sc_dev))); 1002 } else { 1003 v |= STP4020_ICR0_IFTYPE_MEM; 1004 #ifndef SUN4U 1005 h->int_enable = h->int_disable = v; 1006 #endif 1007 DPRINTF(("%s: configuring card for IO useage\n", device_xname(h->sc->sc_dev))); 1008 DPRINTF(("%s: configuring card for MEM ONLY useage\n", device_xname(h->sc->sc_dev))); 1009 } 1010 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, v); 1011 } 1012 1013 void 1014 stp4020_chip_socket_disable(pcmcia_chipset_handle_t pch) 1015 { 1016 struct stp4020_socket *h = (struct stp4020_socket *)pch; 1017 int v; 1018 1019 /* 1020 * Disable socket I/O interrupts. 1021 */ 1022 v = stp4020_rd_sockctl(h, STP4020_ICR0_IDX); 1023 v &= ~(STP4020_ICR0_IOIE | STP4020_ICR0_IOILVL | STP4020_ICR0_IFTYPE | 1024 STP4020_ICR0_SPKREN); 1025 stp4020_wr_sockctl(h, STP4020_ICR0_IDX, v); 1026 1027 /* Power down the socket */ 1028 stp4020_wr_sockctl(h, STP4020_ICR1_IDX, 0); 1029 1030 /* 1031 * wait 300ms until power fails (Tpf). 1032 */ 1033 stp4020_delay(h->sc, 300); 1034 } 1035 1036 void * 1037 stp4020_chip_intr_establish(pcmcia_chipset_handle_t pch, struct pcmcia_function *pf, int ipl, int (*handler)(void *), void *arg) 1038 { 1039 struct stp4020_socket *h = (struct stp4020_socket *)pch; 1040 1041 /* only one interrupt handler per slot */ 1042 if (h->intrhandler != NULL) return NULL; 1043 1044 h->intrhandler = handler; 1045 h->intrarg = arg; 1046 #ifndef SUN4U 1047 if (h->sc->sc_use_softint) { 1048 h->softint = sparc_softintr_establish(ipl, stp4020_intr_dispatch, h); 1049 return h->softint; 1050 } 1051 #endif 1052 return h; 1053 } 1054 1055 void 1056 stp4020_chip_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 1057 { 1058 struct stp4020_socket *h = (struct stp4020_socket *)pch; 1059 1060 h->intrhandler = NULL; 1061 h->intrarg = NULL; 1062 #ifndef SUN4U 1063 if (h->softint) { 1064 sparc_softintr_disestablish(h->softint); 1065 h->softint = NULL; 1066 } 1067 #endif 1068 } 1069 1070 /* 1071 * Delay and possibly yield CPU. 1072 * XXX - assumes a context 1073 */ 1074 void 1075 stp4020_delay(struct stp4020_softc *sc, unsigned int ms) 1076 { 1077 unsigned int ticks = mstohz(ms); 1078 1079 if (cold || ticks == 0) { 1080 delay(ms); 1081 return; 1082 } 1083 1084 #ifdef DIAGNOSTIC 1085 if (ticks > 60*hz) 1086 panic("stp4020: preposterous delay: %u", ticks); 1087 #endif 1088 tsleep(sc, 0, "nelldel", ticks); 1089 } 1090 1091 #ifdef STP4020_DEBUG 1092 void 1093 stp4020_dump_regs(struct stp4020_socket *h) 1094 { 1095 char bits[64]; 1096 /* 1097 * Dump control and status registers. 1098 */ 1099 printf("socket[%d] registers:\n", h->sock); 1100 snprintb(bits, sizeof(bits), STP4020_ICR0_BITS, 1101 stp4020_rd_sockctl(h, STP4020_ICR0_IDX)); 1102 printf("\tICR0=%s\n", bits); 1103 1104 snprintb(bits, sizeof(bits), STP4020_ICR1_BITS, 1105 stp4020_rd_sockctl(h, STP4020_ICR1_IDX)); 1106 printf("\tICR1=%s\n", bits); 1107 1108 snprintb(bits, sizeof(bits), STP4020_ISR0_IOBITS, 1109 stp4020_rd_sockctl(h, STP4020_ISR0_IDX)); 1110 printf("\tISR0=%s\n", bits); 1111 1112 snprintb(bits, sizeof(bits), STP4020_ISR1_BITS, 1113 stp4020_rd_sockctl(h, STP4020_ISR1_IDX)); 1114 printf("\tISR1=%s\n", bits); 1115 } 1116 #endif /* STP4020_DEBUG */ 1117
Indexes created Fri Oct 03 02:09:57 GMT 2025