tcx.c revision 1.25
1 /* $NetBSD: tcx.c,v 1.25 2008/06/11 21:25:31 drochner Exp $ */ 2 3 /* 4 * Copyright (c) 1996,1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * color display (TCX) driver. 34 * 35 * Does not handle interrupts, even though they can occur. 36 * 37 * XXX should defer colormap updates to vertical retrace interrupts 38 */ 39 40 #include <sys/cdefs.h> 41 __KERNEL_RCSID(0, "$NetBSD: tcx.c,v 1.25 2008/06/11 21:25:31 drochner Exp $"); 42 43 /* 44 * define for cg8 emulation on S24 (24-bit version of tcx) for the SS5; 45 * it is bypassed on the 8-bit version (onboard framebuffer for SS4) 46 */ 47 #undef TCX_CG8 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/buf.h> 52 #include <sys/device.h> 53 #include <sys/ioctl.h> 54 #include <sys/malloc.h> 55 #include <sys/mman.h> 56 #include <sys/tty.h> 57 #include <sys/conf.h> 58 59 #ifdef DEBUG 60 #include <sys/proc.h> 61 #include <sys/syslog.h> 62 #endif 63 64 #include <sys/bus.h> 65 #include <machine/autoconf.h> 66 67 #include <dev/sun/fbio.h> 68 #include <dev/sun/fbvar.h> 69 #include <dev/sun/btreg.h> 70 #include <dev/sun/btvar.h> 71 72 #include <dev/sbus/sbusvar.h> 73 #include <dev/sbus/tcxreg.h> 74 75 /* per-display variables */ 76 struct tcx_softc { 77 struct device sc_dev; /* base device */ 78 struct sbusdev sc_sd; /* sbus device */ 79 struct fbdevice sc_fb; /* frame buffer device */ 80 bus_space_tag_t sc_bustag; 81 struct openprom_addr sc_physadr[TCX_NREG];/* phys addr of h/w */ 82 83 volatile struct bt_regs *sc_bt; /* Brooktree registers */ 84 volatile struct tcx_thc *sc_thc;/* THC registers */ 85 #ifdef TCX_CG8 86 volatile ulong *sc_cplane; /* framebuffer with control planes */ 87 #endif 88 short sc_8bit; /* true if 8-bit hardware */ 89 short sc_blanked; /* true if blanked */ 90 union bt_cmap sc_cmap; /* Brooktree color map */ 91 }; 92 93 /* 94 * The S24 provides the framebuffer RAM mapped in three ways: 95 * 26 bits per pixel, in 32-bit words; the low-order 24 bits are 96 * blue, green, and red values, and the other two bits select the 97 * display modes, per pixel); 98 * 24 bits per pixel, in 32-bit words; the high-order byte reads as 99 * zero, and is ignored on writes (so the mode bits cannot be altered); 100 * 8 bits per pixel, unpadded; writes to this space do not modify the 101 * other 18 bits. 102 */ 103 #define TCX_CTL_8_MAPPED 0x00000000 /* 8 bits, uses color map */ 104 #define TCX_CTL_24_MAPPED 0x01000000 /* 24 bits, uses color map */ 105 #define TCX_CTL_24_LEVEL 0x03000000 /* 24 bits, ignores color map */ 106 #define TCX_CTL_PIXELMASK 0x00FFFFFF /* mask for index/level */ 107 108 /* autoconfiguration driver */ 109 static void tcxattach(struct device *, struct device *, void *); 110 static int tcxmatch(struct device *, struct cfdata *, void *); 111 static void tcx_unblank(struct device *); 112 113 CFATTACH_DECL(tcx, sizeof(struct tcx_softc), 114 tcxmatch, tcxattach, NULL, NULL); 115 116 extern struct cfdriver tcx_cd; 117 118 dev_type_open(tcxopen); 119 dev_type_close(tcxclose); 120 dev_type_ioctl(tcxioctl); 121 dev_type_mmap(tcxmmap); 122 123 const struct cdevsw tcx_cdevsw = { 124 tcxopen, tcxclose, noread, nowrite, tcxioctl, 125 nostop, notty, nopoll, tcxmmap, nokqfilter, 126 }; 127 128 /* frame buffer generic driver */ 129 static struct fbdriver tcx_fbdriver = { 130 tcx_unblank, tcxopen, tcxclose, tcxioctl, nopoll, tcxmmap, 131 nokqfilter 132 }; 133 134 static void tcx_reset(struct tcx_softc *); 135 static void tcx_loadcmap(struct tcx_softc *, int, int); 136 137 #define OBPNAME "SUNW,tcx" 138 139 #ifdef TCX_CG8 140 /* 141 * For CG8 emulation, we map the 32-bit-deep framebuffer at an offset of 142 * 256K; the cg8 space begins with a mono overlay plane and an overlay 143 * enable plane (128K bytes each, 1 bit per pixel), immediately followed 144 * by the color planes, 32 bits per pixel. We also map just the 32-bit 145 * framebuffer at 0x04000000 (TCX_USER_RAM_COMPAT), for compatibility 146 * with the cg8 driver. 147 */ 148 #define TCX_CG8OVERLAY (256 * 1024) 149 #define TCX_SIZE_DFB32 (1152 * 900 * 4) /* max size of the framebuffer */ 150 #endif 151 152 /* 153 * Match a tcx. 154 */ 155 int 156 tcxmatch(parent, cf, aux) 157 struct device *parent; 158 struct cfdata *cf; 159 void *aux; 160 { 161 struct sbus_attach_args *sa = aux; 162 163 return (strcmp(sa->sa_name, OBPNAME) == 0); 164 } 165 166 /* 167 * Attach a display. 168 */ 169 void 170 tcxattach(parent, self, args) 171 struct device *parent, *self; 172 void *args; 173 { 174 struct tcx_softc *sc = device_private(self); 175 struct sbus_attach_args *sa = args; 176 int node, ramsize; 177 volatile struct bt_regs *bt; 178 struct fbdevice *fb = &sc->sc_fb; 179 bus_space_handle_t bh; 180 int isconsole; 181 182 sc->sc_bustag = sa->sa_bustag; 183 node = sa->sa_node; 184 185 fb->fb_driver = &tcx_fbdriver; 186 fb->fb_device = &sc->sc_dev; 187 /* Mask out invalid flags from the user. */ 188 fb->fb_flags = device_cfdata(&sc->sc_dev)->cf_flags & FB_USERMASK; 189 /* 190 * The onboard framebuffer on the SS4 supports only 8-bit mode; 191 * it can be distinguished from the S24 card for the SS5 by the 192 * presence of the "tcx-8-bit" attribute on the SS4 version. 193 */ 194 sc->sc_8bit = node_has_property(node, "tcx-8-bit"); 195 #ifdef TCX_CG8 196 if (sc->sc_8bit) { 197 #endif 198 /* 199 * cg8 emulation is either not compiled in or not supported 200 * on this hardware. Report values for the 8-bit framebuffer 201 * so cg3 emulation works. (If this hardware supports 202 * 24-bit mode, the 24-bit framebuffer will also be available) 203 */ 204 fb->fb_type.fb_depth = 8; 205 fb_setsize_obp(fb, fb->fb_type.fb_depth, 1152, 900, node); 206 207 ramsize = fb->fb_type.fb_height * fb->fb_linebytes; 208 #ifdef TCX_CG8 209 } else { 210 /* 211 * for cg8 emulation, unconditionally report the depth as 212 * 32 bits, but use the height and width reported by the 213 * boot prom. cg8 users want to see the full size of 214 * overlay planes plus color planes included in the 215 * reported framebuffer size. 216 */ 217 fb->fb_type.fb_depth = 32; 218 fb_setsize_obp(fb, fb->fb_type.fb_depth, 1152, 900, node); 219 fb->fb_linebytes = 220 (fb->fb_type.fb_width * fb->fb_type.fb_depth) / 8; 221 ramsize = TCX_CG8OVERLAY + 222 (fb->fb_type.fb_height * fb->fb_linebytes); 223 } 224 #endif 225 fb->fb_type.fb_cmsize = 256; 226 fb->fb_type.fb_size = ramsize; 227 printf(": %s, %d x %d", OBPNAME, 228 fb->fb_type.fb_width, 229 fb->fb_type.fb_height); 230 #ifdef TCX_CG8 231 /* 232 * if cg8 emulation is enabled, say so; but if hardware can't 233 * emulate cg8, explain that instead 234 */ 235 printf( (sc->sc_8bit)? 236 " (8-bit only)" : 237 " (emulating cg8)"); 238 #endif 239 240 /* 241 * XXX - should be set to FBTYPE_TCX. 242 * XXX For CG3 emulation to work in current (96/6) X11 servers, 243 * XXX `fbtype' must point to an "unregocnised" entry. 244 */ 245 #ifdef TCX_CG8 246 if (sc->sc_8bit) { 247 fb->fb_type.fb_type = FBTYPE_RESERVED3; 248 } else { 249 fb->fb_type.fb_type = FBTYPE_MEMCOLOR; 250 } 251 #else 252 fb->fb_type.fb_type = FBTYPE_RESERVED3; 253 #endif 254 255 256 if (sa->sa_nreg != TCX_NREG) { 257 printf("%s: only %d register sets\n", 258 device_xname(self), sa->sa_nreg); 259 return; 260 } 261 bcopy(sa->sa_reg, sc->sc_physadr, 262 sa->sa_nreg * sizeof(struct openprom_addr)); 263 264 /* XXX - fix THC and TEC offsets */ 265 sc->sc_physadr[TCX_REG_TEC].oa_base += 0x1000; 266 sc->sc_physadr[TCX_REG_THC].oa_base += 0x1000; 267 268 /* Map the register banks we care about */ 269 if (sbus_bus_map(sa->sa_bustag, 270 sc->sc_physadr[TCX_REG_THC].oa_space, 271 sc->sc_physadr[TCX_REG_THC].oa_base, 272 sizeof (struct tcx_thc), 273 BUS_SPACE_MAP_LINEAR, &bh) != 0) { 274 printf("tcxattach: cannot map thc registers\n"); 275 return; 276 } 277 sc->sc_thc = (volatile struct tcx_thc *) 278 bus_space_vaddr(sa->sa_bustag, bh); 279 280 if (sbus_bus_map(sa->sa_bustag, 281 sc->sc_physadr[TCX_REG_CMAP].oa_space, 282 sc->sc_physadr[TCX_REG_CMAP].oa_base, 283 sizeof (struct bt_regs), 284 BUS_SPACE_MAP_LINEAR, &bh) != 0) { 285 printf("tcxattach: cannot map bt registers\n"); 286 return; 287 } 288 sc->sc_bt = bt = (volatile struct bt_regs *) 289 bus_space_vaddr(sa->sa_bustag, bh); 290 291 #ifdef TCX_CG8 292 if (!sc->sc_8bit) { 293 if (sbus_bus_map(sa->sa_bustag, 294 sc->sc_physadr[TCX_REG_RDFB32].oa_space, 295 sc->sc_physadr[TCX_REG_RDFB32].oa_base, 296 TCX_SIZE_DFB32, 297 BUS_SPACE_MAP_LINEAR, 298 &bh) != 0) { 299 printf("tcxattach: cannot map control planes\n"); 300 return; 301 } 302 sc->sc_cplane = (volatile ulong *)bh; 303 } 304 #endif 305 306 isconsole = fb_is_console(node); 307 308 printf(", id %d, rev %d, sense %d", 309 (sc->sc_thc->thc_config & THC_CFG_FBID) >> THC_CFG_FBID_SHIFT, 310 (sc->sc_thc->thc_config & THC_CFG_REV) >> THC_CFG_REV_SHIFT, 311 (sc->sc_thc->thc_config & THC_CFG_SENSE) >> THC_CFG_SENSE_SHIFT 312 ); 313 314 /* reset cursor & frame buffer controls */ 315 tcx_reset(sc); 316 317 /* Initialize the default color map. */ 318 bt_initcmap(&sc->sc_cmap, 256); 319 tcx_loadcmap(sc, 0, 256); 320 321 /* enable video */ 322 sc->sc_thc->thc_hcmisc |= THC_MISC_VIDEN; 323 324 if (isconsole) { 325 printf(" (console)\n"); 326 } else 327 printf("\n"); 328 329 sbus_establish(&sc->sc_sd, &sc->sc_dev); 330 fb_attach(&sc->sc_fb, isconsole); 331 } 332 333 #ifdef TCX_CG8 334 /* 335 * keep track of the number of opens, so we can switch to 24-bit mode 336 * when the device is first opened, and return to 8-bit mode on the 337 * last close. (stolen from cgfourteen driver...) There can only be 338 * one TCX per system, so we only need one flag. 339 */ 340 static int tcx_opens = 0; 341 #endif 342 343 int 344 tcxopen(dev, flags, mode, l) 345 dev_t dev; 346 int flags, mode; 347 struct lwp *l; 348 { 349 #ifdef TCX_CG8 350 int unit = minor(dev); 351 struct tcx_softc *sc; 352 int i, s, oldopens; 353 volatile ulong *cptr; 354 struct fbdevice *fb; 355 356 sc = device_lookup_private(&tcx_cd, unit); 357 if (!sc) 358 return (ENXIO); 359 if (!sc->sc_8bit) { 360 s = splhigh(); 361 oldopens = tcx_opens++; 362 splx(s); 363 if (oldopens == 0) { 364 /* 365 * rewrite the control planes to select 24-bit mode 366 * and clear the screen 367 */ 368 fb = &sc->sc_fb; 369 i = fb->fb_type.fb_height * fb->fb_type.fb_width; 370 cptr = sc->sc_cplane; 371 while (--i >= 0) 372 *cptr++ = TCX_CTL_24_LEVEL; 373 } 374 } 375 #endif 376 return (0); 377 } 378 379 int 380 tcxclose(dev, flags, mode, l) 381 dev_t dev; 382 int flags, mode; 383 struct lwp *l; 384 { 385 struct tcx_softc *sc = device_lookup_private(&tcx_cd, minor(dev)); 386 #ifdef TCX_CG8 387 int i, s, opens; 388 volatile ulong *cptr; 389 struct fbdevice *fb; 390 #endif 391 392 tcx_reset(sc); 393 #ifdef TCX_CG8 394 if (!sc->sc_8bit) { 395 s = splhigh(); 396 opens = --tcx_opens; 397 if (tcx_opens <= 0) 398 opens = tcx_opens = 0; 399 splx(s); 400 if (opens == 0) { 401 /* 402 * rewrite the control planes to select 8-bit mode, 403 * preserving the contents of the screen. 404 * (or we could just bzero the whole thing...) 405 */ 406 fb = &sc->sc_fb; 407 i = fb->fb_type.fb_height * fb->fb_type.fb_width; 408 cptr = sc->sc_cplane; 409 while (--i >= 0) 410 *cptr++ &= TCX_CTL_PIXELMASK; 411 } 412 } 413 #endif 414 return (0); 415 } 416 417 int 418 tcxioctl(dev, cmd, data, flags, l) 419 dev_t dev; 420 u_long cmd; 421 void *data; 422 int flags; 423 struct lwp *l; 424 { 425 struct tcx_softc *sc = device_lookup_private(&tcx_cd, minor(dev)); 426 int error; 427 428 switch (cmd) { 429 430 case FBIOGTYPE: 431 *(struct fbtype *)data = sc->sc_fb.fb_type; 432 break; 433 434 case FBIOGATTR: 435 #define fba ((struct fbgattr *)data) 436 fba->real_type = sc->sc_fb.fb_type.fb_type; 437 fba->owner = 0; /* XXX ??? */ 438 fba->fbtype = sc->sc_fb.fb_type; 439 fba->sattr.flags = 0; 440 fba->sattr.emu_type = sc->sc_fb.fb_type.fb_type; 441 fba->sattr.dev_specific[0] = -1; 442 fba->emu_types[0] = sc->sc_fb.fb_type.fb_type; 443 fba->emu_types[1] = FBTYPE_SUN3COLOR; 444 fba->emu_types[2] = -1; 445 #undef fba 446 break; 447 448 case FBIOGETCMAP: 449 #define p ((struct fbcmap *)data) 450 return (bt_getcmap(p, &sc->sc_cmap, 256, 1)); 451 452 case FBIOPUTCMAP: 453 /* copy to software map */ 454 #ifdef TCX_CG8 455 if (!sc->sc_8bit) { 456 /* 457 * cg8 has extra bits in high-order byte of the index 458 * that bt_putcmap doesn't recognize 459 */ 460 p->index &= 0xffffff; 461 } 462 #endif 463 error = bt_putcmap(p, &sc->sc_cmap, 256, 1); 464 if (error) 465 return (error); 466 /* now blast them into the chip */ 467 /* XXX should use retrace interrupt */ 468 tcx_loadcmap(sc, p->index, p->count); 469 #undef p 470 break; 471 472 case FBIOGVIDEO: 473 *(int *)data = sc->sc_blanked; 474 break; 475 476 case FBIOSVIDEO: 477 if (*(int *)data) 478 tcx_unblank(&sc->sc_dev); 479 else if (!sc->sc_blanked) { 480 sc->sc_blanked = 1; 481 sc->sc_thc->thc_hcmisc &= ~THC_MISC_VIDEN; 482 /* Put monitor in `power-saving mode' */ 483 sc->sc_thc->thc_hcmisc |= THC_MISC_VSYNC_DISABLE; 484 sc->sc_thc->thc_hcmisc |= THC_MISC_HSYNC_DISABLE; 485 } 486 break; 487 488 default: 489 #ifdef DEBUG 490 log(LOG_NOTICE, "tcxioctl(0x%lx) (%s[%d])\n", cmd, 491 l->l_proc->p_comm, l->l_proc->p_pid); 492 #endif 493 return (ENOTTY); 494 } 495 return (0); 496 } 497 498 /* 499 * Clean up hardware state (e.g., after bootup or after X crashes). 500 */ 501 static void 502 tcx_reset(sc) 503 struct tcx_softc *sc; 504 { 505 volatile struct bt_regs *bt; 506 507 /* Enable cursor in Brooktree DAC. */ 508 bt = sc->sc_bt; 509 bt->bt_addr = 0x06 << 24; 510 bt->bt_ctrl |= 0x03 << 24; 511 } 512 513 /* 514 * Load a subset of the current (new) colormap into the color DAC. 515 */ 516 static void 517 tcx_loadcmap(sc, start, ncolors) 518 struct tcx_softc *sc; 519 int start, ncolors; 520 { 521 volatile struct bt_regs *bt; 522 u_int *ip, i; 523 int count; 524 525 ip = &sc->sc_cmap.cm_chip[BT_D4M3(start)]; /* start/4 * 3 */ 526 count = BT_D4M3(start + ncolors - 1) - BT_D4M3(start) + 3; 527 bt = sc->sc_bt; 528 bt->bt_addr = BT_D4M4(start) << 24; 529 while (--count >= 0) { 530 i = *ip++; 531 /* hardware that makes one want to pound boards with hammers */ 532 bt->bt_cmap = i; 533 bt->bt_cmap = i << 8; 534 bt->bt_cmap = i << 16; 535 bt->bt_cmap = i << 24; 536 } 537 } 538 539 static void 540 tcx_unblank(dev) 541 struct device *dev; 542 { 543 struct tcx_softc *sc = device_private(dev); 544 545 if (sc->sc_blanked) { 546 sc->sc_blanked = 0; 547 sc->sc_thc->thc_hcmisc &= ~THC_MISC_VSYNC_DISABLE; 548 sc->sc_thc->thc_hcmisc &= ~THC_MISC_HSYNC_DISABLE; 549 sc->sc_thc->thc_hcmisc |= THC_MISC_VIDEN; 550 } 551 } 552 553 /* 554 * Base addresses at which users can mmap() the various pieces of a tcx. 555 */ 556 #define TCX_USER_RAM 0x00000000 557 #define TCX_USER_RAM24 0x01000000 558 #define TCX_USER_RAM_COMPAT 0x04000000 /* cg3 emulation */ 559 #define TCX_USER_STIP 0x10000000 560 #define TCX_USER_BLIT 0x20000000 561 #define TCX_USER_RDFB32 0x28000000 562 #define TCX_USER_RSTIP 0x30000000 563 #define TCX_USER_RBLIT 0x38000000 564 #define TCX_USER_TEC 0x70001000 565 #define TCX_USER_BTREGS 0x70002000 566 #define TCX_USER_THC 0x70004000 567 #define TCX_USER_DHC 0x70008000 568 #define TCX_USER_ALT 0x7000a000 569 #define TCX_USER_UART 0x7000c000 570 #define TCX_USER_VRT 0x7000e000 571 #define TCX_USER_ROM 0x70010000 572 573 struct mmo { 574 u_int mo_uaddr; /* user (virtual) address */ 575 u_int mo_size; /* size, or 0 for video ram size */ 576 u_int mo_bank; /* register bank number */ 577 }; 578 579 /* 580 * Return the address that would map the given device at the given 581 * offset, allowing for the given protection, or return -1 for error. 582 * 583 * XXX needs testing against `demanding' applications (e.g., aviator) 584 */ 585 paddr_t 586 tcxmmap(dev, off, prot) 587 dev_t dev; 588 off_t off; 589 int prot; 590 { 591 struct tcx_softc *sc = device_lookup_private(&tcx_cd, minor(dev)); 592 struct openprom_addr *rr = sc->sc_physadr; 593 struct mmo *mo, *mo_end; 594 u_int u, sz; 595 static struct mmo mmo[] = { 596 { TCX_USER_RAM, 0, TCX_REG_DFB8 }, 597 { TCX_USER_RAM24, 0, TCX_REG_DFB24 }, 598 { TCX_USER_RAM_COMPAT, 0, TCX_REG_DFB8 }, 599 600 { TCX_USER_STIP, 1, TCX_REG_STIP }, 601 { TCX_USER_BLIT, 1, TCX_REG_BLIT }, 602 { TCX_USER_RDFB32, 0, TCX_REG_RDFB32 }, 603 { TCX_USER_RSTIP, 1, TCX_REG_RSTIP }, 604 { TCX_USER_RBLIT, 1, TCX_REG_RBLIT }, 605 { TCX_USER_TEC, 1, TCX_REG_TEC }, 606 { TCX_USER_BTREGS, 8192 /* XXX */, TCX_REG_CMAP }, 607 { TCX_USER_THC, sizeof(struct tcx_thc), TCX_REG_THC }, 608 { TCX_USER_DHC, 1, TCX_REG_DHC }, 609 { TCX_USER_ALT, 1, TCX_REG_ALT }, 610 { TCX_USER_ROM, 65536, TCX_REG_ROM }, 611 }; 612 #define NMMO (sizeof mmo / sizeof *mmo) 613 #ifdef TCX_CG8 614 /* 615 * alternate mapping for CG8 emulation: 616 * map part of the 8-bit-deep framebuffer into the cg8 overlay 617 * space, just so there's something there, and map the 32-bit-deep 618 * framebuffer where cg8 users expect to find it. 619 */ 620 static struct mmo mmo_cg8[] = { 621 { TCX_USER_RAM, TCX_CG8OVERLAY, TCX_REG_DFB8 }, 622 { TCX_CG8OVERLAY, TCX_SIZE_DFB32, TCX_REG_DFB24 }, 623 { TCX_USER_RAM_COMPAT, TCX_SIZE_DFB32, TCX_REG_DFB24 } 624 }; 625 #define NMMO_CG8 (sizeof mmo_cg8 / sizeof *mmo_cg8) 626 #endif 627 628 if (off & PGOFSET) 629 panic("tcxmmap"); 630 631 /* 632 * Entries with size 0 map video RAM (i.e., the size in fb data). 633 * Entries that map 32-bit deep regions are adjusted for their 634 * depth (fb_size gives the size of the 8-bit-deep region). 635 * 636 * Since we work in pages, the fact that the map offset table's 637 * sizes are sometimes bizarre (e.g., 1) is effectively ignored: 638 * one byte is as good as one page. 639 */ 640 #ifdef TCX_CG8 641 if (sc->sc_8bit) { 642 mo = mmo; 643 mo_end = &mmo[NMMO]; 644 } else { 645 mo = mmo_cg8; 646 mo_end = &mmo_cg8[NMMO_CG8]; 647 } 648 #else 649 mo = mmo; 650 mo_end = &mmo[NMMO]; 651 #endif 652 for (; mo < mo_end; mo++) { 653 if ((u_int)off < mo->mo_uaddr) 654 continue; 655 u = off - mo->mo_uaddr; 656 sz = mo->mo_size; 657 if (sz == 0) { 658 sz = sc->sc_fb.fb_type.fb_size; 659 /* 660 * check for the 32-bit-deep regions and adjust 661 * accordingly 662 */ 663 if (mo->mo_uaddr == TCX_USER_RAM24 || 664 mo->mo_uaddr == TCX_USER_RDFB32) { 665 if (sc->sc_8bit) { 666 /* 667 * not present on 8-bit hardware 668 */ 669 continue; 670 } 671 sz *= 4; 672 } 673 } 674 if (u < sz) { 675 return (bus_space_mmap(sc->sc_bustag, 676 BUS_ADDR(rr[mo->mo_bank].oa_space, 677 rr[mo->mo_bank].oa_base), 678 u, 679 prot, 680 BUS_SPACE_MAP_LINEAR)); 681 } 682 } 683 return (-1); 684 } 685
Indexes created Wed Sep 24 22:09:59 GMT 2025