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zxreg.h revision 1.4.2.1
      1  1.4.2.1  wrstuden /*	$NetBSD: zxreg.h,v 1.4.2.1 2008/09/24 16:38:55 wrstuden Exp $	*/
      2      1.1        ad 
      3      1.1        ad /*
      4      1.1        ad  *  Copyright (c) 2002 The NetBSD Foundation, Inc.
      5      1.1        ad  *  All rights reserved.
      6      1.1        ad  *
      7      1.1        ad  *  This code is derived from software contributed to The NetBSD Foundation
      8      1.1        ad  *  by Andrew Doran.
      9      1.1        ad  *
     10      1.1        ad  *  Redistribution and use in source and binary forms, with or without
     11      1.1        ad  *  modification, are permitted provided that the following conditions
     12      1.1        ad  *  are met:
     13      1.1        ad  *  1. Redistributions of source code must retain the above copyright
     14      1.1        ad  *     notice, this list of conditions and the following disclaimer.
     15      1.1        ad  *  2. Redistributions in binary form must reproduce the above copyright
     16      1.1        ad  *     notice, this list of conditions and the following disclaimer in the
     17      1.1        ad  *     documentation and/or other materials provided with the distribution.
     18      1.1        ad  *
     19      1.1        ad  *  THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20      1.1        ad  *  ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21      1.1        ad  *  TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22      1.1        ad  *  PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23      1.1        ad  *  BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24      1.1        ad  *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25      1.1        ad  *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26      1.1        ad  *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27      1.1        ad  *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28      1.1        ad  *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29      1.1        ad  *  POSSIBILITY OF SUCH DAMAGE.
     30      1.1        ad  */
     31      1.1        ad 
     32      1.1        ad /*
     33      1.1        ad  * Copyright (C) 1999, 2000 Jakub Jelinek (jakub (at) redhat.com)
     34      1.1        ad  *
     35      1.1        ad  * Permission is hereby granted, free of charge, to any person obtaining a copy
     36      1.1        ad  * of this software and associated documentation files (the "Software"), to deal
     37      1.1        ad  * in the Software without restriction, including without limitation the rights
     38      1.1        ad  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
     39      1.1        ad  * copies of the Software, and to permit persons to whom the Software is
     40      1.1        ad  * furnished to do so, subject to the following conditions:
     41      1.1        ad  *
     42      1.1        ad  * The above copyright notice and this permission notice shall be included in
     43      1.1        ad  * all copies or substantial portions of the Software.
     44      1.1        ad  *
     45      1.1        ad  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     46      1.1        ad  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     47      1.1        ad  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     48      1.1        ad  * JAKUB JELINEK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
     49      1.1        ad  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
     50      1.1        ad  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
     51      1.1        ad  *
     52      1.1        ad  */
     53      1.2     perry 
     54      1.1        ad #ifndef _DEV_SBUS_ZXREG_H_
     55      1.1        ad #define _DEV_SBUS_ZXREG_H_
     56      1.1        ad 
     57      1.1        ad /* Hardware offsets. */
     58      1.1        ad #define ZX_OFF_UNK2		0x00000000
     59      1.1        ad #define ZX_OFF_LC_SS0_KRN	0x00200000
     60      1.1        ad #define ZX_OFF_LC_SS0_USR	0x00201000
     61      1.1        ad #define ZX_OFF_LD_SS0		0x00400000
     62      1.1        ad #define ZX_OFF_LD_GBL		0x00401000
     63      1.1        ad #define ZX_OFF_LX_CROSS	0x00600000
     64      1.1        ad #define ZX_OFF_LX_CURSOR	0x00601000
     65      1.1        ad #define ZX_OFF_UNK		0x00602000
     66      1.1        ad #define ZX_OFF_SS0		0x00800000
     67      1.1        ad #define ZX_OFF_LC_SS1_KRN	0x01200000
     68      1.1        ad #define ZX_OFF_LC_SS1_USR	0x01201000
     69      1.1        ad #define ZX_OFF_LD_SS1		0x01400000
     70      1.1        ad #define ZX_OFF_SS1		0x01800000
     71      1.1        ad 
     72      1.1        ad /* ROP register */
     73      1.1        ad #define ZX_ATTR_PICK_DISABLE	0x00000000
     74      1.1        ad #define ZX_ATTR_PICK_2D	0x80000000
     75      1.1        ad #define ZX_ATTR_PICK_3D	0xa0000000
     76      1.1        ad #define ZX_ATTR_PICK_2D_REND	0xc0000000
     77      1.1        ad #define ZX_ATTR_PICK_3D_REND	0xe0000000
     78      1.1        ad 
     79      1.1        ad #define ZX_ATTR_DCE_DISABLE	0x00000000
     80      1.1        ad #define ZX_ATTR_DCE_ENABLE	0x10000000
     81      1.1        ad 
     82      1.1        ad #define ZX_ATTR_APE_DISABLE	0x00000000
     83      1.1        ad #define ZX_ATTR_APE_ENABLE	0x08000000
     84      1.1        ad 
     85      1.1        ad #define ZX_ATTR_COLOR_VAR	0x00000000
     86      1.1        ad #define ZX_ATTR_COLOR_CONST	0x04000000
     87      1.1        ad 
     88      1.1        ad #define ZX_ATTR_AA_DISABLE	0x02000000
     89      1.1        ad #define ZX_ATTR_AA_ENABLE	0x01000000
     90      1.1        ad 
     91      1.1        ad #define ZX_ATTR_ABE_BG		0x00000000	/* dst + alpha * (src - bg) */
     92      1.1        ad #define ZX_ATTR_ABE_FB		0x00800000	/* dst + alpha * (src - dst) */
     93      1.1        ad 
     94      1.1        ad #define ZX_ATTR_ABE_DISABLE	0x00000000
     95      1.1        ad #define ZX_ATTR_ABE_ENABLE	0x00400000
     96      1.1        ad 
     97      1.1        ad #define ZX_ATTR_BLTSRC_A	0x00000000
     98      1.1        ad #define ZX_ATTR_BLTSRC_B	0x00200000
     99      1.1        ad 
    100      1.1        ad #define ZX_ROP_ZERO		(0x0 << 18)
    101      1.1        ad #define ZX_ROP_NEW_AND_OLD	(0x8 << 18)
    102      1.1        ad #define ZX_ROP_NEW_AND_NOLD	(0x4 << 18)
    103      1.1        ad #define ZX_ROP_NEW		(0xc << 18)
    104      1.1        ad #define ZX_ROP_NNEW_AND_OLD	(0x2 << 18)
    105      1.1        ad #define ZX_ROP_OLD		(0xa << 18)
    106      1.1        ad #define ZX_ROP_NEW_XOR_OLD	(0x6 << 18)
    107      1.1        ad #define ZX_ROP_NEW_OR_OLD	(0xe << 18)
    108      1.1        ad #define ZX_ROP_NNEW_AND_NOLD	(0x1 << 18)
    109      1.1        ad #define ZX_ROP_NNEW_XOR_NOLD	(0x9 << 18)
    110      1.1        ad #define ZX_ROP_NOLD		(0x5 << 18)
    111      1.1        ad #define ZX_ROP_NEW_OR_NOLD	(0xd << 18)
    112      1.1        ad #define ZX_ROP_NNEW		(0x3 << 18)
    113      1.1        ad #define ZX_ROP_NNEW_OR_OLD	(0xb << 18)
    114      1.1        ad #define ZX_ROP_NNEW_OR_NOLD	(0x7 << 18)
    115      1.1        ad #define ZX_ROP_ONES		(0xf << 18)
    116      1.1        ad 
    117      1.1        ad #define ZX_ATTR_HSR_DISABLE	0x00000000
    118      1.1        ad #define ZX_ATTR_HSR_ENABLE	0x00020000
    119      1.1        ad 
    120      1.1        ad #define ZX_ATTR_WRITEZ_DISABLE	0x00000000
    121      1.1        ad #define ZX_ATTR_WRITEZ_ENABLE	0x00010000
    122      1.1        ad 
    123      1.1        ad #define ZX_ATTR_Z_VAR		0x00000000
    124      1.1        ad #define ZX_ATTR_Z_CONST	0x00008000
    125      1.1        ad 
    126      1.1        ad #define ZX_ATTR_WCLIP_DISABLE	0x00000000
    127      1.1        ad #define ZX_ATTR_WCLIP_ENABLE	0x00004000
    128      1.1        ad 
    129      1.1        ad #define ZX_ATTR_MONO		0x00000000
    130      1.1        ad #define ZX_ATTR_STEREO_LEFT	0x00001000
    131      1.1        ad #define ZX_ATTR_STEREO_RIGHT	0x00003000
    132      1.1        ad 
    133      1.1        ad #define ZX_ATTR_WE_DISABLE	0x00000000
    134      1.1        ad #define ZX_ATTR_WE_ENABLE	0x00000800
    135      1.1        ad 
    136      1.1        ad #define ZX_ATTR_FCE_DISABLE	0x00000000
    137      1.1        ad #define ZX_ATTR_FCE_ENABLE	0x00000400
    138      1.1        ad 
    139      1.1        ad #define ZX_ATTR_RE_DISABLE	0x00000000
    140      1.1        ad #define ZX_ATTR_RE_ENABLE	0x00000200
    141      1.1        ad 
    142      1.1        ad #define ZX_ATTR_GE_DISABLE	0x00000000
    143      1.1        ad #define ZX_ATTR_GE_ENABLE	0x00000100
    144      1.1        ad 
    145      1.1        ad #define ZX_ATTR_BE_DISABLE	0x00000000
    146      1.1        ad #define ZX_ATTR_BE_ENABLE	0x00000080
    147      1.1        ad 
    148      1.1        ad #define ZX_ATTR_RGBE_DISABLE	0x00000000
    149      1.1        ad #define ZX_ATTR_RGBE_ENABLE	0x00000380
    150      1.1        ad 
    151      1.1        ad #define ZX_ATTR_OE_DISABLE	0x00000000
    152      1.1        ad #define ZX_ATTR_OE_ENABLE	0x00000040
    153      1.1        ad 
    154      1.1        ad #define ZX_ATTR_ZE_DISABLE	0x00000000
    155      1.1        ad #define ZX_ATTR_ZE_ENABLE	0x00000020
    156      1.1        ad 
    157      1.1        ad #define ZX_ATTR_FORCE_WID	0x00000010
    158      1.1        ad 
    159      1.1        ad #define ZX_ATTR_FC_PLANE_MASK	0x0000000e
    160      1.1        ad 
    161      1.1        ad #define ZX_ATTR_BUFFER_A	0x00000000
    162      1.1        ad #define ZX_ATTR_BUFFER_B	0x00000001
    163      1.1        ad 
    164      1.1        ad /* CSR */
    165      1.1        ad #define ZX_CSR_BLT_BUSY	0x20000000
    166      1.1        ad 
    167      1.1        ad struct zx_draw {
    168      1.1        ad 	u_int32_t	zd_pad0[896];
    169      1.1        ad 	u_int32_t	zd_csr;
    170      1.1        ad 	u_int32_t	zd_wid;
    171      1.1        ad 	u_int32_t	zd_wmask;
    172      1.1        ad 	u_int32_t	zd_widclip;
    173      1.1        ad 	u_int32_t	zd_vclipmin;
    174      1.1        ad 	u_int32_t	zd_vclipmax;
    175      1.1        ad 	u_int32_t	zd_pickmin;	/* SS1 only */
    176      1.1        ad 	u_int32_t	zd_pickmax;	/* SS1 only */
    177      1.1        ad 	u_int32_t	zd_fg;
    178      1.1        ad 	u_int32_t	zd_bg;
    179      1.1        ad 	u_int32_t	zd_src;		/* Copy/Scroll (SS0 only) */
    180      1.1        ad 	u_int32_t	zd_dst;		/* Copy/Scroll/Fill (SS0 only) */
    181      1.1        ad 	u_int32_t	zd_extent;	/* Copy/Scroll/Fill size (SS0 only) */
    182      1.1        ad 	u_int32_t	zd_pad1[3];
    183      1.1        ad 	u_int32_t	zd_setsem;	/* SS1 only */
    184      1.1        ad 	u_int32_t	zd_clrsem;	/* SS1 only */
    185      1.1        ad 	u_int32_t	zd_clrpick;	/* SS1 only */
    186      1.1        ad 	u_int32_t	zd_clrdat;	/* SS1 only */
    187      1.1        ad 	u_int32_t	zd_alpha;	/* SS1 only */
    188      1.1        ad 	u_int32_t	zd_pad2[11];
    189      1.1        ad 	u_int32_t	zd_winbg;
    190      1.1        ad 	u_int32_t	zd_planemask;
    191      1.1        ad 	u_int32_t	zd_rop;
    192      1.1        ad 	u_int32_t	zd_z;
    193      1.1        ad 	u_int32_t	zd_dczf;	/* SS1 only */
    194      1.1        ad 	u_int32_t	zd_dczb;	/* SS1 only */
    195      1.1        ad 	u_int32_t	zd_dcs;		/* SS1 only */
    196      1.1        ad 	u_int32_t	zd_dczs;	/* SS1 only */
    197      1.1        ad 	u_int32_t	zd_pickfb;	/* SS1 only */
    198      1.1        ad 	u_int32_t	zd_pickbb;	/* SS1 only */
    199      1.1        ad 	u_int32_t	zd_dcfc;	/* SS1 only */
    200      1.1        ad 	u_int32_t	zd_forcecol;	/* SS1 only */
    201      1.1        ad 	u_int32_t	zd_door[8];	/* SS1 only */
    202      1.1        ad 	u_int32_t	zd_pick[5];	/* SS1 only */
    203  1.4.2.1  wrstuden } __packed;
    204      1.1        ad 
    205      1.1        ad struct zx_draw_ss1 {
    206      1.1        ad 	u_int32_t	zd_pad0[957];
    207      1.1        ad 	u_int32_t	zd_misc;
    208  1.4.2.1  wrstuden } __packed;
    209      1.1        ad #define	ZX_SS1_MISC_ENABLE	0x00000001
    210      1.1        ad #define	ZX_SS1_MISC_STEREO	0x00000002
    211      1.1        ad 
    212      1.1        ad #define ZX_ADDRSPC_OBGR		0x00
    213      1.1        ad #define ZX_ADDRSPC_Z		0x01
    214      1.1        ad #define ZX_ADDRSPC_W		0x02
    215      1.1        ad #define ZX_ADDRSPC_FONT_OBGR	0x04
    216      1.1        ad #define ZX_ADDRSPC_FONT_Z	0x05
    217      1.1        ad #define ZX_ADDRSPC_FONT_W	0x06
    218      1.1        ad #define ZX_ADDRSPC_O		0x08
    219      1.1        ad #define ZX_ADDRSPC_B		0x09
    220      1.1        ad #define ZX_ADDRSPC_G		0x0a
    221      1.1        ad #define ZX_ADDRSPC_R		0x0b
    222      1.1        ad 
    223      1.1        ad struct zx_command {
    224      1.1        ad 	u_int32_t	zc_csr;
    225      1.1        ad 	u_int32_t	zc_addrspace;
    226      1.1        ad 	u_int32_t 	zc_fontmsk;
    227      1.1        ad 	u_int32_t	zc_fontt;
    228      1.1        ad 	u_int32_t	zc_extent;
    229      1.1        ad 	u_int32_t	zc_src;
    230      1.1        ad 	u_int32_t	zc_dst;
    231      1.1        ad 	u_int32_t	zc_copy;
    232      1.1        ad 	u_int32_t	zc_fill;
    233  1.4.2.1  wrstuden } __packed;
    234      1.1        ad 
    235      1.1        ad #define ZX_CROSS_TYPE_CLUT0	0x00001000
    236      1.1        ad #define ZX_CROSS_TYPE_CLUT1	0x00001001
    237      1.1        ad #define ZX_CROSS_TYPE_CLUT2	0x00001002
    238      1.1        ad #define ZX_CROSS_TYPE_WID	0x00001003
    239      1.1        ad #define ZX_CROSS_TYPE_UNK	0x00001006
    240      1.1        ad #define ZX_CROSS_TYPE_VIDEO	0x00002003
    241      1.1        ad #define ZX_CROSS_TYPE_CLUTDATA	0x00004000
    242      1.1        ad 
    243      1.1        ad #define ZX_CROSS_CSR_ENABLE	0x00000008
    244      1.1        ad #define ZX_CROSS_CSR_PROGRESS	0x00000004
    245      1.1        ad #define ZX_CROSS_CSR_UNK	0x00000002
    246      1.1        ad #define ZX_CROSS_CSR_UNK2	0x00000001
    247      1.1        ad 
    248      1.1        ad struct zx_cross {
    249      1.1        ad 	u_int32_t	zx_type;
    250      1.1        ad 	u_int32_t	zx_csr;
    251      1.1        ad 	u_int32_t	zx_value;
    252  1.4.2.1  wrstuden } __packed;
    253      1.1        ad 
    254      1.1        ad struct zx_cursor {
    255      1.1        ad 	u_int32_t	zcu_pad0[4];
    256      1.1        ad 	u_int32_t	zcu_type;
    257      1.1        ad 	u_int32_t	zcu_misc;
    258      1.1        ad 	u_int32_t	zcu_sxy;
    259      1.1        ad 	u_int32_t	zcu_data;
    260  1.4.2.1  wrstuden } __packed;
    261      1.1        ad 
    262      1.1        ad #endif	/* !_DEV_SBUS_ZXREG_H_ */
    263