sdhc.c revision 1.121
1 /* $NetBSD: sdhc.c,v 1.121 2025/02/16 11:15:18 jmcneill Exp $ */ 2 /* $OpenBSD: sdhc.c,v 1.25 2009/01/13 19:44:20 grange Exp $ */ 3 4 /* 5 * Copyright (c) 2006 Uwe Stuehler <uwe (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * SD Host Controller driver based on the SD Host Controller Standard 22 * Simplified Specification Version 1.00 (www.sdcard.com). 23 */ 24 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: sdhc.c,v 1.121 2025/02/16 11:15:18 jmcneill Exp $"); 27 28 #ifdef _KERNEL_OPT 29 #include "opt_sdmmc.h" 30 #endif 31 32 #include <sys/param.h> 33 #include <sys/device.h> 34 #include <sys/kernel.h> 35 #include <sys/malloc.h> 36 #include <sys/systm.h> 37 #include <sys/mutex.h> 38 #include <sys/condvar.h> 39 #include <sys/atomic.h> 40 41 #include <dev/sdmmc/sdhcreg.h> 42 #include <dev/sdmmc/sdhcvar.h> 43 #include <dev/sdmmc/sdmmcchip.h> 44 #include <dev/sdmmc/sdmmcreg.h> 45 #include <dev/sdmmc/sdmmcvar.h> 46 47 #ifdef SDHC_DEBUG 48 int sdhcdebug = 1; 49 #define DPRINTF(n,s) do { if ((n) <= sdhcdebug) printf s; } while (0) 50 void sdhc_dump_regs(struct sdhc_host *); 51 #else 52 #define DPRINTF(n,s) do {} while (0) 53 #endif 54 55 #define SDHC_COMMAND_TIMEOUT hz 56 #define SDHC_BUFFER_TIMEOUT hz 57 #define SDHC_TRANSFER_TIMEOUT hz 58 #define SDHC_DMA_TIMEOUT (hz*3) 59 #define SDHC_TUNING_TIMEOUT hz 60 61 struct sdhc_host { 62 struct sdhc_softc *sc; /* host controller device */ 63 64 bus_space_tag_t iot; /* host register set tag */ 65 bus_space_handle_t ioh; /* host register set handle */ 66 bus_size_t ios; /* host register space size */ 67 bus_dma_tag_t dmat; /* host DMA tag */ 68 69 device_t sdmmc; /* generic SD/MMC device */ 70 71 u_int clkbase; /* base clock frequency in KHz */ 72 int maxblklen; /* maximum block length */ 73 uint32_t ocr; /* OCR value from capabilities */ 74 75 uint8_t regs[14]; /* host controller state */ 76 77 uint16_t intr_status; /* soft interrupt status */ 78 uint16_t intr_error_status; /* soft error status */ 79 kmutex_t intr_lock; 80 kmutex_t bus_clock_lock; 81 kcondvar_t intr_cv; 82 83 callout_t tuning_timer; 84 int tuning_timing; 85 u_int tuning_timer_count; 86 u_int tuning_timer_pending; 87 88 int specver; /* spec. version */ 89 90 uint32_t flags; /* flags for this host */ 91 #define SHF_USE_DMA 0x0001 92 #define SHF_USE_4BIT_MODE 0x0002 93 #define SHF_USE_8BIT_MODE 0x0004 94 #define SHF_MODE_DMAEN 0x0008 /* needs SDHC_DMA_ENABLE in mode */ 95 #define SHF_USE_ADMA2_32 0x0010 96 #define SHF_USE_ADMA2_64 0x0020 97 #define SHF_USE_ADMA2_MASK 0x0030 98 99 bus_dmamap_t adma_map; 100 bus_dma_segment_t adma_segs[1]; 101 void *adma2; 102 103 uint8_t vdd; /* last vdd setting */ 104 }; 105 106 #define HDEVNAME(hp) (device_xname((hp)->sc->sc_dev)) 107 108 static uint8_t 109 hread1(struct sdhc_host *hp, bus_size_t reg) 110 { 111 112 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) 113 return bus_space_read_1(hp->iot, hp->ioh, reg); 114 return bus_space_read_4(hp->iot, hp->ioh, reg & -4) >> (8 * (reg & 3)); 115 } 116 117 static uint16_t 118 hread2(struct sdhc_host *hp, bus_size_t reg) 119 { 120 121 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) 122 return bus_space_read_2(hp->iot, hp->ioh, reg); 123 return bus_space_read_4(hp->iot, hp->ioh, reg & -4) >> (8 * (reg & 2)); 124 } 125 126 #define HREAD1(hp, reg) hread1(hp, reg) 127 #define HREAD2(hp, reg) hread2(hp, reg) 128 #define HREAD4(hp, reg) \ 129 (bus_space_read_4((hp)->iot, (hp)->ioh, (reg))) 130 131 132 static void 133 hwrite1(struct sdhc_host *hp, bus_size_t o, uint8_t val) 134 { 135 136 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 137 bus_space_write_1(hp->iot, hp->ioh, o, val); 138 } else { 139 const size_t shift = 8 * (o & 3); 140 o &= -4; 141 uint32_t tmp = bus_space_read_4(hp->iot, hp->ioh, o); 142 tmp = (val << shift) | (tmp & ~(0xffU << shift)); 143 bus_space_write_4(hp->iot, hp->ioh, o, tmp); 144 } 145 } 146 147 static void 148 hwrite2(struct sdhc_host *hp, bus_size_t o, uint16_t val) 149 { 150 151 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 152 bus_space_write_2(hp->iot, hp->ioh, o, val); 153 } else { 154 const size_t shift = 8 * (o & 2); 155 o &= -4; 156 uint32_t tmp = bus_space_read_4(hp->iot, hp->ioh, o); 157 tmp = (val << shift) | (tmp & ~(0xffffU << shift)); 158 bus_space_write_4(hp->iot, hp->ioh, o, tmp); 159 } 160 } 161 162 static void 163 hwrite4(struct sdhc_host *hp, bus_size_t o, uint32_t val) 164 { 165 166 bus_space_write_4(hp->iot, hp->ioh, o, val); 167 } 168 169 #define HWRITE1(hp, reg, val) hwrite1(hp, reg, val) 170 #define HWRITE2(hp, reg, val) hwrite2(hp, reg, val) 171 #define HWRITE4(hp, reg, val) hwrite4(hp, reg, val) 172 173 #define HCLR1(hp, reg, bits) \ 174 do if ((bits) != 0) HWRITE1((hp), (reg), HREAD1((hp), (reg)) & ~(bits)); while (0) 175 #define HCLR2(hp, reg, bits) \ 176 do if ((bits) != 0) HWRITE2((hp), (reg), HREAD2((hp), (reg)) & ~(bits)); while (0) 177 #define HCLR4(hp, reg, bits) \ 178 do if ((bits) != 0) HWRITE4((hp), (reg), HREAD4((hp), (reg)) & ~(bits)); while (0) 179 #define HSET1(hp, reg, bits) \ 180 do if ((bits) != 0) HWRITE1((hp), (reg), HREAD1((hp), (reg)) | (bits)); while (0) 181 #define HSET2(hp, reg, bits) \ 182 do if ((bits) != 0) HWRITE2((hp), (reg), HREAD2((hp), (reg)) | (bits)); while (0) 183 #define HSET4(hp, reg, bits) \ 184 do if ((bits) != 0) HWRITE4((hp), (reg), HREAD4((hp), (reg)) | (bits)); while (0) 185 186 static int sdhc_host_reset(sdmmc_chipset_handle_t); 187 static int sdhc_host_reset1(sdmmc_chipset_handle_t); 188 static uint32_t sdhc_host_ocr(sdmmc_chipset_handle_t); 189 static int sdhc_host_maxblklen(sdmmc_chipset_handle_t); 190 static int sdhc_card_detect(sdmmc_chipset_handle_t); 191 static int sdhc_write_protect(sdmmc_chipset_handle_t); 192 static int sdhc_bus_power(sdmmc_chipset_handle_t, uint32_t); 193 static int sdhc_bus_clock_ddr(sdmmc_chipset_handle_t, int, bool); 194 static int sdhc_bus_width(sdmmc_chipset_handle_t, int); 195 static int sdhc_bus_rod(sdmmc_chipset_handle_t, int); 196 static void sdhc_card_enable_intr(sdmmc_chipset_handle_t, int); 197 static void sdhc_card_intr_ack(sdmmc_chipset_handle_t); 198 static void sdhc_exec_command(sdmmc_chipset_handle_t, 199 struct sdmmc_command *); 200 static int sdhc_signal_voltage(sdmmc_chipset_handle_t, int); 201 static int sdhc_execute_tuning1(struct sdhc_host *, int); 202 static int sdhc_execute_tuning(sdmmc_chipset_handle_t, int); 203 static void sdhc_tuning_timer(void *); 204 static void sdhc_hw_reset(sdmmc_chipset_handle_t); 205 static int sdhc_start_command(struct sdhc_host *, struct sdmmc_command *); 206 static int sdhc_wait_state(struct sdhc_host *, uint32_t, uint32_t); 207 static int sdhc_soft_reset(struct sdhc_host *, int); 208 static int sdhc_wait_intr(struct sdhc_host *, int, int, bool); 209 static void sdhc_transfer_data(struct sdhc_host *, struct sdmmc_command *); 210 static int sdhc_transfer_data_dma(struct sdhc_host *, struct sdmmc_command *); 211 static int sdhc_transfer_data_pio(struct sdhc_host *, struct sdmmc_command *); 212 static void sdhc_read_data_pio(struct sdhc_host *, uint8_t *, u_int); 213 static void sdhc_write_data_pio(struct sdhc_host *, uint8_t *, u_int); 214 static void esdhc_read_data_pio(struct sdhc_host *, uint8_t *, u_int); 215 static void esdhc_write_data_pio(struct sdhc_host *, uint8_t *, u_int); 216 217 static struct sdmmc_chip_functions sdhc_functions = { 218 /* host controller reset */ 219 .host_reset = sdhc_host_reset, 220 221 /* host controller capabilities */ 222 .host_ocr = sdhc_host_ocr, 223 .host_maxblklen = sdhc_host_maxblklen, 224 225 /* card detection */ 226 .card_detect = sdhc_card_detect, 227 228 /* write protect */ 229 .write_protect = sdhc_write_protect, 230 231 /* bus power, clock frequency, width and ROD(OpenDrain/PushPull) */ 232 .bus_power = sdhc_bus_power, 233 .bus_clock = NULL, /* see sdhc_bus_clock_ddr */ 234 .bus_width = sdhc_bus_width, 235 .bus_rod = sdhc_bus_rod, 236 237 /* command execution */ 238 .exec_command = sdhc_exec_command, 239 240 /* card interrupt */ 241 .card_enable_intr = sdhc_card_enable_intr, 242 .card_intr_ack = sdhc_card_intr_ack, 243 244 /* UHS functions */ 245 .signal_voltage = sdhc_signal_voltage, 246 .bus_clock_ddr = sdhc_bus_clock_ddr, 247 .execute_tuning = sdhc_execute_tuning, 248 .hw_reset = sdhc_hw_reset, 249 }; 250 251 static int 252 sdhc_cfprint(void *aux, const char *pnp) 253 { 254 const struct sdmmcbus_attach_args * const saa = aux; 255 const struct sdhc_host * const hp = saa->saa_sch; 256 257 if (pnp) { 258 aprint_normal("sdmmc at %s", pnp); 259 } 260 for (size_t host = 0; host < hp->sc->sc_nhosts; host++) { 261 if (hp->sc->sc_host[host] == hp) { 262 aprint_normal(" slot %zu", host); 263 } 264 } 265 266 return UNCONF; 267 } 268 269 /* 270 * Called by attachment driver. For each SD card slot there is one SD 271 * host controller standard register set. (1.3) 272 */ 273 int 274 sdhc_host_found(struct sdhc_softc *sc, bus_space_tag_t iot, 275 bus_space_handle_t ioh, bus_size_t iosize) 276 { 277 struct sdmmcbus_attach_args saa; 278 struct sdhc_host *hp; 279 uint32_t caps, caps2; 280 uint16_t sdhcver; 281 int error; 282 283 /* Allocate one more host structure. */ 284 hp = malloc(sizeof(struct sdhc_host), M_DEVBUF, M_WAITOK|M_ZERO); 285 if (hp == NULL) { 286 aprint_error_dev(sc->sc_dev, 287 "couldn't alloc memory (sdhc host)\n"); 288 goto err1; 289 } 290 sc->sc_host[sc->sc_nhosts++] = hp; 291 292 /* Fill in the new host structure. */ 293 hp->sc = sc; 294 hp->iot = iot; 295 hp->ioh = ioh; 296 hp->ios = iosize; 297 hp->dmat = sc->sc_dmat; 298 299 mutex_init(&hp->intr_lock, MUTEX_DEFAULT, IPL_SDMMC); 300 mutex_init(&hp->bus_clock_lock, MUTEX_DEFAULT, IPL_NONE); 301 cv_init(&hp->intr_cv, "sdhcintr"); 302 callout_init(&hp->tuning_timer, CALLOUT_MPSAFE); 303 callout_setfunc(&hp->tuning_timer, sdhc_tuning_timer, hp); 304 305 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_USDHC)) { 306 sdhcver = SDHC_SPEC_VERS_300 << SDHC_SPEC_VERS_SHIFT; 307 } else if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 308 sdhcver = HREAD4(hp, SDHC_ESDHC_HOST_CTL_VERSION); 309 } else if (iosize <= SDHC_HOST_CTL_VERSION) { 310 sdhcver = SDHC_SPEC_NOVERS << SDHC_SPEC_VERS_SHIFT; 311 } else { 312 sdhcver = HREAD2(hp, SDHC_HOST_CTL_VERSION); 313 } 314 aprint_normal_dev(sc->sc_dev, "SDHC "); 315 hp->specver = SDHC_SPEC_VERSION(sdhcver); 316 switch (SDHC_SPEC_VERSION(sdhcver)) { 317 case SDHC_SPEC_VERS_100: 318 aprint_normal("1.0"); 319 break; 320 case SDHC_SPEC_VERS_200: 321 aprint_normal("2.0"); 322 break; 323 case SDHC_SPEC_VERS_300: 324 aprint_normal("3.0"); 325 break; 326 case SDHC_SPEC_VERS_400: 327 aprint_normal("4.0"); 328 break; 329 case SDHC_SPEC_VERS_410: 330 aprint_normal("4.1"); 331 break; 332 case SDHC_SPEC_VERS_420: 333 aprint_normal("4.2"); 334 break; 335 case SDHC_SPEC_NOVERS: 336 hp->specver = -1; 337 aprint_normal("NO-VERS"); 338 break; 339 default: 340 aprint_normal("unknown version(0x%x)", 341 SDHC_SPEC_VERSION(sdhcver)); 342 break; 343 } 344 if (SDHC_SPEC_VERSION(sdhcver) != SDHC_SPEC_NOVERS) 345 aprint_normal(", rev %u", SDHC_VENDOR_VERSION(sdhcver)); 346 347 /* 348 * Reset the host controller and enable interrupts. 349 */ 350 (void)sdhc_host_reset(hp); 351 352 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_USDHC)) { 353 /* init uSDHC registers */ 354 HWRITE4(hp, SDHC_MMC_BOOT, 0); 355 HWRITE4(hp, SDHC_HOST_CTL, SDHC_USDHC_BURST_LEN_EN | 356 SDHC_USDHC_HOST_CTL_RESV23 | SDHC_USDHC_EMODE_LE); 357 HWRITE4(hp, SDHC_WATERMARK_LEVEL, 358 (0x10 << SDHC_WATERMARK_WR_BRST_SHIFT) | 359 (0x40 << SDHC_WATERMARK_WRITE_SHIFT) | 360 (0x10 << SDHC_WATERMARK_RD_BRST_SHIFT) | 361 (0x40 << SDHC_WATERMARK_READ_SHIFT)); 362 HSET4(hp, SDHC_VEND_SPEC, 363 SDHC_VEND_SPEC_MBO | 364 SDHC_VEND_SPEC_CARD_CLK_SOFT_EN | 365 SDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN | 366 SDHC_VEND_SPEC_HCLK_SOFT_EN | 367 SDHC_VEND_SPEC_IPG_CLK_SOFT_EN | 368 SDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN | 369 SDHC_VEND_SPEC_FRC_SDCLK_ON); 370 } 371 372 /* Determine host capabilities. */ 373 if (ISSET(sc->sc_flags, SDHC_FLAG_HOSTCAPS)) { 374 caps = sc->sc_caps; 375 caps2 = sc->sc_caps2; 376 } else if (ISSET(hp->sc->sc_flags, SDHC_FLAG_USDHC)) { 377 /* uSDHC capability register is little bit different */ 378 caps = HREAD4(hp, SDHC_CAPABILITIES); 379 caps |= SDHC_8BIT_SUPP; 380 if (caps & SDHC_ADMA1_SUPP) 381 caps |= SDHC_ADMA2_SUPP; 382 sc->sc_caps = caps; 383 /* uSDHC has no SDHC_CAPABILITIES2 register */ 384 caps2 = sc->sc_caps2 = SDHC_SDR50_SUPP | SDHC_DDR50_SUPP; 385 } else { 386 caps = sc->sc_caps = HREAD4(hp, SDHC_CAPABILITIES); 387 if (hp->specver >= SDHC_SPEC_VERS_300) { 388 caps2 = sc->sc_caps2 = HREAD4(hp, SDHC_CAPABILITIES2); 389 } else { 390 caps2 = sc->sc_caps2 = 0; 391 } 392 } 393 394 aprint_verbose(", caps <%08x/%08x>", caps, caps2); 395 396 const u_int retuning_mode = (caps2 >> SDHC_RETUNING_MODES_SHIFT) & 397 SDHC_RETUNING_MODES_MASK; 398 if (retuning_mode == SDHC_RETUNING_MODE_1) { 399 hp->tuning_timer_count = (caps2 >> SDHC_TIMER_COUNT_SHIFT) & 400 SDHC_TIMER_COUNT_MASK; 401 if (hp->tuning_timer_count == 0xf) 402 hp->tuning_timer_count = 0; 403 if (hp->tuning_timer_count) 404 hp->tuning_timer_count = 405 1 << (hp->tuning_timer_count - 1); 406 } 407 408 /* 409 * Use DMA if the host system and the controller support it. 410 * Supports integrated or external DMA egine, with or without 411 * SDHC_DMA_ENABLE in the command. 412 */ 413 if (ISSET(sc->sc_flags, SDHC_FLAG_FORCE_DMA) || 414 (ISSET(sc->sc_flags, SDHC_FLAG_USE_DMA && 415 ISSET(caps, SDHC_DMA_SUPPORT)))) { 416 SET(hp->flags, SHF_USE_DMA); 417 418 if (ISSET(caps, SDHC_ADMA2_SUPP) && 419 !ISSET(sc->sc_flags, SDHC_FLAG_BROKEN_ADMA)) { 420 SET(hp->flags, SHF_MODE_DMAEN); 421 /* 422 * 64-bit mode was present in the 2.00 spec, removed 423 * from 3.00, and re-added in 4.00 with a different 424 * descriptor layout. We only support 2.00 and 3.00 425 * descriptors for now. 426 */ 427 if (hp->specver == SDHC_SPEC_VERS_200 && 428 ISSET(caps, SDHC_64BIT_SYS_BUS)) { 429 SET(hp->flags, SHF_USE_ADMA2_64); 430 aprint_normal(", 64-bit ADMA2"); 431 } else { 432 SET(hp->flags, SHF_USE_ADMA2_32); 433 aprint_normal(", 32-bit ADMA2"); 434 } 435 } else { 436 if (!ISSET(sc->sc_flags, SDHC_FLAG_EXTERNAL_DMA) || 437 ISSET(sc->sc_flags, SDHC_FLAG_EXTDMA_DMAEN)) 438 SET(hp->flags, SHF_MODE_DMAEN); 439 if (sc->sc_vendor_transfer_data_dma) { 440 aprint_normal(", platform DMA"); 441 } else { 442 aprint_normal(", SDMA"); 443 } 444 } 445 } else { 446 aprint_normal(", PIO"); 447 } 448 449 /* 450 * Determine the base clock frequency. (2.2.24) 451 */ 452 if (hp->specver >= SDHC_SPEC_VERS_300) { 453 hp->clkbase = SDHC_BASE_V3_FREQ_KHZ(caps); 454 } else { 455 hp->clkbase = SDHC_BASE_FREQ_KHZ(caps); 456 } 457 if (hp->clkbase == 0 || 458 ISSET(sc->sc_flags, SDHC_FLAG_NO_CLKBASE)) { 459 if (sc->sc_clkbase == 0) { 460 /* The attachment driver must tell us. */ 461 aprint_error_dev(sc->sc_dev, 462 "unknown base clock frequency\n"); 463 goto err; 464 } 465 hp->clkbase = sc->sc_clkbase; 466 } 467 if (hp->clkbase < 10000 || hp->clkbase > 10000 * 256) { 468 /* SDHC 1.0 supports only 10-63 MHz. */ 469 aprint_error_dev(sc->sc_dev, 470 "base clock frequency out of range: %u MHz\n", 471 hp->clkbase / 1000); 472 goto err; 473 } 474 aprint_normal(", %u kHz", hp->clkbase); 475 476 /* 477 * XXX Set the data timeout counter value according to 478 * capabilities. (2.2.15) 479 */ 480 HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX); 481 #if 1 482 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 483 HWRITE4(hp, SDHC_NINTR_STATUS, SDHC_CMD_TIMEOUT_ERROR << 16); 484 #endif 485 486 if (ISSET(caps, SDHC_EMBEDDED_SLOT)) 487 aprint_normal(", embedded slot"); 488 489 /* 490 * Determine SD bus voltage levels supported by the controller. 491 */ 492 aprint_normal(","); 493 if (ISSET(caps, SDHC_HIGH_SPEED_SUPP)) { 494 SET(hp->ocr, MMC_OCR_HCS); 495 aprint_normal(" HS"); 496 } 497 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_1_8_V)) { 498 if (ISSET(caps2, SDHC_SDR50_SUPP)) { 499 SET(hp->ocr, MMC_OCR_S18A); 500 aprint_normal(" SDR50"); 501 } 502 if (ISSET(caps2, SDHC_DDR50_SUPP)) { 503 SET(hp->ocr, MMC_OCR_S18A); 504 aprint_normal(" DDR50"); 505 } 506 if (ISSET(caps2, SDHC_SDR104_SUPP)) { 507 SET(hp->ocr, MMC_OCR_S18A); 508 aprint_normal(" SDR104 HS200"); 509 } 510 if (ISSET(caps, SDHC_VOLTAGE_SUPP_1_8V)) { 511 SET(hp->ocr, MMC_OCR_1_65V_1_95V); 512 aprint_normal(" 1.8V"); 513 } 514 } 515 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_0V)) { 516 SET(hp->ocr, MMC_OCR_2_9V_3_0V | MMC_OCR_3_0V_3_1V); 517 aprint_normal(" 3.0V"); 518 } 519 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_3V)) { 520 SET(hp->ocr, MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V); 521 aprint_normal(" 3.3V"); 522 } 523 if (hp->specver >= SDHC_SPEC_VERS_300) { 524 aprint_normal(", re-tuning mode %d", retuning_mode + 1); 525 if (hp->tuning_timer_count) 526 aprint_normal(" (%us timer)", hp->tuning_timer_count); 527 } 528 529 /* 530 * Determine the maximum block length supported by the host 531 * controller. (2.2.24) 532 */ 533 switch((caps >> SDHC_MAX_BLK_LEN_SHIFT) & SDHC_MAX_BLK_LEN_MASK) { 534 case SDHC_MAX_BLK_LEN_512: 535 hp->maxblklen = 512; 536 break; 537 538 case SDHC_MAX_BLK_LEN_1024: 539 hp->maxblklen = 1024; 540 break; 541 542 case SDHC_MAX_BLK_LEN_2048: 543 hp->maxblklen = 2048; 544 break; 545 546 case SDHC_MAX_BLK_LEN_4096: 547 hp->maxblklen = 4096; 548 break; 549 550 default: 551 aprint_error_dev(sc->sc_dev, "max block length unknown\n"); 552 goto err; 553 } 554 aprint_normal(", %u byte blocks", hp->maxblklen); 555 aprint_normal("\n"); 556 557 if (ISSET(hp->flags, SHF_USE_ADMA2_MASK)) { 558 int rseg; 559 560 /* Allocate ADMA2 descriptor memory */ 561 error = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, PAGE_SIZE, 562 PAGE_SIZE, hp->adma_segs, 1, &rseg, BUS_DMA_WAITOK); 563 if (error) { 564 aprint_error_dev(sc->sc_dev, 565 "ADMA2 dmamem_alloc failed (%d)\n", error); 566 goto adma_done; 567 } 568 error = bus_dmamem_map(sc->sc_dmat, hp->adma_segs, rseg, 569 PAGE_SIZE, (void **)&hp->adma2, BUS_DMA_WAITOK); 570 if (error) { 571 aprint_error_dev(sc->sc_dev, 572 "ADMA2 dmamem_map failed (%d)\n", error); 573 goto adma_done; 574 } 575 error = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, 1, PAGE_SIZE, 576 0, BUS_DMA_WAITOK, &hp->adma_map); 577 if (error) { 578 aprint_error_dev(sc->sc_dev, 579 "ADMA2 dmamap_create failed (%d)\n", error); 580 goto adma_done; 581 } 582 error = bus_dmamap_load(sc->sc_dmat, hp->adma_map, 583 hp->adma2, PAGE_SIZE, NULL, 584 BUS_DMA_WAITOK|BUS_DMA_WRITE); 585 if (error) { 586 aprint_error_dev(sc->sc_dev, 587 "ADMA2 dmamap_load failed (%d)\n", error); 588 goto adma_done; 589 } 590 591 memset(hp->adma2, 0, PAGE_SIZE); 592 593 adma_done: 594 if (error) 595 CLR(hp->flags, SHF_USE_ADMA2_MASK); 596 } 597 598 /* 599 * Attach the generic SD/MMC bus driver. (The bus driver must 600 * not invoke any chipset functions before it is attached.) 601 */ 602 memset(&saa, 0, sizeof(saa)); 603 saa.saa_busname = "sdmmc"; 604 saa.saa_sct = &sdhc_functions; 605 saa.saa_sch = hp; 606 saa.saa_dmat = hp->dmat; 607 saa.saa_clkmax = hp->clkbase; 608 if (ISSET(sc->sc_flags, SDHC_FLAG_HAVE_CGM)) 609 saa.saa_clkmin = hp->clkbase / 256 / 2046; 610 else if (ISSET(sc->sc_flags, SDHC_FLAG_HAVE_DVS)) 611 saa.saa_clkmin = hp->clkbase / 256 / 16; 612 else if (hp->sc->sc_clkmsk != 0) 613 saa.saa_clkmin = hp->clkbase / (hp->sc->sc_clkmsk >> 614 (ffs(hp->sc->sc_clkmsk) - 1)); 615 else if (hp->specver >= SDHC_SPEC_VERS_300) 616 saa.saa_clkmin = hp->clkbase / 0x3ff; 617 else 618 saa.saa_clkmin = hp->clkbase / 256; 619 if (!ISSET(sc->sc_flags, SDHC_FLAG_NO_AUTO_STOP)) 620 saa.saa_caps |= SMC_CAPS_AUTO_STOP; 621 saa.saa_caps |= SMC_CAPS_4BIT_MODE; 622 if (ISSET(sc->sc_flags, SDHC_FLAG_8BIT_MODE)) 623 saa.saa_caps |= SMC_CAPS_8BIT_MODE; 624 if (ISSET(caps, SDHC_HIGH_SPEED_SUPP)) 625 saa.saa_caps |= SMC_CAPS_SD_HIGHSPEED | 626 SMC_CAPS_MMC_HIGHSPEED; 627 if (ISSET(caps2, SDHC_SDR104_SUPP)) 628 saa.saa_caps |= SMC_CAPS_UHS_SDR104 | 629 SMC_CAPS_UHS_SDR50 | 630 SMC_CAPS_MMC_HS200; 631 if (ISSET(caps2, SDHC_SDR50_SUPP)) 632 saa.saa_caps |= SMC_CAPS_UHS_SDR50; 633 if (ISSET(caps2, SDHC_DDR50_SUPP)) 634 saa.saa_caps |= SMC_CAPS_UHS_DDR50; 635 if (ISSET(hp->flags, SHF_USE_DMA)) { 636 saa.saa_caps |= SMC_CAPS_DMA; 637 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 638 saa.saa_caps |= SMC_CAPS_MULTI_SEG_DMA; 639 } 640 if (ISSET(sc->sc_flags, SDHC_FLAG_SINGLE_ONLY)) 641 saa.saa_caps |= SMC_CAPS_SINGLE_ONLY; 642 if (ISSET(sc->sc_flags, SDHC_FLAG_POLL_CARD_DET)) 643 saa.saa_caps |= SMC_CAPS_POLL_CARD_DET; 644 645 if (ISSET(sc->sc_flags, SDHC_FLAG_BROKEN_ADMA2_ZEROLEN)) 646 saa.saa_max_seg = 65535; 647 648 hp->sdmmc = config_found(sc->sc_dev, &saa, sdhc_cfprint, CFARGS_NONE); 649 650 return 0; 651 652 err: 653 callout_destroy(&hp->tuning_timer); 654 cv_destroy(&hp->intr_cv); 655 mutex_destroy(&hp->bus_clock_lock); 656 mutex_destroy(&hp->intr_lock); 657 free(hp, M_DEVBUF); 658 sc->sc_host[--sc->sc_nhosts] = NULL; 659 err1: 660 return 1; 661 } 662 663 int 664 sdhc_detach(struct sdhc_softc *sc, int flags) 665 { 666 struct sdhc_host *hp; 667 int rv = 0; 668 669 for (size_t n = 0; n < sc->sc_nhosts; n++) { 670 hp = sc->sc_host[n]; 671 if (hp == NULL) 672 continue; 673 if (hp->sdmmc != NULL) { 674 rv = config_detach(hp->sdmmc, flags); 675 if (rv) 676 break; 677 hp->sdmmc = NULL; 678 } 679 /* disable interrupts */ 680 if ((flags & DETACH_FORCE) == 0) { 681 mutex_enter(&hp->intr_lock); 682 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 683 HWRITE4(hp, SDHC_NINTR_SIGNAL_EN, 0); 684 } else { 685 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, 0); 686 } 687 sdhc_soft_reset(hp, SDHC_RESET_ALL); 688 mutex_exit(&hp->intr_lock); 689 } 690 callout_halt(&hp->tuning_timer, NULL); 691 callout_destroy(&hp->tuning_timer); 692 cv_destroy(&hp->intr_cv); 693 mutex_destroy(&hp->intr_lock); 694 if (hp->ios > 0) { 695 bus_space_unmap(hp->iot, hp->ioh, hp->ios); 696 hp->ios = 0; 697 } 698 if (ISSET(hp->flags, SHF_USE_ADMA2_MASK)) { 699 bus_dmamap_unload(sc->sc_dmat, hp->adma_map); 700 bus_dmamap_destroy(sc->sc_dmat, hp->adma_map); 701 bus_dmamem_unmap(sc->sc_dmat, hp->adma2, PAGE_SIZE); 702 bus_dmamem_free(sc->sc_dmat, hp->adma_segs, 1); 703 } 704 free(hp, M_DEVBUF); 705 sc->sc_host[n] = NULL; 706 } 707 708 return rv; 709 } 710 711 bool 712 sdhc_suspend(device_t dev, const pmf_qual_t *qual) 713 { 714 struct sdhc_softc *sc = device_private(dev); 715 struct sdhc_host *hp; 716 size_t i; 717 718 /* XXX poll for command completion or suspend command 719 * in progress */ 720 721 /* Save the host controller state. */ 722 for (size_t n = 0; n < sc->sc_nhosts; n++) { 723 hp = sc->sc_host[n]; 724 if (ISSET(sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 725 for (i = 0; i < sizeof hp->regs; i += 4) { 726 uint32_t v = HREAD4(hp, i); 727 hp->regs[i + 0] = (v >> 0); 728 hp->regs[i + 1] = (v >> 8); 729 if (i + 3 < sizeof hp->regs) { 730 hp->regs[i + 2] = (v >> 16); 731 hp->regs[i + 3] = (v >> 24); 732 } 733 } 734 } else { 735 for (i = 0; i < sizeof hp->regs; i++) { 736 hp->regs[i] = HREAD1(hp, i); 737 } 738 } 739 } 740 return true; 741 } 742 743 bool 744 sdhc_resume(device_t dev, const pmf_qual_t *qual) 745 { 746 struct sdhc_softc *sc = device_private(dev); 747 struct sdhc_host *hp; 748 size_t i; 749 750 /* Restore the host controller state. */ 751 for (size_t n = 0; n < sc->sc_nhosts; n++) { 752 hp = sc->sc_host[n]; 753 (void)sdhc_host_reset(hp); 754 if (ISSET(sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 755 for (i = 0; i < sizeof hp->regs; i += 4) { 756 if (i + 3 < sizeof hp->regs) { 757 HWRITE4(hp, i, 758 (hp->regs[i + 0] << 0) 759 | (hp->regs[i + 1] << 8) 760 | (hp->regs[i + 2] << 16) 761 | (hp->regs[i + 3] << 24)); 762 } else { 763 HWRITE4(hp, i, 764 (hp->regs[i + 0] << 0) 765 | (hp->regs[i + 1] << 8)); 766 } 767 } 768 } else { 769 for (i = 0; i < sizeof hp->regs; i++) { 770 HWRITE1(hp, i, hp->regs[i]); 771 } 772 } 773 } 774 return true; 775 } 776 777 bool 778 sdhc_shutdown(device_t dev, int flags) 779 { 780 struct sdhc_softc *sc = device_private(dev); 781 struct sdhc_host *hp; 782 783 /* XXX chip locks up if we don't disable it before reboot. */ 784 for (size_t i = 0; i < sc->sc_nhosts; i++) { 785 hp = sc->sc_host[i]; 786 (void)sdhc_host_reset(hp); 787 } 788 return true; 789 } 790 791 /* 792 * Reset the host controller. Called during initialization, when 793 * cards are removed, upon resume, and during error recovery. 794 */ 795 static int 796 sdhc_host_reset1(sdmmc_chipset_handle_t sch) 797 { 798 struct sdhc_host *hp = (struct sdhc_host *)sch; 799 uint32_t sdhcimask; 800 int error; 801 802 KASSERT(mutex_owned(&hp->intr_lock)); 803 804 /* Disable all interrupts. */ 805 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 806 HWRITE4(hp, SDHC_NINTR_SIGNAL_EN, 0); 807 } else { 808 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, 0); 809 } 810 811 /* Let sdhc_bus_power restore power */ 812 hp->vdd = 0; 813 814 /* 815 * Reset the entire host controller and wait up to 100ms for 816 * the controller to clear the reset bit. 817 */ 818 error = sdhc_soft_reset(hp, SDHC_RESET_ALL); 819 if (error) 820 goto out; 821 822 /* Set data timeout counter value to max for now. */ 823 HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX); 824 #if 1 825 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 826 HWRITE4(hp, SDHC_NINTR_STATUS, SDHC_CMD_TIMEOUT_ERROR << 16); 827 #endif 828 829 /* Enable interrupts. */ 830 sdhcimask = SDHC_CARD_REMOVAL | SDHC_CARD_INSERTION | 831 SDHC_BUFFER_READ_READY | SDHC_BUFFER_WRITE_READY | 832 SDHC_DMA_INTERRUPT | SDHC_BLOCK_GAP_EVENT | 833 SDHC_TRANSFER_COMPLETE | SDHC_COMMAND_COMPLETE; 834 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 835 sdhcimask |= SDHC_EINTR_STATUS_MASK << 16; 836 HWRITE4(hp, SDHC_NINTR_STATUS_EN, sdhcimask); 837 sdhcimask ^= 838 (SDHC_EINTR_STATUS_MASK ^ SDHC_EINTR_SIGNAL_MASK) << 16; 839 sdhcimask ^= SDHC_BUFFER_READ_READY ^ SDHC_BUFFER_WRITE_READY; 840 HWRITE4(hp, SDHC_NINTR_SIGNAL_EN, sdhcimask); 841 } else { 842 HWRITE2(hp, SDHC_NINTR_STATUS_EN, sdhcimask); 843 HWRITE2(hp, SDHC_EINTR_STATUS_EN, SDHC_EINTR_STATUS_MASK); 844 sdhcimask ^= SDHC_BUFFER_READ_READY ^ SDHC_BUFFER_WRITE_READY; 845 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, sdhcimask); 846 HWRITE2(hp, SDHC_EINTR_SIGNAL_EN, SDHC_EINTR_SIGNAL_MASK); 847 } 848 849 out: 850 return error; 851 } 852 853 static int 854 sdhc_host_reset(sdmmc_chipset_handle_t sch) 855 { 856 struct sdhc_host *hp = (struct sdhc_host *)sch; 857 int error; 858 859 mutex_enter(&hp->intr_lock); 860 error = sdhc_host_reset1(sch); 861 mutex_exit(&hp->intr_lock); 862 863 return error; 864 } 865 866 static uint32_t 867 sdhc_host_ocr(sdmmc_chipset_handle_t sch) 868 { 869 struct sdhc_host *hp = (struct sdhc_host *)sch; 870 871 return hp->ocr; 872 } 873 874 static int 875 sdhc_host_maxblklen(sdmmc_chipset_handle_t sch) 876 { 877 struct sdhc_host *hp = (struct sdhc_host *)sch; 878 879 return hp->maxblklen; 880 } 881 882 /* 883 * Return non-zero if the card is currently inserted. 884 */ 885 static int 886 sdhc_card_detect(sdmmc_chipset_handle_t sch) 887 { 888 struct sdhc_host *hp = (struct sdhc_host *)sch; 889 int r; 890 891 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_NON_REMOVABLE)) 892 return 1; 893 894 if (hp->sc->sc_vendor_card_detect) 895 return (*hp->sc->sc_vendor_card_detect)(hp->sc); 896 897 r = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CARD_INSERTED); 898 899 return r ? 1 : 0; 900 } 901 902 /* 903 * Return non-zero if the card is currently write-protected. 904 */ 905 static int 906 sdhc_write_protect(sdmmc_chipset_handle_t sch) 907 { 908 struct sdhc_host *hp = (struct sdhc_host *)sch; 909 int r; 910 911 if (hp->sc->sc_vendor_write_protect) 912 return (*hp->sc->sc_vendor_write_protect)(hp->sc); 913 914 r = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_WRITE_PROTECT_SWITCH); 915 916 return r ? 0 : 1; 917 } 918 919 /* 920 * Set or change SD bus voltage and enable or disable SD bus power. 921 * Return zero on success. 922 */ 923 static int 924 sdhc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 925 { 926 struct sdhc_host *hp = (struct sdhc_host *)sch; 927 uint8_t vdd; 928 int error = 0; 929 const uint32_t pcmask = 930 ~(SDHC_BUS_POWER | (SDHC_VOLTAGE_MASK << SDHC_VOLTAGE_SHIFT)); 931 uint32_t reg; 932 933 mutex_enter(&hp->intr_lock); 934 935 /* 936 * Disable bus power before voltage change. 937 */ 938 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS) 939 && !ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_PWR0)) { 940 hp->vdd = 0; 941 HWRITE1(hp, SDHC_POWER_CTL, 0); 942 } 943 944 /* If power is disabled, reset the host and return now. */ 945 if (ocr == 0) { 946 (void)sdhc_host_reset1(hp); 947 callout_halt(&hp->tuning_timer, &hp->intr_lock); 948 goto out; 949 } 950 951 /* 952 * Select the lowest voltage according to capabilities. 953 */ 954 ocr &= hp->ocr; 955 if (ISSET(ocr, MMC_OCR_1_65V_1_95V)) { 956 vdd = SDHC_VOLTAGE_1_8V; 957 } else if (ISSET(ocr, MMC_OCR_2_9V_3_0V|MMC_OCR_3_0V_3_1V)) { 958 vdd = SDHC_VOLTAGE_3_0V; 959 } else if (ISSET(ocr, MMC_OCR_3_2V_3_3V|MMC_OCR_3_3V_3_4V)) { 960 vdd = SDHC_VOLTAGE_3_3V; 961 } else { 962 /* Unsupported voltage level requested. */ 963 error = EINVAL; 964 goto out; 965 } 966 967 /* 968 * Did voltage change ? 969 */ 970 if (vdd == hp->vdd) 971 goto out; 972 973 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 974 /* 975 * Enable bus power. Wait at least 1 ms (or 74 clocks) plus 976 * voltage ramp until power rises. 977 */ 978 979 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_SINGLE_POWER_WRITE)) { 980 HWRITE1(hp, SDHC_POWER_CTL, 981 (vdd << SDHC_VOLTAGE_SHIFT) | SDHC_BUS_POWER); 982 } else { 983 reg = HREAD1(hp, SDHC_POWER_CTL) & pcmask; 984 HWRITE1(hp, SDHC_POWER_CTL, reg); 985 sdmmc_delay(1); 986 reg |= (vdd << SDHC_VOLTAGE_SHIFT); 987 HWRITE1(hp, SDHC_POWER_CTL, reg); 988 sdmmc_delay(1); 989 reg |= SDHC_BUS_POWER; 990 HWRITE1(hp, SDHC_POWER_CTL, reg); 991 sdmmc_delay(10000); 992 } 993 994 /* 995 * The host system may not power the bus due to battery low, 996 * etc. In that case, the host controller should clear the 997 * bus power bit. 998 */ 999 if (!ISSET(HREAD1(hp, SDHC_POWER_CTL), SDHC_BUS_POWER)) { 1000 error = ENXIO; 1001 goto out; 1002 } 1003 } 1004 1005 /* power successfully changed */ 1006 hp->vdd = vdd; 1007 1008 out: 1009 mutex_exit(&hp->intr_lock); 1010 1011 return error; 1012 } 1013 1014 /* 1015 * Return the smallest possible base clock frequency divisor value 1016 * for the CLOCK_CTL register to produce `freq' (KHz). 1017 */ 1018 static bool 1019 sdhc_clock_divisor(struct sdhc_host *hp, u_int freq, u_int *divp) 1020 { 1021 u_int div; 1022 1023 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_HAVE_CGM)) { 1024 for (div = hp->clkbase / freq; div <= 0x3ff; div++) { 1025 if ((hp->clkbase / div) <= freq) { 1026 *divp = SDHC_SDCLK_CGM 1027 | ((div & 0x300) << SDHC_SDCLK_XDIV_SHIFT) 1028 | ((div & 0x0ff) << SDHC_SDCLK_DIV_SHIFT); 1029 //freq = hp->clkbase / div; 1030 return true; 1031 } 1032 } 1033 /* No divisor found. */ 1034 return false; 1035 } 1036 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_HAVE_DVS)) { 1037 u_int dvs = (hp->clkbase + freq - 1) / freq; 1038 u_int roundup = dvs & 1; 1039 for (dvs >>= 1, div = 1; div <= 256; div <<= 1, dvs >>= 1) { 1040 if (dvs + roundup <= 16) { 1041 dvs += roundup - 1; 1042 *divp = (div << SDHC_SDCLK_DIV_SHIFT) 1043 | (dvs << SDHC_SDCLK_DVS_SHIFT); 1044 DPRINTF(2, 1045 ("%s: divisor for freq %u is %u * %u\n", 1046 HDEVNAME(hp), freq, div * 2, dvs + 1)); 1047 //freq = hp->clkbase / (div * 2) * (dvs + 1); 1048 return true; 1049 } 1050 /* 1051 * If we drop bits, we need to round up the divisor. 1052 */ 1053 roundup |= dvs & 1; 1054 } 1055 /* No divisor found. */ 1056 return false; 1057 } 1058 if (hp->sc->sc_clkmsk != 0) { 1059 div = howmany(hp->clkbase, freq); 1060 if (div > (hp->sc->sc_clkmsk >> (ffs(hp->sc->sc_clkmsk) - 1))) 1061 return false; 1062 *divp = div << (ffs(hp->sc->sc_clkmsk) - 1); 1063 //freq = hp->clkbase / div; 1064 return true; 1065 } 1066 if (hp->specver >= SDHC_SPEC_VERS_300) { 1067 div = howmany(hp->clkbase, freq); 1068 div = div > 1 ? howmany(div, 2) : 0; 1069 if (div > 0x3ff) 1070 return false; 1071 *divp = (((div >> 8) & SDHC_SDCLK_XDIV_MASK) 1072 << SDHC_SDCLK_XDIV_SHIFT) | 1073 (((div >> 0) & SDHC_SDCLK_DIV_MASK) 1074 << SDHC_SDCLK_DIV_SHIFT); 1075 //freq = hp->clkbase / (div ? div * 2 : 1); 1076 return true; 1077 } else { 1078 for (div = 1; div <= 256; div *= 2) { 1079 if ((hp->clkbase / div) <= freq) { 1080 *divp = (div / 2) << SDHC_SDCLK_DIV_SHIFT; 1081 //freq = hp->clkbase / div; 1082 return true; 1083 } 1084 } 1085 /* No divisor found. */ 1086 return false; 1087 } 1088 /* No divisor found. */ 1089 return false; 1090 } 1091 1092 /* 1093 * Set or change SDCLK frequency or disable the SD clock. 1094 * Return zero on success. 1095 */ 1096 static int 1097 sdhc_bus_clock_ddr(sdmmc_chipset_handle_t sch, int freq, bool ddr) 1098 { 1099 struct sdhc_host *hp = (struct sdhc_host *)sch; 1100 u_int div; 1101 u_int timo; 1102 int16_t reg; 1103 int error = 0; 1104 bool present __diagused; 1105 1106 #ifdef DIAGNOSTIC 1107 present = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CMD_INHIBIT_MASK); 1108 1109 /* Must not stop the clock if commands are in progress. */ 1110 if (present && sdhc_card_detect(hp)) { 1111 aprint_normal_dev(hp->sc->sc_dev, 1112 "%s: command in progress\n", __func__); 1113 } 1114 #endif 1115 1116 if (hp->sc->sc_vendor_bus_clock) { 1117 mutex_enter(&hp->bus_clock_lock); 1118 error = (*hp->sc->sc_vendor_bus_clock)(hp->sc, freq); 1119 mutex_exit(&hp->bus_clock_lock); 1120 if (error != 0) 1121 return error; 1122 } 1123 1124 mutex_enter(&hp->intr_lock); 1125 1126 /* 1127 * Stop SD clock before changing the frequency. 1128 */ 1129 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_USDHC)) { 1130 HCLR4(hp, SDHC_VEND_SPEC, 1131 SDHC_VEND_SPEC_CARD_CLK_SOFT_EN | 1132 SDHC_VEND_SPEC_FRC_SDCLK_ON); 1133 if (freq == SDMMC_SDCLK_OFF) { 1134 goto out; 1135 } 1136 } else if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1137 HCLR4(hp, SDHC_CLOCK_CTL, 0xfff8); 1138 if (freq == SDMMC_SDCLK_OFF) { 1139 HSET4(hp, SDHC_CLOCK_CTL, 0x80f0); 1140 goto out; 1141 } 1142 } else { 1143 HCLR2(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE); 1144 if (freq == SDMMC_SDCLK_OFF) 1145 goto out; 1146 } 1147 1148 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_USDHC)) { 1149 if (ddr) 1150 HSET4(hp, SDHC_MIX_CTRL, SDHC_USDHC_DDR_EN); 1151 else 1152 HCLR4(hp, SDHC_MIX_CTRL, SDHC_USDHC_DDR_EN); 1153 } else if (hp->specver >= SDHC_SPEC_VERS_300) { 1154 HCLR2(hp, SDHC_HOST_CTL2, SDHC_UHS_MODE_SELECT_MASK); 1155 if (freq > 100000) { 1156 HSET2(hp, SDHC_HOST_CTL2, SDHC_UHS_MODE_SELECT_SDR104); 1157 } else if (freq > 50000) { 1158 if (ddr) { 1159 HSET2(hp, SDHC_HOST_CTL2, 1160 SDHC_UHS_MODE_SELECT_DDR50); 1161 } else { 1162 HSET2(hp, SDHC_HOST_CTL2, 1163 SDHC_UHS_MODE_SELECT_SDR50); 1164 } 1165 } else if (freq > 25000) { 1166 if (ddr) { 1167 HSET2(hp, SDHC_HOST_CTL2, 1168 SDHC_UHS_MODE_SELECT_DDR50); 1169 } else { 1170 HSET2(hp, SDHC_HOST_CTL2, 1171 SDHC_UHS_MODE_SELECT_SDR25); 1172 } 1173 } else if (freq > 400) { 1174 HSET2(hp, SDHC_HOST_CTL2, SDHC_UHS_MODE_SELECT_SDR12); 1175 } 1176 } 1177 1178 /* 1179 * Slow down Ricoh 5U823 controller that isn't reliable 1180 * at 100MHz bus clock. 1181 */ 1182 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_SLOW_SDR50)) { 1183 if (freq == 100000) 1184 --freq; 1185 } 1186 1187 /* 1188 * Set the minimum base clock frequency divisor. 1189 */ 1190 if (!sdhc_clock_divisor(hp, freq, &div)) { 1191 /* Invalid base clock frequency or `freq' value. */ 1192 aprint_error_dev(hp->sc->sc_dev, 1193 "Invalid bus clock %d kHz\n", freq); 1194 error = EINVAL; 1195 goto out; 1196 } 1197 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_USDHC)) { 1198 if (ddr) { 1199 /* in ddr mode, divisor >>= 1 */ 1200 div = ((div >> 1) & (SDHC_SDCLK_DIV_MASK << 1201 SDHC_SDCLK_DIV_SHIFT)) | 1202 (div & (SDHC_SDCLK_DVS_MASK << 1203 SDHC_SDCLK_DVS_SHIFT)); 1204 } 1205 for (timo = 1000; timo > 0; timo--) { 1206 if (ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_SDSTB)) 1207 break; 1208 sdmmc_delay(10); 1209 } 1210 HWRITE4(hp, SDHC_CLOCK_CTL, 1211 div | (SDHC_TIMEOUT_MAX << 16) | 0x0f); 1212 } else if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1213 HWRITE4(hp, SDHC_CLOCK_CTL, 1214 div | (SDHC_TIMEOUT_MAX << 16)); 1215 } else { 1216 reg = HREAD2(hp, SDHC_CLOCK_CTL); 1217 reg &= (SDHC_INTCLK_STABLE | SDHC_INTCLK_ENABLE); 1218 HWRITE2(hp, SDHC_CLOCK_CTL, reg | div); 1219 } 1220 1221 /* 1222 * Start internal clock. Wait 10ms for stabilization. 1223 */ 1224 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_USDHC)) { 1225 HSET4(hp, SDHC_VEND_SPEC, 1226 SDHC_VEND_SPEC_CARD_CLK_SOFT_EN | 1227 SDHC_VEND_SPEC_FRC_SDCLK_ON); 1228 } else if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1229 sdmmc_delay(10000); 1230 HSET4(hp, SDHC_CLOCK_CTL, 1231 8 | SDHC_INTCLK_ENABLE | SDHC_INTCLK_STABLE); 1232 } else { 1233 HSET2(hp, SDHC_CLOCK_CTL, SDHC_INTCLK_ENABLE); 1234 for (timo = 1000; timo > 0; timo--) { 1235 if (ISSET(HREAD2(hp, SDHC_CLOCK_CTL), 1236 SDHC_INTCLK_STABLE)) 1237 break; 1238 sdmmc_delay(10); 1239 } 1240 if (timo == 0) { 1241 error = ETIMEDOUT; 1242 DPRINTF(1,("%s: timeout\n", __func__)); 1243 goto out; 1244 } 1245 } 1246 1247 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED | SDHC_FLAG_USDHC)) { 1248 HSET1(hp, SDHC_SOFTWARE_RESET, SDHC_INIT_ACTIVE); 1249 /* 1250 * Sending 80 clocks at 400kHz takes 200us. 1251 * So delay for that time + slop and then 1252 * check a few times for completion. 1253 */ 1254 sdmmc_delay(210); 1255 for (timo = 10; timo > 0; timo--) { 1256 if (!ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), 1257 SDHC_INIT_ACTIVE)) 1258 break; 1259 sdmmc_delay(10); 1260 } 1261 DPRINTF(2,("%s: %u init spins\n", __func__, 10 - timo)); 1262 1263 /* 1264 * Enable SD clock. 1265 */ 1266 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_USDHC)) { 1267 HSET4(hp, SDHC_VEND_SPEC, 1268 SDHC_VEND_SPEC_CARD_CLK_SOFT_EN | 1269 SDHC_VEND_SPEC_FRC_SDCLK_ON); 1270 } else { 1271 HSET4(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE); 1272 } 1273 } else { 1274 /* 1275 * Enable SD clock. 1276 */ 1277 HSET2(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE); 1278 1279 if (freq > 25000 && 1280 !ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_HS_BIT)) 1281 HSET1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED); 1282 else 1283 HCLR1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED); 1284 } 1285 1286 mutex_exit(&hp->intr_lock); 1287 1288 if (hp->sc->sc_vendor_bus_clock_post) { 1289 mutex_enter(&hp->bus_clock_lock); 1290 error = (*hp->sc->sc_vendor_bus_clock_post)(hp->sc, freq); 1291 mutex_exit(&hp->bus_clock_lock); 1292 } 1293 return error; 1294 1295 out: 1296 mutex_exit(&hp->intr_lock); 1297 1298 return error; 1299 } 1300 1301 static int 1302 sdhc_bus_width(sdmmc_chipset_handle_t sch, int width) 1303 { 1304 struct sdhc_host *hp = (struct sdhc_host *)sch; 1305 int reg; 1306 1307 switch (width) { 1308 case 1: 1309 case 4: 1310 break; 1311 1312 case 8: 1313 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_8BIT_MODE)) 1314 break; 1315 /* FALLTHROUGH */ 1316 default: 1317 DPRINTF(0,("%s: unsupported bus width (%d)\n", 1318 HDEVNAME(hp), width)); 1319 return 1; 1320 } 1321 1322 if (hp->sc->sc_vendor_bus_width) { 1323 const int error = hp->sc->sc_vendor_bus_width(hp->sc, width); 1324 if (error != 0) 1325 return error; 1326 } 1327 1328 mutex_enter(&hp->intr_lock); 1329 1330 reg = HREAD1(hp, SDHC_HOST_CTL); 1331 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED | SDHC_FLAG_USDHC)) { 1332 reg &= ~(SDHC_4BIT_MODE|SDHC_ESDHC_8BIT_MODE); 1333 if (width == 4) 1334 reg |= SDHC_4BIT_MODE; 1335 else if (width == 8) 1336 reg |= SDHC_ESDHC_8BIT_MODE; 1337 } else { 1338 reg &= ~SDHC_4BIT_MODE; 1339 if (hp->specver >= SDHC_SPEC_VERS_300) { 1340 reg &= ~SDHC_8BIT_MODE; 1341 } 1342 if (width == 4) { 1343 reg |= SDHC_4BIT_MODE; 1344 } else if (width == 8 && hp->specver >= SDHC_SPEC_VERS_300) { 1345 reg |= SDHC_8BIT_MODE; 1346 } 1347 } 1348 HWRITE1(hp, SDHC_HOST_CTL, reg); 1349 1350 mutex_exit(&hp->intr_lock); 1351 1352 return 0; 1353 } 1354 1355 static int 1356 sdhc_bus_rod(sdmmc_chipset_handle_t sch, int on) 1357 { 1358 struct sdhc_host *hp = (struct sdhc_host *)sch; 1359 1360 if (hp->sc->sc_vendor_rod) 1361 return (*hp->sc->sc_vendor_rod)(hp->sc, on); 1362 1363 return 0; 1364 } 1365 1366 static void 1367 sdhc_card_enable_intr(sdmmc_chipset_handle_t sch, int enable) 1368 { 1369 struct sdhc_host *hp = (struct sdhc_host *)sch; 1370 1371 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED | SDHC_FLAG_USDHC)) { 1372 mutex_enter(&hp->intr_lock); 1373 if (enable) { 1374 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 1375 HSET2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT); 1376 } else { 1377 HCLR2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT); 1378 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 1379 } 1380 mutex_exit(&hp->intr_lock); 1381 } 1382 } 1383 1384 static void 1385 sdhc_card_intr_ack(sdmmc_chipset_handle_t sch) 1386 { 1387 struct sdhc_host *hp = (struct sdhc_host *)sch; 1388 1389 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED | SDHC_FLAG_USDHC)) { 1390 mutex_enter(&hp->intr_lock); 1391 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 1392 mutex_exit(&hp->intr_lock); 1393 } 1394 } 1395 1396 static int 1397 sdhc_signal_voltage(sdmmc_chipset_handle_t sch, int signal_voltage) 1398 { 1399 struct sdhc_host *hp = (struct sdhc_host *)sch; 1400 int error = 0; 1401 1402 if (hp->specver < SDHC_SPEC_VERS_300) 1403 return EINVAL; 1404 1405 mutex_enter(&hp->intr_lock); 1406 switch (signal_voltage) { 1407 case SDMMC_SIGNAL_VOLTAGE_180: 1408 if (hp->sc->sc_vendor_signal_voltage != NULL) { 1409 error = hp->sc->sc_vendor_signal_voltage(hp->sc, 1410 signal_voltage); 1411 if (error != 0) 1412 break; 1413 } 1414 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_USDHC)) 1415 HSET2(hp, SDHC_HOST_CTL2, SDHC_1_8V_SIGNAL_EN); 1416 break; 1417 case SDMMC_SIGNAL_VOLTAGE_330: 1418 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_USDHC)) 1419 HCLR2(hp, SDHC_HOST_CTL2, SDHC_1_8V_SIGNAL_EN); 1420 if (hp->sc->sc_vendor_signal_voltage != NULL) { 1421 error = hp->sc->sc_vendor_signal_voltage(hp->sc, 1422 signal_voltage); 1423 if (error != 0) 1424 break; 1425 } 1426 break; 1427 default: 1428 error = EINVAL; 1429 break; 1430 } 1431 mutex_exit(&hp->intr_lock); 1432 1433 return error; 1434 } 1435 1436 /* 1437 * Sampling clock tuning procedure (UHS) 1438 */ 1439 static int 1440 sdhc_execute_tuning1(struct sdhc_host *hp, int timing) 1441 { 1442 struct sdmmc_command cmd; 1443 uint8_t hostctl; 1444 int opcode, error, retry = 40; 1445 1446 KASSERT(mutex_owned(&hp->intr_lock)); 1447 1448 hp->tuning_timing = timing; 1449 1450 switch (timing) { 1451 case SDMMC_TIMING_MMC_HS200: 1452 opcode = MMC_SEND_TUNING_BLOCK_HS200; 1453 break; 1454 case SDMMC_TIMING_UHS_SDR50: 1455 if (!ISSET(hp->sc->sc_caps2, SDHC_TUNING_SDR50)) 1456 return 0; 1457 /* FALLTHROUGH */ 1458 case SDMMC_TIMING_UHS_SDR104: 1459 opcode = MMC_SEND_TUNING_BLOCK; 1460 break; 1461 default: 1462 return EINVAL; 1463 } 1464 1465 hostctl = HREAD1(hp, SDHC_HOST_CTL); 1466 1467 /* enable buffer read ready interrupt */ 1468 HSET2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_BUFFER_READ_READY); 1469 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_BUFFER_READ_READY); 1470 1471 /* disable DMA */ 1472 HCLR1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT); 1473 1474 /* reset tuning circuit */ 1475 HCLR2(hp, SDHC_HOST_CTL2, SDHC_SAMPLING_CLOCK_SEL); 1476 1477 /* start of tuning */ 1478 HWRITE2(hp, SDHC_HOST_CTL2, SDHC_EXECUTE_TUNING); 1479 1480 do { 1481 memset(&cmd, 0, sizeof(cmd)); 1482 cmd.c_opcode = opcode; 1483 cmd.c_arg = 0; 1484 cmd.c_flags = SCF_CMD_ADTC | SCF_CMD_READ | SCF_RSP_R1; 1485 if (ISSET(hostctl, SDHC_8BIT_MODE)) { 1486 cmd.c_blklen = cmd.c_datalen = 128; 1487 } else { 1488 cmd.c_blklen = cmd.c_datalen = 64; 1489 } 1490 1491 error = sdhc_start_command(hp, &cmd); 1492 if (error) 1493 break; 1494 1495 if (!sdhc_wait_intr(hp, SDHC_BUFFER_READ_READY, 1496 SDHC_TUNING_TIMEOUT, false)) { 1497 break; 1498 } 1499 1500 delay(1000); 1501 } while (HREAD2(hp, SDHC_HOST_CTL2) & SDHC_EXECUTE_TUNING && --retry); 1502 1503 /* disable buffer read ready interrupt */ 1504 HCLR2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_BUFFER_READ_READY); 1505 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_BUFFER_READ_READY); 1506 1507 if (HREAD2(hp, SDHC_HOST_CTL2) & SDHC_EXECUTE_TUNING) { 1508 HCLR2(hp, SDHC_HOST_CTL2, 1509 SDHC_SAMPLING_CLOCK_SEL|SDHC_EXECUTE_TUNING); 1510 sdhc_soft_reset(hp, SDHC_RESET_DAT|SDHC_RESET_CMD); 1511 aprint_error_dev(hp->sc->sc_dev, 1512 "tuning did not complete, using fixed sampling clock\n"); 1513 return 0; /* tuning did not complete */ 1514 } 1515 1516 if ((HREAD2(hp, SDHC_HOST_CTL2) & SDHC_SAMPLING_CLOCK_SEL) == 0) { 1517 HCLR2(hp, SDHC_HOST_CTL2, 1518 SDHC_SAMPLING_CLOCK_SEL|SDHC_EXECUTE_TUNING); 1519 sdhc_soft_reset(hp, SDHC_RESET_DAT|SDHC_RESET_CMD); 1520 aprint_error_dev(hp->sc->sc_dev, 1521 "tuning failed, using fixed sampling clock\n"); 1522 return 0; /* tuning failed */ 1523 } 1524 1525 if (hp->tuning_timer_count) { 1526 callout_schedule(&hp->tuning_timer, 1527 hz * hp->tuning_timer_count); 1528 } 1529 1530 return 0; /* tuning completed */ 1531 } 1532 1533 static int 1534 sdhc_execute_tuning(sdmmc_chipset_handle_t sch, int timing) 1535 { 1536 struct sdhc_host *hp = (struct sdhc_host *)sch; 1537 int error; 1538 1539 mutex_enter(&hp->intr_lock); 1540 error = sdhc_execute_tuning1(hp, timing); 1541 mutex_exit(&hp->intr_lock); 1542 return error; 1543 } 1544 1545 static void 1546 sdhc_tuning_timer(void *arg) 1547 { 1548 struct sdhc_host *hp = arg; 1549 1550 atomic_swap_uint(&hp->tuning_timer_pending, 1); 1551 } 1552 1553 static void 1554 sdhc_hw_reset(sdmmc_chipset_handle_t sch) 1555 { 1556 struct sdhc_host *hp = (struct sdhc_host *)sch; 1557 struct sdhc_softc *sc = hp->sc; 1558 1559 if (sc->sc_vendor_hw_reset != NULL) 1560 sc->sc_vendor_hw_reset(sc, hp); 1561 } 1562 1563 static int 1564 sdhc_wait_state(struct sdhc_host *hp, uint32_t mask, uint32_t value) 1565 { 1566 struct timeval start, diff; 1567 uint32_t state; 1568 1569 microuptime(&start); 1570 for (;;) { 1571 state = HREAD4(hp, SDHC_PRESENT_STATE); 1572 if ((state & mask) == value) { 1573 return 0; 1574 } 1575 microuptime(&diff); 1576 timersub(&diff, &start, &diff); 1577 if (diff.tv_sec != 0) { 1578 aprint_error_dev(hp->sc->sc_dev, 1579 "timeout waiting for mask %#x value %#x " 1580 "(state=%#x)\n", 1581 mask, value, state); 1582 return ETIMEDOUT; 1583 } 1584 } 1585 } 1586 1587 static void 1588 sdhc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 1589 { 1590 struct sdhc_host *hp = (struct sdhc_host *)sch; 1591 int error; 1592 bool probing; 1593 1594 mutex_enter(&hp->intr_lock); 1595 1596 if (atomic_cas_uint(&hp->tuning_timer_pending, 1, 0) == 1) { 1597 (void)sdhc_execute_tuning1(hp, hp->tuning_timing); 1598 } 1599 1600 if (cmd->c_data && 1601 ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED | SDHC_FLAG_USDHC)) { 1602 const uint16_t ready = SDHC_BUFFER_READ_READY | SDHC_BUFFER_WRITE_READY; 1603 if (ISSET(hp->flags, SHF_USE_DMA)) { 1604 HCLR2(hp, SDHC_NINTR_SIGNAL_EN, ready); 1605 HCLR2(hp, SDHC_NINTR_STATUS_EN, ready); 1606 } else { 1607 HSET2(hp, SDHC_NINTR_SIGNAL_EN, ready); 1608 HSET2(hp, SDHC_NINTR_STATUS_EN, ready); 1609 } 1610 } 1611 1612 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_TIMEOUT)) { 1613 const uint16_t eintr = SDHC_CMD_TIMEOUT_ERROR; 1614 if (cmd->c_data != NULL) { 1615 HCLR2(hp, SDHC_EINTR_SIGNAL_EN, eintr); 1616 HCLR2(hp, SDHC_EINTR_STATUS_EN, eintr); 1617 } else { 1618 HSET2(hp, SDHC_EINTR_SIGNAL_EN, eintr); 1619 HSET2(hp, SDHC_EINTR_STATUS_EN, eintr); 1620 } 1621 } 1622 1623 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_STOP_WITH_TC)) { 1624 if (cmd->c_opcode == MMC_STOP_TRANSMISSION) 1625 SET(cmd->c_flags, SCF_RSP_BSY); 1626 } 1627 1628 /* 1629 * Start the MMC command, or mark `cmd' as failed and return. 1630 */ 1631 error = sdhc_start_command(hp, cmd); 1632 if (error) { 1633 cmd->c_error = error; 1634 goto out; 1635 } 1636 1637 /* 1638 * Wait until the command phase is done, or until the command 1639 * is marked done for any other reason. 1640 */ 1641 probing = (cmd->c_flags & SCF_TOUT_OK) != 0; 1642 if (!sdhc_wait_intr(hp, SDHC_COMMAND_COMPLETE, SDHC_COMMAND_TIMEOUT*3, probing)) { 1643 DPRINTF(1,("%s: timeout for command\n", __func__)); 1644 sdmmc_delay(50); 1645 cmd->c_error = ETIMEDOUT; 1646 goto out; 1647 } 1648 1649 /* 1650 * The host controller removes bits [0:7] from the response 1651 * data (CRC) and we pass the data up unchanged to the bus 1652 * driver (without padding). 1653 */ 1654 if (cmd->c_error == 0 && ISSET(cmd->c_flags, SCF_RSP_PRESENT)) { 1655 cmd->c_resp[0] = HREAD4(hp, SDHC_RESPONSE + 0); 1656 if (ISSET(cmd->c_flags, SCF_RSP_136)) { 1657 cmd->c_resp[1] = HREAD4(hp, SDHC_RESPONSE + 4); 1658 cmd->c_resp[2] = HREAD4(hp, SDHC_RESPONSE + 8); 1659 cmd->c_resp[3] = HREAD4(hp, SDHC_RESPONSE + 12); 1660 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_RSP136_CRC)) { 1661 cmd->c_resp[0] = (cmd->c_resp[0] >> 8) | 1662 (cmd->c_resp[1] << 24); 1663 cmd->c_resp[1] = (cmd->c_resp[1] >> 8) | 1664 (cmd->c_resp[2] << 24); 1665 cmd->c_resp[2] = (cmd->c_resp[2] >> 8) | 1666 (cmd->c_resp[3] << 24); 1667 cmd->c_resp[3] = (cmd->c_resp[3] >> 8); 1668 } 1669 } 1670 } 1671 DPRINTF(1,("%s: resp = %08x\n", HDEVNAME(hp), cmd->c_resp[0])); 1672 1673 /* 1674 * If the command has data to transfer in any direction, 1675 * execute the transfer now. 1676 */ 1677 if (cmd->c_error == 0 && cmd->c_data != NULL) 1678 sdhc_transfer_data(hp, cmd); 1679 else if (ISSET(cmd->c_flags, SCF_RSP_BSY)) { 1680 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_BUSY_INTR) && 1681 !sdhc_wait_intr(hp, SDHC_TRANSFER_COMPLETE, hz * 10, false)) { 1682 DPRINTF(1,("%s: sdhc_exec_command: RSP_BSY\n", 1683 HDEVNAME(hp))); 1684 cmd->c_error = ETIMEDOUT; 1685 goto out; 1686 } 1687 } 1688 1689 out: 1690 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED) 1691 && !ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_LED_ON)) { 1692 /* Turn off the LED. */ 1693 HCLR1(hp, SDHC_HOST_CTL, SDHC_LED_ON); 1694 } 1695 SET(cmd->c_flags, SCF_ITSDONE); 1696 1697 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_AUTO_STOP) && 1698 cmd->c_opcode == MMC_STOP_TRANSMISSION) 1699 (void)sdhc_soft_reset(hp, SDHC_RESET_CMD|SDHC_RESET_DAT); 1700 1701 mutex_exit(&hp->intr_lock); 1702 1703 DPRINTF(1,("%s: cmd %d %s (flags=%08x error=%d)\n", HDEVNAME(hp), 1704 cmd->c_opcode, (cmd->c_error == 0) ? "done" : "abort", 1705 cmd->c_flags, cmd->c_error)); 1706 } 1707 1708 static int 1709 sdhc_start_command(struct sdhc_host *hp, struct sdmmc_command *cmd) 1710 { 1711 struct sdhc_softc * const sc = hp->sc; 1712 uint16_t blksize = 0; 1713 uint16_t blkcount = 0; 1714 uint16_t mode; 1715 uint16_t command; 1716 uint32_t pmask; 1717 int error; 1718 1719 KASSERT(mutex_owned(&hp->intr_lock)); 1720 1721 DPRINTF(1,("%s: start cmd %d arg=%08x data=%p dlen=%d flags=%08x, status=%#x\n", 1722 HDEVNAME(hp), cmd->c_opcode, cmd->c_arg, cmd->c_data, 1723 cmd->c_datalen, cmd->c_flags, HREAD4(hp, SDHC_NINTR_STATUS))); 1724 1725 /* 1726 * The maximum block length for commands should be the minimum 1727 * of the host buffer size and the card buffer size. (1.7.2) 1728 */ 1729 1730 /* Fragment the data into proper blocks. */ 1731 if (cmd->c_datalen > 0) { 1732 blksize = MIN(cmd->c_datalen, cmd->c_blklen); 1733 blkcount = cmd->c_datalen / blksize; 1734 if (cmd->c_datalen % blksize > 0) { 1735 /* XXX: Split this command. (1.7.4) */ 1736 aprint_error_dev(sc->sc_dev, 1737 "data not a multiple of %u bytes\n", blksize); 1738 return EINVAL; 1739 } 1740 } 1741 1742 /* Check limit imposed by 9-bit block count. (1.7.2) */ 1743 if (blkcount > SDHC_BLOCK_COUNT_MAX) { 1744 aprint_error_dev(sc->sc_dev, "too much data\n"); 1745 return EINVAL; 1746 } 1747 1748 /* Prepare transfer mode register value. (2.2.5) */ 1749 mode = 0; 1750 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 1751 mode |= SDHC_READ_MODE; 1752 if (blkcount > 0) { 1753 mode |= SDHC_BLOCK_COUNT_ENABLE; 1754 if (blkcount > 1) { 1755 mode |= SDHC_MULTI_BLOCK_MODE; 1756 if (!ISSET(sc->sc_flags, SDHC_FLAG_NO_AUTO_STOP) 1757 && !ISSET(cmd->c_flags, SCF_NO_STOP)) 1758 mode |= SDHC_AUTO_CMD12_ENABLE; 1759 } 1760 } 1761 if (cmd->c_dmamap != NULL && cmd->c_datalen > 0 && 1762 ISSET(hp->flags, SHF_MODE_DMAEN)) { 1763 mode |= SDHC_DMA_ENABLE; 1764 } 1765 1766 /* 1767 * Prepare command register value. (2.2.6) 1768 */ 1769 command = (cmd->c_opcode & SDHC_COMMAND_INDEX_MASK) << SDHC_COMMAND_INDEX_SHIFT; 1770 1771 if (ISSET(cmd->c_flags, SCF_RSP_CRC)) 1772 command |= SDHC_CRC_CHECK_ENABLE; 1773 if (ISSET(cmd->c_flags, SCF_RSP_IDX)) 1774 command |= SDHC_INDEX_CHECK_ENABLE; 1775 if (cmd->c_datalen > 0) 1776 command |= SDHC_DATA_PRESENT_SELECT; 1777 1778 if (!ISSET(cmd->c_flags, SCF_RSP_PRESENT)) 1779 command |= SDHC_NO_RESPONSE; 1780 else if (ISSET(cmd->c_flags, SCF_RSP_136)) 1781 command |= SDHC_RESP_LEN_136; 1782 else if (ISSET(cmd->c_flags, SCF_RSP_BSY)) 1783 command |= SDHC_RESP_LEN_48_CHK_BUSY; 1784 else 1785 command |= SDHC_RESP_LEN_48; 1786 1787 /* Wait until command and optionally data inhibit bits are clear. (1.5) */ 1788 pmask = SDHC_CMD_INHIBIT_CMD; 1789 if (cmd->c_flags & (SCF_CMD_ADTC|SCF_RSP_BSY)) 1790 pmask |= SDHC_CMD_INHIBIT_DAT; 1791 error = sdhc_wait_state(hp, pmask, 0); 1792 if (error) { 1793 (void) sdhc_soft_reset(hp, SDHC_RESET_DAT|SDHC_RESET_CMD); 1794 device_printf(sc->sc_dev, "command or data phase inhibited\n"); 1795 return error; 1796 } 1797 1798 DPRINTF(1,("%s: writing cmd: blksize=%d blkcnt=%d mode=%04x cmd=%04x\n", 1799 HDEVNAME(hp), blksize, blkcount, mode, command)); 1800 1801 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED | SDHC_FLAG_USDHC)) { 1802 blksize |= (MAX(0, PAGE_SHIFT - 12) & SDHC_DMA_BOUNDARY_MASK) << 1803 SDHC_DMA_BOUNDARY_SHIFT; /* PAGE_SIZE DMA boundary */ 1804 } 1805 1806 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1807 /* Alert the user not to remove the card. */ 1808 HSET1(hp, SDHC_HOST_CTL, SDHC_LED_ON); 1809 } 1810 1811 /* Set DMA start address. */ 1812 if (ISSET(hp->flags, SHF_USE_ADMA2_MASK) && cmd->c_data != NULL) { 1813 for (int seg = 0; seg < cmd->c_dmamap->dm_nsegs; seg++) { 1814 bus_addr_t paddr = 1815 cmd->c_dmamap->dm_segs[seg].ds_addr; 1816 uint16_t len = 1817 cmd->c_dmamap->dm_segs[seg].ds_len == 65536 ? 1818 0 : cmd->c_dmamap->dm_segs[seg].ds_len; 1819 uint16_t attr = 1820 SDHC_ADMA2_VALID | SDHC_ADMA2_ACT_TRANS; 1821 if (seg == cmd->c_dmamap->dm_nsegs - 1) { 1822 attr |= SDHC_ADMA2_END; 1823 } 1824 if (ISSET(hp->flags, SHF_USE_ADMA2_32)) { 1825 struct sdhc_adma2_descriptor32 *desc = 1826 hp->adma2; 1827 desc[seg].attribute = htole16(attr); 1828 desc[seg].length = htole16(len); 1829 desc[seg].address = htole32(paddr); 1830 } else { 1831 struct sdhc_adma2_descriptor64 *desc = 1832 hp->adma2; 1833 desc[seg].attribute = htole16(attr); 1834 desc[seg].length = htole16(len); 1835 desc[seg].address = htole32(paddr & 0xffffffff); 1836 desc[seg].address_hi = htole32( 1837 (uint64_t)paddr >> 32); 1838 } 1839 } 1840 if (ISSET(hp->flags, SHF_USE_ADMA2_32)) { 1841 struct sdhc_adma2_descriptor32 *desc = hp->adma2; 1842 desc[cmd->c_dmamap->dm_nsegs].attribute = htole16(0); 1843 } else { 1844 struct sdhc_adma2_descriptor64 *desc = hp->adma2; 1845 desc[cmd->c_dmamap->dm_nsegs].attribute = htole16(0); 1846 } 1847 bus_dmamap_sync(sc->sc_dmat, hp->adma_map, 0, PAGE_SIZE, 1848 BUS_DMASYNC_PREWRITE); 1849 1850 const bus_addr_t desc_addr = hp->adma_map->dm_segs[0].ds_addr; 1851 HWRITE4(hp, SDHC_ADMA_SYSTEM_ADDR, desc_addr & 0xffffffff); 1852 if (ISSET(hp->flags, SHF_USE_ADMA2_64)) { 1853 HWRITE4(hp, SDHC_ADMA_SYSTEM_ADDR + 4, 1854 (uint64_t)desc_addr >> 32); 1855 } 1856 1857 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_USDHC)) { 1858 HCLR4(hp, SDHC_HOST_CTL, SDHC_USDHC_DMA_SELECT); 1859 HSET4(hp, SDHC_HOST_CTL, SDHC_USDHC_DMA_SELECT_ADMA2); 1860 } else { 1861 HCLR1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT); 1862 HSET1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT_ADMA2); 1863 } 1864 } else if (ISSET(mode, SDHC_DMA_ENABLE) && 1865 !ISSET(sc->sc_flags, SDHC_FLAG_EXTERNAL_DMA)) { 1866 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_USDHC)) { 1867 HCLR4(hp, SDHC_HOST_CTL, SDHC_USDHC_DMA_SELECT); 1868 } 1869 HWRITE4(hp, SDHC_DMA_ADDR, cmd->c_dmamap->dm_segs[0].ds_addr); 1870 } 1871 1872 /* 1873 * Start a CPU data transfer. Writing to the high order byte 1874 * of the SDHC_COMMAND register triggers the SD command. (1.5) 1875 */ 1876 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 1877 HWRITE4(hp, SDHC_BLOCK_SIZE, blksize | (blkcount << 16)); 1878 HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg); 1879 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_USDHC)) { 1880 /* mode bits is in MIX_CTRL register on uSDHC */ 1881 HWRITE4(hp, SDHC_MIX_CTRL, mode | 1882 (HREAD4(hp, SDHC_MIX_CTRL) & ~SDHC_TRANSFER_MODE_MASK)); 1883 if (cmd->c_opcode == MMC_STOP_TRANSMISSION) 1884 command |= SDHC_COMMAND_TYPE_ABORT; 1885 HWRITE4(hp, SDHC_TRANSFER_MODE, command << 16); 1886 } else { 1887 HWRITE4(hp, SDHC_TRANSFER_MODE, mode | (command << 16)); 1888 } 1889 } else { 1890 HWRITE2(hp, SDHC_BLOCK_SIZE, blksize); 1891 HWRITE2(hp, SDHC_BLOCK_COUNT, blkcount); 1892 HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg); 1893 HWRITE2(hp, SDHC_TRANSFER_MODE, mode); 1894 HWRITE2(hp, SDHC_COMMAND, command); 1895 } 1896 1897 return 0; 1898 } 1899 1900 static void 1901 sdhc_transfer_data(struct sdhc_host *hp, struct sdmmc_command *cmd) 1902 { 1903 struct sdhc_softc *sc = hp->sc; 1904 int error; 1905 1906 KASSERT(mutex_owned(&hp->intr_lock)); 1907 1908 DPRINTF(1,("%s: data transfer: resp=%08x datalen=%u\n", HDEVNAME(hp), 1909 MMC_R1(cmd->c_resp), cmd->c_datalen)); 1910 1911 #ifdef SDHC_DEBUG 1912 /* XXX I forgot why I wanted to know when this happens :-( */ 1913 if ((cmd->c_opcode == 52 || cmd->c_opcode == 53) && 1914 ISSET(MMC_R1(cmd->c_resp), 0xcb00)) { 1915 aprint_error_dev(hp->sc->sc_dev, 1916 "CMD52/53 error response flags %#x\n", 1917 MMC_R1(cmd->c_resp) & 0xff00); 1918 } 1919 #endif 1920 1921 if (cmd->c_dmamap != NULL) { 1922 if (hp->sc->sc_vendor_transfer_data_dma != NULL) { 1923 error = hp->sc->sc_vendor_transfer_data_dma(sc, cmd); 1924 if (error == 0 && !sdhc_wait_intr(hp, 1925 SDHC_TRANSFER_COMPLETE, SDHC_DMA_TIMEOUT, false)) { 1926 DPRINTF(1,("%s: timeout\n", __func__)); 1927 error = ETIMEDOUT; 1928 } 1929 } else { 1930 error = sdhc_transfer_data_dma(hp, cmd); 1931 } 1932 } else 1933 error = sdhc_transfer_data_pio(hp, cmd); 1934 if (error) 1935 cmd->c_error = error; 1936 SET(cmd->c_flags, SCF_ITSDONE); 1937 1938 DPRINTF(1,("%s: data transfer done (error=%d)\n", 1939 HDEVNAME(hp), cmd->c_error)); 1940 } 1941 1942 static int 1943 sdhc_transfer_data_dma(struct sdhc_host *hp, struct sdmmc_command *cmd) 1944 { 1945 bus_dma_segment_t *dm_segs = cmd->c_dmamap->dm_segs; 1946 bus_addr_t posaddr; 1947 bus_addr_t segaddr; 1948 bus_size_t seglen; 1949 u_int seg = 0; 1950 int error = 0; 1951 int status; 1952 1953 KASSERT(mutex_owned(&hp->intr_lock)); 1954 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_DMA_INTERRUPT); 1955 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_DMA_INTERRUPT); 1956 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_TRANSFER_COMPLETE); 1957 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_TRANSFER_COMPLETE); 1958 1959 for (;;) { 1960 status = sdhc_wait_intr(hp, 1961 SDHC_DMA_INTERRUPT|SDHC_TRANSFER_COMPLETE, 1962 SDHC_DMA_TIMEOUT, false); 1963 1964 if (status & SDHC_TRANSFER_COMPLETE) { 1965 break; 1966 } 1967 if (!status) { 1968 DPRINTF(1,("%s: timeout\n", __func__)); 1969 error = ETIMEDOUT; 1970 break; 1971 } 1972 1973 if (ISSET(hp->flags, SHF_USE_ADMA2_MASK)) { 1974 continue; 1975 } 1976 1977 if ((status & SDHC_DMA_INTERRUPT) == 0) { 1978 continue; 1979 } 1980 1981 /* DMA Interrupt (boundary crossing) */ 1982 1983 segaddr = dm_segs[seg].ds_addr; 1984 seglen = dm_segs[seg].ds_len; 1985 posaddr = HREAD4(hp, SDHC_DMA_ADDR); 1986 1987 if ((seg == (cmd->c_dmamap->dm_nsegs-1)) && (posaddr == (segaddr + seglen))) { 1988 continue; 1989 } 1990 if ((posaddr >= segaddr) && (posaddr < (segaddr + seglen))) 1991 HWRITE4(hp, SDHC_DMA_ADDR, posaddr); 1992 else if ((posaddr >= segaddr) && (posaddr == (segaddr + seglen)) && (seg + 1) < cmd->c_dmamap->dm_nsegs) 1993 HWRITE4(hp, SDHC_DMA_ADDR, dm_segs[++seg].ds_addr); 1994 KASSERT(seg < cmd->c_dmamap->dm_nsegs); 1995 } 1996 1997 if (ISSET(hp->flags, SHF_USE_ADMA2_MASK)) { 1998 bus_dmamap_sync(hp->sc->sc_dmat, hp->adma_map, 0, 1999 PAGE_SIZE, BUS_DMASYNC_POSTWRITE); 2000 } 2001 2002 return error; 2003 } 2004 2005 static int 2006 sdhc_transfer_data_pio(struct sdhc_host *hp, struct sdmmc_command *cmd) 2007 { 2008 uint8_t *data = cmd->c_data; 2009 void (*pio_func)(struct sdhc_host *, uint8_t *, u_int); 2010 u_int len, datalen; 2011 u_int imask; 2012 u_int pmask; 2013 int error = 0; 2014 2015 KASSERT(mutex_owned(&hp->intr_lock)); 2016 2017 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 2018 imask = SDHC_BUFFER_READ_READY; 2019 pmask = SDHC_BUFFER_READ_ENABLE; 2020 if (ISSET(hp->sc->sc_flags, 2021 SDHC_FLAG_ENHANCED | SDHC_FLAG_USDHC)) { 2022 pio_func = esdhc_read_data_pio; 2023 } else { 2024 pio_func = sdhc_read_data_pio; 2025 } 2026 } else { 2027 imask = SDHC_BUFFER_WRITE_READY; 2028 pmask = SDHC_BUFFER_WRITE_ENABLE; 2029 if (ISSET(hp->sc->sc_flags, 2030 SDHC_FLAG_ENHANCED | SDHC_FLAG_USDHC)) { 2031 pio_func = esdhc_write_data_pio; 2032 } else { 2033 pio_func = sdhc_write_data_pio; 2034 } 2035 } 2036 datalen = cmd->c_datalen; 2037 2038 KASSERT(mutex_owned(&hp->intr_lock)); 2039 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & imask); 2040 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_TRANSFER_COMPLETE); 2041 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_TRANSFER_COMPLETE); 2042 2043 while (datalen > 0) { 2044 if (!ISSET(HREAD4(hp, SDHC_PRESENT_STATE), pmask)) { 2045 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 2046 HSET4(hp, SDHC_NINTR_SIGNAL_EN, imask); 2047 } else { 2048 HSET2(hp, SDHC_NINTR_SIGNAL_EN, imask); 2049 } 2050 if (!sdhc_wait_intr(hp, imask, SDHC_BUFFER_TIMEOUT, false)) { 2051 DPRINTF(1,("%s: timeout\n", __func__)); 2052 error = ETIMEDOUT; 2053 break; 2054 } 2055 2056 error = sdhc_wait_state(hp, pmask, pmask); 2057 if (error) 2058 break; 2059 } 2060 2061 len = MIN(datalen, cmd->c_blklen); 2062 (*pio_func)(hp, data, len); 2063 DPRINTF(2,("%s: pio data transfer %u @ %p\n", 2064 HDEVNAME(hp), len, data)); 2065 2066 data += len; 2067 datalen -= len; 2068 } 2069 2070 if (error == 0 && !sdhc_wait_intr(hp, SDHC_TRANSFER_COMPLETE, 2071 SDHC_TRANSFER_TIMEOUT, false)) { 2072 DPRINTF(1,("%s: timeout for transfer\n", __func__)); 2073 error = ETIMEDOUT; 2074 } 2075 2076 return error; 2077 } 2078 2079 static void 2080 sdhc_read_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 2081 { 2082 2083 if (((__uintptr_t)data & 3) == 0) { 2084 while (datalen > 3) { 2085 *(uint32_t *)data = le32toh(HREAD4(hp, SDHC_DATA)); 2086 data += 4; 2087 datalen -= 4; 2088 } 2089 if (datalen > 1) { 2090 *(uint16_t *)data = le16toh(HREAD2(hp, SDHC_DATA)); 2091 data += 2; 2092 datalen -= 2; 2093 } 2094 if (datalen > 0) { 2095 *data = HREAD1(hp, SDHC_DATA); 2096 data += 1; 2097 datalen -= 1; 2098 } 2099 } else if (((__uintptr_t)data & 1) == 0) { 2100 while (datalen > 1) { 2101 *(uint16_t *)data = le16toh(HREAD2(hp, SDHC_DATA)); 2102 data += 2; 2103 datalen -= 2; 2104 } 2105 if (datalen > 0) { 2106 *data = HREAD1(hp, SDHC_DATA); 2107 data += 1; 2108 datalen -= 1; 2109 } 2110 } else { 2111 while (datalen > 0) { 2112 *data = HREAD1(hp, SDHC_DATA); 2113 data += 1; 2114 datalen -= 1; 2115 } 2116 } 2117 } 2118 2119 static void 2120 sdhc_write_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 2121 { 2122 2123 if (((__uintptr_t)data & 3) == 0) { 2124 while (datalen > 3) { 2125 HWRITE4(hp, SDHC_DATA, htole32(*(uint32_t *)data)); 2126 data += 4; 2127 datalen -= 4; 2128 } 2129 if (datalen > 1) { 2130 HWRITE2(hp, SDHC_DATA, htole16(*(uint16_t *)data)); 2131 data += 2; 2132 datalen -= 2; 2133 } 2134 if (datalen > 0) { 2135 HWRITE1(hp, SDHC_DATA, *data); 2136 data += 1; 2137 datalen -= 1; 2138 } 2139 } else if (((__uintptr_t)data & 1) == 0) { 2140 while (datalen > 1) { 2141 HWRITE2(hp, SDHC_DATA, htole16(*(uint16_t *)data)); 2142 data += 2; 2143 datalen -= 2; 2144 } 2145 if (datalen > 0) { 2146 HWRITE1(hp, SDHC_DATA, *data); 2147 data += 1; 2148 datalen -= 1; 2149 } 2150 } else { 2151 while (datalen > 0) { 2152 HWRITE1(hp, SDHC_DATA, *data); 2153 data += 1; 2154 datalen -= 1; 2155 } 2156 } 2157 } 2158 2159 static void 2160 esdhc_read_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 2161 { 2162 uint16_t status = HREAD2(hp, SDHC_NINTR_STATUS); 2163 uint32_t v; 2164 2165 const size_t watermark = (HREAD4(hp, SDHC_WATERMARK_LEVEL) >> SDHC_WATERMARK_READ_SHIFT) & SDHC_WATERMARK_READ_MASK; 2166 size_t count = 0; 2167 2168 while (datalen > 3 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 2169 if (count == 0) { 2170 /* 2171 * If we've drained "watermark" words, we need to wait 2172 * a little bit so the read FIFO can refill. 2173 */ 2174 sdmmc_delay(10); 2175 count = watermark; 2176 } 2177 v = HREAD4(hp, SDHC_DATA); 2178 v = le32toh(v); 2179 *(uint32_t *)data = v; 2180 data += 4; 2181 datalen -= 4; 2182 status = HREAD2(hp, SDHC_NINTR_STATUS); 2183 count--; 2184 } 2185 if (datalen > 0 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 2186 if (count == 0) { 2187 sdmmc_delay(10); 2188 } 2189 v = HREAD4(hp, SDHC_DATA); 2190 v = le32toh(v); 2191 do { 2192 *data++ = v; 2193 v >>= 8; 2194 } while (--datalen > 0); 2195 } 2196 } 2197 2198 static void 2199 esdhc_write_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 2200 { 2201 uint16_t status = HREAD2(hp, SDHC_NINTR_STATUS); 2202 uint32_t v; 2203 2204 const size_t watermark = (HREAD4(hp, SDHC_WATERMARK_LEVEL) >> SDHC_WATERMARK_WRITE_SHIFT) & SDHC_WATERMARK_WRITE_MASK; 2205 size_t count = watermark; 2206 2207 while (datalen > 3 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 2208 if (count == 0) { 2209 sdmmc_delay(10); 2210 count = watermark; 2211 } 2212 v = *(uint32_t *)data; 2213 v = htole32(v); 2214 HWRITE4(hp, SDHC_DATA, v); 2215 data += 4; 2216 datalen -= 4; 2217 status = HREAD2(hp, SDHC_NINTR_STATUS); 2218 count--; 2219 } 2220 if (datalen > 0 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 2221 if (count == 0) { 2222 sdmmc_delay(10); 2223 } 2224 v = *(uint32_t *)data; 2225 v = htole32(v); 2226 HWRITE4(hp, SDHC_DATA, v); 2227 } 2228 } 2229 2230 /* Prepare for another command. */ 2231 static int 2232 sdhc_soft_reset(struct sdhc_host *hp, int mask) 2233 { 2234 int timo; 2235 2236 KASSERT(mutex_owned(&hp->intr_lock)); 2237 2238 DPRINTF(1,("%s: software reset reg=%08x\n", HDEVNAME(hp), mask)); 2239 2240 /* Request the reset. */ 2241 HWRITE1(hp, SDHC_SOFTWARE_RESET, mask); 2242 2243 /* 2244 * If necessary, wait for the controller to set the bits to 2245 * acknowledge the reset. 2246 */ 2247 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_WAIT_RESET) && 2248 ISSET(mask, (SDHC_RESET_DAT | SDHC_RESET_CMD))) { 2249 for (timo = 10000; timo > 0; timo--) { 2250 if (ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), mask)) 2251 break; 2252 /* Short delay because I worry we may miss it... */ 2253 sdmmc_delay(1); 2254 } 2255 if (timo == 0) { 2256 DPRINTF(1,("%s: timeout for reset on\n", __func__)); 2257 return ETIMEDOUT; 2258 } 2259 } 2260 2261 /* 2262 * Wait for the controller to clear the bits to indicate that 2263 * the reset has completed. 2264 */ 2265 for (timo = 10; timo > 0; timo--) { 2266 if (!ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), mask)) 2267 break; 2268 sdmmc_delay(10000); 2269 } 2270 if (timo == 0) { 2271 DPRINTF(1,("%s: timeout reg=%08x\n", HDEVNAME(hp), 2272 HREAD1(hp, SDHC_SOFTWARE_RESET))); 2273 return ETIMEDOUT; 2274 } 2275 2276 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 2277 HSET4(hp, SDHC_DMA_CTL, SDHC_DMA_SNOOP); 2278 } 2279 2280 return 0; 2281 } 2282 2283 static int 2284 sdhc_wait_intr(struct sdhc_host *hp, int mask, int timo, bool probing) 2285 { 2286 int status, error, nointr; 2287 2288 KASSERT(mutex_owned(&hp->intr_lock)); 2289 2290 mask |= SDHC_ERROR_INTERRUPT; 2291 2292 nointr = 0; 2293 status = hp->intr_status & mask; 2294 while (status == 0) { 2295 if (cv_timedwait(&hp->intr_cv, &hp->intr_lock, timo) 2296 == EWOULDBLOCK) { 2297 nointr = 1; 2298 break; 2299 } 2300 status = hp->intr_status & mask; 2301 } 2302 error = hp->intr_error_status; 2303 2304 DPRINTF(2,("%s: intr status %#x error %#x\n", HDEVNAME(hp), status, 2305 error)); 2306 2307 hp->intr_status &= ~status; 2308 hp->intr_error_status &= ~error; 2309 2310 if (ISSET(status, SDHC_ERROR_INTERRUPT)) { 2311 if (ISSET(error, SDHC_DMA_ERROR)) 2312 device_printf(hp->sc->sc_dev,"dma error\n"); 2313 if (ISSET(error, SDHC_ADMA_ERROR)) 2314 device_printf(hp->sc->sc_dev,"adma error\n"); 2315 if (ISSET(error, SDHC_AUTO_CMD12_ERROR)) 2316 device_printf(hp->sc->sc_dev,"auto_cmd12 error\n"); 2317 if (ISSET(error, SDHC_CURRENT_LIMIT_ERROR)) 2318 device_printf(hp->sc->sc_dev,"current limit error\n"); 2319 if (ISSET(error, SDHC_DATA_END_BIT_ERROR)) 2320 device_printf(hp->sc->sc_dev,"data end bit error\n"); 2321 if (ISSET(error, SDHC_DATA_CRC_ERROR)) 2322 device_printf(hp->sc->sc_dev,"data crc error\n"); 2323 if (ISSET(error, SDHC_DATA_TIMEOUT_ERROR)) 2324 device_printf(hp->sc->sc_dev,"data timeout error\n"); 2325 if (ISSET(error, SDHC_CMD_INDEX_ERROR)) 2326 device_printf(hp->sc->sc_dev,"cmd index error\n"); 2327 if (ISSET(error, SDHC_CMD_END_BIT_ERROR)) 2328 device_printf(hp->sc->sc_dev,"cmd end bit error\n"); 2329 if (ISSET(error, SDHC_CMD_CRC_ERROR)) 2330 device_printf(hp->sc->sc_dev,"cmd crc error\n"); 2331 if (ISSET(error, SDHC_CMD_TIMEOUT_ERROR)) { 2332 if (!probing) 2333 device_printf(hp->sc->sc_dev,"cmd timeout error\n"); 2334 #ifdef SDHC_DEBUG 2335 else if (sdhcdebug > 0) 2336 device_printf(hp->sc->sc_dev,"cmd timeout (expected)\n"); 2337 #endif 2338 } 2339 if ((error & ~SDHC_EINTR_STATUS_MASK) != 0) 2340 device_printf(hp->sc->sc_dev,"vendor error %#x\n", 2341 (error & ~SDHC_EINTR_STATUS_MASK)); 2342 if (error == 0) 2343 device_printf(hp->sc->sc_dev,"no error\n"); 2344 2345 /* Command timeout has higher priority than command complete. */ 2346 if (ISSET(error, SDHC_CMD_TIMEOUT_ERROR)) 2347 CLR(status, SDHC_COMMAND_COMPLETE); 2348 2349 /* Transfer complete has higher priority than data timeout. */ 2350 if (ISSET(status, SDHC_TRANSFER_COMPLETE)) 2351 CLR(error, SDHC_DATA_TIMEOUT_ERROR); 2352 } 2353 2354 if (nointr || 2355 (ISSET(status, SDHC_ERROR_INTERRUPT) && error)) { 2356 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 2357 (void)sdhc_soft_reset(hp, SDHC_RESET_CMD|SDHC_RESET_DAT); 2358 hp->intr_error_status = 0; 2359 status = 0; 2360 } 2361 2362 return status; 2363 } 2364 2365 /* 2366 * Established by attachment driver at interrupt priority IPL_SDMMC. 2367 */ 2368 int 2369 sdhc_intr(void *arg) 2370 { 2371 struct sdhc_softc *sc = (struct sdhc_softc *)arg; 2372 struct sdhc_host *hp; 2373 int done = 0; 2374 uint16_t status; 2375 uint16_t error; 2376 2377 /* We got an interrupt, but we don't know from which slot. */ 2378 for (size_t host = 0; host < sc->sc_nhosts; host++) { 2379 hp = sc->sc_host[host]; 2380 if (hp == NULL) 2381 continue; 2382 2383 mutex_enter(&hp->intr_lock); 2384 2385 if (ISSET(sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 2386 /* Find out which interrupts are pending. */ 2387 uint32_t xstatus = HREAD4(hp, SDHC_NINTR_STATUS); 2388 status = xstatus; 2389 error = xstatus >> 16; 2390 if (ISSET(sc->sc_flags, SDHC_FLAG_USDHC) && 2391 (xstatus & SDHC_TRANSFER_COMPLETE) && 2392 !(xstatus & SDHC_DMA_INTERRUPT)) { 2393 /* read again due to uSDHC errata */ 2394 status = xstatus = HREAD4(hp, 2395 SDHC_NINTR_STATUS); 2396 error = xstatus >> 16; 2397 } 2398 if (ISSET(sc->sc_flags, 2399 SDHC_FLAG_ENHANCED | SDHC_FLAG_USDHC)) { 2400 if ((error & SDHC_NINTR_STATUS_MASK) != 0) 2401 SET(status, SDHC_ERROR_INTERRUPT); 2402 } 2403 if (error) 2404 xstatus |= SDHC_ERROR_INTERRUPT; 2405 else if (!ISSET(status, SDHC_NINTR_STATUS_MASK)) 2406 goto next_port; /* no interrupt for us */ 2407 /* Acknowledge the interrupts we are about to handle. */ 2408 HWRITE4(hp, SDHC_NINTR_STATUS, xstatus); 2409 } else { 2410 /* Find out which interrupts are pending. */ 2411 error = 0; 2412 status = HREAD2(hp, SDHC_NINTR_STATUS); 2413 if (!ISSET(status, SDHC_NINTR_STATUS_MASK)) 2414 goto next_port; /* no interrupt for us */ 2415 /* Acknowledge the interrupts we are about to handle. */ 2416 HWRITE2(hp, SDHC_NINTR_STATUS, status); 2417 if (ISSET(status, SDHC_ERROR_INTERRUPT)) { 2418 /* Acknowledge error interrupts. */ 2419 error = HREAD2(hp, SDHC_EINTR_STATUS); 2420 HWRITE2(hp, SDHC_EINTR_STATUS, error); 2421 } 2422 } 2423 2424 DPRINTF(2,("%s: interrupt status=%x error=%x\n", HDEVNAME(hp), 2425 status, error)); 2426 2427 /* Claim this interrupt. */ 2428 done = 1; 2429 2430 if (ISSET(status, SDHC_ERROR_INTERRUPT) && 2431 ISSET(error, SDHC_ADMA_ERROR)) { 2432 uint8_t adma_err = HREAD1(hp, SDHC_ADMA_ERROR_STATUS); 2433 printf("%s: ADMA error, status %02x\n", HDEVNAME(hp), 2434 adma_err); 2435 } 2436 2437 /* 2438 * Wake up the sdmmc event thread to scan for cards. 2439 */ 2440 if (ISSET(status, SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)) { 2441 if (hp->sdmmc != NULL) { 2442 sdmmc_needs_discover(hp->sdmmc); 2443 } 2444 if (ISSET(sc->sc_flags, 2445 SDHC_FLAG_ENHANCED | SDHC_FLAG_USDHC)) { 2446 HCLR4(hp, SDHC_NINTR_STATUS_EN, 2447 status & (SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)); 2448 HCLR4(hp, SDHC_NINTR_SIGNAL_EN, 2449 status & (SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)); 2450 } 2451 } 2452 2453 /* 2454 * Schedule re-tuning process (UHS). 2455 */ 2456 if (ISSET(status, SDHC_RETUNING_EVENT)) { 2457 atomic_swap_uint(&hp->tuning_timer_pending, 1); 2458 } 2459 2460 /* 2461 * Wake up the blocking process to service command 2462 * related interrupt(s). 2463 */ 2464 if (ISSET(status, SDHC_COMMAND_COMPLETE|SDHC_ERROR_INTERRUPT| 2465 SDHC_BUFFER_READ_READY|SDHC_BUFFER_WRITE_READY| 2466 SDHC_TRANSFER_COMPLETE|SDHC_DMA_INTERRUPT)) { 2467 hp->intr_error_status |= error; 2468 hp->intr_status |= status; 2469 if (ISSET(sc->sc_flags, 2470 SDHC_FLAG_ENHANCED | SDHC_FLAG_USDHC)) { 2471 HCLR4(hp, SDHC_NINTR_SIGNAL_EN, 2472 status & (SDHC_BUFFER_READ_READY|SDHC_BUFFER_WRITE_READY)); 2473 } 2474 cv_broadcast(&hp->intr_cv); 2475 } 2476 2477 /* 2478 * Service SD card interrupts. 2479 */ 2480 if (!ISSET(sc->sc_flags, SDHC_FLAG_ENHANCED | SDHC_FLAG_USDHC) 2481 && ISSET(status, SDHC_CARD_INTERRUPT)) { 2482 DPRINTF(0,("%s: card interrupt\n", HDEVNAME(hp))); 2483 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 2484 sdmmc_card_intr(hp->sdmmc); 2485 } 2486 next_port: 2487 mutex_exit(&hp->intr_lock); 2488 } 2489 2490 return done; 2491 } 2492 2493 kmutex_t * 2494 sdhc_host_lock(struct sdhc_host *hp) 2495 { 2496 return &hp->intr_lock; 2497 } 2498 2499 uint8_t 2500 sdhc_host_read_1(struct sdhc_host *hp, int reg) 2501 { 2502 return HREAD1(hp, reg); 2503 } 2504 2505 uint16_t 2506 sdhc_host_read_2(struct sdhc_host *hp, int reg) 2507 { 2508 return HREAD2(hp, reg); 2509 } 2510 2511 uint32_t 2512 sdhc_host_read_4(struct sdhc_host *hp, int reg) 2513 { 2514 return HREAD4(hp, reg); 2515 } 2516 2517 void 2518 sdhc_host_write_1(struct sdhc_host *hp, int reg, uint8_t val) 2519 { 2520 HWRITE1(hp, reg, val); 2521 } 2522 2523 void 2524 sdhc_host_write_2(struct sdhc_host *hp, int reg, uint16_t val) 2525 { 2526 HWRITE2(hp, reg, val); 2527 } 2528 2529 void 2530 sdhc_host_write_4(struct sdhc_host *hp, int reg, uint32_t val) 2531 { 2532 HWRITE4(hp, reg, val); 2533 } 2534 2535 #ifdef SDHC_DEBUG 2536 void 2537 sdhc_dump_regs(struct sdhc_host *hp) 2538 { 2539 2540 printf("0x%02x PRESENT_STATE: %x\n", SDHC_PRESENT_STATE, 2541 HREAD4(hp, SDHC_PRESENT_STATE)); 2542 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 2543 printf("0x%02x POWER_CTL: %x\n", SDHC_POWER_CTL, 2544 HREAD1(hp, SDHC_POWER_CTL)); 2545 printf("0x%02x NINTR_STATUS: %x\n", SDHC_NINTR_STATUS, 2546 HREAD2(hp, SDHC_NINTR_STATUS)); 2547 printf("0x%02x EINTR_STATUS: %x\n", SDHC_EINTR_STATUS, 2548 HREAD2(hp, SDHC_EINTR_STATUS)); 2549 printf("0x%02x NINTR_STATUS_EN: %x\n", SDHC_NINTR_STATUS_EN, 2550 HREAD2(hp, SDHC_NINTR_STATUS_EN)); 2551 printf("0x%02x EINTR_STATUS_EN: %x\n", SDHC_EINTR_STATUS_EN, 2552 HREAD2(hp, SDHC_EINTR_STATUS_EN)); 2553 printf("0x%02x NINTR_SIGNAL_EN: %x\n", SDHC_NINTR_SIGNAL_EN, 2554 HREAD2(hp, SDHC_NINTR_SIGNAL_EN)); 2555 printf("0x%02x EINTR_SIGNAL_EN: %x\n", SDHC_EINTR_SIGNAL_EN, 2556 HREAD2(hp, SDHC_EINTR_SIGNAL_EN)); 2557 printf("0x%02x CAPABILITIES: %x\n", SDHC_CAPABILITIES, 2558 HREAD4(hp, SDHC_CAPABILITIES)); 2559 printf("0x%02x MAX_CAPABILITIES: %x\n", SDHC_MAX_CAPABILITIES, 2560 HREAD4(hp, SDHC_MAX_CAPABILITIES)); 2561 } 2562 #endif 2563
Indexes created Sun Sep 28 16:09:52 GMT 2025