sdhc.c revision 1.18
1 /* $NetBSD: sdhc.c,v 1.18 2012/07/12 17:15:27 jakllsch Exp $ */ 2 /* $OpenBSD: sdhc.c,v 1.25 2009/01/13 19:44:20 grange Exp $ */ 3 4 /* 5 * Copyright (c) 2006 Uwe Stuehler <uwe (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * SD Host Controller driver based on the SD Host Controller Standard 22 * Simplified Specification Version 1.00 (www.sdcard.com). 23 */ 24 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: sdhc.c,v 1.18 2012/07/12 17:15:27 jakllsch Exp $"); 27 28 #ifdef _KERNEL_OPT 29 #include "opt_sdmmc.h" 30 #endif 31 32 #include <sys/param.h> 33 #include <sys/device.h> 34 #include <sys/kernel.h> 35 #include <sys/kthread.h> 36 #include <sys/malloc.h> 37 #include <sys/systm.h> 38 #include <sys/mutex.h> 39 #include <sys/condvar.h> 40 41 #include <dev/sdmmc/sdhcreg.h> 42 #include <dev/sdmmc/sdhcvar.h> 43 #include <dev/sdmmc/sdmmcchip.h> 44 #include <dev/sdmmc/sdmmcreg.h> 45 #include <dev/sdmmc/sdmmcvar.h> 46 47 #ifdef SDHC_DEBUG 48 int sdhcdebug = 1; 49 #define DPRINTF(n,s) do { if ((n) <= sdhcdebug) printf s; } while (0) 50 void sdhc_dump_regs(struct sdhc_host *); 51 #else 52 #define DPRINTF(n,s) do {} while (0) 53 #endif 54 55 #define SDHC_COMMAND_TIMEOUT hz 56 #define SDHC_BUFFER_TIMEOUT hz 57 #define SDHC_TRANSFER_TIMEOUT hz 58 #define SDHC_DMA_TIMEOUT hz 59 60 struct sdhc_host { 61 struct sdhc_softc *sc; /* host controller device */ 62 63 bus_space_tag_t iot; /* host register set tag */ 64 bus_space_handle_t ioh; /* host register set handle */ 65 bus_dma_tag_t dmat; /* host DMA tag */ 66 67 device_t sdmmc; /* generic SD/MMC device */ 68 69 struct kmutex host_mtx; 70 71 u_int clkbase; /* base clock frequency in KHz */ 72 int maxblklen; /* maximum block length */ 73 uint32_t ocr; /* OCR value from capabilities */ 74 75 uint8_t regs[14]; /* host controller state */ 76 77 uint16_t intr_status; /* soft interrupt status */ 78 uint16_t intr_error_status; /* soft error status */ 79 struct kmutex intr_mtx; 80 struct kcondvar intr_cv; 81 82 int specver; /* spec. version */ 83 84 uint32_t flags; /* flags for this host */ 85 #define SHF_USE_DMA 0x0001 86 #define SHF_USE_4BIT_MODE 0x0002 87 #define SHF_USE_8BIT_MODE 0x0004 88 }; 89 90 #define HDEVNAME(hp) (device_xname((hp)->sc->sc_dev)) 91 #define HDEVINST(hp) ((int)(((hp)-(hp)->sc->sc_host[0])/sizeof(*(hp)))) 92 93 static uint8_t 94 hread1(struct sdhc_host *hp, bus_size_t reg) 95 { 96 97 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) 98 return bus_space_read_1(hp->iot, hp->ioh, reg); 99 return bus_space_read_4(hp->iot, hp->ioh, reg & -4) >> (8 * (reg & 3)); 100 } 101 102 static uint16_t 103 hread2(struct sdhc_host *hp, bus_size_t reg) 104 { 105 106 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) 107 return bus_space_read_2(hp->iot, hp->ioh, reg); 108 return bus_space_read_4(hp->iot, hp->ioh, reg & -4) >> (8 * (reg & 2)); 109 } 110 111 #define HREAD1(hp, reg) hread1(hp, reg) 112 #define HREAD2(hp, reg) hread2(hp, reg) 113 #define HREAD4(hp, reg) \ 114 (bus_space_read_4((hp)->iot, (hp)->ioh, (reg))) 115 116 117 static void 118 hwrite1(struct sdhc_host *hp, bus_size_t o, uint8_t val) 119 { 120 121 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 122 bus_space_write_1(hp->iot, hp->ioh, o, val); 123 } else { 124 const size_t shift = 8 * (o & 3); 125 o &= -4; 126 uint32_t tmp = bus_space_read_4(hp->iot, hp->ioh, o); 127 tmp = (val << shift) | (tmp & ~(0xff << shift)); 128 bus_space_write_4(hp->iot, hp->ioh, o, tmp); 129 } 130 } 131 132 static void 133 hwrite2(struct sdhc_host *hp, bus_size_t o, uint16_t val) 134 { 135 136 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 137 bus_space_write_2(hp->iot, hp->ioh, o, val); 138 } else { 139 const size_t shift = 8 * (o & 2); 140 o &= -4; 141 uint32_t tmp = bus_space_read_4(hp->iot, hp->ioh, o); 142 tmp = (val << shift) | (tmp & ~(0xffff << shift)); 143 bus_space_write_4(hp->iot, hp->ioh, o, tmp); 144 } 145 } 146 147 #define HWRITE1(hp, reg, val) hwrite1(hp, reg, val) 148 #define HWRITE2(hp, reg, val) hwrite2(hp, reg, val) 149 #define HWRITE4(hp, reg, val) \ 150 bus_space_write_4((hp)->iot, (hp)->ioh, (reg), (val)) 151 152 #define HCLR1(hp, reg, bits) \ 153 do if (bits) HWRITE1((hp), (reg), HREAD1((hp), (reg)) & ~(bits)); while (0) 154 #define HCLR2(hp, reg, bits) \ 155 do if (bits) HWRITE2((hp), (reg), HREAD2((hp), (reg)) & ~(bits)); while (0) 156 #define HCLR4(hp, reg, bits) \ 157 do if (bits) HWRITE4((hp), (reg), HREAD4((hp), (reg)) & ~(bits)); while (0) 158 #define HSET1(hp, reg, bits) \ 159 do if (bits) HWRITE1((hp), (reg), HREAD1((hp), (reg)) | (bits)); while (0) 160 #define HSET2(hp, reg, bits) \ 161 do if (bits) HWRITE2((hp), (reg), HREAD2((hp), (reg)) | (bits)); while (0) 162 #define HSET4(hp, reg, bits) \ 163 do if (bits) HWRITE4((hp), (reg), HREAD4((hp), (reg)) | (bits)); while (0) 164 165 static int sdhc_host_reset(sdmmc_chipset_handle_t); 166 static int sdhc_host_reset1(sdmmc_chipset_handle_t); 167 static uint32_t sdhc_host_ocr(sdmmc_chipset_handle_t); 168 static int sdhc_host_maxblklen(sdmmc_chipset_handle_t); 169 static int sdhc_card_detect(sdmmc_chipset_handle_t); 170 static int sdhc_write_protect(sdmmc_chipset_handle_t); 171 static int sdhc_bus_power(sdmmc_chipset_handle_t, uint32_t); 172 static int sdhc_bus_clock(sdmmc_chipset_handle_t, int); 173 static int sdhc_bus_width(sdmmc_chipset_handle_t, int); 174 static int sdhc_bus_rod(sdmmc_chipset_handle_t, int); 175 static void sdhc_card_enable_intr(sdmmc_chipset_handle_t, int); 176 static void sdhc_card_intr_ack(sdmmc_chipset_handle_t); 177 static void sdhc_exec_command(sdmmc_chipset_handle_t, 178 struct sdmmc_command *); 179 static int sdhc_start_command(struct sdhc_host *, struct sdmmc_command *); 180 static int sdhc_wait_state(struct sdhc_host *, uint32_t, uint32_t); 181 static int sdhc_soft_reset(struct sdhc_host *, int); 182 static int sdhc_wait_intr(struct sdhc_host *, int, int); 183 static void sdhc_transfer_data(struct sdhc_host *, struct sdmmc_command *); 184 static int sdhc_transfer_data_dma(struct sdhc_host *, struct sdmmc_command *); 185 static int sdhc_transfer_data_pio(struct sdhc_host *, struct sdmmc_command *); 186 static void sdhc_read_data_pio(struct sdhc_host *, uint8_t *, u_int); 187 static void sdhc_write_data_pio(struct sdhc_host *, uint8_t *, u_int); 188 static void esdhc_read_data_pio(struct sdhc_host *, uint8_t *, u_int); 189 static void esdhc_write_data_pio(struct sdhc_host *, uint8_t *, u_int); 190 191 192 static struct sdmmc_chip_functions sdhc_functions = { 193 /* host controller reset */ 194 sdhc_host_reset, 195 196 /* host controller capabilities */ 197 sdhc_host_ocr, 198 sdhc_host_maxblklen, 199 200 /* card detection */ 201 sdhc_card_detect, 202 203 /* write protect */ 204 sdhc_write_protect, 205 206 /* bus power, clock frequency and width */ 207 sdhc_bus_power, 208 sdhc_bus_clock, 209 sdhc_bus_width, 210 sdhc_bus_rod, 211 212 /* command execution */ 213 sdhc_exec_command, 214 215 /* card interrupt */ 216 sdhc_card_enable_intr, 217 sdhc_card_intr_ack 218 }; 219 220 static int 221 sdhc_cfprint(void *aux, const char *pnp) 222 { 223 const struct sdmmcbus_attach_args const * saa = aux; 224 const struct sdhc_host * const hp = saa->saa_sch; 225 226 if (pnp) { 227 aprint_normal("sdmmc at %s", pnp); 228 } 229 aprint_normal(" slot %d", HDEVINST(hp)); 230 231 return UNCONF; 232 } 233 234 /* 235 * Called by attachment driver. For each SD card slot there is one SD 236 * host controller standard register set. (1.3) 237 */ 238 int 239 sdhc_host_found(struct sdhc_softc *sc, bus_space_tag_t iot, 240 bus_space_handle_t ioh, bus_size_t iosize) 241 { 242 struct sdmmcbus_attach_args saa; 243 struct sdhc_host *hp; 244 uint32_t caps; 245 uint16_t sdhcver; 246 247 sdhcver = bus_space_read_2(iot, ioh, SDHC_HOST_CTL_VERSION); 248 aprint_normal_dev(sc->sc_dev, "SD Host Specification "); 249 switch (SDHC_SPEC_VERSION(sdhcver)) { 250 case SDHC_SPEC_VERS_100: 251 aprint_normal("1.0"); 252 break; 253 254 case SDHC_SPEC_VERS_200: 255 aprint_normal("2.0"); 256 break; 257 258 case SDHC_SPEC_VERS_300: 259 aprint_normal("3.0"); 260 break; 261 262 default: 263 aprint_normal("unknown version(0x%x)", 264 SDHC_SPEC_VERSION(sdhcver)); 265 break; 266 } 267 aprint_normal(", rev.%u\n", SDHC_VENDOR_VERSION(sdhcver)); 268 269 /* Allocate one more host structure. */ 270 hp = malloc(sizeof(struct sdhc_host), M_DEVBUF, M_WAITOK|M_ZERO); 271 if (hp == NULL) { 272 aprint_error_dev(sc->sc_dev, 273 "couldn't alloc memory (sdhc host)\n"); 274 goto err1; 275 } 276 sc->sc_host[sc->sc_nhosts++] = hp; 277 278 /* Fill in the new host structure. */ 279 hp->sc = sc; 280 hp->iot = iot; 281 hp->ioh = ioh; 282 hp->dmat = sc->sc_dmat; 283 hp->specver = SDHC_SPEC_VERSION(sdhcver); 284 285 mutex_init(&hp->host_mtx, MUTEX_DEFAULT, IPL_SDMMC); 286 mutex_init(&hp->intr_mtx, MUTEX_DEFAULT, IPL_SDMMC); 287 cv_init(&hp->intr_cv, "sdhcintr"); 288 289 /* 290 * Reset the host controller and enable interrupts. 291 */ 292 (void)sdhc_host_reset(hp); 293 294 /* Determine host capabilities. */ 295 mutex_enter(&hp->host_mtx); 296 caps = HREAD4(hp, SDHC_CAPABILITIES); 297 mutex_exit(&hp->host_mtx); 298 299 #if notyet 300 /* Use DMA if the host system and the controller support it. */ 301 if (ISSET(sc->sc_flags, SDHC_FLAG_FORCE_DMA) 302 || ((ISSET(sc->sc_flags, SDHC_FLAG_USE_DMA) 303 && ISSET(caps, SDHC_DMA_SUPPORT)))) { 304 SET(hp->flags, SHF_USE_DMA); 305 aprint_normal_dev(sc->sc_dev, "using DMA transfer\n"); 306 } 307 #endif 308 309 /* 310 * Determine the base clock frequency. (2.2.24) 311 */ 312 hp->clkbase = SDHC_BASE_FREQ_KHZ(caps); 313 if (hp->clkbase == 0) { 314 if (sc->sc_clkbase == 0) { 315 /* The attachment driver must tell us. */ 316 aprint_error_dev(sc->sc_dev, 317 "unknown base clock frequency\n"); 318 goto err; 319 } 320 hp->clkbase = sc->sc_clkbase; 321 } 322 if (hp->clkbase < 10000 || hp->clkbase > 10000 * 256) { 323 /* SDHC 1.0 supports only 10-63 MHz. */ 324 aprint_error_dev(sc->sc_dev, 325 "base clock frequency out of range: %u MHz\n", 326 hp->clkbase / 1000); 327 goto err; 328 } 329 DPRINTF(1,("%s: base clock frequency %u MHz\n", 330 device_xname(sc->sc_dev), hp->clkbase / 1000)); 331 332 /* 333 * XXX Set the data timeout counter value according to 334 * capabilities. (2.2.15) 335 */ 336 HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX); 337 #if 0 338 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 339 HWRITE4(hp, SDHC_NINTR_STATUS, SDHC_CMD_TIMEOUT_ERROR << 16); 340 #endif 341 342 /* 343 * Determine SD bus voltage levels supported by the controller. 344 */ 345 if (ISSET(caps, SDHC_VOLTAGE_SUPP_1_8V)) { 346 SET(hp->ocr, MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V); 347 } 348 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_0V)) { 349 SET(hp->ocr, MMC_OCR_2_9V_3_0V | MMC_OCR_3_0V_3_1V); 350 } 351 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_3V)) { 352 SET(hp->ocr, MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V); 353 } 354 355 /* 356 * Determine the maximum block length supported by the host 357 * controller. (2.2.24) 358 */ 359 switch((caps >> SDHC_MAX_BLK_LEN_SHIFT) & SDHC_MAX_BLK_LEN_MASK) { 360 case SDHC_MAX_BLK_LEN_512: 361 hp->maxblklen = 512; 362 break; 363 364 case SDHC_MAX_BLK_LEN_1024: 365 hp->maxblklen = 1024; 366 break; 367 368 case SDHC_MAX_BLK_LEN_2048: 369 hp->maxblklen = 2048; 370 break; 371 372 case SDHC_MAX_BLK_LEN_4096: 373 hp->maxblklen = 4096; 374 break; 375 376 default: 377 aprint_error_dev(sc->sc_dev, "max block length unknown\n"); 378 goto err; 379 } 380 DPRINTF(1, ("%s: max block length %u byte%s\n", 381 device_xname(sc->sc_dev), hp->maxblklen, 382 hp->maxblklen > 1 ? "s" : "")); 383 384 /* 385 * Attach the generic SD/MMC bus driver. (The bus driver must 386 * not invoke any chipset functions before it is attached.) 387 */ 388 memset(&saa, 0, sizeof(saa)); 389 saa.saa_busname = "sdmmc"; 390 saa.saa_sct = &sdhc_functions; 391 saa.saa_sch = hp; 392 saa.saa_dmat = hp->dmat; 393 saa.saa_clkmin = hp->clkbase / 256; 394 saa.saa_clkmax = hp->clkbase; 395 if (ISSET(sc->sc_flags, SDHC_FLAG_HAVE_CGM)) 396 saa.saa_clkmin /= 2046; 397 else if (ISSET(sc->sc_flags, SDHC_FLAG_HAVE_DVS)) 398 saa.saa_clkmin /= 16; 399 saa.saa_caps = SMC_CAPS_4BIT_MODE|SMC_CAPS_AUTO_STOP; 400 if (ISSET(sc->sc_flags, SDHC_FLAG_8BIT_MODE)) 401 saa.saa_caps |= SMC_CAPS_8BIT_MODE; 402 if (ISSET(caps, SDHC_HIGH_SPEED_SUPP)) 403 saa.saa_caps |= SMC_CAPS_SD_HIGHSPEED; 404 #if notyet 405 if (ISSET(hp->flags, SHF_USE_DMA)) 406 saa.saa_caps |= SMC_CAPS_DMA; 407 #endif 408 hp->sdmmc = config_found(sc->sc_dev, &saa, sdhc_cfprint); 409 410 return 0; 411 412 err: 413 cv_destroy(&hp->intr_cv); 414 mutex_destroy(&hp->intr_mtx); 415 mutex_destroy(&hp->host_mtx); 416 free(hp, M_DEVBUF); 417 sc->sc_host[--sc->sc_nhosts] = NULL; 418 err1: 419 return 1; 420 } 421 422 int 423 sdhc_detach(device_t dev, int flags) 424 { 425 struct sdhc_host *hp = (struct sdhc_host *)dev; 426 struct sdhc_softc *sc = hp->sc; 427 int rv = 0; 428 429 if (hp->sdmmc) 430 rv = config_detach(hp->sdmmc, flags); 431 432 cv_destroy(&hp->intr_cv); 433 mutex_destroy(&hp->intr_mtx); 434 mutex_destroy(&hp->host_mtx); 435 free(hp, M_DEVBUF); 436 sc->sc_host[--sc->sc_nhosts] = NULL; 437 438 return rv; 439 } 440 441 bool 442 sdhc_suspend(device_t dev, const pmf_qual_t *qual) 443 { 444 struct sdhc_softc *sc = device_private(dev); 445 struct sdhc_host *hp; 446 size_t i; 447 448 /* XXX poll for command completion or suspend command 449 * in progress */ 450 451 /* Save the host controller state. */ 452 for (size_t n = 0; n < sc->sc_nhosts; n++) { 453 hp = sc->sc_host[n]; 454 if (ISSET(sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 455 for (i = 0; i < sizeof hp->regs; i += 4) { 456 uint32_t v = HREAD4(hp, i); 457 hp->regs[i + 0] = (v >> 0); 458 hp->regs[i + 1] = (v >> 8); 459 if (i + 3 < sizeof hp->regs) { 460 hp->regs[i + 2] = (v >> 16); 461 hp->regs[i + 3] = (v >> 24); 462 } 463 } 464 } else { 465 for (i = 0; i < sizeof hp->regs; i++) { 466 hp->regs[i] = HREAD1(hp, i); 467 } 468 } 469 } 470 return true; 471 } 472 473 bool 474 sdhc_resume(device_t dev, const pmf_qual_t *qual) 475 { 476 struct sdhc_softc *sc = device_private(dev); 477 struct sdhc_host *hp; 478 size_t i; 479 480 /* Restore the host controller state. */ 481 for (size_t n = 0; n < sc->sc_nhosts; n++) { 482 hp = sc->sc_host[n]; 483 (void)sdhc_host_reset(hp); 484 if (ISSET(sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 485 for (i = 0; i < sizeof hp->regs; i += 4) { 486 if (i + 3 < sizeof hp->regs) { 487 HWRITE4(hp, i, 488 (hp->regs[i + 0] << 0) 489 | (hp->regs[i + 1] << 8) 490 | (hp->regs[i + 2] << 16) 491 | (hp->regs[i + 3] << 24)); 492 } else { 493 HWRITE4(hp, i, 494 (hp->regs[i + 0] << 0) 495 | (hp->regs[i + 1] << 8)); 496 } 497 } 498 } else { 499 for (i = 0; i < sizeof hp->regs; i++) { 500 HWRITE1(hp, i, hp->regs[i]); 501 } 502 } 503 } 504 return true; 505 } 506 507 bool 508 sdhc_shutdown(device_t dev, int flags) 509 { 510 struct sdhc_softc *sc = device_private(dev); 511 struct sdhc_host *hp; 512 513 /* XXX chip locks up if we don't disable it before reboot. */ 514 for (size_t i = 0; i < sc->sc_nhosts; i++) { 515 hp = sc->sc_host[i]; 516 (void)sdhc_host_reset(hp); 517 } 518 return true; 519 } 520 521 /* 522 * Reset the host controller. Called during initialization, when 523 * cards are removed, upon resume, and during error recovery. 524 */ 525 static int 526 sdhc_host_reset1(sdmmc_chipset_handle_t sch) 527 { 528 struct sdhc_host *hp = (struct sdhc_host *)sch; 529 uint32_t sdhcimask; 530 int error; 531 532 /* Don't lock. */ 533 534 /* Disable all interrupts. */ 535 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 536 HWRITE4(hp, SDHC_NINTR_SIGNAL_EN, 0); 537 } else { 538 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, 0); 539 } 540 541 /* 542 * Reset the entire host controller and wait up to 100ms for 543 * the controller to clear the reset bit. 544 */ 545 error = sdhc_soft_reset(hp, SDHC_RESET_ALL); 546 if (error) 547 goto out; 548 549 /* Set data timeout counter value to max for now. */ 550 HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX); 551 #if 0 552 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 553 HWRITE4(hp, SDHC_NINTR_STATUS, SDHC_CMD_TIMEOUT_ERROR << 16); 554 #endif 555 556 /* Enable interrupts. */ 557 sdhcimask = SDHC_CARD_REMOVAL | SDHC_CARD_INSERTION | 558 SDHC_BUFFER_READ_READY | SDHC_BUFFER_WRITE_READY | 559 SDHC_DMA_INTERRUPT | SDHC_BLOCK_GAP_EVENT | 560 SDHC_TRANSFER_COMPLETE | SDHC_COMMAND_COMPLETE; 561 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 562 sdhcimask |= SDHC_EINTR_STATUS_MASK << 16; 563 HWRITE4(hp, SDHC_NINTR_STATUS_EN, sdhcimask); 564 sdhcimask ^= 565 (SDHC_EINTR_STATUS_MASK ^ SDHC_EINTR_SIGNAL_MASK) << 16; 566 sdhcimask ^= SDHC_BUFFER_READ_READY ^ SDHC_BUFFER_WRITE_READY; 567 HWRITE4(hp, SDHC_NINTR_SIGNAL_EN, sdhcimask); 568 } else { 569 HWRITE2(hp, SDHC_NINTR_STATUS_EN, sdhcimask); 570 HWRITE2(hp, SDHC_EINTR_STATUS_EN, SDHC_EINTR_STATUS_MASK); 571 sdhcimask ^= SDHC_BUFFER_READ_READY ^ SDHC_BUFFER_WRITE_READY; 572 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, sdhcimask); 573 HWRITE2(hp, SDHC_EINTR_SIGNAL_EN, SDHC_EINTR_SIGNAL_MASK); 574 } 575 576 out: 577 return error; 578 } 579 580 static int 581 sdhc_host_reset(sdmmc_chipset_handle_t sch) 582 { 583 struct sdhc_host *hp = (struct sdhc_host *)sch; 584 int error; 585 586 mutex_enter(&hp->host_mtx); 587 error = sdhc_host_reset1(sch); 588 mutex_exit(&hp->host_mtx); 589 590 return error; 591 } 592 593 static uint32_t 594 sdhc_host_ocr(sdmmc_chipset_handle_t sch) 595 { 596 struct sdhc_host *hp = (struct sdhc_host *)sch; 597 598 return hp->ocr; 599 } 600 601 static int 602 sdhc_host_maxblklen(sdmmc_chipset_handle_t sch) 603 { 604 struct sdhc_host *hp = (struct sdhc_host *)sch; 605 606 return hp->maxblklen; 607 } 608 609 /* 610 * Return non-zero if the card is currently inserted. 611 */ 612 static int 613 sdhc_card_detect(sdmmc_chipset_handle_t sch) 614 { 615 struct sdhc_host *hp = (struct sdhc_host *)sch; 616 int r; 617 618 mutex_enter(&hp->host_mtx); 619 r = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CARD_INSERTED); 620 mutex_exit(&hp->host_mtx); 621 622 return r ? 1 : 0; 623 } 624 625 /* 626 * Return non-zero if the card is currently write-protected. 627 */ 628 static int 629 sdhc_write_protect(sdmmc_chipset_handle_t sch) 630 { 631 struct sdhc_host *hp = (struct sdhc_host *)sch; 632 int r; 633 634 mutex_enter(&hp->host_mtx); 635 r = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_WRITE_PROTECT_SWITCH); 636 mutex_exit(&hp->host_mtx); 637 638 return r ? 0 : 1; 639 } 640 641 /* 642 * Set or change SD bus voltage and enable or disable SD bus power. 643 * Return zero on success. 644 */ 645 static int 646 sdhc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 647 { 648 struct sdhc_host *hp = (struct sdhc_host *)sch; 649 uint8_t vdd; 650 int error = 0; 651 652 mutex_enter(&hp->host_mtx); 653 654 /* 655 * Disable bus power before voltage change. 656 */ 657 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS) 658 && !ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_PWR0)) 659 HWRITE1(hp, SDHC_POWER_CTL, 0); 660 661 /* If power is disabled, reset the host and return now. */ 662 if (ocr == 0) { 663 (void)sdhc_host_reset1(hp); 664 goto out; 665 } 666 667 /* 668 * Select the lowest voltage according to capabilities. 669 */ 670 ocr &= hp->ocr; 671 if (ISSET(ocr, MMC_OCR_1_7V_1_8V|MMC_OCR_1_8V_1_9V)) { 672 vdd = SDHC_VOLTAGE_1_8V; 673 } else if (ISSET(ocr, MMC_OCR_2_9V_3_0V|MMC_OCR_3_0V_3_1V)) { 674 vdd = SDHC_VOLTAGE_3_0V; 675 } else if (ISSET(ocr, MMC_OCR_3_2V_3_3V|MMC_OCR_3_3V_3_4V)) { 676 vdd = SDHC_VOLTAGE_3_3V; 677 } else { 678 /* Unsupported voltage level requested. */ 679 error = EINVAL; 680 goto out; 681 } 682 683 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 684 /* 685 * Enable bus power. Wait at least 1 ms (or 74 clocks) plus 686 * voltage ramp until power rises. 687 */ 688 HWRITE1(hp, SDHC_POWER_CTL, 689 (vdd << SDHC_VOLTAGE_SHIFT) | SDHC_BUS_POWER); 690 sdmmc_delay(10000); 691 692 /* 693 * The host system may not power the bus due to battery low, 694 * etc. In that case, the host controller should clear the 695 * bus power bit. 696 */ 697 if (!ISSET(HREAD1(hp, SDHC_POWER_CTL), SDHC_BUS_POWER)) { 698 error = ENXIO; 699 goto out; 700 } 701 } 702 703 out: 704 mutex_exit(&hp->host_mtx); 705 706 return error; 707 } 708 709 /* 710 * Return the smallest possible base clock frequency divisor value 711 * for the CLOCK_CTL register to produce `freq' (KHz). 712 */ 713 static bool 714 sdhc_clock_divisor(struct sdhc_host *hp, u_int freq, u_int *divp) 715 { 716 u_int div; 717 718 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_HAVE_CGM)) { 719 for (div = hp->clkbase / freq; div <= 0x3ff; div++) { 720 if ((hp->clkbase / div) <= freq) { 721 *divp = SDHC_SDCLK_CGM 722 | ((div & 0x300) << SDHC_SDCLK_XDIV_SHIFT) 723 | ((div & 0x0ff) << SDHC_SDCLK_DIV_SHIFT); 724 //freq = hp->clkbase / div; 725 return true; 726 } 727 } 728 /* No divisor found. */ 729 return false; 730 } 731 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_HAVE_DVS)) { 732 u_int dvs = (hp->clkbase + freq - 1) / freq; 733 u_int roundup = dvs & 1; 734 for (dvs >>= 1, div = 1; div <= 256; div <<= 1, dvs >>= 1) { 735 if (dvs + roundup <= 16) { 736 dvs += roundup - 1; 737 *divp = (div << SDHC_SDCLK_DIV_SHIFT) 738 | (dvs << SDHC_SDCLK_DVS_SHIFT); 739 DPRINTF(2, 740 ("%s: divisor for freq %u is %u * %u\n", 741 HDEVNAME(hp), freq, div * 2, dvs + 1)); 742 //freq = hp->clkbase / (div * 2) * (dvs + 1); 743 return true; 744 } 745 /* 746 * If we drop bits, we need to round up the divisor. 747 */ 748 roundup |= dvs & 1; 749 } 750 /* No divisor found. */ 751 return false; 752 } else { 753 for (div = 1; div <= 256; div *= 2) { 754 if ((hp->clkbase / div) <= freq) { 755 *divp = (div / 2) << SDHC_SDCLK_DIV_SHIFT; 756 //freq = hp->clkbase / div; 757 return true; 758 } 759 } 760 } 761 /* No divisor found. */ 762 return false; 763 } 764 765 /* 766 * Set or change SDCLK frequency or disable the SD clock. 767 * Return zero on success. 768 */ 769 static int 770 sdhc_bus_clock(sdmmc_chipset_handle_t sch, int freq) 771 { 772 struct sdhc_host *hp = (struct sdhc_host *)sch; 773 u_int div; 774 u_int timo; 775 int error = 0; 776 #ifdef DIAGNOSTIC 777 bool present; 778 779 mutex_enter(&hp->host_mtx); 780 present = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CMD_INHIBIT_MASK); 781 mutex_exit(&hp->host_mtx); 782 783 /* Must not stop the clock if commands are in progress. */ 784 if (present && sdhc_card_detect(hp)) { 785 printf("%s: sdhc_sdclk_frequency_select: command in progress\n", 786 device_xname(hp->sc->sc_dev)); 787 } 788 #endif 789 790 mutex_enter(&hp->host_mtx); 791 792 /* 793 * Stop SD clock before changing the frequency. 794 */ 795 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 796 HCLR4(hp, SDHC_CLOCK_CTL, 0xfff8); 797 if (freq == SDMMC_SDCLK_OFF) { 798 HSET4(hp, SDHC_CLOCK_CTL, 0x80f0); 799 goto out; 800 } 801 } else { 802 HWRITE2(hp, SDHC_CLOCK_CTL, 0); 803 if (freq == SDMMC_SDCLK_OFF) 804 goto out; 805 } 806 807 /* 808 * Set the minimum base clock frequency divisor. 809 */ 810 if (!sdhc_clock_divisor(hp, freq, &div)) { 811 /* Invalid base clock frequency or `freq' value. */ 812 error = EINVAL; 813 goto out; 814 } 815 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 816 HWRITE4(hp, SDHC_CLOCK_CTL, 817 div | (SDHC_TIMEOUT_MAX << 16)); 818 } else { 819 HWRITE2(hp, SDHC_CLOCK_CTL, div); 820 } 821 822 /* 823 * Start internal clock. Wait 10ms for stabilization. 824 */ 825 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 826 sdmmc_delay(10000); 827 HSET4(hp, SDHC_CLOCK_CTL, 828 8 | SDHC_INTCLK_ENABLE | SDHC_INTCLK_STABLE); 829 } else { 830 HSET2(hp, SDHC_CLOCK_CTL, SDHC_INTCLK_ENABLE); 831 for (timo = 1000; timo > 0; timo--) { 832 if (ISSET(HREAD2(hp, SDHC_CLOCK_CTL), 833 SDHC_INTCLK_STABLE)) 834 break; 835 sdmmc_delay(10); 836 } 837 if (timo == 0) { 838 error = ETIMEDOUT; 839 goto out; 840 } 841 } 842 843 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 844 HSET1(hp, SDHC_SOFTWARE_RESET, SDHC_INIT_ACTIVE); 845 /* 846 * Sending 80 clocks at 400kHz takes 200us. 847 * So delay for that time + slop and then 848 * check a few times for completion. 849 */ 850 sdmmc_delay(210); 851 for (timo = 10; timo > 0; timo--) { 852 if (!ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), 853 SDHC_INIT_ACTIVE)) 854 break; 855 sdmmc_delay(10); 856 } 857 DPRINTF(2,("%s: %u init spins\n", __func__, 10 - timo)); 858 859 /* 860 * Enable SD clock. 861 */ 862 HSET4(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE); 863 } else { 864 /* 865 * Enable SD clock. 866 */ 867 HSET2(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE); 868 869 if (freq > 25000) 870 HSET1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED); 871 else 872 HCLR1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED); 873 } 874 875 out: 876 mutex_exit(&hp->host_mtx); 877 878 return error; 879 } 880 881 static int 882 sdhc_bus_width(sdmmc_chipset_handle_t sch, int width) 883 { 884 struct sdhc_host *hp = (struct sdhc_host *)sch; 885 int reg; 886 887 switch (width) { 888 case 1: 889 case 4: 890 break; 891 892 case 8: 893 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_8BIT_MODE)) 894 break; 895 /* FALLTHROUGH */ 896 default: 897 DPRINTF(0,("%s: unsupported bus width (%d)\n", 898 HDEVNAME(hp), width)); 899 return 1; 900 } 901 902 mutex_enter(&hp->host_mtx); 903 reg = HREAD1(hp, SDHC_HOST_CTL); 904 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 905 reg &= ~(SDHC_4BIT_MODE|SDHC_ESDHC_8BIT_MODE); 906 if (width == 4) 907 reg |= SDHC_4BIT_MODE; 908 else if (width == 8) 909 reg |= SDHC_ESDHC_8BIT_MODE; 910 } else { 911 reg &= ~SDHC_4BIT_MODE; 912 if (width == 4) 913 reg |= SDHC_4BIT_MODE; 914 } 915 HWRITE1(hp, SDHC_HOST_CTL, reg); 916 mutex_exit(&hp->host_mtx); 917 918 return 0; 919 } 920 921 static int 922 sdhc_bus_rod(sdmmc_chipset_handle_t sch, int on) 923 { 924 925 /* Nothing ?? */ 926 return 0; 927 } 928 929 static void 930 sdhc_card_enable_intr(sdmmc_chipset_handle_t sch, int enable) 931 { 932 struct sdhc_host *hp = (struct sdhc_host *)sch; 933 934 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 935 mutex_enter(&hp->host_mtx); 936 if (enable) { 937 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 938 HSET2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT); 939 } else { 940 HCLR2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT); 941 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 942 } 943 mutex_exit(&hp->host_mtx); 944 } 945 } 946 947 static void 948 sdhc_card_intr_ack(sdmmc_chipset_handle_t sch) 949 { 950 struct sdhc_host *hp = (struct sdhc_host *)sch; 951 952 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 953 mutex_enter(&hp->host_mtx); 954 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 955 mutex_exit(&hp->host_mtx); 956 } 957 } 958 959 static int 960 sdhc_wait_state(struct sdhc_host *hp, uint32_t mask, uint32_t value) 961 { 962 uint32_t state; 963 int timeout; 964 965 for (timeout = 10; timeout > 0; timeout--) { 966 if (((state = HREAD4(hp, SDHC_PRESENT_STATE)) & mask) == value) 967 return 0; 968 sdmmc_delay(10000); 969 } 970 DPRINTF(0,("%s: timeout waiting for %x (state=%x)\n", HDEVNAME(hp), 971 value, state)); 972 return ETIMEDOUT; 973 } 974 975 static void 976 sdhc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 977 { 978 struct sdhc_host *hp = (struct sdhc_host *)sch; 979 int error; 980 981 #if 0 982 if (cmd->c_data) { 983 const uint16_t ready = SDHC_BUFFER_READ_READY | SDHC_BUFFER_WRITE_READY; 984 if (ISSET(hp->flags, SHF_USE_DMA)) { 985 HCLR2(hp, SDHC_NINTR_SIGNAL_EN, ready); 986 HCLR2(hp, SDHC_NINTR_STATUS_EN, ready); 987 } else { 988 HSET2(hp, SDHC_NINTR_SIGNAL_EN, ready); 989 HSET2(hp, SDHC_NINTR_STATUS_EN, ready); 990 } 991 } 992 #endif 993 994 /* 995 * Start the MMC command, or mark `cmd' as failed and return. 996 */ 997 error = sdhc_start_command(hp, cmd); 998 if (error) { 999 cmd->c_error = error; 1000 goto out; 1001 } 1002 1003 /* 1004 * Wait until the command phase is done, or until the command 1005 * is marked done for any other reason. 1006 */ 1007 if (!sdhc_wait_intr(hp, SDHC_COMMAND_COMPLETE, SDHC_COMMAND_TIMEOUT)) { 1008 cmd->c_error = ETIMEDOUT; 1009 goto out; 1010 } 1011 1012 /* 1013 * The host controller removes bits [0:7] from the response 1014 * data (CRC) and we pass the data up unchanged to the bus 1015 * driver (without padding). 1016 */ 1017 mutex_enter(&hp->host_mtx); 1018 if (cmd->c_error == 0 && ISSET(cmd->c_flags, SCF_RSP_PRESENT)) { 1019 uint32_t *p = cmd->c_resp; 1020 int i; 1021 1022 for (i = 0; i < 4; i++) { 1023 *p++ = bus_space_read_stream_4(hp->iot, hp->ioh, 1024 SDHC_RESPONSE + i * 4); 1025 if (!ISSET(cmd->c_flags, SCF_RSP_136)) 1026 break; 1027 } 1028 } 1029 mutex_exit(&hp->host_mtx); 1030 DPRINTF(1,("%s: resp = %08x\n", HDEVNAME(hp), cmd->c_resp[0])); 1031 1032 /* 1033 * If the command has data to transfer in any direction, 1034 * execute the transfer now. 1035 */ 1036 if (cmd->c_error == 0 && cmd->c_data != NULL) 1037 sdhc_transfer_data(hp, cmd); 1038 1039 out: 1040 #if 0 1041 if (cmd->c_dmamap != NULL && cmd->c_error == 0 1042 && ISSET(hp->flags, SHF_USE_DMA) 1043 && ISSET(cmd->c_flags, SCF_CMD_READ) { 1044 if (((uintptr_t)cmd->c_data & PAGE_MASK) + cmd->c_datalen > PAGE_SIZE) { 1045 memcpy(cmd->c_data, 1046 (void *)hp->sc->dma_map->dm_segs[0].ds_addr, 1047 cmd->c_datalen); 1048 } 1049 bus_dmamap_unload(hp->sc->dt, hp->sc->dma_map); 1050 } 1051 #endif 1052 1053 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED) 1054 && !ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_LED_ON)) { 1055 mutex_enter(&hp->host_mtx); 1056 /* Turn off the LED. */ 1057 HCLR1(hp, SDHC_HOST_CTL, SDHC_LED_ON); 1058 mutex_exit(&hp->host_mtx); 1059 } 1060 SET(cmd->c_flags, SCF_ITSDONE); 1061 1062 DPRINTF(1,("%s: cmd %d %s (flags=%08x error=%d)\n", HDEVNAME(hp), 1063 cmd->c_opcode, (cmd->c_error == 0) ? "done" : "abort", 1064 cmd->c_flags, cmd->c_error)); 1065 } 1066 1067 static int 1068 sdhc_start_command(struct sdhc_host *hp, struct sdmmc_command *cmd) 1069 { 1070 struct sdhc_softc * const sc = hp->sc; 1071 uint16_t blksize = 0; 1072 uint16_t blkcount = 0; 1073 uint16_t mode; 1074 uint16_t command; 1075 int error; 1076 1077 DPRINTF(1,("%s: start cmd %d arg=%08x data=%p dlen=%d flags=%08x, status=%#x\n", 1078 HDEVNAME(hp), cmd->c_opcode, cmd->c_arg, cmd->c_data, 1079 cmd->c_datalen, cmd->c_flags, HREAD4(hp, SDHC_NINTR_STATUS))); 1080 1081 /* 1082 * The maximum block length for commands should be the minimum 1083 * of the host buffer size and the card buffer size. (1.7.2) 1084 */ 1085 1086 /* Fragment the data into proper blocks. */ 1087 if (cmd->c_datalen > 0) { 1088 blksize = MIN(cmd->c_datalen, cmd->c_blklen); 1089 blkcount = cmd->c_datalen / blksize; 1090 if (cmd->c_datalen % blksize > 0) { 1091 /* XXX: Split this command. (1.7.4) */ 1092 aprint_error_dev(sc->sc_dev, 1093 "data not a multiple of %u bytes\n", blksize); 1094 return EINVAL; 1095 } 1096 } 1097 1098 /* Check limit imposed by 9-bit block count. (1.7.2) */ 1099 if (blkcount > SDHC_BLOCK_COUNT_MAX) { 1100 aprint_error_dev(sc->sc_dev, "too much data\n"); 1101 return EINVAL; 1102 } 1103 1104 /* Prepare transfer mode register value. (2.2.5) */ 1105 mode = SDHC_BLOCK_COUNT_ENABLE; 1106 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 1107 mode |= SDHC_READ_MODE; 1108 if (blkcount > 1) { 1109 mode |= SDHC_MULTI_BLOCK_MODE; 1110 /* XXX only for memory commands? */ 1111 mode |= SDHC_AUTO_CMD12_ENABLE; 1112 } 1113 if (cmd->c_dmamap != NULL && cmd->c_datalen > 0) { 1114 if (cmd->c_dmamap->dm_nsegs == 1) { 1115 mode |= SDHC_DMA_ENABLE; 1116 } else { 1117 cmd->c_dmamap = NULL; 1118 } 1119 } 1120 1121 /* 1122 * Prepare command register value. (2.2.6) 1123 */ 1124 command = (cmd->c_opcode & SDHC_COMMAND_INDEX_MASK) << SDHC_COMMAND_INDEX_SHIFT; 1125 1126 if (ISSET(cmd->c_flags, SCF_RSP_CRC)) 1127 command |= SDHC_CRC_CHECK_ENABLE; 1128 if (ISSET(cmd->c_flags, SCF_RSP_IDX)) 1129 command |= SDHC_INDEX_CHECK_ENABLE; 1130 if (cmd->c_data != NULL) 1131 command |= SDHC_DATA_PRESENT_SELECT; 1132 1133 if (!ISSET(cmd->c_flags, SCF_RSP_PRESENT)) 1134 command |= SDHC_NO_RESPONSE; 1135 else if (ISSET(cmd->c_flags, SCF_RSP_136)) 1136 command |= SDHC_RESP_LEN_136; 1137 else if (ISSET(cmd->c_flags, SCF_RSP_BSY)) 1138 command |= SDHC_RESP_LEN_48_CHK_BUSY; 1139 else 1140 command |= SDHC_RESP_LEN_48; 1141 1142 /* Wait until command and data inhibit bits are clear. (1.5) */ 1143 error = sdhc_wait_state(hp, SDHC_CMD_INHIBIT_MASK, 0); 1144 if (error) 1145 return error; 1146 1147 DPRINTF(1,("%s: writing cmd: blksize=%d blkcnt=%d mode=%04x cmd=%04x\n", 1148 HDEVNAME(hp), blksize, blkcount, mode, command)); 1149 1150 mutex_enter(&hp->host_mtx); 1151 1152 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1153 /* Alert the user not to remove the card. */ 1154 HSET1(hp, SDHC_HOST_CTL, SDHC_LED_ON); 1155 } 1156 1157 /* Set DMA start address. */ 1158 if (ISSET(mode, SDHC_DMA_ENABLE)) 1159 HWRITE4(hp, SDHC_DMA_ADDR, cmd->c_dmamap->dm_segs[0].ds_addr); 1160 1161 /* 1162 * Start a CPU data transfer. Writing to the high order byte 1163 * of the SDHC_COMMAND register triggers the SD command. (1.5) 1164 */ 1165 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 1166 HWRITE4(hp, SDHC_BLOCK_SIZE, blksize | (blkcount << 16)); 1167 HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg); 1168 HWRITE4(hp, SDHC_TRANSFER_MODE, mode | (command << 16)); 1169 } else { 1170 HWRITE2(hp, SDHC_BLOCK_SIZE, blksize); 1171 HWRITE2(hp, SDHC_BLOCK_COUNT, blkcount); 1172 HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg); 1173 HWRITE2(hp, SDHC_TRANSFER_MODE, mode); 1174 HWRITE2(hp, SDHC_COMMAND, command); 1175 } 1176 1177 mutex_exit(&hp->host_mtx); 1178 1179 return 0; 1180 } 1181 1182 static void 1183 sdhc_transfer_data(struct sdhc_host *hp, struct sdmmc_command *cmd) 1184 { 1185 int error; 1186 1187 DPRINTF(1,("%s: data transfer: resp=%08x datalen=%u\n", HDEVNAME(hp), 1188 MMC_R1(cmd->c_resp), cmd->c_datalen)); 1189 1190 #ifdef SDHC_DEBUG 1191 /* XXX I forgot why I wanted to know when this happens :-( */ 1192 if ((cmd->c_opcode == 52 || cmd->c_opcode == 53) && 1193 ISSET(MMC_R1(cmd->c_resp), 0xcb00)) { 1194 aprint_error_dev(hp->sc->sc_dev, 1195 "CMD52/53 error response flags %#x\n", 1196 MMC_R1(cmd->c_resp) & 0xff00); 1197 } 1198 #endif 1199 1200 if (cmd->c_dmamap != NULL) 1201 error = sdhc_transfer_data_dma(hp, cmd); 1202 else 1203 error = sdhc_transfer_data_pio(hp, cmd); 1204 if (error) 1205 cmd->c_error = error; 1206 SET(cmd->c_flags, SCF_ITSDONE); 1207 1208 DPRINTF(1,("%s: data transfer done (error=%d)\n", 1209 HDEVNAME(hp), cmd->c_error)); 1210 } 1211 1212 static int 1213 sdhc_transfer_data_dma(struct sdhc_host *hp, struct sdmmc_command *cmd) 1214 { 1215 bus_dmamap_t dmap = cmd->c_dmamap; 1216 uint16_t blklen = cmd->c_blklen; 1217 uint16_t blkcnt = cmd->c_datalen / blklen; 1218 uint16_t remain; 1219 int error = 0; 1220 1221 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_DMA_INTERRUPT); 1222 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_DMA_INTERRUPT); 1223 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_TRANSFER_COMPLETE); 1224 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_TRANSFER_COMPLETE); 1225 1226 for (;;) { 1227 if (!sdhc_wait_intr(hp, 1228 SDHC_DMA_INTERRUPT|SDHC_TRANSFER_COMPLETE, 1229 SDHC_DMA_TIMEOUT)) { 1230 error = ETIMEDOUT; 1231 break; 1232 } 1233 1234 /* single block mode */ 1235 if (blkcnt == 1) 1236 break; 1237 1238 /* multi block mode */ 1239 remain = HREAD2(hp, SDHC_BLOCK_COUNT); 1240 if (remain == 0) 1241 break; 1242 1243 HWRITE4(hp, SDHC_DMA_ADDR, 1244 dmap->dm_segs[0].ds_addr + (blkcnt - remain) * blklen); 1245 } 1246 1247 #if 0 1248 if (error == 0 && !sdhc_wait_intr(hp, SDHC_TRANSFER_COMPLETE, 1249 SDHC_TRANSFER_TIMEOUT)) 1250 error = ETIMEDOUT; 1251 #endif 1252 1253 return error; 1254 } 1255 1256 static int 1257 sdhc_transfer_data_pio(struct sdhc_host *hp, struct sdmmc_command *cmd) 1258 { 1259 uint8_t *data = cmd->c_data; 1260 void (*pio_func)(struct sdhc_host *, uint8_t *, u_int); 1261 u_int len, datalen; 1262 u_int imask; 1263 u_int pmask; 1264 int error = 0; 1265 1266 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 1267 imask = SDHC_BUFFER_READ_READY; 1268 pmask = SDHC_BUFFER_READ_ENABLE; 1269 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1270 pio_func = esdhc_read_data_pio; 1271 } else { 1272 pio_func = sdhc_read_data_pio; 1273 } 1274 } else { 1275 imask = SDHC_BUFFER_WRITE_READY; 1276 pmask = SDHC_BUFFER_WRITE_ENABLE; 1277 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1278 pio_func = esdhc_write_data_pio; 1279 } else { 1280 pio_func = sdhc_write_data_pio; 1281 } 1282 } 1283 datalen = cmd->c_datalen; 1284 1285 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & imask); 1286 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_TRANSFER_COMPLETE); 1287 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_TRANSFER_COMPLETE); 1288 1289 while (datalen > 0) { 1290 if (!ISSET(HREAD4(hp, SDHC_PRESENT_STATE), imask)) { 1291 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 1292 HSET4(hp, SDHC_NINTR_SIGNAL_EN, imask); 1293 } else { 1294 HSET2(hp, SDHC_NINTR_SIGNAL_EN, imask); 1295 } 1296 if (!sdhc_wait_intr(hp, imask, SDHC_BUFFER_TIMEOUT)) { 1297 error = ETIMEDOUT; 1298 break; 1299 } 1300 1301 error = sdhc_wait_state(hp, pmask, pmask); 1302 if (error) 1303 break; 1304 } 1305 1306 len = MIN(datalen, cmd->c_blklen); 1307 (*pio_func)(hp, data, len); 1308 DPRINTF(2,("%s: pio data transfer %u @ %p\n", 1309 HDEVNAME(hp), len, data)); 1310 1311 data += len; 1312 datalen -= len; 1313 } 1314 1315 if (error == 0 && !sdhc_wait_intr(hp, SDHC_TRANSFER_COMPLETE, 1316 SDHC_TRANSFER_TIMEOUT)) 1317 error = ETIMEDOUT; 1318 1319 return error; 1320 } 1321 1322 static void 1323 sdhc_read_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1324 { 1325 1326 if (((__uintptr_t)data & 3) == 0) { 1327 while (datalen > 3) { 1328 *(uint32_t *)data = HREAD4(hp, SDHC_DATA); 1329 data += 4; 1330 datalen -= 4; 1331 } 1332 if (datalen > 1) { 1333 *(uint16_t *)data = HREAD2(hp, SDHC_DATA); 1334 data += 2; 1335 datalen -= 2; 1336 } 1337 if (datalen > 0) { 1338 *data = HREAD1(hp, SDHC_DATA); 1339 data += 1; 1340 datalen -= 1; 1341 } 1342 } else if (((__uintptr_t)data & 1) == 0) { 1343 while (datalen > 1) { 1344 *(uint16_t *)data = HREAD2(hp, SDHC_DATA); 1345 data += 2; 1346 datalen -= 2; 1347 } 1348 if (datalen > 0) { 1349 *data = HREAD1(hp, SDHC_DATA); 1350 data += 1; 1351 datalen -= 1; 1352 } 1353 } else { 1354 while (datalen > 0) { 1355 *data = HREAD1(hp, SDHC_DATA); 1356 data += 1; 1357 datalen -= 1; 1358 } 1359 } 1360 } 1361 1362 static void 1363 sdhc_write_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1364 { 1365 1366 if (((__uintptr_t)data & 3) == 0) { 1367 while (datalen > 3) { 1368 HWRITE4(hp, SDHC_DATA, *(uint32_t *)data); 1369 data += 4; 1370 datalen -= 4; 1371 } 1372 if (datalen > 1) { 1373 HWRITE2(hp, SDHC_DATA, *(uint16_t *)data); 1374 data += 2; 1375 datalen -= 2; 1376 } 1377 if (datalen > 0) { 1378 HWRITE1(hp, SDHC_DATA, *data); 1379 data += 1; 1380 datalen -= 1; 1381 } 1382 } else if (((__uintptr_t)data & 1) == 0) { 1383 while (datalen > 1) { 1384 HWRITE2(hp, SDHC_DATA, *(uint16_t *)data); 1385 data += 2; 1386 datalen -= 2; 1387 } 1388 if (datalen > 0) { 1389 HWRITE1(hp, SDHC_DATA, *data); 1390 data += 1; 1391 datalen -= 1; 1392 } 1393 } else { 1394 while (datalen > 0) { 1395 HWRITE1(hp, SDHC_DATA, *data); 1396 data += 1; 1397 datalen -= 1; 1398 } 1399 } 1400 } 1401 1402 static void 1403 esdhc_read_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1404 { 1405 uint16_t status = HREAD2(hp, SDHC_NINTR_STATUS); 1406 uint32_t v; 1407 1408 while (datalen > 3 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1409 v = HREAD4(hp, SDHC_DATA); 1410 v = le32toh(v); 1411 *(uint32_t *)data = v; 1412 data += 4; 1413 datalen -= 4; 1414 status = HREAD2(hp, SDHC_NINTR_STATUS); 1415 } 1416 if (datalen > 0 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1417 v = HREAD4(hp, SDHC_DATA); 1418 v = le32toh(v); 1419 do { 1420 *data++ = v; 1421 v >>= 8; 1422 } while (--datalen > 0); 1423 } 1424 } 1425 1426 static void 1427 esdhc_write_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1428 { 1429 uint16_t status = HREAD2(hp, SDHC_NINTR_STATUS); 1430 uint32_t v; 1431 1432 while (datalen > 3 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1433 v = *(uint32_t *)data; 1434 v = htole32(v); 1435 HWRITE4(hp, SDHC_DATA, v); 1436 data += 4; 1437 datalen -= 4; 1438 status = HREAD2(hp, SDHC_NINTR_STATUS); 1439 } 1440 if (datalen > 0 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1441 v = *(uint32_t *)data; 1442 v = htole32(v); 1443 HWRITE4(hp, SDHC_DATA, v); 1444 } 1445 } 1446 1447 /* Prepare for another command. */ 1448 static int 1449 sdhc_soft_reset(struct sdhc_host *hp, int mask) 1450 { 1451 int timo; 1452 1453 DPRINTF(1,("%s: software reset reg=%08x\n", HDEVNAME(hp), mask)); 1454 1455 HWRITE1(hp, SDHC_SOFTWARE_RESET, mask); 1456 for (timo = 10; timo > 0; timo--) { 1457 if (!ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), mask)) 1458 break; 1459 sdmmc_delay(10000); 1460 HWRITE1(hp, SDHC_SOFTWARE_RESET, 0); 1461 } 1462 if (timo == 0) { 1463 DPRINTF(1,("%s: timeout reg=%08x\n", HDEVNAME(hp), 1464 HREAD1(hp, SDHC_SOFTWARE_RESET))); 1465 HWRITE1(hp, SDHC_SOFTWARE_RESET, 0); 1466 return ETIMEDOUT; 1467 } 1468 1469 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1470 HWRITE4(hp, SDHC_DMA_CTL, SDHC_DMA_SNOOP); 1471 } 1472 1473 return 0; 1474 } 1475 1476 static int 1477 sdhc_wait_intr(struct sdhc_host *hp, int mask, int timo) 1478 { 1479 int status; 1480 1481 mask |= SDHC_ERROR_INTERRUPT; 1482 1483 mutex_enter(&hp->intr_mtx); 1484 status = hp->intr_status & mask; 1485 while (status == 0) { 1486 if (cv_timedwait(&hp->intr_cv, &hp->intr_mtx, timo) 1487 == EWOULDBLOCK) { 1488 status |= SDHC_ERROR_INTERRUPT; 1489 break; 1490 } 1491 status = hp->intr_status & mask; 1492 } 1493 hp->intr_status &= ~status; 1494 1495 DPRINTF(2,("%s: intr status %#x error %#x\n", HDEVNAME(hp), status, 1496 hp->intr_error_status)); 1497 1498 /* Command timeout has higher priority than command complete. */ 1499 if (ISSET(status, SDHC_ERROR_INTERRUPT) || hp->intr_error_status) { 1500 hp->intr_error_status = 0; 1501 hp->intr_status &= ~SDHC_ERROR_INTERRUPT; 1502 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1503 (void)sdhc_soft_reset(hp, SDHC_RESET_DAT|SDHC_RESET_CMD); 1504 } 1505 status = 0; 1506 } 1507 mutex_exit(&hp->intr_mtx); 1508 1509 return status; 1510 } 1511 1512 /* 1513 * Established by attachment driver at interrupt priority IPL_SDMMC. 1514 */ 1515 int 1516 sdhc_intr(void *arg) 1517 { 1518 struct sdhc_softc *sc = (struct sdhc_softc *)arg; 1519 struct sdhc_host *hp; 1520 int done = 0; 1521 uint16_t status; 1522 uint16_t error; 1523 1524 /* We got an interrupt, but we don't know from which slot. */ 1525 for (size_t host = 0; host < sc->sc_nhosts; host++) { 1526 hp = sc->sc_host[host]; 1527 if (hp == NULL) 1528 continue; 1529 1530 if (ISSET(sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 1531 /* Find out which interrupts are pending. */ 1532 uint32_t xstatus = HREAD4(hp, SDHC_NINTR_STATUS); 1533 status = xstatus; 1534 error = xstatus >> 16; 1535 status |= (error ? SDHC_ERROR_INTERRUPT : 0); 1536 if (!ISSET(status, SDHC_NINTR_STATUS_MASK)) 1537 continue; /* no interrupt for us */ 1538 /* Acknowledge the interrupts we are about to handle. */ 1539 HWRITE4(hp, SDHC_NINTR_STATUS, xstatus); 1540 } else { 1541 /* Find out which interrupts are pending. */ 1542 error = 0; 1543 status = HREAD2(hp, SDHC_NINTR_STATUS); 1544 if (!ISSET(status, SDHC_NINTR_STATUS_MASK)) 1545 continue; /* no interrupt for us */ 1546 /* Acknowledge the interrupts we are about to handle. */ 1547 HWRITE2(hp, SDHC_NINTR_STATUS, status); 1548 if (ISSET(status, SDHC_ERROR_INTERRUPT)) { 1549 /* Acknowledge error interrupts. */ 1550 error = HREAD2(hp, SDHC_EINTR_STATUS); 1551 HWRITE2(hp, SDHC_EINTR_STATUS, error); 1552 } 1553 } 1554 1555 DPRINTF(2,("%s: interrupt status=%x error=%x\n", HDEVNAME(hp), 1556 status, error)); 1557 1558 /* Claim this interrupt. */ 1559 done = 1; 1560 1561 /* 1562 * Service error interrupts. 1563 */ 1564 if (ISSET(error, SDHC_CMD_TIMEOUT_ERROR| 1565 SDHC_DATA_TIMEOUT_ERROR)) { 1566 hp->intr_error_status |= error; 1567 hp->intr_status |= status; 1568 cv_broadcast(&hp->intr_cv); 1569 } 1570 1571 /* 1572 * Wake up the sdmmc event thread to scan for cards. 1573 */ 1574 if (ISSET(status, SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)) { 1575 sdmmc_needs_discover(hp->sdmmc); 1576 if (ISSET(sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1577 HCLR4(hp, SDHC_NINTR_STATUS_EN, 1578 status & (SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)); 1579 HCLR4(hp, SDHC_NINTR_SIGNAL_EN, 1580 status & (SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)); 1581 } 1582 } 1583 1584 /* 1585 * Wake up the blocking process to service command 1586 * related interrupt(s). 1587 */ 1588 if (ISSET(status, SDHC_COMMAND_COMPLETE| 1589 SDHC_BUFFER_READ_READY|SDHC_BUFFER_WRITE_READY| 1590 SDHC_TRANSFER_COMPLETE|SDHC_DMA_INTERRUPT)) { 1591 hp->intr_status |= status; 1592 if (ISSET(sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1593 HCLR4(hp, SDHC_NINTR_SIGNAL_EN, 1594 status & (SDHC_BUFFER_READ_READY|SDHC_BUFFER_WRITE_READY)); 1595 } 1596 cv_broadcast(&hp->intr_cv); 1597 } 1598 1599 /* 1600 * Service SD card interrupts. 1601 */ 1602 if (!ISSET(sc->sc_flags, SDHC_FLAG_ENHANCED) 1603 && ISSET(status, SDHC_CARD_INTERRUPT)) { 1604 DPRINTF(0,("%s: card interrupt\n", HDEVNAME(hp))); 1605 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 1606 sdmmc_card_intr(hp->sdmmc); 1607 } 1608 } 1609 1610 return done; 1611 } 1612 1613 #ifdef SDHC_DEBUG 1614 void 1615 sdhc_dump_regs(struct sdhc_host *hp) 1616 { 1617 1618 printf("0x%02x PRESENT_STATE: %x\n", SDHC_PRESENT_STATE, 1619 HREAD4(hp, SDHC_PRESENT_STATE)); 1620 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 1621 printf("0x%02x POWER_CTL: %x\n", SDHC_POWER_CTL, 1622 HREAD1(hp, SDHC_POWER_CTL)); 1623 printf("0x%02x NINTR_STATUS: %x\n", SDHC_NINTR_STATUS, 1624 HREAD2(hp, SDHC_NINTR_STATUS)); 1625 printf("0x%02x EINTR_STATUS: %x\n", SDHC_EINTR_STATUS, 1626 HREAD2(hp, SDHC_EINTR_STATUS)); 1627 printf("0x%02x NINTR_STATUS_EN: %x\n", SDHC_NINTR_STATUS_EN, 1628 HREAD2(hp, SDHC_NINTR_STATUS_EN)); 1629 printf("0x%02x EINTR_STATUS_EN: %x\n", SDHC_EINTR_STATUS_EN, 1630 HREAD2(hp, SDHC_EINTR_STATUS_EN)); 1631 printf("0x%02x NINTR_SIGNAL_EN: %x\n", SDHC_NINTR_SIGNAL_EN, 1632 HREAD2(hp, SDHC_NINTR_SIGNAL_EN)); 1633 printf("0x%02x EINTR_SIGNAL_EN: %x\n", SDHC_EINTR_SIGNAL_EN, 1634 HREAD2(hp, SDHC_EINTR_SIGNAL_EN)); 1635 printf("0x%02x CAPABILITIES: %x\n", SDHC_CAPABILITIES, 1636 HREAD4(hp, SDHC_CAPABILITIES)); 1637 printf("0x%02x MAX_CAPABILITIES: %x\n", SDHC_MAX_CAPABILITIES, 1638 HREAD4(hp, SDHC_MAX_CAPABILITIES)); 1639 } 1640 #endif 1641
Indexes created Tue Sep 23 07:09:52 GMT 2025