sdhc.c revision 1.23
1 /* $NetBSD: sdhc.c,v 1.23 2012/07/20 02:04:13 matt Exp $ */ 2 /* $OpenBSD: sdhc.c,v 1.25 2009/01/13 19:44:20 grange Exp $ */ 3 4 /* 5 * Copyright (c) 2006 Uwe Stuehler <uwe (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * SD Host Controller driver based on the SD Host Controller Standard 22 * Simplified Specification Version 1.00 (www.sdcard.com). 23 */ 24 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: sdhc.c,v 1.23 2012/07/20 02:04:13 matt Exp $"); 27 28 #ifdef _KERNEL_OPT 29 #include "opt_sdmmc.h" 30 #endif 31 32 #include <sys/param.h> 33 #include <sys/device.h> 34 #include <sys/kernel.h> 35 #include <sys/kthread.h> 36 #include <sys/malloc.h> 37 #include <sys/systm.h> 38 #include <sys/mutex.h> 39 #include <sys/condvar.h> 40 41 #include <dev/sdmmc/sdhcreg.h> 42 #include <dev/sdmmc/sdhcvar.h> 43 #include <dev/sdmmc/sdmmcchip.h> 44 #include <dev/sdmmc/sdmmcreg.h> 45 #include <dev/sdmmc/sdmmcvar.h> 46 47 #ifdef SDHC_DEBUG 48 int sdhcdebug = 1; 49 #define DPRINTF(n,s) do { if ((n) <= sdhcdebug) printf s; } while (0) 50 void sdhc_dump_regs(struct sdhc_host *); 51 #else 52 #define DPRINTF(n,s) do {} while (0) 53 #endif 54 55 #define SDHC_COMMAND_TIMEOUT hz 56 #define SDHC_BUFFER_TIMEOUT hz 57 #define SDHC_TRANSFER_TIMEOUT hz 58 #define SDHC_DMA_TIMEOUT hz 59 60 struct sdhc_host { 61 struct sdhc_softc *sc; /* host controller device */ 62 63 bus_space_tag_t iot; /* host register set tag */ 64 bus_space_handle_t ioh; /* host register set handle */ 65 bus_dma_tag_t dmat; /* host DMA tag */ 66 67 device_t sdmmc; /* generic SD/MMC device */ 68 69 struct kmutex host_mtx; 70 71 u_int clkbase; /* base clock frequency in KHz */ 72 int maxblklen; /* maximum block length */ 73 uint32_t ocr; /* OCR value from capabilities */ 74 75 uint8_t regs[14]; /* host controller state */ 76 77 uint16_t intr_status; /* soft interrupt status */ 78 uint16_t intr_error_status; /* soft error status */ 79 struct kmutex intr_mtx; 80 struct kcondvar intr_cv; 81 82 int specver; /* spec. version */ 83 84 uint32_t flags; /* flags for this host */ 85 #define SHF_USE_DMA 0x0001 86 #define SHF_USE_4BIT_MODE 0x0002 87 #define SHF_USE_8BIT_MODE 0x0004 88 }; 89 90 #define HDEVNAME(hp) (device_xname((hp)->sc->sc_dev)) 91 #define HDEVINST(hp) ((int)(((hp)-(hp)->sc->sc_host[0])/sizeof(*(hp)))) 92 93 static uint8_t 94 hread1(struct sdhc_host *hp, bus_size_t reg) 95 { 96 97 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) 98 return bus_space_read_1(hp->iot, hp->ioh, reg); 99 return bus_space_read_4(hp->iot, hp->ioh, reg & -4) >> (8 * (reg & 3)); 100 } 101 102 static uint16_t 103 hread2(struct sdhc_host *hp, bus_size_t reg) 104 { 105 106 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) 107 return bus_space_read_2(hp->iot, hp->ioh, reg); 108 return bus_space_read_4(hp->iot, hp->ioh, reg & -4) >> (8 * (reg & 2)); 109 } 110 111 #define HREAD1(hp, reg) hread1(hp, reg) 112 #define HREAD2(hp, reg) hread2(hp, reg) 113 #define HREAD4(hp, reg) \ 114 (bus_space_read_4((hp)->iot, (hp)->ioh, (reg))) 115 116 117 static void 118 hwrite1(struct sdhc_host *hp, bus_size_t o, uint8_t val) 119 { 120 121 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 122 bus_space_write_1(hp->iot, hp->ioh, o, val); 123 } else { 124 const size_t shift = 8 * (o & 3); 125 o &= -4; 126 uint32_t tmp = bus_space_read_4(hp->iot, hp->ioh, o); 127 tmp = (val << shift) | (tmp & ~(0xff << shift)); 128 bus_space_write_4(hp->iot, hp->ioh, o, tmp); 129 } 130 } 131 132 static void 133 hwrite2(struct sdhc_host *hp, bus_size_t o, uint16_t val) 134 { 135 136 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 137 bus_space_write_2(hp->iot, hp->ioh, o, val); 138 } else { 139 const size_t shift = 8 * (o & 2); 140 o &= -4; 141 uint32_t tmp = bus_space_read_4(hp->iot, hp->ioh, o); 142 tmp = (val << shift) | (tmp & ~(0xffff << shift)); 143 bus_space_write_4(hp->iot, hp->ioh, o, tmp); 144 } 145 } 146 147 #define HWRITE1(hp, reg, val) hwrite1(hp, reg, val) 148 #define HWRITE2(hp, reg, val) hwrite2(hp, reg, val) 149 #define HWRITE4(hp, reg, val) \ 150 bus_space_write_4((hp)->iot, (hp)->ioh, (reg), (val)) 151 152 #define HCLR1(hp, reg, bits) \ 153 do if (bits) HWRITE1((hp), (reg), HREAD1((hp), (reg)) & ~(bits)); while (0) 154 #define HCLR2(hp, reg, bits) \ 155 do if (bits) HWRITE2((hp), (reg), HREAD2((hp), (reg)) & ~(bits)); while (0) 156 #define HCLR4(hp, reg, bits) \ 157 do if (bits) HWRITE4((hp), (reg), HREAD4((hp), (reg)) & ~(bits)); while (0) 158 #define HSET1(hp, reg, bits) \ 159 do if (bits) HWRITE1((hp), (reg), HREAD1((hp), (reg)) | (bits)); while (0) 160 #define HSET2(hp, reg, bits) \ 161 do if (bits) HWRITE2((hp), (reg), HREAD2((hp), (reg)) | (bits)); while (0) 162 #define HSET4(hp, reg, bits) \ 163 do if (bits) HWRITE4((hp), (reg), HREAD4((hp), (reg)) | (bits)); while (0) 164 165 static int sdhc_host_reset(sdmmc_chipset_handle_t); 166 static int sdhc_host_reset1(sdmmc_chipset_handle_t); 167 static uint32_t sdhc_host_ocr(sdmmc_chipset_handle_t); 168 static int sdhc_host_maxblklen(sdmmc_chipset_handle_t); 169 static int sdhc_card_detect(sdmmc_chipset_handle_t); 170 static int sdhc_write_protect(sdmmc_chipset_handle_t); 171 static int sdhc_bus_power(sdmmc_chipset_handle_t, uint32_t); 172 static int sdhc_bus_clock(sdmmc_chipset_handle_t, int); 173 static int sdhc_bus_width(sdmmc_chipset_handle_t, int); 174 static int sdhc_bus_rod(sdmmc_chipset_handle_t, int); 175 static void sdhc_card_enable_intr(sdmmc_chipset_handle_t, int); 176 static void sdhc_card_intr_ack(sdmmc_chipset_handle_t); 177 static void sdhc_exec_command(sdmmc_chipset_handle_t, 178 struct sdmmc_command *); 179 static int sdhc_start_command(struct sdhc_host *, struct sdmmc_command *); 180 static int sdhc_wait_state(struct sdhc_host *, uint32_t, uint32_t); 181 static int sdhc_soft_reset(struct sdhc_host *, int); 182 static int sdhc_wait_intr(struct sdhc_host *, int, int); 183 static void sdhc_transfer_data(struct sdhc_host *, struct sdmmc_command *); 184 static int sdhc_transfer_data_dma(struct sdhc_host *, struct sdmmc_command *); 185 static int sdhc_transfer_data_pio(struct sdhc_host *, struct sdmmc_command *); 186 static void sdhc_read_data_pio(struct sdhc_host *, uint8_t *, u_int); 187 static void sdhc_write_data_pio(struct sdhc_host *, uint8_t *, u_int); 188 static void esdhc_read_data_pio(struct sdhc_host *, uint8_t *, u_int); 189 static void esdhc_write_data_pio(struct sdhc_host *, uint8_t *, u_int); 190 191 192 static struct sdmmc_chip_functions sdhc_functions = { 193 /* host controller reset */ 194 sdhc_host_reset, 195 196 /* host controller capabilities */ 197 sdhc_host_ocr, 198 sdhc_host_maxblklen, 199 200 /* card detection */ 201 sdhc_card_detect, 202 203 /* write protect */ 204 sdhc_write_protect, 205 206 /* bus power, clock frequency and width */ 207 sdhc_bus_power, 208 sdhc_bus_clock, 209 sdhc_bus_width, 210 sdhc_bus_rod, 211 212 /* command execution */ 213 sdhc_exec_command, 214 215 /* card interrupt */ 216 sdhc_card_enable_intr, 217 sdhc_card_intr_ack 218 }; 219 220 static int 221 sdhc_cfprint(void *aux, const char *pnp) 222 { 223 const struct sdmmcbus_attach_args const * saa = aux; 224 const struct sdhc_host * const hp = saa->saa_sch; 225 226 if (pnp) { 227 aprint_normal("sdmmc at %s", pnp); 228 } 229 aprint_normal(" slot %d", HDEVINST(hp)); 230 231 return UNCONF; 232 } 233 234 /* 235 * Called by attachment driver. For each SD card slot there is one SD 236 * host controller standard register set. (1.3) 237 */ 238 int 239 sdhc_host_found(struct sdhc_softc *sc, bus_space_tag_t iot, 240 bus_space_handle_t ioh, bus_size_t iosize) 241 { 242 struct sdmmcbus_attach_args saa; 243 struct sdhc_host *hp; 244 uint32_t caps; 245 uint16_t sdhcver; 246 247 sdhcver = bus_space_read_2(iot, ioh, SDHC_HOST_CTL_VERSION); 248 aprint_normal_dev(sc->sc_dev, "SD Host Specification "); 249 switch (SDHC_SPEC_VERSION(sdhcver)) { 250 case SDHC_SPEC_VERS_100: 251 aprint_normal("1.0"); 252 break; 253 254 case SDHC_SPEC_VERS_200: 255 aprint_normal("2.0"); 256 break; 257 258 case SDHC_SPEC_VERS_300: 259 aprint_normal("3.0"); 260 break; 261 262 default: 263 aprint_normal("unknown version(0x%x)", 264 SDHC_SPEC_VERSION(sdhcver)); 265 break; 266 } 267 aprint_normal(", rev.%u\n", SDHC_VENDOR_VERSION(sdhcver)); 268 269 /* Allocate one more host structure. */ 270 hp = malloc(sizeof(struct sdhc_host), M_DEVBUF, M_WAITOK|M_ZERO); 271 if (hp == NULL) { 272 aprint_error_dev(sc->sc_dev, 273 "couldn't alloc memory (sdhc host)\n"); 274 goto err1; 275 } 276 sc->sc_host[sc->sc_nhosts++] = hp; 277 278 /* Fill in the new host structure. */ 279 hp->sc = sc; 280 hp->iot = iot; 281 hp->ioh = ioh; 282 hp->dmat = sc->sc_dmat; 283 hp->specver = SDHC_SPEC_VERSION(sdhcver); 284 285 mutex_init(&hp->host_mtx, MUTEX_DEFAULT, IPL_SDMMC); 286 mutex_init(&hp->intr_mtx, MUTEX_DEFAULT, IPL_SDMMC); 287 cv_init(&hp->intr_cv, "sdhcintr"); 288 289 /* 290 * Reset the host controller and enable interrupts. 291 */ 292 (void)sdhc_host_reset(hp); 293 294 /* Determine host capabilities. */ 295 mutex_enter(&hp->host_mtx); 296 caps = HREAD4(hp, SDHC_CAPABILITIES); 297 mutex_exit(&hp->host_mtx); 298 299 /* Use DMA if the host system and the controller support it. */ 300 if (ISSET(sc->sc_flags, SDHC_FLAG_FORCE_DMA) 301 || ((ISSET(sc->sc_flags, SDHC_FLAG_USE_DMA) 302 && ISSET(caps, SDHC_DMA_SUPPORT)))) { 303 SET(hp->flags, SHF_USE_DMA); 304 aprint_normal_dev(sc->sc_dev, "using DMA transfer\n"); 305 } 306 307 /* 308 * Determine the base clock frequency. (2.2.24) 309 */ 310 hp->clkbase = SDHC_BASE_FREQ_KHZ(caps); 311 if (hp->clkbase == 0) { 312 if (sc->sc_clkbase == 0) { 313 /* The attachment driver must tell us. */ 314 aprint_error_dev(sc->sc_dev, 315 "unknown base clock frequency\n"); 316 goto err; 317 } 318 hp->clkbase = sc->sc_clkbase; 319 } 320 if (hp->clkbase < 10000 || hp->clkbase > 10000 * 256) { 321 /* SDHC 1.0 supports only 10-63 MHz. */ 322 aprint_error_dev(sc->sc_dev, 323 "base clock frequency out of range: %u MHz\n", 324 hp->clkbase / 1000); 325 goto err; 326 } 327 DPRINTF(1,("%s: base clock frequency %u MHz\n", 328 device_xname(sc->sc_dev), hp->clkbase / 1000)); 329 330 /* 331 * XXX Set the data timeout counter value according to 332 * capabilities. (2.2.15) 333 */ 334 HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX); 335 #if 0 336 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 337 HWRITE4(hp, SDHC_NINTR_STATUS, SDHC_CMD_TIMEOUT_ERROR << 16); 338 #endif 339 340 /* 341 * Determine SD bus voltage levels supported by the controller. 342 */ 343 if (ISSET(caps, SDHC_VOLTAGE_SUPP_1_8V)) { 344 SET(hp->ocr, MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V); 345 } 346 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_0V)) { 347 SET(hp->ocr, MMC_OCR_2_9V_3_0V | MMC_OCR_3_0V_3_1V); 348 } 349 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_3V)) { 350 SET(hp->ocr, MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V); 351 } 352 353 /* 354 * Determine the maximum block length supported by the host 355 * controller. (2.2.24) 356 */ 357 switch((caps >> SDHC_MAX_BLK_LEN_SHIFT) & SDHC_MAX_BLK_LEN_MASK) { 358 case SDHC_MAX_BLK_LEN_512: 359 hp->maxblklen = 512; 360 break; 361 362 case SDHC_MAX_BLK_LEN_1024: 363 hp->maxblklen = 1024; 364 break; 365 366 case SDHC_MAX_BLK_LEN_2048: 367 hp->maxblklen = 2048; 368 break; 369 370 case SDHC_MAX_BLK_LEN_4096: 371 hp->maxblklen = 4096; 372 break; 373 374 default: 375 aprint_error_dev(sc->sc_dev, "max block length unknown\n"); 376 goto err; 377 } 378 DPRINTF(1, ("%s: max block length %u byte%s\n", 379 device_xname(sc->sc_dev), hp->maxblklen, 380 hp->maxblklen > 1 ? "s" : "")); 381 382 /* 383 * Attach the generic SD/MMC bus driver. (The bus driver must 384 * not invoke any chipset functions before it is attached.) 385 */ 386 memset(&saa, 0, sizeof(saa)); 387 saa.saa_busname = "sdmmc"; 388 saa.saa_sct = &sdhc_functions; 389 saa.saa_sch = hp; 390 saa.saa_dmat = hp->dmat; 391 saa.saa_clkmin = hp->clkbase / 256; 392 saa.saa_clkmax = hp->clkbase; 393 if (ISSET(sc->sc_flags, SDHC_FLAG_HAVE_CGM)) 394 saa.saa_clkmin /= 2046; 395 else if (ISSET(sc->sc_flags, SDHC_FLAG_HAVE_DVS)) 396 saa.saa_clkmin /= 16; 397 saa.saa_caps = SMC_CAPS_4BIT_MODE|SMC_CAPS_AUTO_STOP; 398 if (ISSET(sc->sc_flags, SDHC_FLAG_8BIT_MODE)) 399 saa.saa_caps |= SMC_CAPS_8BIT_MODE; 400 if (ISSET(caps, SDHC_HIGH_SPEED_SUPP)) 401 saa.saa_caps |= SMC_CAPS_SD_HIGHSPEED; 402 if (ISSET(hp->flags, SHF_USE_DMA)) 403 saa.saa_caps |= SMC_CAPS_DMA | SMC_CAPS_MULTI_SEG_DMA; 404 hp->sdmmc = config_found(sc->sc_dev, &saa, sdhc_cfprint); 405 406 return 0; 407 408 err: 409 cv_destroy(&hp->intr_cv); 410 mutex_destroy(&hp->intr_mtx); 411 mutex_destroy(&hp->host_mtx); 412 free(hp, M_DEVBUF); 413 sc->sc_host[--sc->sc_nhosts] = NULL; 414 err1: 415 return 1; 416 } 417 418 int 419 sdhc_detach(device_t dev, int flags) 420 { 421 struct sdhc_host *hp = (struct sdhc_host *)dev; 422 struct sdhc_softc *sc = hp->sc; 423 int rv = 0; 424 425 if (hp->sdmmc) 426 rv = config_detach(hp->sdmmc, flags); 427 428 cv_destroy(&hp->intr_cv); 429 mutex_destroy(&hp->intr_mtx); 430 mutex_destroy(&hp->host_mtx); 431 free(hp, M_DEVBUF); 432 sc->sc_host[--sc->sc_nhosts] = NULL; 433 434 return rv; 435 } 436 437 bool 438 sdhc_suspend(device_t dev, const pmf_qual_t *qual) 439 { 440 struct sdhc_softc *sc = device_private(dev); 441 struct sdhc_host *hp; 442 size_t i; 443 444 /* XXX poll for command completion or suspend command 445 * in progress */ 446 447 /* Save the host controller state. */ 448 for (size_t n = 0; n < sc->sc_nhosts; n++) { 449 hp = sc->sc_host[n]; 450 if (ISSET(sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 451 for (i = 0; i < sizeof hp->regs; i += 4) { 452 uint32_t v = HREAD4(hp, i); 453 hp->regs[i + 0] = (v >> 0); 454 hp->regs[i + 1] = (v >> 8); 455 if (i + 3 < sizeof hp->regs) { 456 hp->regs[i + 2] = (v >> 16); 457 hp->regs[i + 3] = (v >> 24); 458 } 459 } 460 } else { 461 for (i = 0; i < sizeof hp->regs; i++) { 462 hp->regs[i] = HREAD1(hp, i); 463 } 464 } 465 } 466 return true; 467 } 468 469 bool 470 sdhc_resume(device_t dev, const pmf_qual_t *qual) 471 { 472 struct sdhc_softc *sc = device_private(dev); 473 struct sdhc_host *hp; 474 size_t i; 475 476 /* Restore the host controller state. */ 477 for (size_t n = 0; n < sc->sc_nhosts; n++) { 478 hp = sc->sc_host[n]; 479 (void)sdhc_host_reset(hp); 480 if (ISSET(sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 481 for (i = 0; i < sizeof hp->regs; i += 4) { 482 if (i + 3 < sizeof hp->regs) { 483 HWRITE4(hp, i, 484 (hp->regs[i + 0] << 0) 485 | (hp->regs[i + 1] << 8) 486 | (hp->regs[i + 2] << 16) 487 | (hp->regs[i + 3] << 24)); 488 } else { 489 HWRITE4(hp, i, 490 (hp->regs[i + 0] << 0) 491 | (hp->regs[i + 1] << 8)); 492 } 493 } 494 } else { 495 for (i = 0; i < sizeof hp->regs; i++) { 496 HWRITE1(hp, i, hp->regs[i]); 497 } 498 } 499 } 500 return true; 501 } 502 503 bool 504 sdhc_shutdown(device_t dev, int flags) 505 { 506 struct sdhc_softc *sc = device_private(dev); 507 struct sdhc_host *hp; 508 509 /* XXX chip locks up if we don't disable it before reboot. */ 510 for (size_t i = 0; i < sc->sc_nhosts; i++) { 511 hp = sc->sc_host[i]; 512 (void)sdhc_host_reset(hp); 513 } 514 return true; 515 } 516 517 /* 518 * Reset the host controller. Called during initialization, when 519 * cards are removed, upon resume, and during error recovery. 520 */ 521 static int 522 sdhc_host_reset1(sdmmc_chipset_handle_t sch) 523 { 524 struct sdhc_host *hp = (struct sdhc_host *)sch; 525 uint32_t sdhcimask; 526 int error; 527 528 /* Don't lock. */ 529 530 /* Disable all interrupts. */ 531 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 532 HWRITE4(hp, SDHC_NINTR_SIGNAL_EN, 0); 533 } else { 534 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, 0); 535 } 536 537 /* 538 * Reset the entire host controller and wait up to 100ms for 539 * the controller to clear the reset bit. 540 */ 541 error = sdhc_soft_reset(hp, SDHC_RESET_ALL); 542 if (error) 543 goto out; 544 545 /* Set data timeout counter value to max for now. */ 546 HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX); 547 #if 0 548 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 549 HWRITE4(hp, SDHC_NINTR_STATUS, SDHC_CMD_TIMEOUT_ERROR << 16); 550 #endif 551 552 /* Enable interrupts. */ 553 sdhcimask = SDHC_CARD_REMOVAL | SDHC_CARD_INSERTION | 554 SDHC_BUFFER_READ_READY | SDHC_BUFFER_WRITE_READY | 555 SDHC_DMA_INTERRUPT | SDHC_BLOCK_GAP_EVENT | 556 SDHC_TRANSFER_COMPLETE | SDHC_COMMAND_COMPLETE; 557 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 558 sdhcimask |= SDHC_EINTR_STATUS_MASK << 16; 559 HWRITE4(hp, SDHC_NINTR_STATUS_EN, sdhcimask); 560 sdhcimask ^= 561 (SDHC_EINTR_STATUS_MASK ^ SDHC_EINTR_SIGNAL_MASK) << 16; 562 sdhcimask ^= SDHC_BUFFER_READ_READY ^ SDHC_BUFFER_WRITE_READY; 563 HWRITE4(hp, SDHC_NINTR_SIGNAL_EN, sdhcimask); 564 } else { 565 HWRITE2(hp, SDHC_NINTR_STATUS_EN, sdhcimask); 566 HWRITE2(hp, SDHC_EINTR_STATUS_EN, SDHC_EINTR_STATUS_MASK); 567 sdhcimask ^= SDHC_BUFFER_READ_READY ^ SDHC_BUFFER_WRITE_READY; 568 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, sdhcimask); 569 HWRITE2(hp, SDHC_EINTR_SIGNAL_EN, SDHC_EINTR_SIGNAL_MASK); 570 } 571 572 out: 573 return error; 574 } 575 576 static int 577 sdhc_host_reset(sdmmc_chipset_handle_t sch) 578 { 579 struct sdhc_host *hp = (struct sdhc_host *)sch; 580 int error; 581 582 mutex_enter(&hp->host_mtx); 583 error = sdhc_host_reset1(sch); 584 mutex_exit(&hp->host_mtx); 585 586 return error; 587 } 588 589 static uint32_t 590 sdhc_host_ocr(sdmmc_chipset_handle_t sch) 591 { 592 struct sdhc_host *hp = (struct sdhc_host *)sch; 593 594 return hp->ocr; 595 } 596 597 static int 598 sdhc_host_maxblklen(sdmmc_chipset_handle_t sch) 599 { 600 struct sdhc_host *hp = (struct sdhc_host *)sch; 601 602 return hp->maxblklen; 603 } 604 605 /* 606 * Return non-zero if the card is currently inserted. 607 */ 608 static int 609 sdhc_card_detect(sdmmc_chipset_handle_t sch) 610 { 611 struct sdhc_host *hp = (struct sdhc_host *)sch; 612 int r; 613 614 mutex_enter(&hp->host_mtx); 615 r = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CARD_INSERTED); 616 mutex_exit(&hp->host_mtx); 617 618 return r ? 1 : 0; 619 } 620 621 /* 622 * Return non-zero if the card is currently write-protected. 623 */ 624 static int 625 sdhc_write_protect(sdmmc_chipset_handle_t sch) 626 { 627 struct sdhc_host *hp = (struct sdhc_host *)sch; 628 int r; 629 630 mutex_enter(&hp->host_mtx); 631 r = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_WRITE_PROTECT_SWITCH); 632 mutex_exit(&hp->host_mtx); 633 634 return r ? 0 : 1; 635 } 636 637 /* 638 * Set or change SD bus voltage and enable or disable SD bus power. 639 * Return zero on success. 640 */ 641 static int 642 sdhc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 643 { 644 struct sdhc_host *hp = (struct sdhc_host *)sch; 645 uint8_t vdd; 646 int error = 0; 647 648 mutex_enter(&hp->host_mtx); 649 650 /* 651 * Disable bus power before voltage change. 652 */ 653 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS) 654 && !ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_PWR0)) 655 HWRITE1(hp, SDHC_POWER_CTL, 0); 656 657 /* If power is disabled, reset the host and return now. */ 658 if (ocr == 0) { 659 (void)sdhc_host_reset1(hp); 660 goto out; 661 } 662 663 /* 664 * Select the lowest voltage according to capabilities. 665 */ 666 ocr &= hp->ocr; 667 if (ISSET(ocr, MMC_OCR_1_7V_1_8V|MMC_OCR_1_8V_1_9V)) { 668 vdd = SDHC_VOLTAGE_1_8V; 669 } else if (ISSET(ocr, MMC_OCR_2_9V_3_0V|MMC_OCR_3_0V_3_1V)) { 670 vdd = SDHC_VOLTAGE_3_0V; 671 } else if (ISSET(ocr, MMC_OCR_3_2V_3_3V|MMC_OCR_3_3V_3_4V)) { 672 vdd = SDHC_VOLTAGE_3_3V; 673 } else { 674 /* Unsupported voltage level requested. */ 675 error = EINVAL; 676 goto out; 677 } 678 679 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 680 /* 681 * Enable bus power. Wait at least 1 ms (or 74 clocks) plus 682 * voltage ramp until power rises. 683 */ 684 HWRITE1(hp, SDHC_POWER_CTL, 685 (vdd << SDHC_VOLTAGE_SHIFT) | SDHC_BUS_POWER); 686 sdmmc_delay(10000); 687 688 /* 689 * The host system may not power the bus due to battery low, 690 * etc. In that case, the host controller should clear the 691 * bus power bit. 692 */ 693 if (!ISSET(HREAD1(hp, SDHC_POWER_CTL), SDHC_BUS_POWER)) { 694 error = ENXIO; 695 goto out; 696 } 697 } 698 699 out: 700 mutex_exit(&hp->host_mtx); 701 702 return error; 703 } 704 705 /* 706 * Return the smallest possible base clock frequency divisor value 707 * for the CLOCK_CTL register to produce `freq' (KHz). 708 */ 709 static bool 710 sdhc_clock_divisor(struct sdhc_host *hp, u_int freq, u_int *divp) 711 { 712 u_int div; 713 714 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_HAVE_CGM)) { 715 for (div = hp->clkbase / freq; div <= 0x3ff; div++) { 716 if ((hp->clkbase / div) <= freq) { 717 *divp = SDHC_SDCLK_CGM 718 | ((div & 0x300) << SDHC_SDCLK_XDIV_SHIFT) 719 | ((div & 0x0ff) << SDHC_SDCLK_DIV_SHIFT); 720 //freq = hp->clkbase / div; 721 return true; 722 } 723 } 724 /* No divisor found. */ 725 return false; 726 } 727 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_HAVE_DVS)) { 728 u_int dvs = (hp->clkbase + freq - 1) / freq; 729 u_int roundup = dvs & 1; 730 for (dvs >>= 1, div = 1; div <= 256; div <<= 1, dvs >>= 1) { 731 if (dvs + roundup <= 16) { 732 dvs += roundup - 1; 733 *divp = (div << SDHC_SDCLK_DIV_SHIFT) 734 | (dvs << SDHC_SDCLK_DVS_SHIFT); 735 DPRINTF(2, 736 ("%s: divisor for freq %u is %u * %u\n", 737 HDEVNAME(hp), freq, div * 2, dvs + 1)); 738 //freq = hp->clkbase / (div * 2) * (dvs + 1); 739 return true; 740 } 741 /* 742 * If we drop bits, we need to round up the divisor. 743 */ 744 roundup |= dvs & 1; 745 } 746 /* No divisor found. */ 747 return false; 748 } else { 749 for (div = 1; div <= 256; div *= 2) { 750 if ((hp->clkbase / div) <= freq) { 751 *divp = (div / 2) << SDHC_SDCLK_DIV_SHIFT; 752 //freq = hp->clkbase / div; 753 return true; 754 } 755 } 756 } 757 /* No divisor found. */ 758 return false; 759 } 760 761 /* 762 * Set or change SDCLK frequency or disable the SD clock. 763 * Return zero on success. 764 */ 765 static int 766 sdhc_bus_clock(sdmmc_chipset_handle_t sch, int freq) 767 { 768 struct sdhc_host *hp = (struct sdhc_host *)sch; 769 u_int div; 770 u_int timo; 771 int error = 0; 772 #ifdef DIAGNOSTIC 773 bool present; 774 775 mutex_enter(&hp->host_mtx); 776 present = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CMD_INHIBIT_MASK); 777 mutex_exit(&hp->host_mtx); 778 779 /* Must not stop the clock if commands are in progress. */ 780 if (present && sdhc_card_detect(hp)) { 781 printf("%s: sdhc_sdclk_frequency_select: command in progress\n", 782 device_xname(hp->sc->sc_dev)); 783 } 784 #endif 785 786 mutex_enter(&hp->host_mtx); 787 788 /* 789 * Stop SD clock before changing the frequency. 790 */ 791 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 792 HCLR4(hp, SDHC_CLOCK_CTL, 0xfff8); 793 if (freq == SDMMC_SDCLK_OFF) { 794 HSET4(hp, SDHC_CLOCK_CTL, 0x80f0); 795 goto out; 796 } 797 } else { 798 HWRITE2(hp, SDHC_CLOCK_CTL, 0); 799 if (freq == SDMMC_SDCLK_OFF) 800 goto out; 801 } 802 803 /* 804 * Set the minimum base clock frequency divisor. 805 */ 806 if (!sdhc_clock_divisor(hp, freq, &div)) { 807 /* Invalid base clock frequency or `freq' value. */ 808 error = EINVAL; 809 goto out; 810 } 811 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 812 HWRITE4(hp, SDHC_CLOCK_CTL, 813 div | (SDHC_TIMEOUT_MAX << 16)); 814 } else { 815 HWRITE2(hp, SDHC_CLOCK_CTL, div); 816 } 817 818 /* 819 * Start internal clock. Wait 10ms for stabilization. 820 */ 821 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 822 sdmmc_delay(10000); 823 HSET4(hp, SDHC_CLOCK_CTL, 824 8 | SDHC_INTCLK_ENABLE | SDHC_INTCLK_STABLE); 825 } else { 826 HSET2(hp, SDHC_CLOCK_CTL, SDHC_INTCLK_ENABLE); 827 for (timo = 1000; timo > 0; timo--) { 828 if (ISSET(HREAD2(hp, SDHC_CLOCK_CTL), 829 SDHC_INTCLK_STABLE)) 830 break; 831 sdmmc_delay(10); 832 } 833 if (timo == 0) { 834 error = ETIMEDOUT; 835 goto out; 836 } 837 } 838 839 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 840 HSET1(hp, SDHC_SOFTWARE_RESET, SDHC_INIT_ACTIVE); 841 /* 842 * Sending 80 clocks at 400kHz takes 200us. 843 * So delay for that time + slop and then 844 * check a few times for completion. 845 */ 846 sdmmc_delay(210); 847 for (timo = 10; timo > 0; timo--) { 848 if (!ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), 849 SDHC_INIT_ACTIVE)) 850 break; 851 sdmmc_delay(10); 852 } 853 DPRINTF(2,("%s: %u init spins\n", __func__, 10 - timo)); 854 855 /* 856 * Enable SD clock. 857 */ 858 HSET4(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE); 859 } else { 860 /* 861 * Enable SD clock. 862 */ 863 HSET2(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE); 864 865 if (freq > 25000) 866 HSET1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED); 867 else 868 HCLR1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED); 869 } 870 871 out: 872 mutex_exit(&hp->host_mtx); 873 874 return error; 875 } 876 877 static int 878 sdhc_bus_width(sdmmc_chipset_handle_t sch, int width) 879 { 880 struct sdhc_host *hp = (struct sdhc_host *)sch; 881 int reg; 882 883 switch (width) { 884 case 1: 885 case 4: 886 break; 887 888 case 8: 889 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_8BIT_MODE)) 890 break; 891 /* FALLTHROUGH */ 892 default: 893 DPRINTF(0,("%s: unsupported bus width (%d)\n", 894 HDEVNAME(hp), width)); 895 return 1; 896 } 897 898 mutex_enter(&hp->host_mtx); 899 reg = HREAD1(hp, SDHC_HOST_CTL); 900 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 901 reg &= ~(SDHC_4BIT_MODE|SDHC_ESDHC_8BIT_MODE); 902 if (width == 4) 903 reg |= SDHC_4BIT_MODE; 904 else if (width == 8) 905 reg |= SDHC_ESDHC_8BIT_MODE; 906 } else { 907 reg &= ~SDHC_4BIT_MODE; 908 if (width == 4) 909 reg |= SDHC_4BIT_MODE; 910 } 911 HWRITE1(hp, SDHC_HOST_CTL, reg); 912 mutex_exit(&hp->host_mtx); 913 914 return 0; 915 } 916 917 static int 918 sdhc_bus_rod(sdmmc_chipset_handle_t sch, int on) 919 { 920 921 /* Nothing ?? */ 922 return 0; 923 } 924 925 static void 926 sdhc_card_enable_intr(sdmmc_chipset_handle_t sch, int enable) 927 { 928 struct sdhc_host *hp = (struct sdhc_host *)sch; 929 930 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 931 mutex_enter(&hp->host_mtx); 932 if (enable) { 933 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 934 HSET2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT); 935 } else { 936 HCLR2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT); 937 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 938 } 939 mutex_exit(&hp->host_mtx); 940 } 941 } 942 943 static void 944 sdhc_card_intr_ack(sdmmc_chipset_handle_t sch) 945 { 946 struct sdhc_host *hp = (struct sdhc_host *)sch; 947 948 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 949 mutex_enter(&hp->host_mtx); 950 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 951 mutex_exit(&hp->host_mtx); 952 } 953 } 954 955 static int 956 sdhc_wait_state(struct sdhc_host *hp, uint32_t mask, uint32_t value) 957 { 958 uint32_t state; 959 int timeout; 960 961 for (timeout = 10; timeout > 0; timeout--) { 962 if (((state = HREAD4(hp, SDHC_PRESENT_STATE)) & mask) == value) 963 return 0; 964 sdmmc_delay(10000); 965 } 966 DPRINTF(0,("%s: timeout waiting for %x (state=%x)\n", HDEVNAME(hp), 967 value, state)); 968 return ETIMEDOUT; 969 } 970 971 static void 972 sdhc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 973 { 974 struct sdhc_host *hp = (struct sdhc_host *)sch; 975 int error; 976 977 #if 0 978 if (cmd->c_data) { 979 const uint16_t ready = SDHC_BUFFER_READ_READY | SDHC_BUFFER_WRITE_READY; 980 if (ISSET(hp->flags, SHF_USE_DMA)) { 981 HCLR2(hp, SDHC_NINTR_SIGNAL_EN, ready); 982 HCLR2(hp, SDHC_NINTR_STATUS_EN, ready); 983 } else { 984 HSET2(hp, SDHC_NINTR_SIGNAL_EN, ready); 985 HSET2(hp, SDHC_NINTR_STATUS_EN, ready); 986 } 987 } 988 #endif 989 990 /* 991 * Start the MMC command, or mark `cmd' as failed and return. 992 */ 993 error = sdhc_start_command(hp, cmd); 994 if (error) { 995 cmd->c_error = error; 996 goto out; 997 } 998 999 /* 1000 * Wait until the command phase is done, or until the command 1001 * is marked done for any other reason. 1002 */ 1003 if (!sdhc_wait_intr(hp, SDHC_COMMAND_COMPLETE, SDHC_COMMAND_TIMEOUT)) { 1004 cmd->c_error = ETIMEDOUT; 1005 goto out; 1006 } 1007 1008 /* 1009 * The host controller removes bits [0:7] from the response 1010 * data (CRC) and we pass the data up unchanged to the bus 1011 * driver (without padding). 1012 */ 1013 mutex_enter(&hp->host_mtx); 1014 if (cmd->c_error == 0 && ISSET(cmd->c_flags, SCF_RSP_PRESENT)) { 1015 cmd->c_resp[0] = HREAD4(hp, SDHC_RESPONSE + 0); 1016 if (ISSET(cmd->c_flags, SCF_RSP_136)) { 1017 cmd->c_resp[1] = HREAD4(hp, SDHC_RESPONSE + 4); 1018 cmd->c_resp[2] = HREAD4(hp, SDHC_RESPONSE + 8); 1019 cmd->c_resp[3] = HREAD4(hp, SDHC_RESPONSE + 12); 1020 } 1021 } 1022 mutex_exit(&hp->host_mtx); 1023 DPRINTF(1,("%s: resp = %08x\n", HDEVNAME(hp), be32toh(cmd->c_resp[0]))); 1024 1025 /* 1026 * If the command has data to transfer in any direction, 1027 * execute the transfer now. 1028 */ 1029 if (cmd->c_error == 0 && cmd->c_data != NULL) 1030 sdhc_transfer_data(hp, cmd); 1031 1032 out: 1033 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED) 1034 && !ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_LED_ON)) { 1035 mutex_enter(&hp->host_mtx); 1036 /* Turn off the LED. */ 1037 HCLR1(hp, SDHC_HOST_CTL, SDHC_LED_ON); 1038 mutex_exit(&hp->host_mtx); 1039 } 1040 SET(cmd->c_flags, SCF_ITSDONE); 1041 1042 DPRINTF(1,("%s: cmd %d %s (flags=%08x error=%d)\n", HDEVNAME(hp), 1043 cmd->c_opcode, (cmd->c_error == 0) ? "done" : "abort", 1044 cmd->c_flags, cmd->c_error)); 1045 } 1046 1047 static int 1048 sdhc_start_command(struct sdhc_host *hp, struct sdmmc_command *cmd) 1049 { 1050 struct sdhc_softc * const sc = hp->sc; 1051 uint16_t blksize = 0; 1052 uint16_t blkcount = 0; 1053 uint16_t mode; 1054 uint16_t command; 1055 int error; 1056 1057 DPRINTF(1,("%s: start cmd %d arg=%08x data=%p dlen=%d flags=%08x, status=%#x\n", 1058 HDEVNAME(hp), cmd->c_opcode, cmd->c_arg, cmd->c_data, 1059 cmd->c_datalen, cmd->c_flags, HREAD4(hp, SDHC_NINTR_STATUS))); 1060 1061 /* 1062 * The maximum block length for commands should be the minimum 1063 * of the host buffer size and the card buffer size. (1.7.2) 1064 */ 1065 1066 /* Fragment the data into proper blocks. */ 1067 if (cmd->c_datalen > 0) { 1068 blksize = MIN(cmd->c_datalen, cmd->c_blklen); 1069 blkcount = cmd->c_datalen / blksize; 1070 if (cmd->c_datalen % blksize > 0) { 1071 /* XXX: Split this command. (1.7.4) */ 1072 aprint_error_dev(sc->sc_dev, 1073 "data not a multiple of %u bytes\n", blksize); 1074 return EINVAL; 1075 } 1076 } 1077 1078 /* Check limit imposed by 9-bit block count. (1.7.2) */ 1079 if (blkcount > SDHC_BLOCK_COUNT_MAX) { 1080 aprint_error_dev(sc->sc_dev, "too much data\n"); 1081 return EINVAL; 1082 } 1083 1084 /* Prepare transfer mode register value. (2.2.5) */ 1085 mode = SDHC_BLOCK_COUNT_ENABLE; 1086 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 1087 mode |= SDHC_READ_MODE; 1088 if (blkcount > 1) { 1089 mode |= SDHC_MULTI_BLOCK_MODE; 1090 /* XXX only for memory commands? */ 1091 mode |= SDHC_AUTO_CMD12_ENABLE; 1092 } 1093 if (cmd->c_dmamap != NULL && cmd->c_datalen > 0) { 1094 mode |= SDHC_DMA_ENABLE; 1095 } 1096 1097 /* 1098 * Prepare command register value. (2.2.6) 1099 */ 1100 command = (cmd->c_opcode & SDHC_COMMAND_INDEX_MASK) << SDHC_COMMAND_INDEX_SHIFT; 1101 1102 if (ISSET(cmd->c_flags, SCF_RSP_CRC)) 1103 command |= SDHC_CRC_CHECK_ENABLE; 1104 if (ISSET(cmd->c_flags, SCF_RSP_IDX)) 1105 command |= SDHC_INDEX_CHECK_ENABLE; 1106 if (cmd->c_data != NULL) 1107 command |= SDHC_DATA_PRESENT_SELECT; 1108 1109 if (!ISSET(cmd->c_flags, SCF_RSP_PRESENT)) 1110 command |= SDHC_NO_RESPONSE; 1111 else if (ISSET(cmd->c_flags, SCF_RSP_136)) 1112 command |= SDHC_RESP_LEN_136; 1113 else if (ISSET(cmd->c_flags, SCF_RSP_BSY)) 1114 command |= SDHC_RESP_LEN_48_CHK_BUSY; 1115 else 1116 command |= SDHC_RESP_LEN_48; 1117 1118 /* Wait until command and data inhibit bits are clear. (1.5) */ 1119 error = sdhc_wait_state(hp, SDHC_CMD_INHIBIT_MASK, 0); 1120 if (error) 1121 return error; 1122 1123 DPRINTF(1,("%s: writing cmd: blksize=%d blkcnt=%d mode=%04x cmd=%04x\n", 1124 HDEVNAME(hp), blksize, blkcount, mode, command)); 1125 1126 blksize |= (MAX(0, PAGE_SHIFT - 12) & SDHC_DMA_BOUNDARY_MASK) << 1127 SDHC_DMA_BOUNDARY_SHIFT; /* PAGE_SIZE DMA boundary */ 1128 1129 mutex_enter(&hp->host_mtx); 1130 1131 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1132 /* Alert the user not to remove the card. */ 1133 HSET1(hp, SDHC_HOST_CTL, SDHC_LED_ON); 1134 } 1135 1136 /* Set DMA start address. */ 1137 if (ISSET(mode, SDHC_DMA_ENABLE)) 1138 HWRITE4(hp, SDHC_DMA_ADDR, cmd->c_dmamap->dm_segs[0].ds_addr); 1139 1140 /* 1141 * Start a CPU data transfer. Writing to the high order byte 1142 * of the SDHC_COMMAND register triggers the SD command. (1.5) 1143 */ 1144 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 1145 HWRITE4(hp, SDHC_BLOCK_SIZE, blksize | (blkcount << 16)); 1146 HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg); 1147 HWRITE4(hp, SDHC_TRANSFER_MODE, mode | (command << 16)); 1148 } else { 1149 HWRITE2(hp, SDHC_BLOCK_SIZE, blksize); 1150 HWRITE2(hp, SDHC_BLOCK_COUNT, blkcount); 1151 HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg); 1152 HWRITE2(hp, SDHC_TRANSFER_MODE, mode); 1153 HWRITE2(hp, SDHC_COMMAND, command); 1154 } 1155 1156 mutex_exit(&hp->host_mtx); 1157 1158 return 0; 1159 } 1160 1161 static void 1162 sdhc_transfer_data(struct sdhc_host *hp, struct sdmmc_command *cmd) 1163 { 1164 int error; 1165 1166 DPRINTF(1,("%s: data transfer: resp=%08x datalen=%u\n", HDEVNAME(hp), 1167 MMC_R1(cmd->c_resp), cmd->c_datalen)); 1168 1169 #ifdef SDHC_DEBUG 1170 /* XXX I forgot why I wanted to know when this happens :-( */ 1171 if ((cmd->c_opcode == 52 || cmd->c_opcode == 53) && 1172 ISSET(MMC_R1(cmd->c_resp), 0xcb00)) { 1173 aprint_error_dev(hp->sc->sc_dev, 1174 "CMD52/53 error response flags %#x\n", 1175 MMC_R1(cmd->c_resp) & 0xff00); 1176 } 1177 #endif 1178 1179 if (cmd->c_dmamap != NULL) 1180 error = sdhc_transfer_data_dma(hp, cmd); 1181 else 1182 error = sdhc_transfer_data_pio(hp, cmd); 1183 if (error) 1184 cmd->c_error = error; 1185 SET(cmd->c_flags, SCF_ITSDONE); 1186 1187 DPRINTF(1,("%s: data transfer done (error=%d)\n", 1188 HDEVNAME(hp), cmd->c_error)); 1189 } 1190 1191 static int 1192 sdhc_transfer_data_dma(struct sdhc_host *hp, struct sdmmc_command *cmd) 1193 { 1194 bus_dma_segment_t *dm_segs = cmd->c_dmamap->dm_segs; 1195 bus_addr_t posaddr; 1196 bus_addr_t segaddr; 1197 bus_size_t seglen; 1198 u_int seg = 0; 1199 int error = 0; 1200 int status; 1201 1202 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_DMA_INTERRUPT); 1203 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_DMA_INTERRUPT); 1204 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_TRANSFER_COMPLETE); 1205 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_TRANSFER_COMPLETE); 1206 1207 for (;;) { 1208 status = sdhc_wait_intr(hp, 1209 SDHC_DMA_INTERRUPT|SDHC_TRANSFER_COMPLETE, 1210 SDHC_DMA_TIMEOUT); 1211 1212 if (status & SDHC_TRANSFER_COMPLETE) { 1213 break; 1214 } 1215 if (!status) { 1216 error = ETIMEDOUT; 1217 break; 1218 } 1219 if ((status & SDHC_DMA_INTERRUPT) == 0) { 1220 continue; 1221 } 1222 1223 /* DMA Interrupt (boundary crossing) */ 1224 1225 segaddr = dm_segs[seg].ds_addr; 1226 seglen = dm_segs[seg].ds_len; 1227 mutex_enter(&hp->host_mtx); 1228 posaddr = HREAD4(hp, SDHC_DMA_ADDR); 1229 mutex_exit(&hp->host_mtx); 1230 1231 if ((seg == (cmd->c_dmamap->dm_nsegs-1)) && (posaddr == (segaddr + seglen))) { 1232 break; 1233 } 1234 mutex_enter(&hp->host_mtx); 1235 if ((posaddr >= segaddr) && (posaddr < (segaddr + seglen))) 1236 HWRITE4(hp, SDHC_DMA_ADDR, posaddr); 1237 else if ((posaddr >= segaddr) && (posaddr == (segaddr + seglen)) && (seg + 1) < cmd->c_dmamap->dm_nsegs) 1238 HWRITE4(hp, SDHC_DMA_ADDR, dm_segs[++seg].ds_addr); 1239 mutex_exit(&hp->host_mtx); 1240 KASSERT(seg < cmd->c_dmamap->dm_nsegs); 1241 } 1242 1243 return error; 1244 } 1245 1246 static int 1247 sdhc_transfer_data_pio(struct sdhc_host *hp, struct sdmmc_command *cmd) 1248 { 1249 uint8_t *data = cmd->c_data; 1250 void (*pio_func)(struct sdhc_host *, uint8_t *, u_int); 1251 u_int len, datalen; 1252 u_int imask; 1253 u_int pmask; 1254 int error = 0; 1255 1256 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 1257 imask = SDHC_BUFFER_READ_READY; 1258 pmask = SDHC_BUFFER_READ_ENABLE; 1259 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1260 pio_func = esdhc_read_data_pio; 1261 } else { 1262 pio_func = sdhc_read_data_pio; 1263 } 1264 } else { 1265 imask = SDHC_BUFFER_WRITE_READY; 1266 pmask = SDHC_BUFFER_WRITE_ENABLE; 1267 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1268 pio_func = esdhc_write_data_pio; 1269 } else { 1270 pio_func = sdhc_write_data_pio; 1271 } 1272 } 1273 datalen = cmd->c_datalen; 1274 1275 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & imask); 1276 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_TRANSFER_COMPLETE); 1277 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_TRANSFER_COMPLETE); 1278 1279 while (datalen > 0) { 1280 if (!ISSET(HREAD4(hp, SDHC_PRESENT_STATE), imask)) { 1281 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 1282 HSET4(hp, SDHC_NINTR_SIGNAL_EN, imask); 1283 } else { 1284 HSET2(hp, SDHC_NINTR_SIGNAL_EN, imask); 1285 } 1286 if (!sdhc_wait_intr(hp, imask, SDHC_BUFFER_TIMEOUT)) { 1287 error = ETIMEDOUT; 1288 break; 1289 } 1290 1291 error = sdhc_wait_state(hp, pmask, pmask); 1292 if (error) 1293 break; 1294 } 1295 1296 len = MIN(datalen, cmd->c_blklen); 1297 (*pio_func)(hp, data, len); 1298 DPRINTF(2,("%s: pio data transfer %u @ %p\n", 1299 HDEVNAME(hp), len, data)); 1300 1301 data += len; 1302 datalen -= len; 1303 } 1304 1305 if (error == 0 && !sdhc_wait_intr(hp, SDHC_TRANSFER_COMPLETE, 1306 SDHC_TRANSFER_TIMEOUT)) 1307 error = ETIMEDOUT; 1308 1309 return error; 1310 } 1311 1312 static void 1313 sdhc_read_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1314 { 1315 1316 if (((__uintptr_t)data & 3) == 0) { 1317 while (datalen > 3) { 1318 *(uint32_t *)data = HREAD4(hp, SDHC_DATA); 1319 data += 4; 1320 datalen -= 4; 1321 } 1322 if (datalen > 1) { 1323 *(uint16_t *)data = HREAD2(hp, SDHC_DATA); 1324 data += 2; 1325 datalen -= 2; 1326 } 1327 if (datalen > 0) { 1328 *data = HREAD1(hp, SDHC_DATA); 1329 data += 1; 1330 datalen -= 1; 1331 } 1332 } else if (((__uintptr_t)data & 1) == 0) { 1333 while (datalen > 1) { 1334 *(uint16_t *)data = HREAD2(hp, SDHC_DATA); 1335 data += 2; 1336 datalen -= 2; 1337 } 1338 if (datalen > 0) { 1339 *data = HREAD1(hp, SDHC_DATA); 1340 data += 1; 1341 datalen -= 1; 1342 } 1343 } else { 1344 while (datalen > 0) { 1345 *data = HREAD1(hp, SDHC_DATA); 1346 data += 1; 1347 datalen -= 1; 1348 } 1349 } 1350 } 1351 1352 static void 1353 sdhc_write_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1354 { 1355 1356 if (((__uintptr_t)data & 3) == 0) { 1357 while (datalen > 3) { 1358 HWRITE4(hp, SDHC_DATA, *(uint32_t *)data); 1359 data += 4; 1360 datalen -= 4; 1361 } 1362 if (datalen > 1) { 1363 HWRITE2(hp, SDHC_DATA, *(uint16_t *)data); 1364 data += 2; 1365 datalen -= 2; 1366 } 1367 if (datalen > 0) { 1368 HWRITE1(hp, SDHC_DATA, *data); 1369 data += 1; 1370 datalen -= 1; 1371 } 1372 } else if (((__uintptr_t)data & 1) == 0) { 1373 while (datalen > 1) { 1374 HWRITE2(hp, SDHC_DATA, *(uint16_t *)data); 1375 data += 2; 1376 datalen -= 2; 1377 } 1378 if (datalen > 0) { 1379 HWRITE1(hp, SDHC_DATA, *data); 1380 data += 1; 1381 datalen -= 1; 1382 } 1383 } else { 1384 while (datalen > 0) { 1385 HWRITE1(hp, SDHC_DATA, *data); 1386 data += 1; 1387 datalen -= 1; 1388 } 1389 } 1390 } 1391 1392 static void 1393 esdhc_read_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1394 { 1395 uint16_t status = HREAD2(hp, SDHC_NINTR_STATUS); 1396 uint32_t v; 1397 1398 const size_t watermark = (HREAD4(hp, SDHC_WATERMARK_LEVEL) >> SDHC_WATERMARK_READ_SHIFT) & SDHC_WATERMARK_READ_MASK; 1399 size_t count = 0; 1400 1401 while (datalen > 3 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1402 if (count == 0) { 1403 /* 1404 * If we've drained "watermark" words, we need to wait 1405 * a little bit so the read FIFO can refill. 1406 */ 1407 sdmmc_delay(10); 1408 count = watermark; 1409 } 1410 v = HREAD4(hp, SDHC_DATA); 1411 v = le32toh(v); 1412 *(uint32_t *)data = v; 1413 data += 4; 1414 datalen -= 4; 1415 status = HREAD2(hp, SDHC_NINTR_STATUS); 1416 count--; 1417 } 1418 if (datalen > 0 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1419 if (count == 0) { 1420 sdmmc_delay(10); 1421 } 1422 v = HREAD4(hp, SDHC_DATA); 1423 v = le32toh(v); 1424 do { 1425 *data++ = v; 1426 v >>= 8; 1427 } while (--datalen > 0); 1428 } 1429 } 1430 1431 static void 1432 esdhc_write_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1433 { 1434 uint16_t status = HREAD2(hp, SDHC_NINTR_STATUS); 1435 uint32_t v; 1436 1437 const size_t watermark = (HREAD4(hp, SDHC_WATERMARK_LEVEL) >> SDHC_WATERMARK_WRITE_SHIFT) & SDHC_WATERMARK_WRITE_MASK; 1438 size_t count = watermark; 1439 1440 while (datalen > 3 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1441 if (count == 0) { 1442 sdmmc_delay(10); 1443 count = watermark; 1444 } 1445 v = *(uint32_t *)data; 1446 v = htole32(v); 1447 HWRITE4(hp, SDHC_DATA, v); 1448 data += 4; 1449 datalen -= 4; 1450 status = HREAD2(hp, SDHC_NINTR_STATUS); 1451 count--; 1452 } 1453 if (datalen > 0 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1454 if (count == 0) { 1455 sdmmc_delay(10); 1456 } 1457 v = *(uint32_t *)data; 1458 v = htole32(v); 1459 HWRITE4(hp, SDHC_DATA, v); 1460 } 1461 } 1462 1463 /* Prepare for another command. */ 1464 static int 1465 sdhc_soft_reset(struct sdhc_host *hp, int mask) 1466 { 1467 int timo; 1468 1469 DPRINTF(1,("%s: software reset reg=%08x\n", HDEVNAME(hp), mask)); 1470 1471 HWRITE1(hp, SDHC_SOFTWARE_RESET, mask); 1472 for (timo = 10; timo > 0; timo--) { 1473 if (!ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), mask)) 1474 break; 1475 sdmmc_delay(10000); 1476 HWRITE1(hp, SDHC_SOFTWARE_RESET, 0); 1477 } 1478 if (timo == 0) { 1479 DPRINTF(1,("%s: timeout reg=%08x\n", HDEVNAME(hp), 1480 HREAD1(hp, SDHC_SOFTWARE_RESET))); 1481 HWRITE1(hp, SDHC_SOFTWARE_RESET, 0); 1482 return ETIMEDOUT; 1483 } 1484 1485 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1486 HWRITE4(hp, SDHC_DMA_CTL, SDHC_DMA_SNOOP); 1487 } 1488 1489 return 0; 1490 } 1491 1492 static int 1493 sdhc_wait_intr(struct sdhc_host *hp, int mask, int timo) 1494 { 1495 int status; 1496 1497 mask |= SDHC_ERROR_INTERRUPT; 1498 1499 mutex_enter(&hp->intr_mtx); 1500 status = hp->intr_status & mask; 1501 while (status == 0) { 1502 if (cv_timedwait(&hp->intr_cv, &hp->intr_mtx, timo) 1503 == EWOULDBLOCK) { 1504 status |= SDHC_ERROR_INTERRUPT; 1505 break; 1506 } 1507 status = hp->intr_status & mask; 1508 } 1509 hp->intr_status &= ~status; 1510 1511 DPRINTF(2,("%s: intr status %#x error %#x\n", HDEVNAME(hp), status, 1512 hp->intr_error_status)); 1513 1514 /* Command timeout has higher priority than command complete. */ 1515 if (ISSET(status, SDHC_ERROR_INTERRUPT) || hp->intr_error_status) { 1516 hp->intr_error_status = 0; 1517 hp->intr_status &= ~SDHC_ERROR_INTERRUPT; 1518 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1519 (void)sdhc_soft_reset(hp, SDHC_RESET_DAT|SDHC_RESET_CMD); 1520 } 1521 status = 0; 1522 } 1523 mutex_exit(&hp->intr_mtx); 1524 1525 return status; 1526 } 1527 1528 /* 1529 * Established by attachment driver at interrupt priority IPL_SDMMC. 1530 */ 1531 int 1532 sdhc_intr(void *arg) 1533 { 1534 struct sdhc_softc *sc = (struct sdhc_softc *)arg; 1535 struct sdhc_host *hp; 1536 int done = 0; 1537 uint16_t status; 1538 uint16_t error; 1539 1540 /* We got an interrupt, but we don't know from which slot. */ 1541 for (size_t host = 0; host < sc->sc_nhosts; host++) { 1542 hp = sc->sc_host[host]; 1543 if (hp == NULL) 1544 continue; 1545 1546 if (ISSET(sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 1547 /* Find out which interrupts are pending. */ 1548 uint32_t xstatus = HREAD4(hp, SDHC_NINTR_STATUS); 1549 status = xstatus; 1550 error = xstatus >> 16; 1551 if (error) 1552 xstatus |= SDHC_ERROR_INTERRUPT; 1553 else if (!ISSET(status, SDHC_NINTR_STATUS_MASK)) 1554 continue; /* no interrupt for us */ 1555 /* Acknowledge the interrupts we are about to handle. */ 1556 HWRITE4(hp, SDHC_NINTR_STATUS, xstatus); 1557 } else { 1558 /* Find out which interrupts are pending. */ 1559 error = 0; 1560 status = HREAD2(hp, SDHC_NINTR_STATUS); 1561 if (!ISSET(status, SDHC_NINTR_STATUS_MASK)) 1562 continue; /* no interrupt for us */ 1563 /* Acknowledge the interrupts we are about to handle. */ 1564 HWRITE2(hp, SDHC_NINTR_STATUS, status); 1565 if (ISSET(status, SDHC_ERROR_INTERRUPT)) { 1566 /* Acknowledge error interrupts. */ 1567 error = HREAD2(hp, SDHC_EINTR_STATUS); 1568 HWRITE2(hp, SDHC_EINTR_STATUS, error); 1569 } 1570 } 1571 1572 DPRINTF(2,("%s: interrupt status=%x error=%x\n", HDEVNAME(hp), 1573 status, error)); 1574 1575 /* Claim this interrupt. */ 1576 done = 1; 1577 1578 /* 1579 * Service error interrupts. 1580 */ 1581 if (ISSET(error, SDHC_CMD_TIMEOUT_ERROR| 1582 SDHC_DATA_TIMEOUT_ERROR)) { 1583 hp->intr_error_status |= error; 1584 hp->intr_status |= status; 1585 cv_broadcast(&hp->intr_cv); 1586 } 1587 1588 /* 1589 * Wake up the sdmmc event thread to scan for cards. 1590 */ 1591 if (ISSET(status, SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)) { 1592 sdmmc_needs_discover(hp->sdmmc); 1593 if (ISSET(sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1594 HCLR4(hp, SDHC_NINTR_STATUS_EN, 1595 status & (SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)); 1596 HCLR4(hp, SDHC_NINTR_SIGNAL_EN, 1597 status & (SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)); 1598 } 1599 } 1600 1601 /* 1602 * Wake up the blocking process to service command 1603 * related interrupt(s). 1604 */ 1605 if (ISSET(status, SDHC_COMMAND_COMPLETE| 1606 SDHC_BUFFER_READ_READY|SDHC_BUFFER_WRITE_READY| 1607 SDHC_TRANSFER_COMPLETE|SDHC_DMA_INTERRUPT)) { 1608 hp->intr_status |= status; 1609 if (ISSET(sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1610 HCLR4(hp, SDHC_NINTR_SIGNAL_EN, 1611 status & (SDHC_BUFFER_READ_READY|SDHC_BUFFER_WRITE_READY)); 1612 } 1613 cv_broadcast(&hp->intr_cv); 1614 } 1615 1616 /* 1617 * Service SD card interrupts. 1618 */ 1619 if (!ISSET(sc->sc_flags, SDHC_FLAG_ENHANCED) 1620 && ISSET(status, SDHC_CARD_INTERRUPT)) { 1621 DPRINTF(0,("%s: card interrupt\n", HDEVNAME(hp))); 1622 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 1623 sdmmc_card_intr(hp->sdmmc); 1624 } 1625 } 1626 1627 return done; 1628 } 1629 1630 #ifdef SDHC_DEBUG 1631 void 1632 sdhc_dump_regs(struct sdhc_host *hp) 1633 { 1634 1635 printf("0x%02x PRESENT_STATE: %x\n", SDHC_PRESENT_STATE, 1636 HREAD4(hp, SDHC_PRESENT_STATE)); 1637 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 1638 printf("0x%02x POWER_CTL: %x\n", SDHC_POWER_CTL, 1639 HREAD1(hp, SDHC_POWER_CTL)); 1640 printf("0x%02x NINTR_STATUS: %x\n", SDHC_NINTR_STATUS, 1641 HREAD2(hp, SDHC_NINTR_STATUS)); 1642 printf("0x%02x EINTR_STATUS: %x\n", SDHC_EINTR_STATUS, 1643 HREAD2(hp, SDHC_EINTR_STATUS)); 1644 printf("0x%02x NINTR_STATUS_EN: %x\n", SDHC_NINTR_STATUS_EN, 1645 HREAD2(hp, SDHC_NINTR_STATUS_EN)); 1646 printf("0x%02x EINTR_STATUS_EN: %x\n", SDHC_EINTR_STATUS_EN, 1647 HREAD2(hp, SDHC_EINTR_STATUS_EN)); 1648 printf("0x%02x NINTR_SIGNAL_EN: %x\n", SDHC_NINTR_SIGNAL_EN, 1649 HREAD2(hp, SDHC_NINTR_SIGNAL_EN)); 1650 printf("0x%02x EINTR_SIGNAL_EN: %x\n", SDHC_EINTR_SIGNAL_EN, 1651 HREAD2(hp, SDHC_EINTR_SIGNAL_EN)); 1652 printf("0x%02x CAPABILITIES: %x\n", SDHC_CAPABILITIES, 1653 HREAD4(hp, SDHC_CAPABILITIES)); 1654 printf("0x%02x MAX_CAPABILITIES: %x\n", SDHC_MAX_CAPABILITIES, 1655 HREAD4(hp, SDHC_MAX_CAPABILITIES)); 1656 } 1657 #endif 1658
Indexes created Thu Sep 25 06:09:39 GMT 2025