sdhc.c revision 1.26
1 /* $NetBSD: sdhc.c,v 1.26 2012/07/26 18:36:09 matt Exp $ */ 2 /* $OpenBSD: sdhc.c,v 1.25 2009/01/13 19:44:20 grange Exp $ */ 3 4 /* 5 * Copyright (c) 2006 Uwe Stuehler <uwe (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * SD Host Controller driver based on the SD Host Controller Standard 22 * Simplified Specification Version 1.00 (www.sdcard.com). 23 */ 24 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: sdhc.c,v 1.26 2012/07/26 18:36:09 matt Exp $"); 27 28 #ifdef _KERNEL_OPT 29 #include "opt_sdmmc.h" 30 #endif 31 32 #include <sys/param.h> 33 #include <sys/device.h> 34 #include <sys/kernel.h> 35 #include <sys/kthread.h> 36 #include <sys/malloc.h> 37 #include <sys/systm.h> 38 #include <sys/mutex.h> 39 #include <sys/condvar.h> 40 41 #include <dev/sdmmc/sdhcreg.h> 42 #include <dev/sdmmc/sdhcvar.h> 43 #include <dev/sdmmc/sdmmcchip.h> 44 #include <dev/sdmmc/sdmmcreg.h> 45 #include <dev/sdmmc/sdmmcvar.h> 46 47 #ifdef SDHC_DEBUG 48 int sdhcdebug = 1; 49 #define DPRINTF(n,s) do { if ((n) <= sdhcdebug) printf s; } while (0) 50 void sdhc_dump_regs(struct sdhc_host *); 51 #else 52 #define DPRINTF(n,s) do {} while (0) 53 #endif 54 55 #define SDHC_COMMAND_TIMEOUT hz 56 #define SDHC_BUFFER_TIMEOUT hz 57 #define SDHC_TRANSFER_TIMEOUT hz 58 #define SDHC_DMA_TIMEOUT hz 59 60 struct sdhc_host { 61 struct sdhc_softc *sc; /* host controller device */ 62 63 bus_space_tag_t iot; /* host register set tag */ 64 bus_space_handle_t ioh; /* host register set handle */ 65 bus_dma_tag_t dmat; /* host DMA tag */ 66 67 device_t sdmmc; /* generic SD/MMC device */ 68 69 struct kmutex host_mtx; 70 71 u_int clkbase; /* base clock frequency in KHz */ 72 int maxblklen; /* maximum block length */ 73 uint32_t ocr; /* OCR value from capabilities */ 74 75 uint8_t regs[14]; /* host controller state */ 76 77 uint16_t intr_status; /* soft interrupt status */ 78 uint16_t intr_error_status; /* soft error status */ 79 struct kmutex intr_mtx; 80 struct kcondvar intr_cv; 81 82 int specver; /* spec. version */ 83 84 uint32_t flags; /* flags for this host */ 85 #define SHF_USE_DMA 0x0001 86 #define SHF_USE_4BIT_MODE 0x0002 87 #define SHF_USE_8BIT_MODE 0x0004 88 }; 89 90 #define HDEVNAME(hp) (device_xname((hp)->sc->sc_dev)) 91 #define HDEVINST(hp) ((int)(((hp)-(hp)->sc->sc_host[0])/sizeof(*(hp)))) 92 93 static uint8_t 94 hread1(struct sdhc_host *hp, bus_size_t reg) 95 { 96 97 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) 98 return bus_space_read_1(hp->iot, hp->ioh, reg); 99 return bus_space_read_4(hp->iot, hp->ioh, reg & -4) >> (8 * (reg & 3)); 100 } 101 102 static uint16_t 103 hread2(struct sdhc_host *hp, bus_size_t reg) 104 { 105 106 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) 107 return bus_space_read_2(hp->iot, hp->ioh, reg); 108 return bus_space_read_4(hp->iot, hp->ioh, reg & -4) >> (8 * (reg & 2)); 109 } 110 111 #define HREAD1(hp, reg) hread1(hp, reg) 112 #define HREAD2(hp, reg) hread2(hp, reg) 113 #define HREAD4(hp, reg) \ 114 (bus_space_read_4((hp)->iot, (hp)->ioh, (reg))) 115 116 117 static void 118 hwrite1(struct sdhc_host *hp, bus_size_t o, uint8_t val) 119 { 120 121 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 122 bus_space_write_1(hp->iot, hp->ioh, o, val); 123 } else { 124 const size_t shift = 8 * (o & 3); 125 o &= -4; 126 uint32_t tmp = bus_space_read_4(hp->iot, hp->ioh, o); 127 tmp = (val << shift) | (tmp & ~(0xff << shift)); 128 bus_space_write_4(hp->iot, hp->ioh, o, tmp); 129 } 130 } 131 132 static void 133 hwrite2(struct sdhc_host *hp, bus_size_t o, uint16_t val) 134 { 135 136 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 137 bus_space_write_2(hp->iot, hp->ioh, o, val); 138 } else { 139 const size_t shift = 8 * (o & 2); 140 o &= -4; 141 uint32_t tmp = bus_space_read_4(hp->iot, hp->ioh, o); 142 tmp = (val << shift) | (tmp & ~(0xffff << shift)); 143 bus_space_write_4(hp->iot, hp->ioh, o, tmp); 144 } 145 } 146 147 #define HWRITE1(hp, reg, val) hwrite1(hp, reg, val) 148 #define HWRITE2(hp, reg, val) hwrite2(hp, reg, val) 149 #define HWRITE4(hp, reg, val) \ 150 bus_space_write_4((hp)->iot, (hp)->ioh, (reg), (val)) 151 152 #define HCLR1(hp, reg, bits) \ 153 do if (bits) HWRITE1((hp), (reg), HREAD1((hp), (reg)) & ~(bits)); while (0) 154 #define HCLR2(hp, reg, bits) \ 155 do if (bits) HWRITE2((hp), (reg), HREAD2((hp), (reg)) & ~(bits)); while (0) 156 #define HCLR4(hp, reg, bits) \ 157 do if (bits) HWRITE4((hp), (reg), HREAD4((hp), (reg)) & ~(bits)); while (0) 158 #define HSET1(hp, reg, bits) \ 159 do if (bits) HWRITE1((hp), (reg), HREAD1((hp), (reg)) | (bits)); while (0) 160 #define HSET2(hp, reg, bits) \ 161 do if (bits) HWRITE2((hp), (reg), HREAD2((hp), (reg)) | (bits)); while (0) 162 #define HSET4(hp, reg, bits) \ 163 do if (bits) HWRITE4((hp), (reg), HREAD4((hp), (reg)) | (bits)); while (0) 164 165 static int sdhc_host_reset(sdmmc_chipset_handle_t); 166 static int sdhc_host_reset1(sdmmc_chipset_handle_t); 167 static uint32_t sdhc_host_ocr(sdmmc_chipset_handle_t); 168 static int sdhc_host_maxblklen(sdmmc_chipset_handle_t); 169 static int sdhc_card_detect(sdmmc_chipset_handle_t); 170 static int sdhc_write_protect(sdmmc_chipset_handle_t); 171 static int sdhc_bus_power(sdmmc_chipset_handle_t, uint32_t); 172 static int sdhc_bus_clock(sdmmc_chipset_handle_t, int); 173 static int sdhc_bus_width(sdmmc_chipset_handle_t, int); 174 static int sdhc_bus_rod(sdmmc_chipset_handle_t, int); 175 static void sdhc_card_enable_intr(sdmmc_chipset_handle_t, int); 176 static void sdhc_card_intr_ack(sdmmc_chipset_handle_t); 177 static void sdhc_exec_command(sdmmc_chipset_handle_t, 178 struct sdmmc_command *); 179 static int sdhc_start_command(struct sdhc_host *, struct sdmmc_command *); 180 static int sdhc_wait_state(struct sdhc_host *, uint32_t, uint32_t); 181 static int sdhc_soft_reset(struct sdhc_host *, int); 182 static int sdhc_wait_intr(struct sdhc_host *, int, int); 183 static void sdhc_transfer_data(struct sdhc_host *, struct sdmmc_command *); 184 static int sdhc_transfer_data_dma(struct sdhc_host *, struct sdmmc_command *); 185 static int sdhc_transfer_data_pio(struct sdhc_host *, struct sdmmc_command *); 186 static void sdhc_read_data_pio(struct sdhc_host *, uint8_t *, u_int); 187 static void sdhc_write_data_pio(struct sdhc_host *, uint8_t *, u_int); 188 static void esdhc_read_data_pio(struct sdhc_host *, uint8_t *, u_int); 189 static void esdhc_write_data_pio(struct sdhc_host *, uint8_t *, u_int); 190 191 192 static struct sdmmc_chip_functions sdhc_functions = { 193 /* host controller reset */ 194 sdhc_host_reset, 195 196 /* host controller capabilities */ 197 sdhc_host_ocr, 198 sdhc_host_maxblklen, 199 200 /* card detection */ 201 sdhc_card_detect, 202 203 /* write protect */ 204 sdhc_write_protect, 205 206 /* bus power, clock frequency and width */ 207 sdhc_bus_power, 208 sdhc_bus_clock, 209 sdhc_bus_width, 210 sdhc_bus_rod, 211 212 /* command execution */ 213 sdhc_exec_command, 214 215 /* card interrupt */ 216 sdhc_card_enable_intr, 217 sdhc_card_intr_ack 218 }; 219 220 static int 221 sdhc_cfprint(void *aux, const char *pnp) 222 { 223 const struct sdmmcbus_attach_args const * saa = aux; 224 const struct sdhc_host * const hp = saa->saa_sch; 225 226 if (pnp) { 227 aprint_normal("sdmmc at %s", pnp); 228 } 229 aprint_normal(" slot %d", HDEVINST(hp)); 230 231 return UNCONF; 232 } 233 234 /* 235 * Called by attachment driver. For each SD card slot there is one SD 236 * host controller standard register set. (1.3) 237 */ 238 int 239 sdhc_host_found(struct sdhc_softc *sc, bus_space_tag_t iot, 240 bus_space_handle_t ioh, bus_size_t iosize) 241 { 242 struct sdmmcbus_attach_args saa; 243 struct sdhc_host *hp; 244 uint32_t caps; 245 uint16_t sdhcver; 246 247 sdhcver = bus_space_read_2(iot, ioh, SDHC_HOST_CTL_VERSION); 248 aprint_normal_dev(sc->sc_dev, "SD Host Specification "); 249 switch (SDHC_SPEC_VERSION(sdhcver)) { 250 case SDHC_SPEC_VERS_100: 251 aprint_normal("1.0"); 252 break; 253 254 case SDHC_SPEC_VERS_200: 255 aprint_normal("2.0"); 256 break; 257 258 case SDHC_SPEC_VERS_300: 259 aprint_normal("3.0"); 260 break; 261 262 default: 263 aprint_normal("unknown version(0x%x)", 264 SDHC_SPEC_VERSION(sdhcver)); 265 break; 266 } 267 aprint_normal(", rev.%u\n", SDHC_VENDOR_VERSION(sdhcver)); 268 269 /* Allocate one more host structure. */ 270 hp = malloc(sizeof(struct sdhc_host), M_DEVBUF, M_WAITOK|M_ZERO); 271 if (hp == NULL) { 272 aprint_error_dev(sc->sc_dev, 273 "couldn't alloc memory (sdhc host)\n"); 274 goto err1; 275 } 276 sc->sc_host[sc->sc_nhosts++] = hp; 277 278 /* Fill in the new host structure. */ 279 hp->sc = sc; 280 hp->iot = iot; 281 hp->ioh = ioh; 282 hp->dmat = sc->sc_dmat; 283 hp->specver = SDHC_SPEC_VERSION(sdhcver); 284 285 mutex_init(&hp->host_mtx, MUTEX_DEFAULT, IPL_SDMMC); 286 mutex_init(&hp->intr_mtx, MUTEX_DEFAULT, IPL_SDMMC); 287 cv_init(&hp->intr_cv, "sdhcintr"); 288 289 /* 290 * Reset the host controller and enable interrupts. 291 */ 292 (void)sdhc_host_reset(hp); 293 294 /* Determine host capabilities. */ 295 if (ISSET(sc->sc_flags, SDHC_FLAG_HOSTCAPS)) { 296 caps = sc->sc_caps; 297 } else { 298 mutex_enter(&hp->host_mtx); 299 caps = HREAD4(hp, SDHC_CAPABILITIES); 300 mutex_exit(&hp->host_mtx); 301 } 302 303 /* Use DMA if the host system and the controller support it. */ 304 if (ISSET(sc->sc_flags, SDHC_FLAG_FORCE_DMA) 305 || ((ISSET(sc->sc_flags, SDHC_FLAG_USE_DMA) 306 && ISSET(caps, SDHC_DMA_SUPPORT)))) { 307 SET(hp->flags, SHF_USE_DMA); 308 aprint_normal_dev(sc->sc_dev, "using DMA transfer\n"); 309 } 310 311 /* 312 * Determine the base clock frequency. (2.2.24) 313 */ 314 hp->clkbase = SDHC_BASE_FREQ_KHZ(caps); 315 if (hp->clkbase == 0) { 316 if (sc->sc_clkbase == 0) { 317 /* The attachment driver must tell us. */ 318 aprint_error_dev(sc->sc_dev, 319 "unknown base clock frequency\n"); 320 goto err; 321 } 322 hp->clkbase = sc->sc_clkbase; 323 } 324 if (hp->clkbase < 10000 || hp->clkbase > 10000 * 256) { 325 /* SDHC 1.0 supports only 10-63 MHz. */ 326 aprint_error_dev(sc->sc_dev, 327 "base clock frequency out of range: %u MHz\n", 328 hp->clkbase / 1000); 329 goto err; 330 } 331 DPRINTF(1,("%s: base clock frequency %u MHz\n", 332 device_xname(sc->sc_dev), hp->clkbase / 1000)); 333 334 /* 335 * XXX Set the data timeout counter value according to 336 * capabilities. (2.2.15) 337 */ 338 HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX); 339 #if 0 340 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 341 HWRITE4(hp, SDHC_NINTR_STATUS, SDHC_CMD_TIMEOUT_ERROR << 16); 342 #endif 343 344 /* 345 * Determine SD bus voltage levels supported by the controller. 346 */ 347 if (ISSET(caps, SDHC_VOLTAGE_SUPP_1_8V)) { 348 SET(hp->ocr, MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V); 349 } 350 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_0V)) { 351 SET(hp->ocr, MMC_OCR_2_9V_3_0V | MMC_OCR_3_0V_3_1V); 352 } 353 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_3V)) { 354 SET(hp->ocr, MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V); 355 } 356 357 /* 358 * Determine the maximum block length supported by the host 359 * controller. (2.2.24) 360 */ 361 switch((caps >> SDHC_MAX_BLK_LEN_SHIFT) & SDHC_MAX_BLK_LEN_MASK) { 362 case SDHC_MAX_BLK_LEN_512: 363 hp->maxblklen = 512; 364 break; 365 366 case SDHC_MAX_BLK_LEN_1024: 367 hp->maxblklen = 1024; 368 break; 369 370 case SDHC_MAX_BLK_LEN_2048: 371 hp->maxblklen = 2048; 372 break; 373 374 case SDHC_MAX_BLK_LEN_4096: 375 hp->maxblklen = 4096; 376 break; 377 378 default: 379 aprint_error_dev(sc->sc_dev, "max block length unknown\n"); 380 goto err; 381 } 382 DPRINTF(1, ("%s: max block length %u byte%s\n", 383 device_xname(sc->sc_dev), hp->maxblklen, 384 hp->maxblklen > 1 ? "s" : "")); 385 386 /* 387 * Attach the generic SD/MMC bus driver. (The bus driver must 388 * not invoke any chipset functions before it is attached.) 389 */ 390 memset(&saa, 0, sizeof(saa)); 391 saa.saa_busname = "sdmmc"; 392 saa.saa_sct = &sdhc_functions; 393 saa.saa_sch = hp; 394 saa.saa_dmat = hp->dmat; 395 saa.saa_clkmin = hp->clkbase / 256; 396 saa.saa_clkmax = hp->clkbase; 397 if (ISSET(sc->sc_flags, SDHC_FLAG_HAVE_CGM)) 398 saa.saa_clkmin /= 2046; 399 else if (ISSET(sc->sc_flags, SDHC_FLAG_HAVE_DVS)) 400 saa.saa_clkmin /= 16; 401 saa.saa_caps = SMC_CAPS_4BIT_MODE|SMC_CAPS_AUTO_STOP; 402 if (ISSET(sc->sc_flags, SDHC_FLAG_8BIT_MODE)) 403 saa.saa_caps |= SMC_CAPS_8BIT_MODE; 404 if (ISSET(caps, SDHC_HIGH_SPEED_SUPP)) 405 saa.saa_caps |= SMC_CAPS_SD_HIGHSPEED; 406 if (ISSET(hp->flags, SHF_USE_DMA)) { 407 saa.saa_caps |= SMC_CAPS_DMA; 408 if (!ISSET(sc->sc_flags, SDHC_FLAG_ENHANCED)) { 409 saa.saa_caps |= SMC_CAPS_MULTI_SEG_DMA; 410 } 411 } 412 hp->sdmmc = config_found(sc->sc_dev, &saa, sdhc_cfprint); 413 414 return 0; 415 416 err: 417 cv_destroy(&hp->intr_cv); 418 mutex_destroy(&hp->intr_mtx); 419 mutex_destroy(&hp->host_mtx); 420 free(hp, M_DEVBUF); 421 sc->sc_host[--sc->sc_nhosts] = NULL; 422 err1: 423 return 1; 424 } 425 426 int 427 sdhc_detach(device_t dev, int flags) 428 { 429 struct sdhc_host *hp = (struct sdhc_host *)dev; 430 struct sdhc_softc *sc = hp->sc; 431 int rv = 0; 432 433 if (hp->sdmmc) 434 rv = config_detach(hp->sdmmc, flags); 435 436 cv_destroy(&hp->intr_cv); 437 mutex_destroy(&hp->intr_mtx); 438 mutex_destroy(&hp->host_mtx); 439 free(hp, M_DEVBUF); 440 sc->sc_host[--sc->sc_nhosts] = NULL; 441 442 return rv; 443 } 444 445 bool 446 sdhc_suspend(device_t dev, const pmf_qual_t *qual) 447 { 448 struct sdhc_softc *sc = device_private(dev); 449 struct sdhc_host *hp; 450 size_t i; 451 452 /* XXX poll for command completion or suspend command 453 * in progress */ 454 455 /* Save the host controller state. */ 456 for (size_t n = 0; n < sc->sc_nhosts; n++) { 457 hp = sc->sc_host[n]; 458 if (ISSET(sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 459 for (i = 0; i < sizeof hp->regs; i += 4) { 460 uint32_t v = HREAD4(hp, i); 461 hp->regs[i + 0] = (v >> 0); 462 hp->regs[i + 1] = (v >> 8); 463 if (i + 3 < sizeof hp->regs) { 464 hp->regs[i + 2] = (v >> 16); 465 hp->regs[i + 3] = (v >> 24); 466 } 467 } 468 } else { 469 for (i = 0; i < sizeof hp->regs; i++) { 470 hp->regs[i] = HREAD1(hp, i); 471 } 472 } 473 } 474 return true; 475 } 476 477 bool 478 sdhc_resume(device_t dev, const pmf_qual_t *qual) 479 { 480 struct sdhc_softc *sc = device_private(dev); 481 struct sdhc_host *hp; 482 size_t i; 483 484 /* Restore the host controller state. */ 485 for (size_t n = 0; n < sc->sc_nhosts; n++) { 486 hp = sc->sc_host[n]; 487 (void)sdhc_host_reset(hp); 488 if (ISSET(sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 489 for (i = 0; i < sizeof hp->regs; i += 4) { 490 if (i + 3 < sizeof hp->regs) { 491 HWRITE4(hp, i, 492 (hp->regs[i + 0] << 0) 493 | (hp->regs[i + 1] << 8) 494 | (hp->regs[i + 2] << 16) 495 | (hp->regs[i + 3] << 24)); 496 } else { 497 HWRITE4(hp, i, 498 (hp->regs[i + 0] << 0) 499 | (hp->regs[i + 1] << 8)); 500 } 501 } 502 } else { 503 for (i = 0; i < sizeof hp->regs; i++) { 504 HWRITE1(hp, i, hp->regs[i]); 505 } 506 } 507 } 508 return true; 509 } 510 511 bool 512 sdhc_shutdown(device_t dev, int flags) 513 { 514 struct sdhc_softc *sc = device_private(dev); 515 struct sdhc_host *hp; 516 517 /* XXX chip locks up if we don't disable it before reboot. */ 518 for (size_t i = 0; i < sc->sc_nhosts; i++) { 519 hp = sc->sc_host[i]; 520 (void)sdhc_host_reset(hp); 521 } 522 return true; 523 } 524 525 /* 526 * Reset the host controller. Called during initialization, when 527 * cards are removed, upon resume, and during error recovery. 528 */ 529 static int 530 sdhc_host_reset1(sdmmc_chipset_handle_t sch) 531 { 532 struct sdhc_host *hp = (struct sdhc_host *)sch; 533 uint32_t sdhcimask; 534 int error; 535 536 /* Don't lock. */ 537 538 /* Disable all interrupts. */ 539 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 540 HWRITE4(hp, SDHC_NINTR_SIGNAL_EN, 0); 541 } else { 542 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, 0); 543 } 544 545 /* 546 * Reset the entire host controller and wait up to 100ms for 547 * the controller to clear the reset bit. 548 */ 549 error = sdhc_soft_reset(hp, SDHC_RESET_ALL); 550 if (error) 551 goto out; 552 553 /* Set data timeout counter value to max for now. */ 554 HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX); 555 #if 0 556 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 557 HWRITE4(hp, SDHC_NINTR_STATUS, SDHC_CMD_TIMEOUT_ERROR << 16); 558 #endif 559 560 /* Enable interrupts. */ 561 sdhcimask = SDHC_CARD_REMOVAL | SDHC_CARD_INSERTION | 562 SDHC_BUFFER_READ_READY | SDHC_BUFFER_WRITE_READY | 563 SDHC_DMA_INTERRUPT | SDHC_BLOCK_GAP_EVENT | 564 SDHC_TRANSFER_COMPLETE | SDHC_COMMAND_COMPLETE; 565 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 566 sdhcimask |= SDHC_EINTR_STATUS_MASK << 16; 567 HWRITE4(hp, SDHC_NINTR_STATUS_EN, sdhcimask); 568 sdhcimask ^= 569 (SDHC_EINTR_STATUS_MASK ^ SDHC_EINTR_SIGNAL_MASK) << 16; 570 sdhcimask ^= SDHC_BUFFER_READ_READY ^ SDHC_BUFFER_WRITE_READY; 571 HWRITE4(hp, SDHC_NINTR_SIGNAL_EN, sdhcimask); 572 } else { 573 HWRITE2(hp, SDHC_NINTR_STATUS_EN, sdhcimask); 574 HWRITE2(hp, SDHC_EINTR_STATUS_EN, SDHC_EINTR_STATUS_MASK); 575 sdhcimask ^= SDHC_BUFFER_READ_READY ^ SDHC_BUFFER_WRITE_READY; 576 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, sdhcimask); 577 HWRITE2(hp, SDHC_EINTR_SIGNAL_EN, SDHC_EINTR_SIGNAL_MASK); 578 } 579 580 out: 581 return error; 582 } 583 584 static int 585 sdhc_host_reset(sdmmc_chipset_handle_t sch) 586 { 587 struct sdhc_host *hp = (struct sdhc_host *)sch; 588 int error; 589 590 mutex_enter(&hp->host_mtx); 591 error = sdhc_host_reset1(sch); 592 mutex_exit(&hp->host_mtx); 593 594 return error; 595 } 596 597 static uint32_t 598 sdhc_host_ocr(sdmmc_chipset_handle_t sch) 599 { 600 struct sdhc_host *hp = (struct sdhc_host *)sch; 601 602 return hp->ocr; 603 } 604 605 static int 606 sdhc_host_maxblklen(sdmmc_chipset_handle_t sch) 607 { 608 struct sdhc_host *hp = (struct sdhc_host *)sch; 609 610 return hp->maxblklen; 611 } 612 613 /* 614 * Return non-zero if the card is currently inserted. 615 */ 616 static int 617 sdhc_card_detect(sdmmc_chipset_handle_t sch) 618 { 619 struct sdhc_host *hp = (struct sdhc_host *)sch; 620 int r; 621 622 mutex_enter(&hp->host_mtx); 623 r = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CARD_INSERTED); 624 mutex_exit(&hp->host_mtx); 625 626 return r ? 1 : 0; 627 } 628 629 /* 630 * Return non-zero if the card is currently write-protected. 631 */ 632 static int 633 sdhc_write_protect(sdmmc_chipset_handle_t sch) 634 { 635 struct sdhc_host *hp = (struct sdhc_host *)sch; 636 int r; 637 638 mutex_enter(&hp->host_mtx); 639 r = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_WRITE_PROTECT_SWITCH); 640 mutex_exit(&hp->host_mtx); 641 642 return r ? 0 : 1; 643 } 644 645 /* 646 * Set or change SD bus voltage and enable or disable SD bus power. 647 * Return zero on success. 648 */ 649 static int 650 sdhc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 651 { 652 struct sdhc_host *hp = (struct sdhc_host *)sch; 653 uint8_t vdd; 654 int error = 0; 655 656 mutex_enter(&hp->host_mtx); 657 658 /* 659 * Disable bus power before voltage change. 660 */ 661 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS) 662 && !ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_PWR0)) 663 HWRITE1(hp, SDHC_POWER_CTL, 0); 664 665 /* If power is disabled, reset the host and return now. */ 666 if (ocr == 0) { 667 (void)sdhc_host_reset1(hp); 668 goto out; 669 } 670 671 /* 672 * Select the lowest voltage according to capabilities. 673 */ 674 ocr &= hp->ocr; 675 if (ISSET(ocr, MMC_OCR_1_7V_1_8V|MMC_OCR_1_8V_1_9V)) { 676 vdd = SDHC_VOLTAGE_1_8V; 677 } else if (ISSET(ocr, MMC_OCR_2_9V_3_0V|MMC_OCR_3_0V_3_1V)) { 678 vdd = SDHC_VOLTAGE_3_0V; 679 } else if (ISSET(ocr, MMC_OCR_3_2V_3_3V|MMC_OCR_3_3V_3_4V)) { 680 vdd = SDHC_VOLTAGE_3_3V; 681 } else { 682 /* Unsupported voltage level requested. */ 683 error = EINVAL; 684 goto out; 685 } 686 687 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 688 /* 689 * Enable bus power. Wait at least 1 ms (or 74 clocks) plus 690 * voltage ramp until power rises. 691 */ 692 HWRITE1(hp, SDHC_POWER_CTL, 693 (vdd << SDHC_VOLTAGE_SHIFT) | SDHC_BUS_POWER); 694 sdmmc_delay(10000); 695 696 /* 697 * The host system may not power the bus due to battery low, 698 * etc. In that case, the host controller should clear the 699 * bus power bit. 700 */ 701 if (!ISSET(HREAD1(hp, SDHC_POWER_CTL), SDHC_BUS_POWER)) { 702 error = ENXIO; 703 goto out; 704 } 705 } 706 707 out: 708 mutex_exit(&hp->host_mtx); 709 710 return error; 711 } 712 713 /* 714 * Return the smallest possible base clock frequency divisor value 715 * for the CLOCK_CTL register to produce `freq' (KHz). 716 */ 717 static bool 718 sdhc_clock_divisor(struct sdhc_host *hp, u_int freq, u_int *divp) 719 { 720 u_int div; 721 722 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_HAVE_CGM)) { 723 for (div = hp->clkbase / freq; div <= 0x3ff; div++) { 724 if ((hp->clkbase / div) <= freq) { 725 *divp = SDHC_SDCLK_CGM 726 | ((div & 0x300) << SDHC_SDCLK_XDIV_SHIFT) 727 | ((div & 0x0ff) << SDHC_SDCLK_DIV_SHIFT); 728 //freq = hp->clkbase / div; 729 return true; 730 } 731 } 732 /* No divisor found. */ 733 return false; 734 } 735 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_HAVE_DVS)) { 736 u_int dvs = (hp->clkbase + freq - 1) / freq; 737 u_int roundup = dvs & 1; 738 for (dvs >>= 1, div = 1; div <= 256; div <<= 1, dvs >>= 1) { 739 if (dvs + roundup <= 16) { 740 dvs += roundup - 1; 741 *divp = (div << SDHC_SDCLK_DIV_SHIFT) 742 | (dvs << SDHC_SDCLK_DVS_SHIFT); 743 DPRINTF(2, 744 ("%s: divisor for freq %u is %u * %u\n", 745 HDEVNAME(hp), freq, div * 2, dvs + 1)); 746 //freq = hp->clkbase / (div * 2) * (dvs + 1); 747 return true; 748 } 749 /* 750 * If we drop bits, we need to round up the divisor. 751 */ 752 roundup |= dvs & 1; 753 } 754 /* No divisor found. */ 755 return false; 756 } else { 757 for (div = 1; div <= 256; div *= 2) { 758 if ((hp->clkbase / div) <= freq) { 759 *divp = (div / 2) << SDHC_SDCLK_DIV_SHIFT; 760 //freq = hp->clkbase / div; 761 return true; 762 } 763 } 764 } 765 /* No divisor found. */ 766 return false; 767 } 768 769 /* 770 * Set or change SDCLK frequency or disable the SD clock. 771 * Return zero on success. 772 */ 773 static int 774 sdhc_bus_clock(sdmmc_chipset_handle_t sch, int freq) 775 { 776 struct sdhc_host *hp = (struct sdhc_host *)sch; 777 u_int div; 778 u_int timo; 779 int error = 0; 780 #ifdef DIAGNOSTIC 781 bool present; 782 783 mutex_enter(&hp->host_mtx); 784 present = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CMD_INHIBIT_MASK); 785 mutex_exit(&hp->host_mtx); 786 787 /* Must not stop the clock if commands are in progress. */ 788 if (present && sdhc_card_detect(hp)) { 789 aprint_normal_dev(hp->sc->sc_dev, 790 "%s: command in progress\n", __func__); 791 } 792 #endif 793 794 mutex_enter(&hp->host_mtx); 795 796 /* 797 * Stop SD clock before changing the frequency. 798 */ 799 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 800 HCLR4(hp, SDHC_CLOCK_CTL, 0xfff8); 801 if (freq == SDMMC_SDCLK_OFF) { 802 HSET4(hp, SDHC_CLOCK_CTL, 0x80f0); 803 goto out; 804 } 805 } else { 806 HWRITE2(hp, SDHC_CLOCK_CTL, 0); 807 if (freq == SDMMC_SDCLK_OFF) 808 goto out; 809 } 810 811 /* 812 * Set the minimum base clock frequency divisor. 813 */ 814 if (!sdhc_clock_divisor(hp, freq, &div)) { 815 /* Invalid base clock frequency or `freq' value. */ 816 error = EINVAL; 817 goto out; 818 } 819 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 820 HWRITE4(hp, SDHC_CLOCK_CTL, 821 div | (SDHC_TIMEOUT_MAX << 16)); 822 } else { 823 HWRITE2(hp, SDHC_CLOCK_CTL, div); 824 } 825 826 /* 827 * Start internal clock. Wait 10ms for stabilization. 828 */ 829 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 830 sdmmc_delay(10000); 831 HSET4(hp, SDHC_CLOCK_CTL, 832 8 | SDHC_INTCLK_ENABLE | SDHC_INTCLK_STABLE); 833 } else { 834 HSET2(hp, SDHC_CLOCK_CTL, SDHC_INTCLK_ENABLE); 835 for (timo = 1000; timo > 0; timo--) { 836 if (ISSET(HREAD2(hp, SDHC_CLOCK_CTL), 837 SDHC_INTCLK_STABLE)) 838 break; 839 sdmmc_delay(10); 840 } 841 if (timo == 0) { 842 error = ETIMEDOUT; 843 goto out; 844 } 845 } 846 847 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 848 HSET1(hp, SDHC_SOFTWARE_RESET, SDHC_INIT_ACTIVE); 849 /* 850 * Sending 80 clocks at 400kHz takes 200us. 851 * So delay for that time + slop and then 852 * check a few times for completion. 853 */ 854 sdmmc_delay(210); 855 for (timo = 10; timo > 0; timo--) { 856 if (!ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), 857 SDHC_INIT_ACTIVE)) 858 break; 859 sdmmc_delay(10); 860 } 861 DPRINTF(2,("%s: %u init spins\n", __func__, 10 - timo)); 862 863 /* 864 * Enable SD clock. 865 */ 866 HSET4(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE); 867 } else { 868 /* 869 * Enable SD clock. 870 */ 871 HSET2(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE); 872 873 if (freq > 25000) 874 HSET1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED); 875 else 876 HCLR1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED); 877 } 878 879 out: 880 mutex_exit(&hp->host_mtx); 881 882 return error; 883 } 884 885 static int 886 sdhc_bus_width(sdmmc_chipset_handle_t sch, int width) 887 { 888 struct sdhc_host *hp = (struct sdhc_host *)sch; 889 int reg; 890 891 switch (width) { 892 case 1: 893 case 4: 894 break; 895 896 case 8: 897 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_8BIT_MODE)) 898 break; 899 /* FALLTHROUGH */ 900 default: 901 DPRINTF(0,("%s: unsupported bus width (%d)\n", 902 HDEVNAME(hp), width)); 903 return 1; 904 } 905 906 mutex_enter(&hp->host_mtx); 907 reg = HREAD1(hp, SDHC_HOST_CTL); 908 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 909 reg &= ~(SDHC_4BIT_MODE|SDHC_ESDHC_8BIT_MODE); 910 if (width == 4) 911 reg |= SDHC_4BIT_MODE; 912 else if (width == 8) 913 reg |= SDHC_ESDHC_8BIT_MODE; 914 } else { 915 reg &= ~SDHC_4BIT_MODE; 916 if (width == 4) 917 reg |= SDHC_4BIT_MODE; 918 } 919 HWRITE1(hp, SDHC_HOST_CTL, reg); 920 mutex_exit(&hp->host_mtx); 921 922 return 0; 923 } 924 925 static int 926 sdhc_bus_rod(sdmmc_chipset_handle_t sch, int on) 927 { 928 929 /* Nothing ?? */ 930 return 0; 931 } 932 933 static void 934 sdhc_card_enable_intr(sdmmc_chipset_handle_t sch, int enable) 935 { 936 struct sdhc_host *hp = (struct sdhc_host *)sch; 937 938 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 939 mutex_enter(&hp->host_mtx); 940 if (enable) { 941 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 942 HSET2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT); 943 } else { 944 HCLR2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT); 945 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 946 } 947 mutex_exit(&hp->host_mtx); 948 } 949 } 950 951 static void 952 sdhc_card_intr_ack(sdmmc_chipset_handle_t sch) 953 { 954 struct sdhc_host *hp = (struct sdhc_host *)sch; 955 956 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 957 mutex_enter(&hp->host_mtx); 958 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 959 mutex_exit(&hp->host_mtx); 960 } 961 } 962 963 static int 964 sdhc_wait_state(struct sdhc_host *hp, uint32_t mask, uint32_t value) 965 { 966 uint32_t state; 967 int timeout; 968 969 for (timeout = 10; timeout > 0; timeout--) { 970 if (((state = HREAD4(hp, SDHC_PRESENT_STATE)) & mask) == value) 971 return 0; 972 sdmmc_delay(10000); 973 } 974 DPRINTF(0,("%s: timeout waiting for %x (state=%x)\n", HDEVNAME(hp), 975 value, state)); 976 return ETIMEDOUT; 977 } 978 979 static void 980 sdhc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 981 { 982 struct sdhc_host *hp = (struct sdhc_host *)sch; 983 int error; 984 985 if (cmd->c_data && ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 986 const uint16_t ready = SDHC_BUFFER_READ_READY | SDHC_BUFFER_WRITE_READY; 987 if (ISSET(hp->flags, SHF_USE_DMA)) { 988 HCLR2(hp, SDHC_NINTR_SIGNAL_EN, ready); 989 HCLR2(hp, SDHC_NINTR_STATUS_EN, ready); 990 } else { 991 HSET2(hp, SDHC_NINTR_SIGNAL_EN, ready); 992 HSET2(hp, SDHC_NINTR_STATUS_EN, ready); 993 } 994 } 995 996 /* 997 * Start the MMC command, or mark `cmd' as failed and return. 998 */ 999 error = sdhc_start_command(hp, cmd); 1000 if (error) { 1001 cmd->c_error = error; 1002 goto out; 1003 } 1004 1005 /* 1006 * Wait until the command phase is done, or until the command 1007 * is marked done for any other reason. 1008 */ 1009 if (!sdhc_wait_intr(hp, SDHC_COMMAND_COMPLETE, SDHC_COMMAND_TIMEOUT)) { 1010 cmd->c_error = ETIMEDOUT; 1011 goto out; 1012 } 1013 1014 /* 1015 * The host controller removes bits [0:7] from the response 1016 * data (CRC) and we pass the data up unchanged to the bus 1017 * driver (without padding). 1018 */ 1019 mutex_enter(&hp->host_mtx); 1020 if (cmd->c_error == 0 && ISSET(cmd->c_flags, SCF_RSP_PRESENT)) { 1021 cmd->c_resp[0] = HREAD4(hp, SDHC_RESPONSE + 0); 1022 if (ISSET(cmd->c_flags, SCF_RSP_136)) { 1023 cmd->c_resp[1] = HREAD4(hp, SDHC_RESPONSE + 4); 1024 cmd->c_resp[2] = HREAD4(hp, SDHC_RESPONSE + 8); 1025 cmd->c_resp[3] = HREAD4(hp, SDHC_RESPONSE + 12); 1026 } 1027 } 1028 mutex_exit(&hp->host_mtx); 1029 DPRINTF(1,("%s: resp = %08x\n", HDEVNAME(hp), cmd->c_resp[0])); 1030 1031 /* 1032 * If the command has data to transfer in any direction, 1033 * execute the transfer now. 1034 */ 1035 if (cmd->c_error == 0 && cmd->c_data != NULL) 1036 sdhc_transfer_data(hp, cmd); 1037 1038 out: 1039 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED) 1040 && !ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_LED_ON)) { 1041 mutex_enter(&hp->host_mtx); 1042 /* Turn off the LED. */ 1043 HCLR1(hp, SDHC_HOST_CTL, SDHC_LED_ON); 1044 mutex_exit(&hp->host_mtx); 1045 } 1046 SET(cmd->c_flags, SCF_ITSDONE); 1047 1048 DPRINTF(1,("%s: cmd %d %s (flags=%08x error=%d)\n", HDEVNAME(hp), 1049 cmd->c_opcode, (cmd->c_error == 0) ? "done" : "abort", 1050 cmd->c_flags, cmd->c_error)); 1051 } 1052 1053 static int 1054 sdhc_start_command(struct sdhc_host *hp, struct sdmmc_command *cmd) 1055 { 1056 struct sdhc_softc * const sc = hp->sc; 1057 uint16_t blksize = 0; 1058 uint16_t blkcount = 0; 1059 uint16_t mode; 1060 uint16_t command; 1061 int error; 1062 1063 DPRINTF(1,("%s: start cmd %d arg=%08x data=%p dlen=%d flags=%08x, status=%#x\n", 1064 HDEVNAME(hp), cmd->c_opcode, cmd->c_arg, cmd->c_data, 1065 cmd->c_datalen, cmd->c_flags, HREAD4(hp, SDHC_NINTR_STATUS))); 1066 1067 /* 1068 * The maximum block length for commands should be the minimum 1069 * of the host buffer size and the card buffer size. (1.7.2) 1070 */ 1071 1072 /* Fragment the data into proper blocks. */ 1073 if (cmd->c_datalen > 0) { 1074 blksize = MIN(cmd->c_datalen, cmd->c_blklen); 1075 blkcount = cmd->c_datalen / blksize; 1076 if (cmd->c_datalen % blksize > 0) { 1077 /* XXX: Split this command. (1.7.4) */ 1078 aprint_error_dev(sc->sc_dev, 1079 "data not a multiple of %u bytes\n", blksize); 1080 return EINVAL; 1081 } 1082 } 1083 1084 /* Check limit imposed by 9-bit block count. (1.7.2) */ 1085 if (blkcount > SDHC_BLOCK_COUNT_MAX) { 1086 aprint_error_dev(sc->sc_dev, "too much data\n"); 1087 return EINVAL; 1088 } 1089 1090 /* Prepare transfer mode register value. (2.2.5) */ 1091 mode = SDHC_BLOCK_COUNT_ENABLE; 1092 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 1093 mode |= SDHC_READ_MODE; 1094 if (blkcount > 1) { 1095 mode |= SDHC_MULTI_BLOCK_MODE; 1096 /* XXX only for memory commands? */ 1097 mode |= SDHC_AUTO_CMD12_ENABLE; 1098 } 1099 if (cmd->c_dmamap != NULL && cmd->c_datalen > 0) { 1100 mode |= SDHC_DMA_ENABLE; 1101 } 1102 1103 /* 1104 * Prepare command register value. (2.2.6) 1105 */ 1106 command = (cmd->c_opcode & SDHC_COMMAND_INDEX_MASK) << SDHC_COMMAND_INDEX_SHIFT; 1107 1108 if (ISSET(cmd->c_flags, SCF_RSP_CRC)) 1109 command |= SDHC_CRC_CHECK_ENABLE; 1110 if (ISSET(cmd->c_flags, SCF_RSP_IDX)) 1111 command |= SDHC_INDEX_CHECK_ENABLE; 1112 if (cmd->c_data != NULL) 1113 command |= SDHC_DATA_PRESENT_SELECT; 1114 1115 if (!ISSET(cmd->c_flags, SCF_RSP_PRESENT)) 1116 command |= SDHC_NO_RESPONSE; 1117 else if (ISSET(cmd->c_flags, SCF_RSP_136)) 1118 command |= SDHC_RESP_LEN_136; 1119 else if (ISSET(cmd->c_flags, SCF_RSP_BSY)) 1120 command |= SDHC_RESP_LEN_48_CHK_BUSY; 1121 else 1122 command |= SDHC_RESP_LEN_48; 1123 1124 /* Wait until command and data inhibit bits are clear. (1.5) */ 1125 error = sdhc_wait_state(hp, SDHC_CMD_INHIBIT_MASK, 0); 1126 if (error) 1127 return error; 1128 1129 DPRINTF(1,("%s: writing cmd: blksize=%d blkcnt=%d mode=%04x cmd=%04x\n", 1130 HDEVNAME(hp), blksize, blkcount, mode, command)); 1131 1132 blksize |= (MAX(0, PAGE_SHIFT - 12) & SDHC_DMA_BOUNDARY_MASK) << 1133 SDHC_DMA_BOUNDARY_SHIFT; /* PAGE_SIZE DMA boundary */ 1134 1135 mutex_enter(&hp->host_mtx); 1136 1137 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1138 /* Alert the user not to remove the card. */ 1139 HSET1(hp, SDHC_HOST_CTL, SDHC_LED_ON); 1140 } 1141 1142 /* Set DMA start address. */ 1143 if (ISSET(mode, SDHC_DMA_ENABLE)) 1144 HWRITE4(hp, SDHC_DMA_ADDR, cmd->c_dmamap->dm_segs[0].ds_addr); 1145 1146 /* 1147 * Start a CPU data transfer. Writing to the high order byte 1148 * of the SDHC_COMMAND register triggers the SD command. (1.5) 1149 */ 1150 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 1151 HWRITE4(hp, SDHC_BLOCK_SIZE, blksize | (blkcount << 16)); 1152 HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg); 1153 HWRITE4(hp, SDHC_TRANSFER_MODE, mode | (command << 16)); 1154 } else { 1155 HWRITE2(hp, SDHC_BLOCK_SIZE, blksize); 1156 HWRITE2(hp, SDHC_BLOCK_COUNT, blkcount); 1157 HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg); 1158 HWRITE2(hp, SDHC_TRANSFER_MODE, mode); 1159 HWRITE2(hp, SDHC_COMMAND, command); 1160 } 1161 1162 mutex_exit(&hp->host_mtx); 1163 1164 return 0; 1165 } 1166 1167 static void 1168 sdhc_transfer_data(struct sdhc_host *hp, struct sdmmc_command *cmd) 1169 { 1170 int error; 1171 1172 DPRINTF(1,("%s: data transfer: resp=%08x datalen=%u\n", HDEVNAME(hp), 1173 MMC_R1(cmd->c_resp), cmd->c_datalen)); 1174 1175 #ifdef SDHC_DEBUG 1176 /* XXX I forgot why I wanted to know when this happens :-( */ 1177 if ((cmd->c_opcode == 52 || cmd->c_opcode == 53) && 1178 ISSET(MMC_R1(cmd->c_resp), 0xcb00)) { 1179 aprint_error_dev(hp->sc->sc_dev, 1180 "CMD52/53 error response flags %#x\n", 1181 MMC_R1(cmd->c_resp) & 0xff00); 1182 } 1183 #endif 1184 1185 if (cmd->c_dmamap != NULL) 1186 error = sdhc_transfer_data_dma(hp, cmd); 1187 else 1188 error = sdhc_transfer_data_pio(hp, cmd); 1189 if (error) 1190 cmd->c_error = error; 1191 SET(cmd->c_flags, SCF_ITSDONE); 1192 1193 DPRINTF(1,("%s: data transfer done (error=%d)\n", 1194 HDEVNAME(hp), cmd->c_error)); 1195 } 1196 1197 static int 1198 sdhc_transfer_data_dma(struct sdhc_host *hp, struct sdmmc_command *cmd) 1199 { 1200 bus_dma_segment_t *dm_segs = cmd->c_dmamap->dm_segs; 1201 bus_addr_t posaddr; 1202 bus_addr_t segaddr; 1203 bus_size_t seglen; 1204 u_int seg = 0; 1205 int error = 0; 1206 int status; 1207 1208 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_DMA_INTERRUPT); 1209 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_DMA_INTERRUPT); 1210 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_TRANSFER_COMPLETE); 1211 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_TRANSFER_COMPLETE); 1212 1213 for (;;) { 1214 status = sdhc_wait_intr(hp, 1215 SDHC_DMA_INTERRUPT|SDHC_TRANSFER_COMPLETE, 1216 SDHC_DMA_TIMEOUT); 1217 1218 if (status & SDHC_TRANSFER_COMPLETE) { 1219 break; 1220 } 1221 if (!status) { 1222 error = ETIMEDOUT; 1223 break; 1224 } 1225 if ((status & SDHC_DMA_INTERRUPT) == 0) { 1226 continue; 1227 } 1228 1229 /* DMA Interrupt (boundary crossing) */ 1230 1231 segaddr = dm_segs[seg].ds_addr; 1232 seglen = dm_segs[seg].ds_len; 1233 mutex_enter(&hp->host_mtx); 1234 posaddr = HREAD4(hp, SDHC_DMA_ADDR); 1235 mutex_exit(&hp->host_mtx); 1236 1237 if ((seg == (cmd->c_dmamap->dm_nsegs-1)) && (posaddr == (segaddr + seglen))) { 1238 break; 1239 } 1240 mutex_enter(&hp->host_mtx); 1241 if ((posaddr >= segaddr) && (posaddr < (segaddr + seglen))) 1242 HWRITE4(hp, SDHC_DMA_ADDR, posaddr); 1243 else if ((posaddr >= segaddr) && (posaddr == (segaddr + seglen)) && (seg + 1) < cmd->c_dmamap->dm_nsegs) 1244 HWRITE4(hp, SDHC_DMA_ADDR, dm_segs[++seg].ds_addr); 1245 mutex_exit(&hp->host_mtx); 1246 KASSERT(seg < cmd->c_dmamap->dm_nsegs); 1247 } 1248 1249 return error; 1250 } 1251 1252 static int 1253 sdhc_transfer_data_pio(struct sdhc_host *hp, struct sdmmc_command *cmd) 1254 { 1255 uint8_t *data = cmd->c_data; 1256 void (*pio_func)(struct sdhc_host *, uint8_t *, u_int); 1257 u_int len, datalen; 1258 u_int imask; 1259 u_int pmask; 1260 int error = 0; 1261 1262 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 1263 imask = SDHC_BUFFER_READ_READY; 1264 pmask = SDHC_BUFFER_READ_ENABLE; 1265 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1266 pio_func = esdhc_read_data_pio; 1267 } else { 1268 pio_func = sdhc_read_data_pio; 1269 } 1270 } else { 1271 imask = SDHC_BUFFER_WRITE_READY; 1272 pmask = SDHC_BUFFER_WRITE_ENABLE; 1273 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1274 pio_func = esdhc_write_data_pio; 1275 } else { 1276 pio_func = sdhc_write_data_pio; 1277 } 1278 } 1279 datalen = cmd->c_datalen; 1280 1281 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & imask); 1282 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_TRANSFER_COMPLETE); 1283 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_TRANSFER_COMPLETE); 1284 1285 while (datalen > 0) { 1286 if (!ISSET(HREAD4(hp, SDHC_PRESENT_STATE), imask)) { 1287 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 1288 HSET4(hp, SDHC_NINTR_SIGNAL_EN, imask); 1289 } else { 1290 HSET2(hp, SDHC_NINTR_SIGNAL_EN, imask); 1291 } 1292 if (!sdhc_wait_intr(hp, imask, SDHC_BUFFER_TIMEOUT)) { 1293 error = ETIMEDOUT; 1294 break; 1295 } 1296 1297 error = sdhc_wait_state(hp, pmask, pmask); 1298 if (error) 1299 break; 1300 } 1301 1302 len = MIN(datalen, cmd->c_blklen); 1303 (*pio_func)(hp, data, len); 1304 DPRINTF(2,("%s: pio data transfer %u @ %p\n", 1305 HDEVNAME(hp), len, data)); 1306 1307 data += len; 1308 datalen -= len; 1309 } 1310 1311 if (error == 0 && !sdhc_wait_intr(hp, SDHC_TRANSFER_COMPLETE, 1312 SDHC_TRANSFER_TIMEOUT)) 1313 error = ETIMEDOUT; 1314 1315 return error; 1316 } 1317 1318 static void 1319 sdhc_read_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1320 { 1321 1322 if (((__uintptr_t)data & 3) == 0) { 1323 while (datalen > 3) { 1324 *(uint32_t *)data = HREAD4(hp, SDHC_DATA); 1325 data += 4; 1326 datalen -= 4; 1327 } 1328 if (datalen > 1) { 1329 *(uint16_t *)data = HREAD2(hp, SDHC_DATA); 1330 data += 2; 1331 datalen -= 2; 1332 } 1333 if (datalen > 0) { 1334 *data = HREAD1(hp, SDHC_DATA); 1335 data += 1; 1336 datalen -= 1; 1337 } 1338 } else if (((__uintptr_t)data & 1) == 0) { 1339 while (datalen > 1) { 1340 *(uint16_t *)data = HREAD2(hp, SDHC_DATA); 1341 data += 2; 1342 datalen -= 2; 1343 } 1344 if (datalen > 0) { 1345 *data = HREAD1(hp, SDHC_DATA); 1346 data += 1; 1347 datalen -= 1; 1348 } 1349 } else { 1350 while (datalen > 0) { 1351 *data = HREAD1(hp, SDHC_DATA); 1352 data += 1; 1353 datalen -= 1; 1354 } 1355 } 1356 } 1357 1358 static void 1359 sdhc_write_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1360 { 1361 1362 if (((__uintptr_t)data & 3) == 0) { 1363 while (datalen > 3) { 1364 HWRITE4(hp, SDHC_DATA, *(uint32_t *)data); 1365 data += 4; 1366 datalen -= 4; 1367 } 1368 if (datalen > 1) { 1369 HWRITE2(hp, SDHC_DATA, *(uint16_t *)data); 1370 data += 2; 1371 datalen -= 2; 1372 } 1373 if (datalen > 0) { 1374 HWRITE1(hp, SDHC_DATA, *data); 1375 data += 1; 1376 datalen -= 1; 1377 } 1378 } else if (((__uintptr_t)data & 1) == 0) { 1379 while (datalen > 1) { 1380 HWRITE2(hp, SDHC_DATA, *(uint16_t *)data); 1381 data += 2; 1382 datalen -= 2; 1383 } 1384 if (datalen > 0) { 1385 HWRITE1(hp, SDHC_DATA, *data); 1386 data += 1; 1387 datalen -= 1; 1388 } 1389 } else { 1390 while (datalen > 0) { 1391 HWRITE1(hp, SDHC_DATA, *data); 1392 data += 1; 1393 datalen -= 1; 1394 } 1395 } 1396 } 1397 1398 static void 1399 esdhc_read_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1400 { 1401 uint16_t status = HREAD2(hp, SDHC_NINTR_STATUS); 1402 uint32_t v; 1403 1404 const size_t watermark = (HREAD4(hp, SDHC_WATERMARK_LEVEL) >> SDHC_WATERMARK_READ_SHIFT) & SDHC_WATERMARK_READ_MASK; 1405 size_t count = 0; 1406 1407 while (datalen > 3 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1408 if (count == 0) { 1409 /* 1410 * If we've drained "watermark" words, we need to wait 1411 * a little bit so the read FIFO can refill. 1412 */ 1413 sdmmc_delay(10); 1414 count = watermark; 1415 } 1416 v = HREAD4(hp, SDHC_DATA); 1417 v = le32toh(v); 1418 *(uint32_t *)data = v; 1419 data += 4; 1420 datalen -= 4; 1421 status = HREAD2(hp, SDHC_NINTR_STATUS); 1422 count--; 1423 } 1424 if (datalen > 0 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1425 if (count == 0) { 1426 sdmmc_delay(10); 1427 } 1428 v = HREAD4(hp, SDHC_DATA); 1429 v = le32toh(v); 1430 do { 1431 *data++ = v; 1432 v >>= 8; 1433 } while (--datalen > 0); 1434 } 1435 } 1436 1437 static void 1438 esdhc_write_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1439 { 1440 uint16_t status = HREAD2(hp, SDHC_NINTR_STATUS); 1441 uint32_t v; 1442 1443 const size_t watermark = (HREAD4(hp, SDHC_WATERMARK_LEVEL) >> SDHC_WATERMARK_WRITE_SHIFT) & SDHC_WATERMARK_WRITE_MASK; 1444 size_t count = watermark; 1445 1446 while (datalen > 3 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1447 if (count == 0) { 1448 sdmmc_delay(10); 1449 count = watermark; 1450 } 1451 v = *(uint32_t *)data; 1452 v = htole32(v); 1453 HWRITE4(hp, SDHC_DATA, v); 1454 data += 4; 1455 datalen -= 4; 1456 status = HREAD2(hp, SDHC_NINTR_STATUS); 1457 count--; 1458 } 1459 if (datalen > 0 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1460 if (count == 0) { 1461 sdmmc_delay(10); 1462 } 1463 v = *(uint32_t *)data; 1464 v = htole32(v); 1465 HWRITE4(hp, SDHC_DATA, v); 1466 } 1467 } 1468 1469 /* Prepare for another command. */ 1470 static int 1471 sdhc_soft_reset(struct sdhc_host *hp, int mask) 1472 { 1473 int timo; 1474 1475 DPRINTF(1,("%s: software reset reg=%08x\n", HDEVNAME(hp), mask)); 1476 1477 HWRITE1(hp, SDHC_SOFTWARE_RESET, mask); 1478 for (timo = 10; timo > 0; timo--) { 1479 if (!ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), mask)) 1480 break; 1481 sdmmc_delay(10000); 1482 HWRITE1(hp, SDHC_SOFTWARE_RESET, 0); 1483 } 1484 if (timo == 0) { 1485 DPRINTF(1,("%s: timeout reg=%08x\n", HDEVNAME(hp), 1486 HREAD1(hp, SDHC_SOFTWARE_RESET))); 1487 HWRITE1(hp, SDHC_SOFTWARE_RESET, 0); 1488 return ETIMEDOUT; 1489 } 1490 1491 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1492 HWRITE4(hp, SDHC_DMA_CTL, SDHC_DMA_SNOOP); 1493 } 1494 1495 return 0; 1496 } 1497 1498 static int 1499 sdhc_wait_intr(struct sdhc_host *hp, int mask, int timo) 1500 { 1501 int status; 1502 1503 mask |= SDHC_ERROR_INTERRUPT; 1504 1505 mutex_enter(&hp->intr_mtx); 1506 status = hp->intr_status & mask; 1507 while (status == 0) { 1508 if (cv_timedwait(&hp->intr_cv, &hp->intr_mtx, timo) 1509 == EWOULDBLOCK) { 1510 status |= SDHC_ERROR_INTERRUPT; 1511 break; 1512 } 1513 status = hp->intr_status & mask; 1514 } 1515 hp->intr_status &= ~status; 1516 1517 DPRINTF(2,("%s: intr status %#x error %#x\n", HDEVNAME(hp), status, 1518 hp->intr_error_status)); 1519 1520 /* Command timeout has higher priority than command complete. */ 1521 if (ISSET(status, SDHC_ERROR_INTERRUPT) || hp->intr_error_status) { 1522 hp->intr_error_status = 0; 1523 hp->intr_status &= ~SDHC_ERROR_INTERRUPT; 1524 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1525 (void)sdhc_soft_reset(hp, SDHC_RESET_DAT|SDHC_RESET_CMD); 1526 } 1527 status = 0; 1528 } 1529 mutex_exit(&hp->intr_mtx); 1530 1531 return status; 1532 } 1533 1534 /* 1535 * Established by attachment driver at interrupt priority IPL_SDMMC. 1536 */ 1537 int 1538 sdhc_intr(void *arg) 1539 { 1540 struct sdhc_softc *sc = (struct sdhc_softc *)arg; 1541 struct sdhc_host *hp; 1542 int done = 0; 1543 uint16_t status; 1544 uint16_t error; 1545 1546 /* We got an interrupt, but we don't know from which slot. */ 1547 for (size_t host = 0; host < sc->sc_nhosts; host++) { 1548 hp = sc->sc_host[host]; 1549 if (hp == NULL) 1550 continue; 1551 1552 if (ISSET(sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 1553 /* Find out which interrupts are pending. */ 1554 uint32_t xstatus = HREAD4(hp, SDHC_NINTR_STATUS); 1555 status = xstatus; 1556 error = xstatus >> 16; 1557 if (error) 1558 xstatus |= SDHC_ERROR_INTERRUPT; 1559 else if (!ISSET(status, SDHC_NINTR_STATUS_MASK)) 1560 continue; /* no interrupt for us */ 1561 /* Acknowledge the interrupts we are about to handle. */ 1562 HWRITE4(hp, SDHC_NINTR_STATUS, xstatus); 1563 } else { 1564 /* Find out which interrupts are pending. */ 1565 error = 0; 1566 status = HREAD2(hp, SDHC_NINTR_STATUS); 1567 if (!ISSET(status, SDHC_NINTR_STATUS_MASK)) 1568 continue; /* no interrupt for us */ 1569 /* Acknowledge the interrupts we are about to handle. */ 1570 HWRITE2(hp, SDHC_NINTR_STATUS, status); 1571 if (ISSET(status, SDHC_ERROR_INTERRUPT)) { 1572 /* Acknowledge error interrupts. */ 1573 error = HREAD2(hp, SDHC_EINTR_STATUS); 1574 HWRITE2(hp, SDHC_EINTR_STATUS, error); 1575 } 1576 } 1577 1578 DPRINTF(2,("%s: interrupt status=%x error=%x\n", HDEVNAME(hp), 1579 status, error)); 1580 1581 /* Claim this interrupt. */ 1582 done = 1; 1583 1584 /* 1585 * Service error interrupts. 1586 */ 1587 if (ISSET(error, SDHC_CMD_TIMEOUT_ERROR| 1588 SDHC_DATA_TIMEOUT_ERROR)) { 1589 hp->intr_error_status |= error; 1590 hp->intr_status |= status; 1591 cv_broadcast(&hp->intr_cv); 1592 } 1593 1594 /* 1595 * Wake up the sdmmc event thread to scan for cards. 1596 */ 1597 if (ISSET(status, SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)) { 1598 sdmmc_needs_discover(hp->sdmmc); 1599 if (ISSET(sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1600 HCLR4(hp, SDHC_NINTR_STATUS_EN, 1601 status & (SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)); 1602 HCLR4(hp, SDHC_NINTR_SIGNAL_EN, 1603 status & (SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)); 1604 } 1605 } 1606 1607 /* 1608 * Wake up the blocking process to service command 1609 * related interrupt(s). 1610 */ 1611 if (ISSET(status, SDHC_COMMAND_COMPLETE| 1612 SDHC_BUFFER_READ_READY|SDHC_BUFFER_WRITE_READY| 1613 SDHC_TRANSFER_COMPLETE|SDHC_DMA_INTERRUPT)) { 1614 hp->intr_status |= status; 1615 if (ISSET(sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1616 HCLR4(hp, SDHC_NINTR_SIGNAL_EN, 1617 status & (SDHC_BUFFER_READ_READY|SDHC_BUFFER_WRITE_READY)); 1618 } 1619 cv_broadcast(&hp->intr_cv); 1620 } 1621 1622 /* 1623 * Service SD card interrupts. 1624 */ 1625 if (!ISSET(sc->sc_flags, SDHC_FLAG_ENHANCED) 1626 && ISSET(status, SDHC_CARD_INTERRUPT)) { 1627 DPRINTF(0,("%s: card interrupt\n", HDEVNAME(hp))); 1628 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 1629 sdmmc_card_intr(hp->sdmmc); 1630 } 1631 } 1632 1633 return done; 1634 } 1635 1636 #ifdef SDHC_DEBUG 1637 void 1638 sdhc_dump_regs(struct sdhc_host *hp) 1639 { 1640 1641 printf("0x%02x PRESENT_STATE: %x\n", SDHC_PRESENT_STATE, 1642 HREAD4(hp, SDHC_PRESENT_STATE)); 1643 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 1644 printf("0x%02x POWER_CTL: %x\n", SDHC_POWER_CTL, 1645 HREAD1(hp, SDHC_POWER_CTL)); 1646 printf("0x%02x NINTR_STATUS: %x\n", SDHC_NINTR_STATUS, 1647 HREAD2(hp, SDHC_NINTR_STATUS)); 1648 printf("0x%02x EINTR_STATUS: %x\n", SDHC_EINTR_STATUS, 1649 HREAD2(hp, SDHC_EINTR_STATUS)); 1650 printf("0x%02x NINTR_STATUS_EN: %x\n", SDHC_NINTR_STATUS_EN, 1651 HREAD2(hp, SDHC_NINTR_STATUS_EN)); 1652 printf("0x%02x EINTR_STATUS_EN: %x\n", SDHC_EINTR_STATUS_EN, 1653 HREAD2(hp, SDHC_EINTR_STATUS_EN)); 1654 printf("0x%02x NINTR_SIGNAL_EN: %x\n", SDHC_NINTR_SIGNAL_EN, 1655 HREAD2(hp, SDHC_NINTR_SIGNAL_EN)); 1656 printf("0x%02x EINTR_SIGNAL_EN: %x\n", SDHC_EINTR_SIGNAL_EN, 1657 HREAD2(hp, SDHC_EINTR_SIGNAL_EN)); 1658 printf("0x%02x CAPABILITIES: %x\n", SDHC_CAPABILITIES, 1659 HREAD4(hp, SDHC_CAPABILITIES)); 1660 printf("0x%02x MAX_CAPABILITIES: %x\n", SDHC_MAX_CAPABILITIES, 1661 HREAD4(hp, SDHC_MAX_CAPABILITIES)); 1662 } 1663 #endif 1664
Indexes created Tue Sep 23 02:09:52 GMT 2025