sdhc.c revision 1.32
1 /* $NetBSD: sdhc.c,v 1.32 2012/10/29 13:30:25 kiyohara Exp $ */ 2 /* $OpenBSD: sdhc.c,v 1.25 2009/01/13 19:44:20 grange Exp $ */ 3 4 /* 5 * Copyright (c) 2006 Uwe Stuehler <uwe (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * SD Host Controller driver based on the SD Host Controller Standard 22 * Simplified Specification Version 1.00 (www.sdcard.com). 23 */ 24 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: sdhc.c,v 1.32 2012/10/29 13:30:25 kiyohara Exp $"); 27 28 #ifdef _KERNEL_OPT 29 #include "opt_sdmmc.h" 30 #endif 31 32 #include <sys/param.h> 33 #include <sys/device.h> 34 #include <sys/kernel.h> 35 #include <sys/kthread.h> 36 #include <sys/malloc.h> 37 #include <sys/systm.h> 38 #include <sys/mutex.h> 39 #include <sys/condvar.h> 40 41 #include <dev/sdmmc/sdhcreg.h> 42 #include <dev/sdmmc/sdhcvar.h> 43 #include <dev/sdmmc/sdmmcchip.h> 44 #include <dev/sdmmc/sdmmcreg.h> 45 #include <dev/sdmmc/sdmmcvar.h> 46 47 #ifdef SDHC_DEBUG 48 int sdhcdebug = 1; 49 #define DPRINTF(n,s) do { if ((n) <= sdhcdebug) printf s; } while (0) 50 void sdhc_dump_regs(struct sdhc_host *); 51 #else 52 #define DPRINTF(n,s) do {} while (0) 53 #endif 54 55 #define SDHC_COMMAND_TIMEOUT hz 56 #define SDHC_BUFFER_TIMEOUT hz 57 #define SDHC_TRANSFER_TIMEOUT hz 58 #define SDHC_DMA_TIMEOUT hz 59 60 struct sdhc_host { 61 struct sdhc_softc *sc; /* host controller device */ 62 63 bus_space_tag_t iot; /* host register set tag */ 64 bus_space_handle_t ioh; /* host register set handle */ 65 bus_dma_tag_t dmat; /* host DMA tag */ 66 67 device_t sdmmc; /* generic SD/MMC device */ 68 69 struct kmutex host_mtx; 70 71 u_int clkbase; /* base clock frequency in KHz */ 72 int maxblklen; /* maximum block length */ 73 uint32_t ocr; /* OCR value from capabilities */ 74 75 uint8_t regs[14]; /* host controller state */ 76 77 uint16_t intr_status; /* soft interrupt status */ 78 uint16_t intr_error_status; /* soft error status */ 79 struct kmutex intr_mtx; 80 struct kcondvar intr_cv; 81 82 int specver; /* spec. version */ 83 84 uint32_t flags; /* flags for this host */ 85 #define SHF_USE_DMA 0x0001 86 #define SHF_USE_4BIT_MODE 0x0002 87 #define SHF_USE_8BIT_MODE 0x0004 88 }; 89 90 #define HDEVNAME(hp) (device_xname((hp)->sc->sc_dev)) 91 #define HDEVINST(hp) ((int)(((hp)-(hp)->sc->sc_host[0])/sizeof(*(hp)))) 92 93 static uint8_t 94 hread1(struct sdhc_host *hp, bus_size_t reg) 95 { 96 97 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) 98 return bus_space_read_1(hp->iot, hp->ioh, reg); 99 return bus_space_read_4(hp->iot, hp->ioh, reg & -4) >> (8 * (reg & 3)); 100 } 101 102 static uint16_t 103 hread2(struct sdhc_host *hp, bus_size_t reg) 104 { 105 106 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) 107 return bus_space_read_2(hp->iot, hp->ioh, reg); 108 return bus_space_read_4(hp->iot, hp->ioh, reg & -4) >> (8 * (reg & 2)); 109 } 110 111 #define HREAD1(hp, reg) hread1(hp, reg) 112 #define HREAD2(hp, reg) hread2(hp, reg) 113 #define HREAD4(hp, reg) \ 114 (bus_space_read_4((hp)->iot, (hp)->ioh, (reg))) 115 116 117 static void 118 hwrite1(struct sdhc_host *hp, bus_size_t o, uint8_t val) 119 { 120 121 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 122 bus_space_write_1(hp->iot, hp->ioh, o, val); 123 } else { 124 const size_t shift = 8 * (o & 3); 125 o &= -4; 126 uint32_t tmp = bus_space_read_4(hp->iot, hp->ioh, o); 127 tmp = (val << shift) | (tmp & ~(0xff << shift)); 128 bus_space_write_4(hp->iot, hp->ioh, o, tmp); 129 } 130 } 131 132 static void 133 hwrite2(struct sdhc_host *hp, bus_size_t o, uint16_t val) 134 { 135 136 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 137 bus_space_write_2(hp->iot, hp->ioh, o, val); 138 } else { 139 const size_t shift = 8 * (o & 2); 140 o &= -4; 141 uint32_t tmp = bus_space_read_4(hp->iot, hp->ioh, o); 142 tmp = (val << shift) | (tmp & ~(0xffff << shift)); 143 bus_space_write_4(hp->iot, hp->ioh, o, tmp); 144 } 145 } 146 147 #define HWRITE1(hp, reg, val) hwrite1(hp, reg, val) 148 #define HWRITE2(hp, reg, val) hwrite2(hp, reg, val) 149 #define HWRITE4(hp, reg, val) \ 150 bus_space_write_4((hp)->iot, (hp)->ioh, (reg), (val)) 151 152 #define HCLR1(hp, reg, bits) \ 153 do if (bits) HWRITE1((hp), (reg), HREAD1((hp), (reg)) & ~(bits)); while (0) 154 #define HCLR2(hp, reg, bits) \ 155 do if (bits) HWRITE2((hp), (reg), HREAD2((hp), (reg)) & ~(bits)); while (0) 156 #define HCLR4(hp, reg, bits) \ 157 do if (bits) HWRITE4((hp), (reg), HREAD4((hp), (reg)) & ~(bits)); while (0) 158 #define HSET1(hp, reg, bits) \ 159 do if (bits) HWRITE1((hp), (reg), HREAD1((hp), (reg)) | (bits)); while (0) 160 #define HSET2(hp, reg, bits) \ 161 do if (bits) HWRITE2((hp), (reg), HREAD2((hp), (reg)) | (bits)); while (0) 162 #define HSET4(hp, reg, bits) \ 163 do if (bits) HWRITE4((hp), (reg), HREAD4((hp), (reg)) | (bits)); while (0) 164 165 static int sdhc_host_reset(sdmmc_chipset_handle_t); 166 static int sdhc_host_reset1(sdmmc_chipset_handle_t); 167 static uint32_t sdhc_host_ocr(sdmmc_chipset_handle_t); 168 static int sdhc_host_maxblklen(sdmmc_chipset_handle_t); 169 static int sdhc_card_detect(sdmmc_chipset_handle_t); 170 static int sdhc_write_protect(sdmmc_chipset_handle_t); 171 static int sdhc_bus_power(sdmmc_chipset_handle_t, uint32_t); 172 static int sdhc_bus_clock(sdmmc_chipset_handle_t, int); 173 static int sdhc_bus_width(sdmmc_chipset_handle_t, int); 174 static int sdhc_bus_rod(sdmmc_chipset_handle_t, int); 175 static void sdhc_card_enable_intr(sdmmc_chipset_handle_t, int); 176 static void sdhc_card_intr_ack(sdmmc_chipset_handle_t); 177 static void sdhc_exec_command(sdmmc_chipset_handle_t, 178 struct sdmmc_command *); 179 static int sdhc_start_command(struct sdhc_host *, struct sdmmc_command *); 180 static int sdhc_wait_state(struct sdhc_host *, uint32_t, uint32_t); 181 static int sdhc_soft_reset(struct sdhc_host *, int); 182 static int sdhc_wait_intr(struct sdhc_host *, int, int); 183 static void sdhc_transfer_data(struct sdhc_host *, struct sdmmc_command *); 184 static int sdhc_transfer_data_dma(struct sdhc_host *, struct sdmmc_command *); 185 static int sdhc_transfer_data_pio(struct sdhc_host *, struct sdmmc_command *); 186 static void sdhc_read_data_pio(struct sdhc_host *, uint8_t *, u_int); 187 static void sdhc_write_data_pio(struct sdhc_host *, uint8_t *, u_int); 188 static void esdhc_read_data_pio(struct sdhc_host *, uint8_t *, u_int); 189 static void esdhc_write_data_pio(struct sdhc_host *, uint8_t *, u_int); 190 191 192 static struct sdmmc_chip_functions sdhc_functions = { 193 /* host controller reset */ 194 sdhc_host_reset, 195 196 /* host controller capabilities */ 197 sdhc_host_ocr, 198 sdhc_host_maxblklen, 199 200 /* card detection */ 201 sdhc_card_detect, 202 203 /* write protect */ 204 sdhc_write_protect, 205 206 /* bus power, clock frequency and width */ 207 sdhc_bus_power, 208 sdhc_bus_clock, 209 sdhc_bus_width, 210 sdhc_bus_rod, 211 212 /* command execution */ 213 sdhc_exec_command, 214 215 /* card interrupt */ 216 sdhc_card_enable_intr, 217 sdhc_card_intr_ack 218 }; 219 220 static int 221 sdhc_cfprint(void *aux, const char *pnp) 222 { 223 const struct sdmmcbus_attach_args * const saa = aux; 224 const struct sdhc_host * const hp = saa->saa_sch; 225 226 if (pnp) { 227 aprint_normal("sdmmc at %s", pnp); 228 } 229 aprint_normal(" slot %d", HDEVINST(hp)); 230 231 return UNCONF; 232 } 233 234 /* 235 * Called by attachment driver. For each SD card slot there is one SD 236 * host controller standard register set. (1.3) 237 */ 238 int 239 sdhc_host_found(struct sdhc_softc *sc, bus_space_tag_t iot, 240 bus_space_handle_t ioh, bus_size_t iosize) 241 { 242 struct sdmmcbus_attach_args saa; 243 struct sdhc_host *hp; 244 uint32_t caps; 245 uint16_t sdhcver; 246 247 sdhcver = bus_space_read_2(iot, ioh, SDHC_HOST_CTL_VERSION); 248 aprint_normal_dev(sc->sc_dev, "SD Host Specification "); 249 switch (SDHC_SPEC_VERSION(sdhcver)) { 250 case SDHC_SPEC_VERS_100: 251 aprint_normal("1.0"); 252 break; 253 254 case SDHC_SPEC_VERS_200: 255 aprint_normal("2.0"); 256 break; 257 258 case SDHC_SPEC_VERS_300: 259 aprint_normal("3.0"); 260 break; 261 262 default: 263 aprint_normal("unknown version(0x%x)", 264 SDHC_SPEC_VERSION(sdhcver)); 265 break; 266 } 267 aprint_normal(", rev.%u\n", SDHC_VENDOR_VERSION(sdhcver)); 268 269 /* Allocate one more host structure. */ 270 hp = malloc(sizeof(struct sdhc_host), M_DEVBUF, M_WAITOK|M_ZERO); 271 if (hp == NULL) { 272 aprint_error_dev(sc->sc_dev, 273 "couldn't alloc memory (sdhc host)\n"); 274 goto err1; 275 } 276 sc->sc_host[sc->sc_nhosts++] = hp; 277 278 /* Fill in the new host structure. */ 279 hp->sc = sc; 280 hp->iot = iot; 281 hp->ioh = ioh; 282 hp->dmat = sc->sc_dmat; 283 hp->specver = SDHC_SPEC_VERSION(sdhcver); 284 285 mutex_init(&hp->host_mtx, MUTEX_DEFAULT, IPL_SDMMC); 286 mutex_init(&hp->intr_mtx, MUTEX_DEFAULT, IPL_SDMMC); 287 cv_init(&hp->intr_cv, "sdhcintr"); 288 289 /* 290 * Reset the host controller and enable interrupts. 291 */ 292 (void)sdhc_host_reset(hp); 293 294 /* Determine host capabilities. */ 295 if (ISSET(sc->sc_flags, SDHC_FLAG_HOSTCAPS)) { 296 caps = sc->sc_caps; 297 } else { 298 mutex_enter(&hp->host_mtx); 299 caps = HREAD4(hp, SDHC_CAPABILITIES); 300 mutex_exit(&hp->host_mtx); 301 } 302 303 /* Use DMA if the host system and the controller support it. */ 304 if (ISSET(sc->sc_flags, SDHC_FLAG_FORCE_DMA) || 305 (ISSET(sc->sc_flags, SDHC_FLAG_USE_DMA && 306 ISSET(caps, SDHC_DMA_SUPPORT)))) { 307 SET(hp->flags, SHF_USE_DMA); 308 aprint_normal_dev(sc->sc_dev, "using DMA transfer\n"); 309 } 310 311 /* 312 * Determine the base clock frequency. (2.2.24) 313 */ 314 if (hp->specver == SDHC_SPEC_VERS_300) { 315 hp->clkbase = SDHC_BASE_V3_FREQ_KHZ(caps); 316 } else { 317 hp->clkbase = SDHC_BASE_FREQ_KHZ(caps); 318 } 319 if (hp->clkbase == 0) { 320 if (sc->sc_clkbase == 0) { 321 /* The attachment driver must tell us. */ 322 aprint_error_dev(sc->sc_dev, 323 "unknown base clock frequency\n"); 324 goto err; 325 } 326 hp->clkbase = sc->sc_clkbase; 327 } 328 if (hp->clkbase < 10000 || hp->clkbase > 10000 * 256) { 329 /* SDHC 1.0 supports only 10-63 MHz. */ 330 aprint_error_dev(sc->sc_dev, 331 "base clock frequency out of range: %u MHz\n", 332 hp->clkbase / 1000); 333 goto err; 334 } 335 DPRINTF(1,("%s: base clock frequency %u MHz\n", 336 device_xname(sc->sc_dev), hp->clkbase / 1000)); 337 338 /* 339 * XXX Set the data timeout counter value according to 340 * capabilities. (2.2.15) 341 */ 342 HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX); 343 #if 1 344 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 345 HWRITE4(hp, SDHC_NINTR_STATUS, SDHC_CMD_TIMEOUT_ERROR << 16); 346 #endif 347 348 /* 349 * Determine SD bus voltage levels supported by the controller. 350 */ 351 if (ISSET(caps, SDHC_VOLTAGE_SUPP_1_8V)) { 352 SET(hp->ocr, MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V); 353 } 354 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_0V)) { 355 SET(hp->ocr, MMC_OCR_2_9V_3_0V | MMC_OCR_3_0V_3_1V); 356 } 357 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_3V)) { 358 SET(hp->ocr, MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V); 359 } 360 361 /* 362 * Determine the maximum block length supported by the host 363 * controller. (2.2.24) 364 */ 365 switch((caps >> SDHC_MAX_BLK_LEN_SHIFT) & SDHC_MAX_BLK_LEN_MASK) { 366 case SDHC_MAX_BLK_LEN_512: 367 hp->maxblklen = 512; 368 break; 369 370 case SDHC_MAX_BLK_LEN_1024: 371 hp->maxblklen = 1024; 372 break; 373 374 case SDHC_MAX_BLK_LEN_2048: 375 hp->maxblklen = 2048; 376 break; 377 378 case SDHC_MAX_BLK_LEN_4096: 379 hp->maxblklen = 4096; 380 break; 381 382 default: 383 aprint_error_dev(sc->sc_dev, "max block length unknown\n"); 384 goto err; 385 } 386 DPRINTF(1, ("%s: max block length %u byte%s\n", 387 device_xname(sc->sc_dev), hp->maxblklen, 388 hp->maxblklen > 1 ? "s" : "")); 389 390 /* 391 * Attach the generic SD/MMC bus driver. (The bus driver must 392 * not invoke any chipset functions before it is attached.) 393 */ 394 memset(&saa, 0, sizeof(saa)); 395 saa.saa_busname = "sdmmc"; 396 saa.saa_sct = &sdhc_functions; 397 saa.saa_sch = hp; 398 saa.saa_dmat = hp->dmat; 399 saa.saa_clkmin = hp->clkbase / 256; 400 saa.saa_clkmax = hp->clkbase; 401 if (ISSET(sc->sc_flags, SDHC_FLAG_HAVE_CGM)) 402 saa.saa_clkmin /= 2046; 403 else if (ISSET(sc->sc_flags, SDHC_FLAG_HAVE_DVS)) 404 saa.saa_clkmin /= 16; 405 saa.saa_caps = SMC_CAPS_4BIT_MODE|SMC_CAPS_AUTO_STOP; 406 if (ISSET(sc->sc_flags, SDHC_FLAG_8BIT_MODE)) 407 saa.saa_caps |= SMC_CAPS_8BIT_MODE; 408 if (ISSET(caps, SDHC_HIGH_SPEED_SUPP)) 409 saa.saa_caps |= SMC_CAPS_SD_HIGHSPEED; 410 if (ISSET(hp->flags, SHF_USE_DMA)) { 411 saa.saa_caps |= SMC_CAPS_DMA; 412 if (hp->specver == SDHC_SPEC_VERS_100) { 413 saa.saa_caps |= SMC_CAPS_MULTI_SEG_DMA; 414 } 415 } 416 if (ISSET(sc->sc_flags, SDHC_FLAG_SINGLE_ONLY)) 417 saa.saa_caps |= SMC_CAPS_SINGLE_ONLY; 418 hp->sdmmc = config_found(sc->sc_dev, &saa, sdhc_cfprint); 419 420 return 0; 421 422 err: 423 cv_destroy(&hp->intr_cv); 424 mutex_destroy(&hp->intr_mtx); 425 mutex_destroy(&hp->host_mtx); 426 free(hp, M_DEVBUF); 427 sc->sc_host[--sc->sc_nhosts] = NULL; 428 err1: 429 return 1; 430 } 431 432 int 433 sdhc_detach(device_t dev, int flags) 434 { 435 struct sdhc_host *hp = (struct sdhc_host *)dev; 436 struct sdhc_softc *sc = hp->sc; 437 int rv = 0; 438 439 if (hp->sdmmc) 440 rv = config_detach(hp->sdmmc, flags); 441 442 cv_destroy(&hp->intr_cv); 443 mutex_destroy(&hp->intr_mtx); 444 mutex_destroy(&hp->host_mtx); 445 free(hp, M_DEVBUF); 446 sc->sc_host[--sc->sc_nhosts] = NULL; 447 448 return rv; 449 } 450 451 bool 452 sdhc_suspend(device_t dev, const pmf_qual_t *qual) 453 { 454 struct sdhc_softc *sc = device_private(dev); 455 struct sdhc_host *hp; 456 size_t i; 457 458 /* XXX poll for command completion or suspend command 459 * in progress */ 460 461 /* Save the host controller state. */ 462 for (size_t n = 0; n < sc->sc_nhosts; n++) { 463 hp = sc->sc_host[n]; 464 if (ISSET(sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 465 for (i = 0; i < sizeof hp->regs; i += 4) { 466 uint32_t v = HREAD4(hp, i); 467 hp->regs[i + 0] = (v >> 0); 468 hp->regs[i + 1] = (v >> 8); 469 if (i + 3 < sizeof hp->regs) { 470 hp->regs[i + 2] = (v >> 16); 471 hp->regs[i + 3] = (v >> 24); 472 } 473 } 474 } else { 475 for (i = 0; i < sizeof hp->regs; i++) { 476 hp->regs[i] = HREAD1(hp, i); 477 } 478 } 479 } 480 return true; 481 } 482 483 bool 484 sdhc_resume(device_t dev, const pmf_qual_t *qual) 485 { 486 struct sdhc_softc *sc = device_private(dev); 487 struct sdhc_host *hp; 488 size_t i; 489 490 /* Restore the host controller state. */ 491 for (size_t n = 0; n < sc->sc_nhosts; n++) { 492 hp = sc->sc_host[n]; 493 (void)sdhc_host_reset(hp); 494 if (ISSET(sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 495 for (i = 0; i < sizeof hp->regs; i += 4) { 496 if (i + 3 < sizeof hp->regs) { 497 HWRITE4(hp, i, 498 (hp->regs[i + 0] << 0) 499 | (hp->regs[i + 1] << 8) 500 | (hp->regs[i + 2] << 16) 501 | (hp->regs[i + 3] << 24)); 502 } else { 503 HWRITE4(hp, i, 504 (hp->regs[i + 0] << 0) 505 | (hp->regs[i + 1] << 8)); 506 } 507 } 508 } else { 509 for (i = 0; i < sizeof hp->regs; i++) { 510 HWRITE1(hp, i, hp->regs[i]); 511 } 512 } 513 } 514 return true; 515 } 516 517 bool 518 sdhc_shutdown(device_t dev, int flags) 519 { 520 struct sdhc_softc *sc = device_private(dev); 521 struct sdhc_host *hp; 522 523 /* XXX chip locks up if we don't disable it before reboot. */ 524 for (size_t i = 0; i < sc->sc_nhosts; i++) { 525 hp = sc->sc_host[i]; 526 (void)sdhc_host_reset(hp); 527 } 528 return true; 529 } 530 531 /* 532 * Reset the host controller. Called during initialization, when 533 * cards are removed, upon resume, and during error recovery. 534 */ 535 static int 536 sdhc_host_reset1(sdmmc_chipset_handle_t sch) 537 { 538 struct sdhc_host *hp = (struct sdhc_host *)sch; 539 uint32_t sdhcimask; 540 int error; 541 542 /* Don't lock. */ 543 544 /* Disable all interrupts. */ 545 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 546 HWRITE4(hp, SDHC_NINTR_SIGNAL_EN, 0); 547 } else { 548 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, 0); 549 } 550 551 /* 552 * Reset the entire host controller and wait up to 100ms for 553 * the controller to clear the reset bit. 554 */ 555 error = sdhc_soft_reset(hp, SDHC_RESET_ALL); 556 if (error) 557 goto out; 558 559 /* Set data timeout counter value to max for now. */ 560 HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX); 561 #if 1 562 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 563 HWRITE4(hp, SDHC_NINTR_STATUS, SDHC_CMD_TIMEOUT_ERROR << 16); 564 #endif 565 566 /* Enable interrupts. */ 567 mutex_enter(&hp->intr_mtx); 568 sdhcimask = SDHC_CARD_REMOVAL | SDHC_CARD_INSERTION | 569 SDHC_BUFFER_READ_READY | SDHC_BUFFER_WRITE_READY | 570 SDHC_DMA_INTERRUPT | SDHC_BLOCK_GAP_EVENT | 571 SDHC_TRANSFER_COMPLETE | SDHC_COMMAND_COMPLETE; 572 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 573 sdhcimask |= SDHC_EINTR_STATUS_MASK << 16; 574 HWRITE4(hp, SDHC_NINTR_STATUS_EN, sdhcimask); 575 sdhcimask ^= 576 (SDHC_EINTR_STATUS_MASK ^ SDHC_EINTR_SIGNAL_MASK) << 16; 577 sdhcimask ^= SDHC_BUFFER_READ_READY ^ SDHC_BUFFER_WRITE_READY; 578 HWRITE4(hp, SDHC_NINTR_SIGNAL_EN, sdhcimask); 579 } else { 580 HWRITE2(hp, SDHC_NINTR_STATUS_EN, sdhcimask); 581 HWRITE2(hp, SDHC_EINTR_STATUS_EN, SDHC_EINTR_STATUS_MASK); 582 sdhcimask ^= SDHC_BUFFER_READ_READY ^ SDHC_BUFFER_WRITE_READY; 583 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, sdhcimask); 584 HWRITE2(hp, SDHC_EINTR_SIGNAL_EN, SDHC_EINTR_SIGNAL_MASK); 585 } 586 mutex_exit(&hp->intr_mtx); 587 588 out: 589 return error; 590 } 591 592 static int 593 sdhc_host_reset(sdmmc_chipset_handle_t sch) 594 { 595 struct sdhc_host *hp = (struct sdhc_host *)sch; 596 int error; 597 598 mutex_enter(&hp->host_mtx); 599 error = sdhc_host_reset1(sch); 600 mutex_exit(&hp->host_mtx); 601 602 return error; 603 } 604 605 static uint32_t 606 sdhc_host_ocr(sdmmc_chipset_handle_t sch) 607 { 608 struct sdhc_host *hp = (struct sdhc_host *)sch; 609 610 return hp->ocr; 611 } 612 613 static int 614 sdhc_host_maxblklen(sdmmc_chipset_handle_t sch) 615 { 616 struct sdhc_host *hp = (struct sdhc_host *)sch; 617 618 return hp->maxblklen; 619 } 620 621 /* 622 * Return non-zero if the card is currently inserted. 623 */ 624 static int 625 sdhc_card_detect(sdmmc_chipset_handle_t sch) 626 { 627 struct sdhc_host *hp = (struct sdhc_host *)sch; 628 int r; 629 630 if (hp->sc->sc_vendor_card_detect) 631 return (*hp->sc->sc_vendor_card_detect)(hp->sc); 632 633 mutex_enter(&hp->host_mtx); 634 r = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CARD_INSERTED); 635 mutex_exit(&hp->host_mtx); 636 637 return r ? 1 : 0; 638 } 639 640 /* 641 * Return non-zero if the card is currently write-protected. 642 */ 643 static int 644 sdhc_write_protect(sdmmc_chipset_handle_t sch) 645 { 646 struct sdhc_host *hp = (struct sdhc_host *)sch; 647 int r; 648 649 if (hp->sc->sc_vendor_write_protect) 650 return (*hp->sc->sc_vendor_write_protect)(hp->sc); 651 652 mutex_enter(&hp->host_mtx); 653 r = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_WRITE_PROTECT_SWITCH); 654 mutex_exit(&hp->host_mtx); 655 656 return r ? 0 : 1; 657 } 658 659 /* 660 * Set or change SD bus voltage and enable or disable SD bus power. 661 * Return zero on success. 662 */ 663 static int 664 sdhc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 665 { 666 struct sdhc_host *hp = (struct sdhc_host *)sch; 667 uint8_t vdd; 668 int error = 0; 669 const uint32_t pcmask = 670 ~(SDHC_BUS_POWER | (SDHC_VOLTAGE_MASK << SDHC_VOLTAGE_SHIFT)); 671 672 mutex_enter(&hp->host_mtx); 673 674 /* 675 * Disable bus power before voltage change. 676 */ 677 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS) 678 && !ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_PWR0)) 679 HWRITE1(hp, SDHC_POWER_CTL, 0); 680 681 /* If power is disabled, reset the host and return now. */ 682 if (ocr == 0) { 683 (void)sdhc_host_reset1(hp); 684 goto out; 685 } 686 687 /* 688 * Select the lowest voltage according to capabilities. 689 */ 690 ocr &= hp->ocr; 691 if (ISSET(ocr, MMC_OCR_1_7V_1_8V|MMC_OCR_1_8V_1_9V)) { 692 vdd = SDHC_VOLTAGE_1_8V; 693 } else if (ISSET(ocr, MMC_OCR_2_9V_3_0V|MMC_OCR_3_0V_3_1V)) { 694 vdd = SDHC_VOLTAGE_3_0V; 695 } else if (ISSET(ocr, MMC_OCR_3_2V_3_3V|MMC_OCR_3_3V_3_4V)) { 696 vdd = SDHC_VOLTAGE_3_3V; 697 } else { 698 /* Unsupported voltage level requested. */ 699 error = EINVAL; 700 goto out; 701 } 702 703 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 704 /* 705 * Enable bus power. Wait at least 1 ms (or 74 clocks) plus 706 * voltage ramp until power rises. 707 */ 708 HWRITE1(hp, SDHC_POWER_CTL, 709 HREAD1(hp, SDHC_POWER_CTL) & pcmask); 710 sdmmc_delay(1); 711 HWRITE1(hp, SDHC_POWER_CTL, (vdd << SDHC_VOLTAGE_SHIFT)); 712 sdmmc_delay(1); 713 HSET1(hp, SDHC_POWER_CTL, SDHC_BUS_POWER); 714 sdmmc_delay(10000); 715 716 /* 717 * The host system may not power the bus due to battery low, 718 * etc. In that case, the host controller should clear the 719 * bus power bit. 720 */ 721 if (!ISSET(HREAD1(hp, SDHC_POWER_CTL), SDHC_BUS_POWER)) { 722 error = ENXIO; 723 goto out; 724 } 725 } 726 727 out: 728 mutex_exit(&hp->host_mtx); 729 730 return error; 731 } 732 733 /* 734 * Return the smallest possible base clock frequency divisor value 735 * for the CLOCK_CTL register to produce `freq' (KHz). 736 */ 737 static bool 738 sdhc_clock_divisor(struct sdhc_host *hp, u_int freq, u_int *divp) 739 { 740 u_int div; 741 742 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_HAVE_CGM)) { 743 for (div = hp->clkbase / freq; div <= 0x3ff; div++) { 744 if ((hp->clkbase / div) <= freq) { 745 *divp = SDHC_SDCLK_CGM 746 | ((div & 0x300) << SDHC_SDCLK_XDIV_SHIFT) 747 | ((div & 0x0ff) << SDHC_SDCLK_DIV_SHIFT); 748 //freq = hp->clkbase / div; 749 return true; 750 } 751 } 752 /* No divisor found. */ 753 return false; 754 } 755 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_HAVE_DVS)) { 756 u_int dvs = (hp->clkbase + freq - 1) / freq; 757 u_int roundup = dvs & 1; 758 for (dvs >>= 1, div = 1; div <= 256; div <<= 1, dvs >>= 1) { 759 if (dvs + roundup <= 16) { 760 dvs += roundup - 1; 761 *divp = (div << SDHC_SDCLK_DIV_SHIFT) 762 | (dvs << SDHC_SDCLK_DVS_SHIFT); 763 DPRINTF(2, 764 ("%s: divisor for freq %u is %u * %u\n", 765 HDEVNAME(hp), freq, div * 2, dvs + 1)); 766 //freq = hp->clkbase / (div * 2) * (dvs + 1); 767 return true; 768 } 769 /* 770 * If we drop bits, we need to round up the divisor. 771 */ 772 roundup |= dvs & 1; 773 } 774 /* No divisor found. */ 775 return false; 776 } else { 777 if (hp->sc->sc_clkmsk != 0) 778 *divp = (hp->clkbase / freq) << 779 (ffs(hp->sc->sc_clkmsk) - 1); 780 else 781 *divp = (hp->clkbase / freq) << SDHC_SDCLK_DIV_SHIFT; 782 return true; 783 } 784 /* No divisor found. */ 785 return false; 786 } 787 788 /* 789 * Set or change SDCLK frequency or disable the SD clock. 790 * Return zero on success. 791 */ 792 static int 793 sdhc_bus_clock(sdmmc_chipset_handle_t sch, int freq) 794 { 795 struct sdhc_host *hp = (struct sdhc_host *)sch; 796 u_int div; 797 u_int timo; 798 int16_t reg; 799 int error = 0; 800 #ifdef DIAGNOSTIC 801 bool present; 802 803 mutex_enter(&hp->host_mtx); 804 present = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CMD_INHIBIT_MASK); 805 mutex_exit(&hp->host_mtx); 806 807 /* Must not stop the clock if commands are in progress. */ 808 if (present && sdhc_card_detect(hp)) { 809 aprint_normal_dev(hp->sc->sc_dev, 810 "%s: command in progress\n", __func__); 811 } 812 #endif 813 814 mutex_enter(&hp->host_mtx); 815 816 /* 817 * Stop SD clock before changing the frequency. 818 */ 819 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 820 HCLR4(hp, SDHC_CLOCK_CTL, 0xfff8); 821 if (freq == SDMMC_SDCLK_OFF) { 822 HSET4(hp, SDHC_CLOCK_CTL, 0x80f0); 823 goto out; 824 } 825 } else { 826 HCLR2(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE); 827 if (freq == SDMMC_SDCLK_OFF) 828 goto out; 829 } 830 831 /* 832 * Set the minimum base clock frequency divisor. 833 */ 834 if (!sdhc_clock_divisor(hp, freq, &div)) { 835 /* Invalid base clock frequency or `freq' value. */ 836 error = EINVAL; 837 goto out; 838 } 839 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 840 HWRITE4(hp, SDHC_CLOCK_CTL, 841 div | (SDHC_TIMEOUT_MAX << 16)); 842 } else { 843 reg = HREAD2(hp, SDHC_CLOCK_CTL); 844 reg &= (SDHC_INTCLK_STABLE | SDHC_INTCLK_ENABLE); 845 HWRITE2(hp, SDHC_CLOCK_CTL, reg | div); 846 } 847 848 /* 849 * Start internal clock. Wait 10ms for stabilization. 850 */ 851 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 852 sdmmc_delay(10000); 853 HSET4(hp, SDHC_CLOCK_CTL, 854 8 | SDHC_INTCLK_ENABLE | SDHC_INTCLK_STABLE); 855 } else { 856 HSET2(hp, SDHC_CLOCK_CTL, SDHC_INTCLK_ENABLE); 857 for (timo = 1000; timo > 0; timo--) { 858 if (ISSET(HREAD2(hp, SDHC_CLOCK_CTL), 859 SDHC_INTCLK_STABLE)) 860 break; 861 sdmmc_delay(10); 862 } 863 if (timo == 0) { 864 error = ETIMEDOUT; 865 goto out; 866 } 867 } 868 869 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 870 HSET1(hp, SDHC_SOFTWARE_RESET, SDHC_INIT_ACTIVE); 871 /* 872 * Sending 80 clocks at 400kHz takes 200us. 873 * So delay for that time + slop and then 874 * check a few times for completion. 875 */ 876 sdmmc_delay(210); 877 for (timo = 10; timo > 0; timo--) { 878 if (!ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), 879 SDHC_INIT_ACTIVE)) 880 break; 881 sdmmc_delay(10); 882 } 883 DPRINTF(2,("%s: %u init spins\n", __func__, 10 - timo)); 884 885 /* 886 * Enable SD clock. 887 */ 888 HSET4(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE); 889 } else { 890 /* 891 * Enable SD clock. 892 */ 893 HSET2(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE); 894 895 if (freq > 25000) 896 HSET1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED); 897 else 898 HCLR1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED); 899 } 900 901 out: 902 mutex_exit(&hp->host_mtx); 903 904 return error; 905 } 906 907 static int 908 sdhc_bus_width(sdmmc_chipset_handle_t sch, int width) 909 { 910 struct sdhc_host *hp = (struct sdhc_host *)sch; 911 int reg; 912 913 switch (width) { 914 case 1: 915 case 4: 916 break; 917 918 case 8: 919 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_8BIT_MODE)) 920 break; 921 /* FALLTHROUGH */ 922 default: 923 DPRINTF(0,("%s: unsupported bus width (%d)\n", 924 HDEVNAME(hp), width)); 925 return 1; 926 } 927 928 mutex_enter(&hp->host_mtx); 929 reg = HREAD1(hp, SDHC_HOST_CTL); 930 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 931 reg &= ~(SDHC_4BIT_MODE|SDHC_ESDHC_8BIT_MODE); 932 if (width == 4) 933 reg |= SDHC_4BIT_MODE; 934 else if (width == 8) 935 reg |= SDHC_ESDHC_8BIT_MODE; 936 } else { 937 reg &= ~SDHC_4BIT_MODE; 938 if (width == 4) 939 reg |= SDHC_4BIT_MODE; 940 } 941 HWRITE1(hp, SDHC_HOST_CTL, reg); 942 mutex_exit(&hp->host_mtx); 943 944 return 0; 945 } 946 947 static int 948 sdhc_bus_rod(sdmmc_chipset_handle_t sch, int on) 949 { 950 struct sdhc_host *hp = (struct sdhc_host *)sch; 951 952 if (hp->sc->sc_vendor_rod) 953 return (*hp->sc->sc_vendor_rod)(hp->sc, on); 954 955 return 0; 956 } 957 958 static void 959 sdhc_card_enable_intr(sdmmc_chipset_handle_t sch, int enable) 960 { 961 struct sdhc_host *hp = (struct sdhc_host *)sch; 962 963 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 964 mutex_enter(&hp->intr_mtx); 965 if (enable) { 966 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 967 HSET2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT); 968 } else { 969 HCLR2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT); 970 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 971 } 972 mutex_exit(&hp->intr_mtx); 973 } 974 } 975 976 static void 977 sdhc_card_intr_ack(sdmmc_chipset_handle_t sch) 978 { 979 struct sdhc_host *hp = (struct sdhc_host *)sch; 980 981 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 982 mutex_enter(&hp->intr_mtx); 983 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 984 mutex_exit(&hp->intr_mtx); 985 } 986 } 987 988 static int 989 sdhc_wait_state(struct sdhc_host *hp, uint32_t mask, uint32_t value) 990 { 991 uint32_t state; 992 int timeout; 993 994 for (timeout = 10; timeout > 0; timeout--) { 995 if (((state = HREAD4(hp, SDHC_PRESENT_STATE)) & mask) == value) 996 return 0; 997 sdmmc_delay(10000); 998 } 999 DPRINTF(0,("%s: timeout waiting for %x (state=%x)\n", HDEVNAME(hp), 1000 value, state)); 1001 return ETIMEDOUT; 1002 } 1003 1004 static void 1005 sdhc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 1006 { 1007 struct sdhc_host *hp = (struct sdhc_host *)sch; 1008 int error; 1009 1010 if (cmd->c_data && ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1011 const uint16_t ready = SDHC_BUFFER_READ_READY | SDHC_BUFFER_WRITE_READY; 1012 mutex_enter(&hp->intr_mtx); 1013 if (ISSET(hp->flags, SHF_USE_DMA)) { 1014 HCLR2(hp, SDHC_NINTR_SIGNAL_EN, ready); 1015 HCLR2(hp, SDHC_NINTR_STATUS_EN, ready); 1016 } else { 1017 HSET2(hp, SDHC_NINTR_SIGNAL_EN, ready); 1018 HSET2(hp, SDHC_NINTR_STATUS_EN, ready); 1019 } 1020 mutex_exit(&hp->intr_mtx); 1021 } 1022 1023 /* 1024 * Start the MMC command, or mark `cmd' as failed and return. 1025 */ 1026 error = sdhc_start_command(hp, cmd); 1027 if (error) { 1028 cmd->c_error = error; 1029 goto out; 1030 } 1031 1032 /* 1033 * Wait until the command phase is done, or until the command 1034 * is marked done for any other reason. 1035 */ 1036 if (!sdhc_wait_intr(hp, SDHC_COMMAND_COMPLETE, SDHC_COMMAND_TIMEOUT)) { 1037 cmd->c_error = ETIMEDOUT; 1038 goto out; 1039 } 1040 1041 /* 1042 * The host controller removes bits [0:7] from the response 1043 * data (CRC) and we pass the data up unchanged to the bus 1044 * driver (without padding). 1045 */ 1046 mutex_enter(&hp->host_mtx); 1047 if (cmd->c_error == 0 && ISSET(cmd->c_flags, SCF_RSP_PRESENT)) { 1048 cmd->c_resp[0] = HREAD4(hp, SDHC_RESPONSE + 0); 1049 if (ISSET(cmd->c_flags, SCF_RSP_136)) { 1050 cmd->c_resp[1] = HREAD4(hp, SDHC_RESPONSE + 4); 1051 cmd->c_resp[2] = HREAD4(hp, SDHC_RESPONSE + 8); 1052 cmd->c_resp[3] = HREAD4(hp, SDHC_RESPONSE + 12); 1053 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_RSP136_CRC)) { 1054 cmd->c_resp[0] = (cmd->c_resp[0] >> 8) | 1055 (cmd->c_resp[1] << 24); 1056 cmd->c_resp[1] = (cmd->c_resp[1] >> 8) | 1057 (cmd->c_resp[2] << 24); 1058 cmd->c_resp[2] = (cmd->c_resp[2] >> 8) | 1059 (cmd->c_resp[3] << 24); 1060 cmd->c_resp[3] = (cmd->c_resp[3] >> 8); 1061 } 1062 } 1063 } 1064 mutex_exit(&hp->host_mtx); 1065 DPRINTF(1,("%s: resp = %08x\n", HDEVNAME(hp), cmd->c_resp[0])); 1066 1067 /* 1068 * If the command has data to transfer in any direction, 1069 * execute the transfer now. 1070 */ 1071 if (cmd->c_error == 0 && cmd->c_data != NULL) 1072 sdhc_transfer_data(hp, cmd); 1073 1074 out: 1075 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED) 1076 && !ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_LED_ON)) { 1077 mutex_enter(&hp->host_mtx); 1078 /* Turn off the LED. */ 1079 HCLR1(hp, SDHC_HOST_CTL, SDHC_LED_ON); 1080 mutex_exit(&hp->host_mtx); 1081 } 1082 SET(cmd->c_flags, SCF_ITSDONE); 1083 1084 DPRINTF(1,("%s: cmd %d %s (flags=%08x error=%d)\n", HDEVNAME(hp), 1085 cmd->c_opcode, (cmd->c_error == 0) ? "done" : "abort", 1086 cmd->c_flags, cmd->c_error)); 1087 } 1088 1089 static int 1090 sdhc_start_command(struct sdhc_host *hp, struct sdmmc_command *cmd) 1091 { 1092 struct sdhc_softc * const sc = hp->sc; 1093 uint16_t blksize = 0; 1094 uint16_t blkcount = 0; 1095 uint16_t mode; 1096 uint16_t command; 1097 int error; 1098 1099 DPRINTF(1,("%s: start cmd %d arg=%08x data=%p dlen=%d flags=%08x, status=%#x\n", 1100 HDEVNAME(hp), cmd->c_opcode, cmd->c_arg, cmd->c_data, 1101 cmd->c_datalen, cmd->c_flags, HREAD4(hp, SDHC_NINTR_STATUS))); 1102 1103 /* 1104 * The maximum block length for commands should be the minimum 1105 * of the host buffer size and the card buffer size. (1.7.2) 1106 */ 1107 1108 /* Fragment the data into proper blocks. */ 1109 if (cmd->c_datalen > 0) { 1110 blksize = MIN(cmd->c_datalen, cmd->c_blklen); 1111 blkcount = cmd->c_datalen / blksize; 1112 if (cmd->c_datalen % blksize > 0) { 1113 /* XXX: Split this command. (1.7.4) */ 1114 aprint_error_dev(sc->sc_dev, 1115 "data not a multiple of %u bytes\n", blksize); 1116 return EINVAL; 1117 } 1118 } 1119 1120 /* Check limit imposed by 9-bit block count. (1.7.2) */ 1121 if (blkcount > SDHC_BLOCK_COUNT_MAX) { 1122 aprint_error_dev(sc->sc_dev, "too much data\n"); 1123 return EINVAL; 1124 } 1125 1126 /* Prepare transfer mode register value. (2.2.5) */ 1127 mode = SDHC_BLOCK_COUNT_ENABLE; 1128 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 1129 mode |= SDHC_READ_MODE; 1130 if (blkcount > 1) { 1131 mode |= SDHC_MULTI_BLOCK_MODE; 1132 /* XXX only for memory commands? */ 1133 mode |= SDHC_AUTO_CMD12_ENABLE; 1134 } 1135 if (cmd->c_dmamap != NULL && cmd->c_datalen > 0) { 1136 mode |= SDHC_DMA_ENABLE; 1137 } 1138 1139 /* 1140 * Prepare command register value. (2.2.6) 1141 */ 1142 command = (cmd->c_opcode & SDHC_COMMAND_INDEX_MASK) << SDHC_COMMAND_INDEX_SHIFT; 1143 1144 if (ISSET(cmd->c_flags, SCF_RSP_CRC)) 1145 command |= SDHC_CRC_CHECK_ENABLE; 1146 if (ISSET(cmd->c_flags, SCF_RSP_IDX)) 1147 command |= SDHC_INDEX_CHECK_ENABLE; 1148 if (cmd->c_data != NULL) 1149 command |= SDHC_DATA_PRESENT_SELECT; 1150 1151 if (!ISSET(cmd->c_flags, SCF_RSP_PRESENT)) 1152 command |= SDHC_NO_RESPONSE; 1153 else if (ISSET(cmd->c_flags, SCF_RSP_136)) 1154 command |= SDHC_RESP_LEN_136; 1155 else if (ISSET(cmd->c_flags, SCF_RSP_BSY)) 1156 command |= SDHC_RESP_LEN_48_CHK_BUSY; 1157 else 1158 command |= SDHC_RESP_LEN_48; 1159 1160 /* Wait until command and data inhibit bits are clear. (1.5) */ 1161 error = sdhc_wait_state(hp, SDHC_CMD_INHIBIT_MASK, 0); 1162 if (error) 1163 return error; 1164 1165 DPRINTF(1,("%s: writing cmd: blksize=%d blkcnt=%d mode=%04x cmd=%04x\n", 1166 HDEVNAME(hp), blksize, blkcount, mode, command)); 1167 1168 blksize |= (MAX(0, PAGE_SHIFT - 12) & SDHC_DMA_BOUNDARY_MASK) << 1169 SDHC_DMA_BOUNDARY_SHIFT; /* PAGE_SIZE DMA boundary */ 1170 1171 mutex_enter(&hp->host_mtx); 1172 1173 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1174 /* Alert the user not to remove the card. */ 1175 HSET1(hp, SDHC_HOST_CTL, SDHC_LED_ON); 1176 } 1177 1178 /* Set DMA start address. */ 1179 if (ISSET(mode, SDHC_DMA_ENABLE)) 1180 HWRITE4(hp, SDHC_DMA_ADDR, cmd->c_dmamap->dm_segs[0].ds_addr); 1181 1182 /* 1183 * Start a CPU data transfer. Writing to the high order byte 1184 * of the SDHC_COMMAND register triggers the SD command. (1.5) 1185 */ 1186 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 1187 HWRITE4(hp, SDHC_BLOCK_SIZE, blksize | (blkcount << 16)); 1188 HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg); 1189 HWRITE4(hp, SDHC_TRANSFER_MODE, mode | (command << 16)); 1190 } else { 1191 HWRITE2(hp, SDHC_BLOCK_SIZE, blksize); 1192 HWRITE2(hp, SDHC_BLOCK_COUNT, blkcount); 1193 HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg); 1194 HWRITE2(hp, SDHC_TRANSFER_MODE, mode); 1195 HWRITE2(hp, SDHC_COMMAND, command); 1196 } 1197 1198 mutex_exit(&hp->host_mtx); 1199 1200 return 0; 1201 } 1202 1203 static void 1204 sdhc_transfer_data(struct sdhc_host *hp, struct sdmmc_command *cmd) 1205 { 1206 int error; 1207 1208 DPRINTF(1,("%s: data transfer: resp=%08x datalen=%u\n", HDEVNAME(hp), 1209 MMC_R1(cmd->c_resp), cmd->c_datalen)); 1210 1211 #ifdef SDHC_DEBUG 1212 /* XXX I forgot why I wanted to know when this happens :-( */ 1213 if ((cmd->c_opcode == 52 || cmd->c_opcode == 53) && 1214 ISSET(MMC_R1(cmd->c_resp), 0xcb00)) { 1215 aprint_error_dev(hp->sc->sc_dev, 1216 "CMD52/53 error response flags %#x\n", 1217 MMC_R1(cmd->c_resp) & 0xff00); 1218 } 1219 #endif 1220 1221 if (cmd->c_dmamap != NULL) 1222 error = sdhc_transfer_data_dma(hp, cmd); 1223 else 1224 error = sdhc_transfer_data_pio(hp, cmd); 1225 if (error) 1226 cmd->c_error = error; 1227 SET(cmd->c_flags, SCF_ITSDONE); 1228 1229 DPRINTF(1,("%s: data transfer done (error=%d)\n", 1230 HDEVNAME(hp), cmd->c_error)); 1231 } 1232 1233 static int 1234 sdhc_transfer_data_dma(struct sdhc_host *hp, struct sdmmc_command *cmd) 1235 { 1236 bus_dma_segment_t *dm_segs = cmd->c_dmamap->dm_segs; 1237 bus_addr_t posaddr; 1238 bus_addr_t segaddr; 1239 bus_size_t seglen; 1240 u_int seg = 0; 1241 int error = 0; 1242 int status; 1243 1244 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_DMA_INTERRUPT); 1245 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_DMA_INTERRUPT); 1246 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_TRANSFER_COMPLETE); 1247 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_TRANSFER_COMPLETE); 1248 1249 for (;;) { 1250 status = sdhc_wait_intr(hp, 1251 SDHC_DMA_INTERRUPT|SDHC_TRANSFER_COMPLETE, 1252 SDHC_DMA_TIMEOUT); 1253 1254 if (status & SDHC_TRANSFER_COMPLETE) { 1255 break; 1256 } 1257 if (!status) { 1258 error = ETIMEDOUT; 1259 break; 1260 } 1261 if ((status & SDHC_DMA_INTERRUPT) == 0) { 1262 continue; 1263 } 1264 1265 /* DMA Interrupt (boundary crossing) */ 1266 1267 segaddr = dm_segs[seg].ds_addr; 1268 seglen = dm_segs[seg].ds_len; 1269 mutex_enter(&hp->host_mtx); 1270 posaddr = HREAD4(hp, SDHC_DMA_ADDR); 1271 mutex_exit(&hp->host_mtx); 1272 1273 if ((seg == (cmd->c_dmamap->dm_nsegs-1)) && (posaddr == (segaddr + seglen))) { 1274 break; 1275 } 1276 mutex_enter(&hp->host_mtx); 1277 if ((posaddr >= segaddr) && (posaddr < (segaddr + seglen))) 1278 HWRITE4(hp, SDHC_DMA_ADDR, posaddr); 1279 else if ((posaddr >= segaddr) && (posaddr == (segaddr + seglen)) && (seg + 1) < cmd->c_dmamap->dm_nsegs) 1280 HWRITE4(hp, SDHC_DMA_ADDR, dm_segs[++seg].ds_addr); 1281 mutex_exit(&hp->host_mtx); 1282 KASSERT(seg < cmd->c_dmamap->dm_nsegs); 1283 } 1284 1285 return error; 1286 } 1287 1288 static int 1289 sdhc_transfer_data_pio(struct sdhc_host *hp, struct sdmmc_command *cmd) 1290 { 1291 uint8_t *data = cmd->c_data; 1292 void (*pio_func)(struct sdhc_host *, uint8_t *, u_int); 1293 u_int len, datalen; 1294 u_int imask; 1295 u_int pmask; 1296 int error = 0; 1297 1298 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 1299 imask = SDHC_BUFFER_READ_READY; 1300 pmask = SDHC_BUFFER_READ_ENABLE; 1301 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1302 pio_func = esdhc_read_data_pio; 1303 } else { 1304 pio_func = sdhc_read_data_pio; 1305 } 1306 } else { 1307 imask = SDHC_BUFFER_WRITE_READY; 1308 pmask = SDHC_BUFFER_WRITE_ENABLE; 1309 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1310 pio_func = esdhc_write_data_pio; 1311 } else { 1312 pio_func = sdhc_write_data_pio; 1313 } 1314 } 1315 datalen = cmd->c_datalen; 1316 1317 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & imask); 1318 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_TRANSFER_COMPLETE); 1319 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_TRANSFER_COMPLETE); 1320 1321 while (datalen > 0) { 1322 if (!ISSET(HREAD4(hp, SDHC_PRESENT_STATE), imask)) { 1323 mutex_enter(&hp->intr_mtx); 1324 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 1325 HSET4(hp, SDHC_NINTR_SIGNAL_EN, imask); 1326 } else { 1327 HSET2(hp, SDHC_NINTR_SIGNAL_EN, imask); 1328 } 1329 mutex_exit(&hp->intr_mtx); 1330 if (!sdhc_wait_intr(hp, imask, SDHC_BUFFER_TIMEOUT)) { 1331 error = ETIMEDOUT; 1332 break; 1333 } 1334 1335 error = sdhc_wait_state(hp, pmask, pmask); 1336 if (error) 1337 break; 1338 } 1339 1340 len = MIN(datalen, cmd->c_blklen); 1341 (*pio_func)(hp, data, len); 1342 DPRINTF(2,("%s: pio data transfer %u @ %p\n", 1343 HDEVNAME(hp), len, data)); 1344 1345 data += len; 1346 datalen -= len; 1347 } 1348 1349 if (error == 0 && !sdhc_wait_intr(hp, SDHC_TRANSFER_COMPLETE, 1350 SDHC_TRANSFER_TIMEOUT)) 1351 error = ETIMEDOUT; 1352 1353 return error; 1354 } 1355 1356 static void 1357 sdhc_read_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1358 { 1359 1360 if (((__uintptr_t)data & 3) == 0) { 1361 while (datalen > 3) { 1362 *(uint32_t *)data = le32toh(HREAD4(hp, SDHC_DATA)); 1363 data += 4; 1364 datalen -= 4; 1365 } 1366 if (datalen > 1) { 1367 *(uint16_t *)data = le16toh(HREAD2(hp, SDHC_DATA)); 1368 data += 2; 1369 datalen -= 2; 1370 } 1371 if (datalen > 0) { 1372 *data = HREAD1(hp, SDHC_DATA); 1373 data += 1; 1374 datalen -= 1; 1375 } 1376 } else if (((__uintptr_t)data & 1) == 0) { 1377 while (datalen > 1) { 1378 *(uint16_t *)data = le16toh(HREAD2(hp, SDHC_DATA)); 1379 data += 2; 1380 datalen -= 2; 1381 } 1382 if (datalen > 0) { 1383 *data = HREAD1(hp, SDHC_DATA); 1384 data += 1; 1385 datalen -= 1; 1386 } 1387 } else { 1388 while (datalen > 0) { 1389 *data = HREAD1(hp, SDHC_DATA); 1390 data += 1; 1391 datalen -= 1; 1392 } 1393 } 1394 } 1395 1396 static void 1397 sdhc_write_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1398 { 1399 1400 if (((__uintptr_t)data & 3) == 0) { 1401 while (datalen > 3) { 1402 HWRITE4(hp, SDHC_DATA, htole32(*(uint32_t *)data)); 1403 data += 4; 1404 datalen -= 4; 1405 } 1406 if (datalen > 1) { 1407 HWRITE2(hp, SDHC_DATA, htole16(*(uint16_t *)data)); 1408 data += 2; 1409 datalen -= 2; 1410 } 1411 if (datalen > 0) { 1412 HWRITE1(hp, SDHC_DATA, *data); 1413 data += 1; 1414 datalen -= 1; 1415 } 1416 } else if (((__uintptr_t)data & 1) == 0) { 1417 while (datalen > 1) { 1418 HWRITE2(hp, SDHC_DATA, htole16(*(uint16_t *)data)); 1419 data += 2; 1420 datalen -= 2; 1421 } 1422 if (datalen > 0) { 1423 HWRITE1(hp, SDHC_DATA, *data); 1424 data += 1; 1425 datalen -= 1; 1426 } 1427 } else { 1428 while (datalen > 0) { 1429 HWRITE1(hp, SDHC_DATA, *data); 1430 data += 1; 1431 datalen -= 1; 1432 } 1433 } 1434 } 1435 1436 static void 1437 esdhc_read_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1438 { 1439 uint16_t status = HREAD2(hp, SDHC_NINTR_STATUS); 1440 uint32_t v; 1441 1442 const size_t watermark = (HREAD4(hp, SDHC_WATERMARK_LEVEL) >> SDHC_WATERMARK_READ_SHIFT) & SDHC_WATERMARK_READ_MASK; 1443 size_t count = 0; 1444 1445 while (datalen > 3 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1446 if (count == 0) { 1447 /* 1448 * If we've drained "watermark" words, we need to wait 1449 * a little bit so the read FIFO can refill. 1450 */ 1451 sdmmc_delay(10); 1452 count = watermark; 1453 } 1454 v = HREAD4(hp, SDHC_DATA); 1455 v = le32toh(v); 1456 *(uint32_t *)data = v; 1457 data += 4; 1458 datalen -= 4; 1459 status = HREAD2(hp, SDHC_NINTR_STATUS); 1460 count--; 1461 } 1462 if (datalen > 0 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1463 if (count == 0) { 1464 sdmmc_delay(10); 1465 } 1466 v = HREAD4(hp, SDHC_DATA); 1467 v = le32toh(v); 1468 do { 1469 *data++ = v; 1470 v >>= 8; 1471 } while (--datalen > 0); 1472 } 1473 } 1474 1475 static void 1476 esdhc_write_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1477 { 1478 uint16_t status = HREAD2(hp, SDHC_NINTR_STATUS); 1479 uint32_t v; 1480 1481 const size_t watermark = (HREAD4(hp, SDHC_WATERMARK_LEVEL) >> SDHC_WATERMARK_WRITE_SHIFT) & SDHC_WATERMARK_WRITE_MASK; 1482 size_t count = watermark; 1483 1484 while (datalen > 3 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1485 if (count == 0) { 1486 sdmmc_delay(10); 1487 count = watermark; 1488 } 1489 v = *(uint32_t *)data; 1490 v = htole32(v); 1491 HWRITE4(hp, SDHC_DATA, v); 1492 data += 4; 1493 datalen -= 4; 1494 status = HREAD2(hp, SDHC_NINTR_STATUS); 1495 count--; 1496 } 1497 if (datalen > 0 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1498 if (count == 0) { 1499 sdmmc_delay(10); 1500 } 1501 v = *(uint32_t *)data; 1502 v = htole32(v); 1503 HWRITE4(hp, SDHC_DATA, v); 1504 } 1505 } 1506 1507 /* Prepare for another command. */ 1508 static int 1509 sdhc_soft_reset(struct sdhc_host *hp, int mask) 1510 { 1511 int timo; 1512 1513 DPRINTF(1,("%s: software reset reg=%08x\n", HDEVNAME(hp), mask)); 1514 1515 HWRITE1(hp, SDHC_SOFTWARE_RESET, mask); 1516 for (timo = 10; timo > 0; timo--) { 1517 if (!ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), mask)) 1518 break; 1519 sdmmc_delay(10000); 1520 HWRITE1(hp, SDHC_SOFTWARE_RESET, 0); 1521 } 1522 if (timo == 0) { 1523 DPRINTF(1,("%s: timeout reg=%08x\n", HDEVNAME(hp), 1524 HREAD1(hp, SDHC_SOFTWARE_RESET))); 1525 HWRITE1(hp, SDHC_SOFTWARE_RESET, 0); 1526 return ETIMEDOUT; 1527 } 1528 1529 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1530 HWRITE4(hp, SDHC_DMA_CTL, SDHC_DMA_SNOOP); 1531 } 1532 1533 return 0; 1534 } 1535 1536 static int 1537 sdhc_wait_intr(struct sdhc_host *hp, int mask, int timo) 1538 { 1539 int status; 1540 1541 mask |= SDHC_ERROR_INTERRUPT; 1542 1543 mutex_enter(&hp->intr_mtx); 1544 status = hp->intr_status & mask; 1545 while (status == 0) { 1546 if (cv_timedwait(&hp->intr_cv, &hp->intr_mtx, timo) 1547 == EWOULDBLOCK) { 1548 status |= SDHC_ERROR_INTERRUPT; 1549 break; 1550 } 1551 status = hp->intr_status & mask; 1552 } 1553 hp->intr_status &= ~status; 1554 1555 DPRINTF(2,("%s: intr status %#x error %#x\n", HDEVNAME(hp), status, 1556 hp->intr_error_status)); 1557 1558 /* Command timeout has higher priority than command complete. */ 1559 if (ISSET(status, SDHC_ERROR_INTERRUPT) || hp->intr_error_status) { 1560 hp->intr_error_status = 0; 1561 hp->intr_status &= ~SDHC_ERROR_INTERRUPT; 1562 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1563 (void)sdhc_soft_reset(hp, SDHC_RESET_DAT|SDHC_RESET_CMD); 1564 } 1565 status = 0; 1566 } 1567 mutex_exit(&hp->intr_mtx); 1568 1569 return status; 1570 } 1571 1572 /* 1573 * Established by attachment driver at interrupt priority IPL_SDMMC. 1574 */ 1575 int 1576 sdhc_intr(void *arg) 1577 { 1578 struct sdhc_softc *sc = (struct sdhc_softc *)arg; 1579 struct sdhc_host *hp; 1580 int done = 0; 1581 uint16_t status; 1582 uint16_t error; 1583 1584 /* We got an interrupt, but we don't know from which slot. */ 1585 for (size_t host = 0; host < sc->sc_nhosts; host++) { 1586 hp = sc->sc_host[host]; 1587 if (hp == NULL) 1588 continue; 1589 1590 if (ISSET(sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 1591 /* Find out which interrupts are pending. */ 1592 uint32_t xstatus = HREAD4(hp, SDHC_NINTR_STATUS); 1593 status = xstatus; 1594 error = xstatus >> 16; 1595 if (error) 1596 xstatus |= SDHC_ERROR_INTERRUPT; 1597 else if (!ISSET(status, SDHC_NINTR_STATUS_MASK)) 1598 continue; /* no interrupt for us */ 1599 /* Acknowledge the interrupts we are about to handle. */ 1600 HWRITE4(hp, SDHC_NINTR_STATUS, xstatus); 1601 } else { 1602 /* Find out which interrupts are pending. */ 1603 error = 0; 1604 status = HREAD2(hp, SDHC_NINTR_STATUS); 1605 if (!ISSET(status, SDHC_NINTR_STATUS_MASK)) 1606 continue; /* no interrupt for us */ 1607 /* Acknowledge the interrupts we are about to handle. */ 1608 HWRITE2(hp, SDHC_NINTR_STATUS, status); 1609 if (ISSET(status, SDHC_ERROR_INTERRUPT)) { 1610 /* Acknowledge error interrupts. */ 1611 error = HREAD2(hp, SDHC_EINTR_STATUS); 1612 HWRITE2(hp, SDHC_EINTR_STATUS, error); 1613 } 1614 } 1615 1616 DPRINTF(2,("%s: interrupt status=%x error=%x\n", HDEVNAME(hp), 1617 status, error)); 1618 1619 mutex_enter(&hp->intr_mtx); 1620 1621 /* Claim this interrupt. */ 1622 done = 1; 1623 1624 /* 1625 * Service error interrupts. 1626 */ 1627 if (ISSET(error, SDHC_CMD_TIMEOUT_ERROR| 1628 SDHC_DATA_TIMEOUT_ERROR)) { 1629 hp->intr_error_status |= error; 1630 hp->intr_status |= status; 1631 cv_broadcast(&hp->intr_cv); 1632 } 1633 1634 /* 1635 * Wake up the sdmmc event thread to scan for cards. 1636 */ 1637 if (ISSET(status, SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)) { 1638 sdmmc_needs_discover(hp->sdmmc); 1639 if (ISSET(sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1640 HCLR4(hp, SDHC_NINTR_STATUS_EN, 1641 status & (SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)); 1642 HCLR4(hp, SDHC_NINTR_SIGNAL_EN, 1643 status & (SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)); 1644 } 1645 } 1646 1647 /* 1648 * Wake up the blocking process to service command 1649 * related interrupt(s). 1650 */ 1651 if (ISSET(status, SDHC_COMMAND_COMPLETE| 1652 SDHC_BUFFER_READ_READY|SDHC_BUFFER_WRITE_READY| 1653 SDHC_TRANSFER_COMPLETE|SDHC_DMA_INTERRUPT)) { 1654 hp->intr_status |= status; 1655 if (ISSET(sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1656 HCLR4(hp, SDHC_NINTR_SIGNAL_EN, 1657 status & (SDHC_BUFFER_READ_READY|SDHC_BUFFER_WRITE_READY)); 1658 } 1659 cv_broadcast(&hp->intr_cv); 1660 } 1661 1662 /* 1663 * Service SD card interrupts. 1664 */ 1665 if (!ISSET(sc->sc_flags, SDHC_FLAG_ENHANCED) 1666 && ISSET(status, SDHC_CARD_INTERRUPT)) { 1667 DPRINTF(0,("%s: card interrupt\n", HDEVNAME(hp))); 1668 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 1669 sdmmc_card_intr(hp->sdmmc); 1670 } 1671 mutex_exit(&hp->intr_mtx); 1672 } 1673 1674 return done; 1675 } 1676 1677 #ifdef SDHC_DEBUG 1678 void 1679 sdhc_dump_regs(struct sdhc_host *hp) 1680 { 1681 1682 printf("0x%02x PRESENT_STATE: %x\n", SDHC_PRESENT_STATE, 1683 HREAD4(hp, SDHC_PRESENT_STATE)); 1684 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 1685 printf("0x%02x POWER_CTL: %x\n", SDHC_POWER_CTL, 1686 HREAD1(hp, SDHC_POWER_CTL)); 1687 printf("0x%02x NINTR_STATUS: %x\n", SDHC_NINTR_STATUS, 1688 HREAD2(hp, SDHC_NINTR_STATUS)); 1689 printf("0x%02x EINTR_STATUS: %x\n", SDHC_EINTR_STATUS, 1690 HREAD2(hp, SDHC_EINTR_STATUS)); 1691 printf("0x%02x NINTR_STATUS_EN: %x\n", SDHC_NINTR_STATUS_EN, 1692 HREAD2(hp, SDHC_NINTR_STATUS_EN)); 1693 printf("0x%02x EINTR_STATUS_EN: %x\n", SDHC_EINTR_STATUS_EN, 1694 HREAD2(hp, SDHC_EINTR_STATUS_EN)); 1695 printf("0x%02x NINTR_SIGNAL_EN: %x\n", SDHC_NINTR_SIGNAL_EN, 1696 HREAD2(hp, SDHC_NINTR_SIGNAL_EN)); 1697 printf("0x%02x EINTR_SIGNAL_EN: %x\n", SDHC_EINTR_SIGNAL_EN, 1698 HREAD2(hp, SDHC_EINTR_SIGNAL_EN)); 1699 printf("0x%02x CAPABILITIES: %x\n", SDHC_CAPABILITIES, 1700 HREAD4(hp, SDHC_CAPABILITIES)); 1701 printf("0x%02x MAX_CAPABILITIES: %x\n", SDHC_MAX_CAPABILITIES, 1702 HREAD4(hp, SDHC_MAX_CAPABILITIES)); 1703 } 1704 #endif 1705
Indexes created Tue Sep 23 07:09:52 GMT 2025