sdhc.c revision 1.44.2.8
1 /* $NetBSD: sdhc.c,v 1.44.2.8 2015/04/19 04:31:40 msaitoh Exp $ */ 2 /* $OpenBSD: sdhc.c,v 1.25 2009/01/13 19:44:20 grange Exp $ */ 3 4 /* 5 * Copyright (c) 2006 Uwe Stuehler <uwe (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * SD Host Controller driver based on the SD Host Controller Standard 22 * Simplified Specification Version 1.00 (www.sdcard.com). 23 */ 24 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: sdhc.c,v 1.44.2.8 2015/04/19 04:31:40 msaitoh Exp $"); 27 28 #ifdef _KERNEL_OPT 29 #include "opt_sdmmc.h" 30 #endif 31 32 #include <sys/param.h> 33 #include <sys/device.h> 34 #include <sys/kernel.h> 35 #include <sys/kthread.h> 36 #include <sys/malloc.h> 37 #include <sys/systm.h> 38 #include <sys/mutex.h> 39 #include <sys/condvar.h> 40 41 #include <dev/sdmmc/sdhcreg.h> 42 #include <dev/sdmmc/sdhcvar.h> 43 #include <dev/sdmmc/sdmmcchip.h> 44 #include <dev/sdmmc/sdmmcreg.h> 45 #include <dev/sdmmc/sdmmcvar.h> 46 47 #ifdef SDHC_DEBUG 48 int sdhcdebug = 1; 49 #define DPRINTF(n,s) do { if ((n) <= sdhcdebug) printf s; } while (0) 50 void sdhc_dump_regs(struct sdhc_host *); 51 #else 52 #define DPRINTF(n,s) do {} while (0) 53 #endif 54 55 #define SDHC_COMMAND_TIMEOUT hz 56 #define SDHC_BUFFER_TIMEOUT hz 57 #define SDHC_TRANSFER_TIMEOUT hz 58 #define SDHC_DMA_TIMEOUT hz 59 60 struct sdhc_host { 61 struct sdhc_softc *sc; /* host controller device */ 62 63 bus_space_tag_t iot; /* host register set tag */ 64 bus_space_handle_t ioh; /* host register set handle */ 65 bus_size_t ios; /* host register space size */ 66 bus_dma_tag_t dmat; /* host DMA tag */ 67 68 device_t sdmmc; /* generic SD/MMC device */ 69 70 struct kmutex host_mtx; 71 72 u_int clkbase; /* base clock frequency in KHz */ 73 int maxblklen; /* maximum block length */ 74 uint32_t ocr; /* OCR value from capabilities */ 75 76 uint8_t regs[14]; /* host controller state */ 77 78 uint16_t intr_status; /* soft interrupt status */ 79 uint16_t intr_error_status; /* soft error status */ 80 struct kmutex intr_mtx; 81 struct kcondvar intr_cv; 82 83 int specver; /* spec. version */ 84 85 uint32_t flags; /* flags for this host */ 86 #define SHF_USE_DMA 0x0001 87 #define SHF_USE_4BIT_MODE 0x0002 88 #define SHF_USE_8BIT_MODE 0x0004 89 #define SHF_MODE_DMAEN 0x0008 /* needs SDHC_DMA_ENABLE in mode */ 90 }; 91 92 #define HDEVNAME(hp) (device_xname((hp)->sc->sc_dev)) 93 94 static uint8_t 95 hread1(struct sdhc_host *hp, bus_size_t reg) 96 { 97 98 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) 99 return bus_space_read_1(hp->iot, hp->ioh, reg); 100 return bus_space_read_4(hp->iot, hp->ioh, reg & -4) >> (8 * (reg & 3)); 101 } 102 103 static uint16_t 104 hread2(struct sdhc_host *hp, bus_size_t reg) 105 { 106 107 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) 108 return bus_space_read_2(hp->iot, hp->ioh, reg); 109 return bus_space_read_4(hp->iot, hp->ioh, reg & -4) >> (8 * (reg & 2)); 110 } 111 112 #define HREAD1(hp, reg) hread1(hp, reg) 113 #define HREAD2(hp, reg) hread2(hp, reg) 114 #define HREAD4(hp, reg) \ 115 (bus_space_read_4((hp)->iot, (hp)->ioh, (reg))) 116 117 118 static void 119 hwrite1(struct sdhc_host *hp, bus_size_t o, uint8_t val) 120 { 121 122 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 123 bus_space_write_1(hp->iot, hp->ioh, o, val); 124 } else { 125 const size_t shift = 8 * (o & 3); 126 o &= -4; 127 uint32_t tmp = bus_space_read_4(hp->iot, hp->ioh, o); 128 tmp = (val << shift) | (tmp & ~(0xff << shift)); 129 bus_space_write_4(hp->iot, hp->ioh, o, tmp); 130 } 131 } 132 133 static void 134 hwrite2(struct sdhc_host *hp, bus_size_t o, uint16_t val) 135 { 136 137 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 138 bus_space_write_2(hp->iot, hp->ioh, o, val); 139 } else { 140 const size_t shift = 8 * (o & 2); 141 o &= -4; 142 uint32_t tmp = bus_space_read_4(hp->iot, hp->ioh, o); 143 tmp = (val << shift) | (tmp & ~(0xffff << shift)); 144 bus_space_write_4(hp->iot, hp->ioh, o, tmp); 145 } 146 } 147 148 #define HWRITE1(hp, reg, val) hwrite1(hp, reg, val) 149 #define HWRITE2(hp, reg, val) hwrite2(hp, reg, val) 150 #define HWRITE4(hp, reg, val) \ 151 bus_space_write_4((hp)->iot, (hp)->ioh, (reg), (val)) 152 153 #define HCLR1(hp, reg, bits) \ 154 do if (bits) HWRITE1((hp), (reg), HREAD1((hp), (reg)) & ~(bits)); while (0) 155 #define HCLR2(hp, reg, bits) \ 156 do if (bits) HWRITE2((hp), (reg), HREAD2((hp), (reg)) & ~(bits)); while (0) 157 #define HCLR4(hp, reg, bits) \ 158 do if (bits) HWRITE4((hp), (reg), HREAD4((hp), (reg)) & ~(bits)); while (0) 159 #define HSET1(hp, reg, bits) \ 160 do if (bits) HWRITE1((hp), (reg), HREAD1((hp), (reg)) | (bits)); while (0) 161 #define HSET2(hp, reg, bits) \ 162 do if (bits) HWRITE2((hp), (reg), HREAD2((hp), (reg)) | (bits)); while (0) 163 #define HSET4(hp, reg, bits) \ 164 do if (bits) HWRITE4((hp), (reg), HREAD4((hp), (reg)) | (bits)); while (0) 165 166 static int sdhc_host_reset(sdmmc_chipset_handle_t); 167 static int sdhc_host_reset1(sdmmc_chipset_handle_t); 168 static uint32_t sdhc_host_ocr(sdmmc_chipset_handle_t); 169 static int sdhc_host_maxblklen(sdmmc_chipset_handle_t); 170 static int sdhc_card_detect(sdmmc_chipset_handle_t); 171 static int sdhc_write_protect(sdmmc_chipset_handle_t); 172 static int sdhc_bus_power(sdmmc_chipset_handle_t, uint32_t); 173 static int sdhc_bus_clock(sdmmc_chipset_handle_t, int); 174 static int sdhc_bus_width(sdmmc_chipset_handle_t, int); 175 static int sdhc_bus_rod(sdmmc_chipset_handle_t, int); 176 static void sdhc_card_enable_intr(sdmmc_chipset_handle_t, int); 177 static void sdhc_card_intr_ack(sdmmc_chipset_handle_t); 178 static void sdhc_exec_command(sdmmc_chipset_handle_t, 179 struct sdmmc_command *); 180 static int sdhc_start_command(struct sdhc_host *, struct sdmmc_command *); 181 static int sdhc_wait_state(struct sdhc_host *, uint32_t, uint32_t); 182 static int sdhc_soft_reset(struct sdhc_host *, int); 183 static int sdhc_wait_intr(struct sdhc_host *, int, int); 184 static void sdhc_transfer_data(struct sdhc_host *, struct sdmmc_command *); 185 static int sdhc_transfer_data_dma(struct sdhc_host *, struct sdmmc_command *); 186 static int sdhc_transfer_data_pio(struct sdhc_host *, struct sdmmc_command *); 187 static void sdhc_read_data_pio(struct sdhc_host *, uint8_t *, u_int); 188 static void sdhc_write_data_pio(struct sdhc_host *, uint8_t *, u_int); 189 static void esdhc_read_data_pio(struct sdhc_host *, uint8_t *, u_int); 190 static void esdhc_write_data_pio(struct sdhc_host *, uint8_t *, u_int); 191 192 193 static struct sdmmc_chip_functions sdhc_functions = { 194 /* host controller reset */ 195 sdhc_host_reset, 196 197 /* host controller capabilities */ 198 sdhc_host_ocr, 199 sdhc_host_maxblklen, 200 201 /* card detection */ 202 sdhc_card_detect, 203 204 /* write protect */ 205 sdhc_write_protect, 206 207 /* bus power, clock frequency and width */ 208 sdhc_bus_power, 209 sdhc_bus_clock, 210 sdhc_bus_width, 211 sdhc_bus_rod, 212 213 /* command execution */ 214 sdhc_exec_command, 215 216 /* card interrupt */ 217 sdhc_card_enable_intr, 218 sdhc_card_intr_ack 219 }; 220 221 static int 222 sdhc_cfprint(void *aux, const char *pnp) 223 { 224 const struct sdmmcbus_attach_args * const saa = aux; 225 const struct sdhc_host * const hp = saa->saa_sch; 226 227 if (pnp) { 228 aprint_normal("sdmmc at %s", pnp); 229 } 230 for (size_t host = 0; host < hp->sc->sc_nhosts; host++) { 231 if (hp->sc->sc_host[host] == hp) { 232 aprint_normal(" slot %zu", host); 233 } 234 } 235 236 return UNCONF; 237 } 238 239 /* 240 * Called by attachment driver. For each SD card slot there is one SD 241 * host controller standard register set. (1.3) 242 */ 243 int 244 sdhc_host_found(struct sdhc_softc *sc, bus_space_tag_t iot, 245 bus_space_handle_t ioh, bus_size_t iosize) 246 { 247 struct sdmmcbus_attach_args saa; 248 struct sdhc_host *hp; 249 uint32_t caps; 250 uint16_t sdhcver; 251 252 /* Allocate one more host structure. */ 253 hp = malloc(sizeof(struct sdhc_host), M_DEVBUF, M_WAITOK|M_ZERO); 254 if (hp == NULL) { 255 aprint_error_dev(sc->sc_dev, 256 "couldn't alloc memory (sdhc host)\n"); 257 goto err1; 258 } 259 sc->sc_host[sc->sc_nhosts++] = hp; 260 261 /* Fill in the new host structure. */ 262 hp->sc = sc; 263 hp->iot = iot; 264 hp->ioh = ioh; 265 hp->ios = iosize; 266 hp->dmat = sc->sc_dmat; 267 268 mutex_init(&hp->host_mtx, MUTEX_DEFAULT, IPL_SDMMC); 269 mutex_init(&hp->intr_mtx, MUTEX_DEFAULT, IPL_SDMMC); 270 cv_init(&hp->intr_cv, "sdhcintr"); 271 272 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 273 sdhcver = HREAD4(hp, SDHC_ESDHC_HOST_CTL_VERSION); 274 } else { 275 sdhcver = HREAD2(hp, SDHC_HOST_CTL_VERSION); 276 } 277 aprint_normal_dev(sc->sc_dev, "SD Host Specification "); 278 hp->specver = SDHC_SPEC_VERSION(sdhcver); 279 switch (SDHC_SPEC_VERSION(sdhcver)) { 280 case SDHC_SPEC_VERS_100: 281 aprint_normal("1.0"); 282 break; 283 284 case SDHC_SPEC_VERS_200: 285 aprint_normal("2.0"); 286 break; 287 288 case SDHC_SPEC_VERS_300: 289 aprint_normal("3.0"); 290 break; 291 292 default: 293 aprint_normal("unknown version(0x%x)", 294 SDHC_SPEC_VERSION(sdhcver)); 295 break; 296 } 297 aprint_normal(", rev.%u\n", SDHC_VENDOR_VERSION(sdhcver)); 298 299 /* 300 * Reset the host controller and enable interrupts. 301 */ 302 (void)sdhc_host_reset(hp); 303 304 /* Determine host capabilities. */ 305 if (ISSET(sc->sc_flags, SDHC_FLAG_HOSTCAPS)) { 306 caps = sc->sc_caps; 307 } else { 308 mutex_enter(&hp->host_mtx); 309 caps = HREAD4(hp, SDHC_CAPABILITIES); 310 mutex_exit(&hp->host_mtx); 311 } 312 313 /* 314 * Use DMA if the host system and the controller support it. 315 * Suports integrated or external DMA egine, with or without 316 * SDHC_DMA_ENABLE in the command. 317 */ 318 if (ISSET(sc->sc_flags, SDHC_FLAG_FORCE_DMA) || 319 (ISSET(sc->sc_flags, SDHC_FLAG_USE_DMA && 320 ISSET(caps, SDHC_DMA_SUPPORT)))) { 321 SET(hp->flags, SHF_USE_DMA); 322 if (!ISSET(sc->sc_flags, SDHC_FLAG_EXTERNAL_DMA) || 323 ISSET(sc->sc_flags, SDHC_FLAG_EXTDMA_DMAEN)) 324 SET(hp->flags, SHF_MODE_DMAEN); 325 326 aprint_normal_dev(sc->sc_dev, "using DMA transfer\n"); 327 } 328 329 /* 330 * Determine the base clock frequency. (2.2.24) 331 */ 332 if (hp->specver == SDHC_SPEC_VERS_300) { 333 hp->clkbase = SDHC_BASE_V3_FREQ_KHZ(caps); 334 } else { 335 hp->clkbase = SDHC_BASE_FREQ_KHZ(caps); 336 } 337 if (hp->clkbase == 0) { 338 if (sc->sc_clkbase == 0) { 339 /* The attachment driver must tell us. */ 340 aprint_error_dev(sc->sc_dev, 341 "unknown base clock frequency\n"); 342 goto err; 343 } 344 hp->clkbase = sc->sc_clkbase; 345 } 346 if (hp->clkbase < 10000 || hp->clkbase > 10000 * 256) { 347 /* SDHC 1.0 supports only 10-63 MHz. */ 348 aprint_error_dev(sc->sc_dev, 349 "base clock frequency out of range: %u MHz\n", 350 hp->clkbase / 1000); 351 goto err; 352 } 353 DPRINTF(1,("%s: base clock frequency %u MHz\n", 354 device_xname(sc->sc_dev), hp->clkbase / 1000)); 355 356 /* 357 * XXX Set the data timeout counter value according to 358 * capabilities. (2.2.15) 359 */ 360 HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX); 361 #if 1 362 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 363 HWRITE4(hp, SDHC_NINTR_STATUS, SDHC_CMD_TIMEOUT_ERROR << 16); 364 #endif 365 366 /* 367 * Determine SD bus voltage levels supported by the controller. 368 */ 369 if (ISSET(caps, SDHC_VOLTAGE_SUPP_1_8V) && 370 (hp->specver < SDHC_SPEC_VERS_300 || 371 ISSET(caps, SDHC_EMBEDDED_SLOT))) { 372 SET(hp->ocr, MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V); 373 } 374 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_0V)) { 375 SET(hp->ocr, MMC_OCR_2_9V_3_0V | MMC_OCR_3_0V_3_1V); 376 } 377 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_3V)) { 378 SET(hp->ocr, MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V); 379 } 380 381 /* 382 * Determine the maximum block length supported by the host 383 * controller. (2.2.24) 384 */ 385 switch((caps >> SDHC_MAX_BLK_LEN_SHIFT) & SDHC_MAX_BLK_LEN_MASK) { 386 case SDHC_MAX_BLK_LEN_512: 387 hp->maxblklen = 512; 388 break; 389 390 case SDHC_MAX_BLK_LEN_1024: 391 hp->maxblklen = 1024; 392 break; 393 394 case SDHC_MAX_BLK_LEN_2048: 395 hp->maxblklen = 2048; 396 break; 397 398 case SDHC_MAX_BLK_LEN_4096: 399 hp->maxblklen = 4096; 400 break; 401 402 default: 403 aprint_error_dev(sc->sc_dev, "max block length unknown\n"); 404 goto err; 405 } 406 DPRINTF(1, ("%s: max block length %u byte%s\n", 407 device_xname(sc->sc_dev), hp->maxblklen, 408 hp->maxblklen > 1 ? "s" : "")); 409 410 /* 411 * Attach the generic SD/MMC bus driver. (The bus driver must 412 * not invoke any chipset functions before it is attached.) 413 */ 414 memset(&saa, 0, sizeof(saa)); 415 saa.saa_busname = "sdmmc"; 416 saa.saa_sct = &sdhc_functions; 417 saa.saa_sch = hp; 418 saa.saa_dmat = hp->dmat; 419 saa.saa_clkmax = hp->clkbase; 420 if (ISSET(sc->sc_flags, SDHC_FLAG_HAVE_CGM)) 421 saa.saa_clkmin = hp->clkbase / 256 / 2046; 422 else if (ISSET(sc->sc_flags, SDHC_FLAG_HAVE_DVS)) 423 saa.saa_clkmin = hp->clkbase / 256 / 16; 424 else if (hp->sc->sc_clkmsk != 0) 425 saa.saa_clkmin = hp->clkbase / (hp->sc->sc_clkmsk >> 426 (ffs(hp->sc->sc_clkmsk) - 1)); 427 else if (hp->specver == SDHC_SPEC_VERS_300) 428 saa.saa_clkmin = hp->clkbase / 0x3ff; 429 else 430 saa.saa_clkmin = hp->clkbase / 256; 431 saa.saa_caps = SMC_CAPS_4BIT_MODE|SMC_CAPS_AUTO_STOP; 432 if (ISSET(sc->sc_flags, SDHC_FLAG_8BIT_MODE)) 433 saa.saa_caps |= SMC_CAPS_8BIT_MODE; 434 if (ISSET(caps, SDHC_HIGH_SPEED_SUPP)) 435 saa.saa_caps |= SMC_CAPS_SD_HIGHSPEED; 436 if (ISSET(hp->flags, SHF_USE_DMA)) { 437 saa.saa_caps |= SMC_CAPS_DMA; 438 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 439 saa.saa_caps |= SMC_CAPS_MULTI_SEG_DMA; 440 } 441 if (ISSET(sc->sc_flags, SDHC_FLAG_SINGLE_ONLY)) 442 saa.saa_caps |= SMC_CAPS_SINGLE_ONLY; 443 hp->sdmmc = config_found(sc->sc_dev, &saa, sdhc_cfprint); 444 445 return 0; 446 447 err: 448 cv_destroy(&hp->intr_cv); 449 mutex_destroy(&hp->intr_mtx); 450 mutex_destroy(&hp->host_mtx); 451 free(hp, M_DEVBUF); 452 sc->sc_host[--sc->sc_nhosts] = NULL; 453 err1: 454 return 1; 455 } 456 457 int 458 sdhc_detach(struct sdhc_softc *sc, int flags) 459 { 460 struct sdhc_host *hp; 461 int rv = 0; 462 463 for (size_t n = 0; n < sc->sc_nhosts; n++) { 464 hp = sc->sc_host[n]; 465 if (hp == NULL) 466 continue; 467 if (hp->sdmmc != NULL) { 468 rv = config_detach(hp->sdmmc, flags); 469 if (rv) 470 break; 471 hp->sdmmc = NULL; 472 } 473 /* disable interrupts */ 474 if ((flags & DETACH_FORCE) == 0) { 475 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 476 HWRITE4(hp, SDHC_NINTR_SIGNAL_EN, 0); 477 } else { 478 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, 0); 479 } 480 sdhc_soft_reset(hp, SDHC_RESET_ALL); 481 } 482 cv_destroy(&hp->intr_cv); 483 mutex_destroy(&hp->intr_mtx); 484 mutex_destroy(&hp->host_mtx); 485 if (hp->ios > 0) { 486 bus_space_unmap(hp->iot, hp->ioh, hp->ios); 487 hp->ios = 0; 488 } 489 free(hp, M_DEVBUF); 490 sc->sc_host[n] = NULL; 491 } 492 493 return rv; 494 } 495 496 bool 497 sdhc_suspend(device_t dev, const pmf_qual_t *qual) 498 { 499 struct sdhc_softc *sc = device_private(dev); 500 struct sdhc_host *hp; 501 size_t i; 502 503 /* XXX poll for command completion or suspend command 504 * in progress */ 505 506 /* Save the host controller state. */ 507 for (size_t n = 0; n < sc->sc_nhosts; n++) { 508 hp = sc->sc_host[n]; 509 if (ISSET(sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 510 for (i = 0; i < sizeof hp->regs; i += 4) { 511 uint32_t v = HREAD4(hp, i); 512 hp->regs[i + 0] = (v >> 0); 513 hp->regs[i + 1] = (v >> 8); 514 if (i + 3 < sizeof hp->regs) { 515 hp->regs[i + 2] = (v >> 16); 516 hp->regs[i + 3] = (v >> 24); 517 } 518 } 519 } else { 520 for (i = 0; i < sizeof hp->regs; i++) { 521 hp->regs[i] = HREAD1(hp, i); 522 } 523 } 524 } 525 return true; 526 } 527 528 bool 529 sdhc_resume(device_t dev, const pmf_qual_t *qual) 530 { 531 struct sdhc_softc *sc = device_private(dev); 532 struct sdhc_host *hp; 533 size_t i; 534 535 /* Restore the host controller state. */ 536 for (size_t n = 0; n < sc->sc_nhosts; n++) { 537 hp = sc->sc_host[n]; 538 (void)sdhc_host_reset(hp); 539 if (ISSET(sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 540 for (i = 0; i < sizeof hp->regs; i += 4) { 541 if (i + 3 < sizeof hp->regs) { 542 HWRITE4(hp, i, 543 (hp->regs[i + 0] << 0) 544 | (hp->regs[i + 1] << 8) 545 | (hp->regs[i + 2] << 16) 546 | (hp->regs[i + 3] << 24)); 547 } else { 548 HWRITE4(hp, i, 549 (hp->regs[i + 0] << 0) 550 | (hp->regs[i + 1] << 8)); 551 } 552 } 553 } else { 554 for (i = 0; i < sizeof hp->regs; i++) { 555 HWRITE1(hp, i, hp->regs[i]); 556 } 557 } 558 } 559 return true; 560 } 561 562 bool 563 sdhc_shutdown(device_t dev, int flags) 564 { 565 struct sdhc_softc *sc = device_private(dev); 566 struct sdhc_host *hp; 567 568 /* XXX chip locks up if we don't disable it before reboot. */ 569 for (size_t i = 0; i < sc->sc_nhosts; i++) { 570 hp = sc->sc_host[i]; 571 (void)sdhc_host_reset(hp); 572 } 573 return true; 574 } 575 576 /* 577 * Reset the host controller. Called during initialization, when 578 * cards are removed, upon resume, and during error recovery. 579 */ 580 static int 581 sdhc_host_reset1(sdmmc_chipset_handle_t sch) 582 { 583 struct sdhc_host *hp = (struct sdhc_host *)sch; 584 uint32_t sdhcimask; 585 int error; 586 587 /* Don't lock. */ 588 589 /* Disable all interrupts. */ 590 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 591 HWRITE4(hp, SDHC_NINTR_SIGNAL_EN, 0); 592 } else { 593 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, 0); 594 } 595 596 /* 597 * Reset the entire host controller and wait up to 100ms for 598 * the controller to clear the reset bit. 599 */ 600 error = sdhc_soft_reset(hp, SDHC_RESET_ALL); 601 if (error) 602 goto out; 603 604 /* Set data timeout counter value to max for now. */ 605 HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX); 606 #if 1 607 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 608 HWRITE4(hp, SDHC_NINTR_STATUS, SDHC_CMD_TIMEOUT_ERROR << 16); 609 #endif 610 611 /* Enable interrupts. */ 612 mutex_enter(&hp->intr_mtx); 613 sdhcimask = SDHC_CARD_REMOVAL | SDHC_CARD_INSERTION | 614 SDHC_BUFFER_READ_READY | SDHC_BUFFER_WRITE_READY | 615 SDHC_DMA_INTERRUPT | SDHC_BLOCK_GAP_EVENT | 616 SDHC_TRANSFER_COMPLETE | SDHC_COMMAND_COMPLETE; 617 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 618 sdhcimask |= SDHC_EINTR_STATUS_MASK << 16; 619 HWRITE4(hp, SDHC_NINTR_STATUS_EN, sdhcimask); 620 sdhcimask ^= 621 (SDHC_EINTR_STATUS_MASK ^ SDHC_EINTR_SIGNAL_MASK) << 16; 622 sdhcimask ^= SDHC_BUFFER_READ_READY ^ SDHC_BUFFER_WRITE_READY; 623 HWRITE4(hp, SDHC_NINTR_SIGNAL_EN, sdhcimask); 624 } else { 625 HWRITE2(hp, SDHC_NINTR_STATUS_EN, sdhcimask); 626 HWRITE2(hp, SDHC_EINTR_STATUS_EN, SDHC_EINTR_STATUS_MASK); 627 sdhcimask ^= SDHC_BUFFER_READ_READY ^ SDHC_BUFFER_WRITE_READY; 628 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, sdhcimask); 629 HWRITE2(hp, SDHC_EINTR_SIGNAL_EN, SDHC_EINTR_SIGNAL_MASK); 630 } 631 mutex_exit(&hp->intr_mtx); 632 633 out: 634 return error; 635 } 636 637 static int 638 sdhc_host_reset(sdmmc_chipset_handle_t sch) 639 { 640 struct sdhc_host *hp = (struct sdhc_host *)sch; 641 int error; 642 643 mutex_enter(&hp->host_mtx); 644 error = sdhc_host_reset1(sch); 645 mutex_exit(&hp->host_mtx); 646 647 return error; 648 } 649 650 static uint32_t 651 sdhc_host_ocr(sdmmc_chipset_handle_t sch) 652 { 653 struct sdhc_host *hp = (struct sdhc_host *)sch; 654 655 return hp->ocr; 656 } 657 658 static int 659 sdhc_host_maxblklen(sdmmc_chipset_handle_t sch) 660 { 661 struct sdhc_host *hp = (struct sdhc_host *)sch; 662 663 return hp->maxblklen; 664 } 665 666 /* 667 * Return non-zero if the card is currently inserted. 668 */ 669 static int 670 sdhc_card_detect(sdmmc_chipset_handle_t sch) 671 { 672 struct sdhc_host *hp = (struct sdhc_host *)sch; 673 int r; 674 675 if (hp->sc->sc_vendor_card_detect) 676 return (*hp->sc->sc_vendor_card_detect)(hp->sc); 677 678 mutex_enter(&hp->host_mtx); 679 r = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CARD_INSERTED); 680 mutex_exit(&hp->host_mtx); 681 682 return r ? 1 : 0; 683 } 684 685 /* 686 * Return non-zero if the card is currently write-protected. 687 */ 688 static int 689 sdhc_write_protect(sdmmc_chipset_handle_t sch) 690 { 691 struct sdhc_host *hp = (struct sdhc_host *)sch; 692 int r; 693 694 if (hp->sc->sc_vendor_write_protect) 695 return (*hp->sc->sc_vendor_write_protect)(hp->sc); 696 697 mutex_enter(&hp->host_mtx); 698 r = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_WRITE_PROTECT_SWITCH); 699 mutex_exit(&hp->host_mtx); 700 701 return r ? 0 : 1; 702 } 703 704 /* 705 * Set or change SD bus voltage and enable or disable SD bus power. 706 * Return zero on success. 707 */ 708 static int 709 sdhc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 710 { 711 struct sdhc_host *hp = (struct sdhc_host *)sch; 712 uint8_t vdd; 713 int error = 0; 714 const uint32_t pcmask = 715 ~(SDHC_BUS_POWER | (SDHC_VOLTAGE_MASK << SDHC_VOLTAGE_SHIFT)); 716 717 mutex_enter(&hp->host_mtx); 718 719 /* 720 * Disable bus power before voltage change. 721 */ 722 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS) 723 && !ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_PWR0)) 724 HWRITE1(hp, SDHC_POWER_CTL, 0); 725 726 /* If power is disabled, reset the host and return now. */ 727 if (ocr == 0) { 728 (void)sdhc_host_reset1(hp); 729 goto out; 730 } 731 732 /* 733 * Select the lowest voltage according to capabilities. 734 */ 735 ocr &= hp->ocr; 736 if (ISSET(ocr, MMC_OCR_1_7V_1_8V|MMC_OCR_1_8V_1_9V)) { 737 vdd = SDHC_VOLTAGE_1_8V; 738 } else if (ISSET(ocr, MMC_OCR_2_9V_3_0V|MMC_OCR_3_0V_3_1V)) { 739 vdd = SDHC_VOLTAGE_3_0V; 740 } else if (ISSET(ocr, MMC_OCR_3_2V_3_3V|MMC_OCR_3_3V_3_4V)) { 741 vdd = SDHC_VOLTAGE_3_3V; 742 } else { 743 /* Unsupported voltage level requested. */ 744 error = EINVAL; 745 goto out; 746 } 747 748 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 749 /* 750 * Enable bus power. Wait at least 1 ms (or 74 clocks) plus 751 * voltage ramp until power rises. 752 */ 753 HWRITE1(hp, SDHC_POWER_CTL, 754 HREAD1(hp, SDHC_POWER_CTL) & pcmask); 755 sdmmc_delay(1); 756 HWRITE1(hp, SDHC_POWER_CTL, (vdd << SDHC_VOLTAGE_SHIFT)); 757 sdmmc_delay(1); 758 HSET1(hp, SDHC_POWER_CTL, SDHC_BUS_POWER); 759 sdmmc_delay(10000); 760 761 /* 762 * The host system may not power the bus due to battery low, 763 * etc. In that case, the host controller should clear the 764 * bus power bit. 765 */ 766 if (!ISSET(HREAD1(hp, SDHC_POWER_CTL), SDHC_BUS_POWER)) { 767 error = ENXIO; 768 goto out; 769 } 770 } 771 772 out: 773 mutex_exit(&hp->host_mtx); 774 775 return error; 776 } 777 778 /* 779 * Return the smallest possible base clock frequency divisor value 780 * for the CLOCK_CTL register to produce `freq' (KHz). 781 */ 782 static bool 783 sdhc_clock_divisor(struct sdhc_host *hp, u_int freq, u_int *divp) 784 { 785 u_int div; 786 787 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_HAVE_CGM)) { 788 for (div = hp->clkbase / freq; div <= 0x3ff; div++) { 789 if ((hp->clkbase / div) <= freq) { 790 *divp = SDHC_SDCLK_CGM 791 | ((div & 0x300) << SDHC_SDCLK_XDIV_SHIFT) 792 | ((div & 0x0ff) << SDHC_SDCLK_DIV_SHIFT); 793 //freq = hp->clkbase / div; 794 return true; 795 } 796 } 797 /* No divisor found. */ 798 return false; 799 } 800 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_HAVE_DVS)) { 801 u_int dvs = (hp->clkbase + freq - 1) / freq; 802 u_int roundup = dvs & 1; 803 for (dvs >>= 1, div = 1; div <= 256; div <<= 1, dvs >>= 1) { 804 if (dvs + roundup <= 16) { 805 dvs += roundup - 1; 806 *divp = (div << SDHC_SDCLK_DIV_SHIFT) 807 | (dvs << SDHC_SDCLK_DVS_SHIFT); 808 DPRINTF(2, 809 ("%s: divisor for freq %u is %u * %u\n", 810 HDEVNAME(hp), freq, div * 2, dvs + 1)); 811 //freq = hp->clkbase / (div * 2) * (dvs + 1); 812 return true; 813 } 814 /* 815 * If we drop bits, we need to round up the divisor. 816 */ 817 roundup |= dvs & 1; 818 } 819 /* No divisor found. */ 820 return false; 821 } 822 if (hp->sc->sc_clkmsk != 0) { 823 div = howmany(hp->clkbase, freq); 824 if (div > (hp->sc->sc_clkmsk >> (ffs(hp->sc->sc_clkmsk) - 1))) 825 return false; 826 *divp = div << (ffs(hp->sc->sc_clkmsk) - 1); 827 //freq = hp->clkbase / div; 828 return true; 829 } 830 if (hp->specver == SDHC_SPEC_VERS_300) { 831 div = howmany(hp->clkbase, freq); 832 div = div > 1 ? howmany(div, 2) : 0; 833 if (div > 0x3ff) 834 return false; 835 *divp = (((div >> 8) & SDHC_SDCLK_XDIV_MASK) 836 << SDHC_SDCLK_XDIV_SHIFT) | 837 (((div >> 0) & SDHC_SDCLK_DIV_MASK) 838 << SDHC_SDCLK_DIV_SHIFT); 839 //freq = hp->clkbase / div; 840 return true; 841 } else { 842 for (div = 1; div <= 256; div *= 2) { 843 if ((hp->clkbase / div) <= freq) { 844 *divp = (div / 2) << SDHC_SDCLK_DIV_SHIFT; 845 //freq = hp->clkbase / div; 846 return true; 847 } 848 } 849 /* No divisor found. */ 850 return false; 851 } 852 /* No divisor found. */ 853 return false; 854 } 855 856 /* 857 * Set or change SDCLK frequency or disable the SD clock. 858 * Return zero on success. 859 */ 860 static int 861 sdhc_bus_clock(sdmmc_chipset_handle_t sch, int freq) 862 { 863 struct sdhc_host *hp = (struct sdhc_host *)sch; 864 u_int div; 865 u_int timo; 866 int16_t reg; 867 int error = 0; 868 #ifdef DIAGNOSTIC 869 bool present; 870 871 mutex_enter(&hp->host_mtx); 872 present = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CMD_INHIBIT_MASK); 873 mutex_exit(&hp->host_mtx); 874 875 /* Must not stop the clock if commands are in progress. */ 876 if (present && sdhc_card_detect(hp)) { 877 aprint_normal_dev(hp->sc->sc_dev, 878 "%s: command in progress\n", __func__); 879 } 880 #endif 881 882 mutex_enter(&hp->host_mtx); 883 884 if (hp->sc->sc_vendor_bus_clock) { 885 error = (*hp->sc->sc_vendor_bus_clock)(hp->sc, freq); 886 if (error != 0) 887 goto out; 888 } 889 890 /* 891 * Stop SD clock before changing the frequency. 892 */ 893 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 894 HCLR4(hp, SDHC_CLOCK_CTL, 0xfff8); 895 if (freq == SDMMC_SDCLK_OFF) { 896 HSET4(hp, SDHC_CLOCK_CTL, 0x80f0); 897 goto out; 898 } 899 } else { 900 HCLR2(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE); 901 if (freq == SDMMC_SDCLK_OFF) 902 goto out; 903 } 904 905 /* 906 * Set the minimum base clock frequency divisor. 907 */ 908 if (!sdhc_clock_divisor(hp, freq, &div)) { 909 /* Invalid base clock frequency or `freq' value. */ 910 error = EINVAL; 911 goto out; 912 } 913 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 914 HWRITE4(hp, SDHC_CLOCK_CTL, 915 div | (SDHC_TIMEOUT_MAX << 16)); 916 } else { 917 reg = HREAD2(hp, SDHC_CLOCK_CTL); 918 reg &= (SDHC_INTCLK_STABLE | SDHC_INTCLK_ENABLE); 919 HWRITE2(hp, SDHC_CLOCK_CTL, reg | div); 920 } 921 922 /* 923 * Start internal clock. Wait 10ms for stabilization. 924 */ 925 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 926 sdmmc_delay(10000); 927 HSET4(hp, SDHC_CLOCK_CTL, 928 8 | SDHC_INTCLK_ENABLE | SDHC_INTCLK_STABLE); 929 } else { 930 HSET2(hp, SDHC_CLOCK_CTL, SDHC_INTCLK_ENABLE); 931 for (timo = 1000; timo > 0; timo--) { 932 if (ISSET(HREAD2(hp, SDHC_CLOCK_CTL), 933 SDHC_INTCLK_STABLE)) 934 break; 935 sdmmc_delay(10); 936 } 937 if (timo == 0) { 938 error = ETIMEDOUT; 939 goto out; 940 } 941 } 942 943 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 944 HSET1(hp, SDHC_SOFTWARE_RESET, SDHC_INIT_ACTIVE); 945 /* 946 * Sending 80 clocks at 400kHz takes 200us. 947 * So delay for that time + slop and then 948 * check a few times for completion. 949 */ 950 sdmmc_delay(210); 951 for (timo = 10; timo > 0; timo--) { 952 if (!ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), 953 SDHC_INIT_ACTIVE)) 954 break; 955 sdmmc_delay(10); 956 } 957 DPRINTF(2,("%s: %u init spins\n", __func__, 10 - timo)); 958 959 /* 960 * Enable SD clock. 961 */ 962 HSET4(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE); 963 } else { 964 /* 965 * Enable SD clock. 966 */ 967 HSET2(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE); 968 969 if (freq > 25000 && 970 !ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_HS_BIT)) 971 HSET1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED); 972 else 973 HCLR1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED); 974 } 975 976 out: 977 mutex_exit(&hp->host_mtx); 978 979 return error; 980 } 981 982 static int 983 sdhc_bus_width(sdmmc_chipset_handle_t sch, int width) 984 { 985 struct sdhc_host *hp = (struct sdhc_host *)sch; 986 int reg; 987 988 switch (width) { 989 case 1: 990 case 4: 991 break; 992 993 case 8: 994 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_8BIT_MODE)) 995 break; 996 /* FALLTHROUGH */ 997 default: 998 DPRINTF(0,("%s: unsupported bus width (%d)\n", 999 HDEVNAME(hp), width)); 1000 return 1; 1001 } 1002 1003 mutex_enter(&hp->host_mtx); 1004 reg = HREAD1(hp, SDHC_HOST_CTL); 1005 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1006 reg &= ~(SDHC_4BIT_MODE|SDHC_ESDHC_8BIT_MODE); 1007 if (width == 4) 1008 reg |= SDHC_4BIT_MODE; 1009 else if (width == 8) 1010 reg |= SDHC_ESDHC_8BIT_MODE; 1011 } else { 1012 reg &= ~SDHC_4BIT_MODE; 1013 if (width == 4) 1014 reg |= SDHC_4BIT_MODE; 1015 } 1016 HWRITE1(hp, SDHC_HOST_CTL, reg); 1017 mutex_exit(&hp->host_mtx); 1018 1019 return 0; 1020 } 1021 1022 static int 1023 sdhc_bus_rod(sdmmc_chipset_handle_t sch, int on) 1024 { 1025 struct sdhc_host *hp = (struct sdhc_host *)sch; 1026 1027 if (hp->sc->sc_vendor_rod) 1028 return (*hp->sc->sc_vendor_rod)(hp->sc, on); 1029 1030 return 0; 1031 } 1032 1033 static void 1034 sdhc_card_enable_intr(sdmmc_chipset_handle_t sch, int enable) 1035 { 1036 struct sdhc_host *hp = (struct sdhc_host *)sch; 1037 1038 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1039 mutex_enter(&hp->intr_mtx); 1040 if (enable) { 1041 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 1042 HSET2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT); 1043 } else { 1044 HCLR2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT); 1045 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 1046 } 1047 mutex_exit(&hp->intr_mtx); 1048 } 1049 } 1050 1051 static void 1052 sdhc_card_intr_ack(sdmmc_chipset_handle_t sch) 1053 { 1054 struct sdhc_host *hp = (struct sdhc_host *)sch; 1055 1056 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1057 mutex_enter(&hp->intr_mtx); 1058 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 1059 mutex_exit(&hp->intr_mtx); 1060 } 1061 } 1062 1063 static int 1064 sdhc_wait_state(struct sdhc_host *hp, uint32_t mask, uint32_t value) 1065 { 1066 uint32_t state; 1067 int timeout; 1068 1069 for (timeout = 10; timeout > 0; timeout--) { 1070 if (((state = HREAD4(hp, SDHC_PRESENT_STATE)) & mask) == value) 1071 return 0; 1072 sdmmc_delay(10000); 1073 } 1074 DPRINTF(0,("%s: timeout waiting for %x (state=%x)\n", HDEVNAME(hp), 1075 value, state)); 1076 return ETIMEDOUT; 1077 } 1078 1079 static void 1080 sdhc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 1081 { 1082 struct sdhc_host *hp = (struct sdhc_host *)sch; 1083 int error; 1084 1085 if (cmd->c_data && ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1086 const uint16_t ready = SDHC_BUFFER_READ_READY | SDHC_BUFFER_WRITE_READY; 1087 mutex_enter(&hp->intr_mtx); 1088 if (ISSET(hp->flags, SHF_USE_DMA)) { 1089 HCLR2(hp, SDHC_NINTR_SIGNAL_EN, ready); 1090 HCLR2(hp, SDHC_NINTR_STATUS_EN, ready); 1091 } else { 1092 HSET2(hp, SDHC_NINTR_SIGNAL_EN, ready); 1093 HSET2(hp, SDHC_NINTR_STATUS_EN, ready); 1094 } 1095 mutex_exit(&hp->intr_mtx); 1096 } 1097 1098 /* 1099 * Start the MMC command, or mark `cmd' as failed and return. 1100 */ 1101 error = sdhc_start_command(hp, cmd); 1102 if (error) { 1103 cmd->c_error = error; 1104 goto out; 1105 } 1106 1107 /* 1108 * Wait until the command phase is done, or until the command 1109 * is marked done for any other reason. 1110 */ 1111 if (!sdhc_wait_intr(hp, SDHC_COMMAND_COMPLETE, SDHC_COMMAND_TIMEOUT)) { 1112 cmd->c_error = ETIMEDOUT; 1113 goto out; 1114 } 1115 1116 /* 1117 * The host controller removes bits [0:7] from the response 1118 * data (CRC) and we pass the data up unchanged to the bus 1119 * driver (without padding). 1120 */ 1121 mutex_enter(&hp->host_mtx); 1122 if (cmd->c_error == 0 && ISSET(cmd->c_flags, SCF_RSP_PRESENT)) { 1123 cmd->c_resp[0] = HREAD4(hp, SDHC_RESPONSE + 0); 1124 if (ISSET(cmd->c_flags, SCF_RSP_136)) { 1125 cmd->c_resp[1] = HREAD4(hp, SDHC_RESPONSE + 4); 1126 cmd->c_resp[2] = HREAD4(hp, SDHC_RESPONSE + 8); 1127 cmd->c_resp[3] = HREAD4(hp, SDHC_RESPONSE + 12); 1128 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_RSP136_CRC)) { 1129 cmd->c_resp[0] = (cmd->c_resp[0] >> 8) | 1130 (cmd->c_resp[1] << 24); 1131 cmd->c_resp[1] = (cmd->c_resp[1] >> 8) | 1132 (cmd->c_resp[2] << 24); 1133 cmd->c_resp[2] = (cmd->c_resp[2] >> 8) | 1134 (cmd->c_resp[3] << 24); 1135 cmd->c_resp[3] = (cmd->c_resp[3] >> 8); 1136 } 1137 } 1138 } 1139 mutex_exit(&hp->host_mtx); 1140 DPRINTF(1,("%s: resp = %08x\n", HDEVNAME(hp), cmd->c_resp[0])); 1141 1142 /* 1143 * If the command has data to transfer in any direction, 1144 * execute the transfer now. 1145 */ 1146 if (cmd->c_error == 0 && cmd->c_data != NULL) 1147 sdhc_transfer_data(hp, cmd); 1148 else if (ISSET(cmd->c_flags, SCF_RSP_BSY)) { 1149 if (!sdhc_wait_intr(hp, SDHC_TRANSFER_COMPLETE, hz * 10)) { 1150 cmd->c_error = ETIMEDOUT; 1151 goto out; 1152 } 1153 } 1154 1155 out: 1156 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED) 1157 && !ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_LED_ON)) { 1158 mutex_enter(&hp->host_mtx); 1159 /* Turn off the LED. */ 1160 HCLR1(hp, SDHC_HOST_CTL, SDHC_LED_ON); 1161 mutex_exit(&hp->host_mtx); 1162 } 1163 SET(cmd->c_flags, SCF_ITSDONE); 1164 1165 DPRINTF(1,("%s: cmd %d %s (flags=%08x error=%d)\n", HDEVNAME(hp), 1166 cmd->c_opcode, (cmd->c_error == 0) ? "done" : "abort", 1167 cmd->c_flags, cmd->c_error)); 1168 } 1169 1170 static int 1171 sdhc_start_command(struct sdhc_host *hp, struct sdmmc_command *cmd) 1172 { 1173 struct sdhc_softc * const sc = hp->sc; 1174 uint16_t blksize = 0; 1175 uint16_t blkcount = 0; 1176 uint16_t mode; 1177 uint16_t command; 1178 int error; 1179 1180 DPRINTF(1,("%s: start cmd %d arg=%08x data=%p dlen=%d flags=%08x, status=%#x\n", 1181 HDEVNAME(hp), cmd->c_opcode, cmd->c_arg, cmd->c_data, 1182 cmd->c_datalen, cmd->c_flags, HREAD4(hp, SDHC_NINTR_STATUS))); 1183 1184 /* 1185 * The maximum block length for commands should be the minimum 1186 * of the host buffer size and the card buffer size. (1.7.2) 1187 */ 1188 1189 /* Fragment the data into proper blocks. */ 1190 if (cmd->c_datalen > 0) { 1191 blksize = MIN(cmd->c_datalen, cmd->c_blklen); 1192 blkcount = cmd->c_datalen / blksize; 1193 if (cmd->c_datalen % blksize > 0) { 1194 /* XXX: Split this command. (1.7.4) */ 1195 aprint_error_dev(sc->sc_dev, 1196 "data not a multiple of %u bytes\n", blksize); 1197 return EINVAL; 1198 } 1199 } 1200 1201 /* Check limit imposed by 9-bit block count. (1.7.2) */ 1202 if (blkcount > SDHC_BLOCK_COUNT_MAX) { 1203 aprint_error_dev(sc->sc_dev, "too much data\n"); 1204 return EINVAL; 1205 } 1206 1207 /* Prepare transfer mode register value. (2.2.5) */ 1208 mode = SDHC_BLOCK_COUNT_ENABLE; 1209 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 1210 mode |= SDHC_READ_MODE; 1211 if (blkcount > 1) { 1212 mode |= SDHC_MULTI_BLOCK_MODE; 1213 /* XXX only for memory commands? */ 1214 mode |= SDHC_AUTO_CMD12_ENABLE; 1215 } 1216 if (cmd->c_dmamap != NULL && cmd->c_datalen > 0 && 1217 ISSET(hp->flags, SHF_MODE_DMAEN)) { 1218 mode |= SDHC_DMA_ENABLE; 1219 } 1220 1221 /* 1222 * Prepare command register value. (2.2.6) 1223 */ 1224 command = (cmd->c_opcode & SDHC_COMMAND_INDEX_MASK) << SDHC_COMMAND_INDEX_SHIFT; 1225 1226 if (ISSET(cmd->c_flags, SCF_RSP_CRC)) 1227 command |= SDHC_CRC_CHECK_ENABLE; 1228 if (ISSET(cmd->c_flags, SCF_RSP_IDX)) 1229 command |= SDHC_INDEX_CHECK_ENABLE; 1230 if (cmd->c_data != NULL) 1231 command |= SDHC_DATA_PRESENT_SELECT; 1232 1233 if (!ISSET(cmd->c_flags, SCF_RSP_PRESENT)) 1234 command |= SDHC_NO_RESPONSE; 1235 else if (ISSET(cmd->c_flags, SCF_RSP_136)) 1236 command |= SDHC_RESP_LEN_136; 1237 else if (ISSET(cmd->c_flags, SCF_RSP_BSY)) 1238 command |= SDHC_RESP_LEN_48_CHK_BUSY; 1239 else 1240 command |= SDHC_RESP_LEN_48; 1241 1242 /* Wait until command and data inhibit bits are clear. (1.5) */ 1243 error = sdhc_wait_state(hp, SDHC_CMD_INHIBIT_MASK, 0); 1244 if (error) 1245 return error; 1246 1247 DPRINTF(1,("%s: writing cmd: blksize=%d blkcnt=%d mode=%04x cmd=%04x\n", 1248 HDEVNAME(hp), blksize, blkcount, mode, command)); 1249 1250 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1251 blksize |= (MAX(0, PAGE_SHIFT - 12) & SDHC_DMA_BOUNDARY_MASK) << 1252 SDHC_DMA_BOUNDARY_SHIFT; /* PAGE_SIZE DMA boundary */ 1253 } 1254 1255 mutex_enter(&hp->host_mtx); 1256 1257 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1258 /* Alert the user not to remove the card. */ 1259 HSET1(hp, SDHC_HOST_CTL, SDHC_LED_ON); 1260 } 1261 1262 /* Set DMA start address. */ 1263 if (ISSET(mode, SDHC_DMA_ENABLE) && 1264 !ISSET(sc->sc_flags, SDHC_FLAG_EXTERNAL_DMA)) 1265 HWRITE4(hp, SDHC_DMA_ADDR, cmd->c_dmamap->dm_segs[0].ds_addr); 1266 1267 /* 1268 * Start a CPU data transfer. Writing to the high order byte 1269 * of the SDHC_COMMAND register triggers the SD command. (1.5) 1270 */ 1271 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 1272 HWRITE4(hp, SDHC_BLOCK_SIZE, blksize | (blkcount << 16)); 1273 HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg); 1274 HWRITE4(hp, SDHC_TRANSFER_MODE, mode | (command << 16)); 1275 } else { 1276 HWRITE2(hp, SDHC_BLOCK_SIZE, blksize); 1277 HWRITE2(hp, SDHC_BLOCK_COUNT, blkcount); 1278 HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg); 1279 HWRITE2(hp, SDHC_TRANSFER_MODE, mode); 1280 HWRITE2(hp, SDHC_COMMAND, command); 1281 } 1282 1283 mutex_exit(&hp->host_mtx); 1284 1285 return 0; 1286 } 1287 1288 static void 1289 sdhc_transfer_data(struct sdhc_host *hp, struct sdmmc_command *cmd) 1290 { 1291 struct sdhc_softc *sc = hp->sc; 1292 int error; 1293 1294 DPRINTF(1,("%s: data transfer: resp=%08x datalen=%u\n", HDEVNAME(hp), 1295 MMC_R1(cmd->c_resp), cmd->c_datalen)); 1296 1297 #ifdef SDHC_DEBUG 1298 /* XXX I forgot why I wanted to know when this happens :-( */ 1299 if ((cmd->c_opcode == 52 || cmd->c_opcode == 53) && 1300 ISSET(MMC_R1(cmd->c_resp), 0xcb00)) { 1301 aprint_error_dev(hp->sc->sc_dev, 1302 "CMD52/53 error response flags %#x\n", 1303 MMC_R1(cmd->c_resp) & 0xff00); 1304 } 1305 #endif 1306 1307 if (cmd->c_dmamap != NULL) { 1308 if (hp->sc->sc_vendor_transfer_data_dma != NULL) { 1309 error = hp->sc->sc_vendor_transfer_data_dma(sc, cmd); 1310 if (error == 0 && !sdhc_wait_intr(hp, 1311 SDHC_TRANSFER_COMPLETE, SDHC_TRANSFER_TIMEOUT)) { 1312 error = ETIMEDOUT; 1313 } 1314 } else { 1315 error = sdhc_transfer_data_dma(hp, cmd); 1316 } 1317 } else 1318 error = sdhc_transfer_data_pio(hp, cmd); 1319 if (error) 1320 cmd->c_error = error; 1321 SET(cmd->c_flags, SCF_ITSDONE); 1322 1323 DPRINTF(1,("%s: data transfer done (error=%d)\n", 1324 HDEVNAME(hp), cmd->c_error)); 1325 } 1326 1327 static int 1328 sdhc_transfer_data_dma(struct sdhc_host *hp, struct sdmmc_command *cmd) 1329 { 1330 bus_dma_segment_t *dm_segs = cmd->c_dmamap->dm_segs; 1331 bus_addr_t posaddr; 1332 bus_addr_t segaddr; 1333 bus_size_t seglen; 1334 u_int seg = 0; 1335 int error = 0; 1336 int status; 1337 1338 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_DMA_INTERRUPT); 1339 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_DMA_INTERRUPT); 1340 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_TRANSFER_COMPLETE); 1341 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_TRANSFER_COMPLETE); 1342 1343 for (;;) { 1344 status = sdhc_wait_intr(hp, 1345 SDHC_DMA_INTERRUPT|SDHC_TRANSFER_COMPLETE, 1346 SDHC_DMA_TIMEOUT); 1347 1348 if (status & SDHC_TRANSFER_COMPLETE) { 1349 break; 1350 } 1351 if (!status) { 1352 error = ETIMEDOUT; 1353 break; 1354 } 1355 if ((status & SDHC_DMA_INTERRUPT) == 0) { 1356 continue; 1357 } 1358 1359 /* DMA Interrupt (boundary crossing) */ 1360 1361 segaddr = dm_segs[seg].ds_addr; 1362 seglen = dm_segs[seg].ds_len; 1363 mutex_enter(&hp->host_mtx); 1364 posaddr = HREAD4(hp, SDHC_DMA_ADDR); 1365 mutex_exit(&hp->host_mtx); 1366 1367 if ((seg == (cmd->c_dmamap->dm_nsegs-1)) && (posaddr == (segaddr + seglen))) { 1368 continue; 1369 } 1370 mutex_enter(&hp->host_mtx); 1371 if ((posaddr >= segaddr) && (posaddr < (segaddr + seglen))) 1372 HWRITE4(hp, SDHC_DMA_ADDR, posaddr); 1373 else if ((posaddr >= segaddr) && (posaddr == (segaddr + seglen)) && (seg + 1) < cmd->c_dmamap->dm_nsegs) 1374 HWRITE4(hp, SDHC_DMA_ADDR, dm_segs[++seg].ds_addr); 1375 mutex_exit(&hp->host_mtx); 1376 KASSERT(seg < cmd->c_dmamap->dm_nsegs); 1377 } 1378 1379 return error; 1380 } 1381 1382 static int 1383 sdhc_transfer_data_pio(struct sdhc_host *hp, struct sdmmc_command *cmd) 1384 { 1385 uint8_t *data = cmd->c_data; 1386 void (*pio_func)(struct sdhc_host *, uint8_t *, u_int); 1387 u_int len, datalen; 1388 u_int imask; 1389 u_int pmask; 1390 int error = 0; 1391 1392 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 1393 imask = SDHC_BUFFER_READ_READY; 1394 pmask = SDHC_BUFFER_READ_ENABLE; 1395 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1396 pio_func = esdhc_read_data_pio; 1397 } else { 1398 pio_func = sdhc_read_data_pio; 1399 } 1400 } else { 1401 imask = SDHC_BUFFER_WRITE_READY; 1402 pmask = SDHC_BUFFER_WRITE_ENABLE; 1403 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1404 pio_func = esdhc_write_data_pio; 1405 } else { 1406 pio_func = sdhc_write_data_pio; 1407 } 1408 } 1409 datalen = cmd->c_datalen; 1410 1411 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & imask); 1412 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_TRANSFER_COMPLETE); 1413 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_TRANSFER_COMPLETE); 1414 1415 while (datalen > 0) { 1416 if (!ISSET(HREAD4(hp, SDHC_PRESENT_STATE), imask)) { 1417 mutex_enter(&hp->intr_mtx); 1418 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 1419 HSET4(hp, SDHC_NINTR_SIGNAL_EN, imask); 1420 } else { 1421 HSET2(hp, SDHC_NINTR_SIGNAL_EN, imask); 1422 } 1423 mutex_exit(&hp->intr_mtx); 1424 if (!sdhc_wait_intr(hp, imask, SDHC_BUFFER_TIMEOUT)) { 1425 error = ETIMEDOUT; 1426 break; 1427 } 1428 1429 error = sdhc_wait_state(hp, pmask, pmask); 1430 if (error) 1431 break; 1432 } 1433 1434 len = MIN(datalen, cmd->c_blklen); 1435 (*pio_func)(hp, data, len); 1436 DPRINTF(2,("%s: pio data transfer %u @ %p\n", 1437 HDEVNAME(hp), len, data)); 1438 1439 data += len; 1440 datalen -= len; 1441 } 1442 1443 if (error == 0 && !sdhc_wait_intr(hp, SDHC_TRANSFER_COMPLETE, 1444 SDHC_TRANSFER_TIMEOUT)) 1445 error = ETIMEDOUT; 1446 1447 return error; 1448 } 1449 1450 static void 1451 sdhc_read_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1452 { 1453 1454 if (((__uintptr_t)data & 3) == 0) { 1455 while (datalen > 3) { 1456 *(uint32_t *)data = le32toh(HREAD4(hp, SDHC_DATA)); 1457 data += 4; 1458 datalen -= 4; 1459 } 1460 if (datalen > 1) { 1461 *(uint16_t *)data = le16toh(HREAD2(hp, SDHC_DATA)); 1462 data += 2; 1463 datalen -= 2; 1464 } 1465 if (datalen > 0) { 1466 *data = HREAD1(hp, SDHC_DATA); 1467 data += 1; 1468 datalen -= 1; 1469 } 1470 } else if (((__uintptr_t)data & 1) == 0) { 1471 while (datalen > 1) { 1472 *(uint16_t *)data = le16toh(HREAD2(hp, SDHC_DATA)); 1473 data += 2; 1474 datalen -= 2; 1475 } 1476 if (datalen > 0) { 1477 *data = HREAD1(hp, SDHC_DATA); 1478 data += 1; 1479 datalen -= 1; 1480 } 1481 } else { 1482 while (datalen > 0) { 1483 *data = HREAD1(hp, SDHC_DATA); 1484 data += 1; 1485 datalen -= 1; 1486 } 1487 } 1488 } 1489 1490 static void 1491 sdhc_write_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1492 { 1493 1494 if (((__uintptr_t)data & 3) == 0) { 1495 while (datalen > 3) { 1496 HWRITE4(hp, SDHC_DATA, htole32(*(uint32_t *)data)); 1497 data += 4; 1498 datalen -= 4; 1499 } 1500 if (datalen > 1) { 1501 HWRITE2(hp, SDHC_DATA, htole16(*(uint16_t *)data)); 1502 data += 2; 1503 datalen -= 2; 1504 } 1505 if (datalen > 0) { 1506 HWRITE1(hp, SDHC_DATA, *data); 1507 data += 1; 1508 datalen -= 1; 1509 } 1510 } else if (((__uintptr_t)data & 1) == 0) { 1511 while (datalen > 1) { 1512 HWRITE2(hp, SDHC_DATA, htole16(*(uint16_t *)data)); 1513 data += 2; 1514 datalen -= 2; 1515 } 1516 if (datalen > 0) { 1517 HWRITE1(hp, SDHC_DATA, *data); 1518 data += 1; 1519 datalen -= 1; 1520 } 1521 } else { 1522 while (datalen > 0) { 1523 HWRITE1(hp, SDHC_DATA, *data); 1524 data += 1; 1525 datalen -= 1; 1526 } 1527 } 1528 } 1529 1530 static void 1531 esdhc_read_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1532 { 1533 uint16_t status = HREAD2(hp, SDHC_NINTR_STATUS); 1534 uint32_t v; 1535 1536 const size_t watermark = (HREAD4(hp, SDHC_WATERMARK_LEVEL) >> SDHC_WATERMARK_READ_SHIFT) & SDHC_WATERMARK_READ_MASK; 1537 size_t count = 0; 1538 1539 while (datalen > 3 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1540 if (count == 0) { 1541 /* 1542 * If we've drained "watermark" words, we need to wait 1543 * a little bit so the read FIFO can refill. 1544 */ 1545 sdmmc_delay(10); 1546 count = watermark; 1547 } 1548 v = HREAD4(hp, SDHC_DATA); 1549 v = le32toh(v); 1550 *(uint32_t *)data = v; 1551 data += 4; 1552 datalen -= 4; 1553 status = HREAD2(hp, SDHC_NINTR_STATUS); 1554 count--; 1555 } 1556 if (datalen > 0 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1557 if (count == 0) { 1558 sdmmc_delay(10); 1559 } 1560 v = HREAD4(hp, SDHC_DATA); 1561 v = le32toh(v); 1562 do { 1563 *data++ = v; 1564 v >>= 8; 1565 } while (--datalen > 0); 1566 } 1567 } 1568 1569 static void 1570 esdhc_write_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1571 { 1572 uint16_t status = HREAD2(hp, SDHC_NINTR_STATUS); 1573 uint32_t v; 1574 1575 const size_t watermark = (HREAD4(hp, SDHC_WATERMARK_LEVEL) >> SDHC_WATERMARK_WRITE_SHIFT) & SDHC_WATERMARK_WRITE_MASK; 1576 size_t count = watermark; 1577 1578 while (datalen > 3 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1579 if (count == 0) { 1580 sdmmc_delay(10); 1581 count = watermark; 1582 } 1583 v = *(uint32_t *)data; 1584 v = htole32(v); 1585 HWRITE4(hp, SDHC_DATA, v); 1586 data += 4; 1587 datalen -= 4; 1588 status = HREAD2(hp, SDHC_NINTR_STATUS); 1589 count--; 1590 } 1591 if (datalen > 0 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1592 if (count == 0) { 1593 sdmmc_delay(10); 1594 } 1595 v = *(uint32_t *)data; 1596 v = htole32(v); 1597 HWRITE4(hp, SDHC_DATA, v); 1598 } 1599 } 1600 1601 /* Prepare for another command. */ 1602 static int 1603 sdhc_soft_reset(struct sdhc_host *hp, int mask) 1604 { 1605 int timo; 1606 1607 DPRINTF(1,("%s: software reset reg=%08x\n", HDEVNAME(hp), mask)); 1608 1609 /* Request the reset. */ 1610 HWRITE1(hp, SDHC_SOFTWARE_RESET, mask); 1611 1612 /* 1613 * If necessary, wait for the controller to set the bits to 1614 * acknowledge the reset. 1615 */ 1616 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_WAIT_RESET) && 1617 ISSET(mask, (SDHC_RESET_DAT | SDHC_RESET_CMD))) { 1618 for (timo = 10000; timo > 0; timo--) { 1619 if (ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), mask)) 1620 break; 1621 /* Short delay because I worry we may miss it... */ 1622 sdmmc_delay(1); 1623 } 1624 if (timo == 0) 1625 return ETIMEDOUT; 1626 } 1627 1628 /* 1629 * Wait for the controller to clear the bits to indicate that 1630 * the reset has completed. 1631 */ 1632 for (timo = 10; timo > 0; timo--) { 1633 if (!ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), mask)) 1634 break; 1635 sdmmc_delay(10000); 1636 } 1637 if (timo == 0) { 1638 DPRINTF(1,("%s: timeout reg=%08x\n", HDEVNAME(hp), 1639 HREAD1(hp, SDHC_SOFTWARE_RESET))); 1640 return ETIMEDOUT; 1641 } 1642 1643 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1644 HWRITE4(hp, SDHC_DMA_CTL, SDHC_DMA_SNOOP); 1645 } 1646 1647 return 0; 1648 } 1649 1650 static int 1651 sdhc_wait_intr(struct sdhc_host *hp, int mask, int timo) 1652 { 1653 int status; 1654 1655 mask |= SDHC_ERROR_INTERRUPT; 1656 1657 mutex_enter(&hp->intr_mtx); 1658 status = hp->intr_status & mask; 1659 while (status == 0) { 1660 if (cv_timedwait(&hp->intr_cv, &hp->intr_mtx, timo) 1661 == EWOULDBLOCK) { 1662 status |= SDHC_ERROR_INTERRUPT; 1663 break; 1664 } 1665 status = hp->intr_status & mask; 1666 } 1667 hp->intr_status &= ~status; 1668 1669 DPRINTF(2,("%s: intr status %#x error %#x\n", HDEVNAME(hp), status, 1670 hp->intr_error_status)); 1671 1672 /* Command timeout has higher priority than command complete. */ 1673 if (ISSET(status, SDHC_ERROR_INTERRUPT) || hp->intr_error_status) { 1674 hp->intr_error_status = 0; 1675 hp->intr_status &= ~SDHC_ERROR_INTERRUPT; 1676 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1677 (void)sdhc_soft_reset(hp, SDHC_RESET_DAT|SDHC_RESET_CMD); 1678 } 1679 status = 0; 1680 } 1681 mutex_exit(&hp->intr_mtx); 1682 1683 return status; 1684 } 1685 1686 /* 1687 * Established by attachment driver at interrupt priority IPL_SDMMC. 1688 */ 1689 int 1690 sdhc_intr(void *arg) 1691 { 1692 struct sdhc_softc *sc = (struct sdhc_softc *)arg; 1693 struct sdhc_host *hp; 1694 int done = 0; 1695 uint16_t status; 1696 uint16_t error; 1697 1698 /* We got an interrupt, but we don't know from which slot. */ 1699 for (size_t host = 0; host < sc->sc_nhosts; host++) { 1700 hp = sc->sc_host[host]; 1701 if (hp == NULL) 1702 continue; 1703 1704 if (ISSET(sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 1705 /* Find out which interrupts are pending. */ 1706 uint32_t xstatus = HREAD4(hp, SDHC_NINTR_STATUS); 1707 status = xstatus; 1708 error = xstatus >> 16; 1709 if (error) 1710 xstatus |= SDHC_ERROR_INTERRUPT; 1711 else if (!ISSET(status, SDHC_NINTR_STATUS_MASK)) 1712 continue; /* no interrupt for us */ 1713 /* Acknowledge the interrupts we are about to handle. */ 1714 HWRITE4(hp, SDHC_NINTR_STATUS, xstatus); 1715 } else { 1716 /* Find out which interrupts are pending. */ 1717 error = 0; 1718 status = HREAD2(hp, SDHC_NINTR_STATUS); 1719 if (!ISSET(status, SDHC_NINTR_STATUS_MASK)) 1720 continue; /* no interrupt for us */ 1721 /* Acknowledge the interrupts we are about to handle. */ 1722 HWRITE2(hp, SDHC_NINTR_STATUS, status); 1723 if (ISSET(status, SDHC_ERROR_INTERRUPT)) { 1724 /* Acknowledge error interrupts. */ 1725 error = HREAD2(hp, SDHC_EINTR_STATUS); 1726 HWRITE2(hp, SDHC_EINTR_STATUS, error); 1727 } 1728 } 1729 1730 DPRINTF(2,("%s: interrupt status=%x error=%x\n", HDEVNAME(hp), 1731 status, error)); 1732 1733 mutex_enter(&hp->intr_mtx); 1734 1735 /* Claim this interrupt. */ 1736 done = 1; 1737 1738 /* 1739 * Service error interrupts. 1740 */ 1741 if (ISSET(error, SDHC_CMD_TIMEOUT_ERROR| 1742 SDHC_DATA_TIMEOUT_ERROR)) { 1743 hp->intr_error_status |= error; 1744 hp->intr_status |= status; 1745 cv_broadcast(&hp->intr_cv); 1746 } 1747 1748 /* 1749 * Wake up the sdmmc event thread to scan for cards. 1750 */ 1751 if (ISSET(status, SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)) { 1752 if (hp->sdmmc != NULL) { 1753 sdmmc_needs_discover(hp->sdmmc); 1754 } 1755 if (ISSET(sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1756 HCLR4(hp, SDHC_NINTR_STATUS_EN, 1757 status & (SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)); 1758 HCLR4(hp, SDHC_NINTR_SIGNAL_EN, 1759 status & (SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)); 1760 } 1761 } 1762 1763 /* 1764 * Wake up the blocking process to service command 1765 * related interrupt(s). 1766 */ 1767 if (ISSET(status, SDHC_COMMAND_COMPLETE| 1768 SDHC_BUFFER_READ_READY|SDHC_BUFFER_WRITE_READY| 1769 SDHC_TRANSFER_COMPLETE|SDHC_DMA_INTERRUPT)) { 1770 hp->intr_status |= status; 1771 if (ISSET(sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1772 HCLR4(hp, SDHC_NINTR_SIGNAL_EN, 1773 status & (SDHC_BUFFER_READ_READY|SDHC_BUFFER_WRITE_READY)); 1774 } 1775 cv_broadcast(&hp->intr_cv); 1776 } 1777 1778 /* 1779 * Service SD card interrupts. 1780 */ 1781 if (!ISSET(sc->sc_flags, SDHC_FLAG_ENHANCED) 1782 && ISSET(status, SDHC_CARD_INTERRUPT)) { 1783 DPRINTF(0,("%s: card interrupt\n", HDEVNAME(hp))); 1784 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 1785 sdmmc_card_intr(hp->sdmmc); 1786 } 1787 mutex_exit(&hp->intr_mtx); 1788 } 1789 1790 return done; 1791 } 1792 1793 #ifdef SDHC_DEBUG 1794 void 1795 sdhc_dump_regs(struct sdhc_host *hp) 1796 { 1797 1798 printf("0x%02x PRESENT_STATE: %x\n", SDHC_PRESENT_STATE, 1799 HREAD4(hp, SDHC_PRESENT_STATE)); 1800 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 1801 printf("0x%02x POWER_CTL: %x\n", SDHC_POWER_CTL, 1802 HREAD1(hp, SDHC_POWER_CTL)); 1803 printf("0x%02x NINTR_STATUS: %x\n", SDHC_NINTR_STATUS, 1804 HREAD2(hp, SDHC_NINTR_STATUS)); 1805 printf("0x%02x EINTR_STATUS: %x\n", SDHC_EINTR_STATUS, 1806 HREAD2(hp, SDHC_EINTR_STATUS)); 1807 printf("0x%02x NINTR_STATUS_EN: %x\n", SDHC_NINTR_STATUS_EN, 1808 HREAD2(hp, SDHC_NINTR_STATUS_EN)); 1809 printf("0x%02x EINTR_STATUS_EN: %x\n", SDHC_EINTR_STATUS_EN, 1810 HREAD2(hp, SDHC_EINTR_STATUS_EN)); 1811 printf("0x%02x NINTR_SIGNAL_EN: %x\n", SDHC_NINTR_SIGNAL_EN, 1812 HREAD2(hp, SDHC_NINTR_SIGNAL_EN)); 1813 printf("0x%02x EINTR_SIGNAL_EN: %x\n", SDHC_EINTR_SIGNAL_EN, 1814 HREAD2(hp, SDHC_EINTR_SIGNAL_EN)); 1815 printf("0x%02x CAPABILITIES: %x\n", SDHC_CAPABILITIES, 1816 HREAD4(hp, SDHC_CAPABILITIES)); 1817 printf("0x%02x MAX_CAPABILITIES: %x\n", SDHC_MAX_CAPABILITIES, 1818 HREAD4(hp, SDHC_MAX_CAPABILITIES)); 1819 } 1820 #endif 1821
Indexes created Mon Oct 20 05:10:11 GMT 2025